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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include "amdgpu.h"
28#include "soc15_common.h"
29#include "soc21.h"
30#include "vcn/vcn_4_0_0_offset.h"
31#include "vcn/vcn_4_0_0_sh_mask.h"
32
33#include "amdgpu_umsch_mm.h"
34#include "umsch_mm_4_0_api_def.h"
35#include "umsch_mm_v4_0.h"
36
37#define regUVD_IPX_DLDO_CONFIG 0x0064
38#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
39#define regUVD_IPX_DLDO_STATUS 0x0065
40#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
41
42#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT 0x00000002
43#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK 0x0000000cUL
44#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT 0x00000001
45#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK 0x00000002UL
46
47static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
48{
49 struct amdgpu_device *adev = umsch->ring.adev;
50 uint64_t data;
51 int r;
52
53 r = amdgpu_umsch_mm_allocate_ucode_buffer(umsch);
54 if (r)
55 return r;
56
57 r = amdgpu_umsch_mm_allocate_ucode_data_buffer(umsch);
58 if (r)
59 goto err_free_ucode_bo;
60
61 umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
62
63 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) {
64 WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
65 1 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
66 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
67 0 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
68 UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
69 }
70
71 data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
72 data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);
73 WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data);
74
75 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
76 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 1);
77 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 1);
78 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 0);
79 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 1);
80 WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);
81
82 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL);
83 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0);
84 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, EXE_DISABLE, 0);
85 data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, CACHE_POLICY, 0);
86 WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_CNTL, data);
87
88 WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START,
89 lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));
90 WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START_HI,
91 upper_32_bits(adev->umsch_mm.irq_start_addr >> 2));
92
93 WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START,
94 lower_32_bits(adev->umsch_mm.uc_start_addr >> 2));
95 WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START_HI,
96 upper_32_bits(adev->umsch_mm.uc_start_addr >> 2));
97
98 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_LO, 0);
99 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_HI, 0);
100
101 data = adev->umsch_mm.uc_start_addr + adev->umsch_mm.ucode_size - 1;
102 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));
103 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data));
104
105 data = adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
106 0 : adev->umsch_mm.ucode_fw_gpu_addr;
107 WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_LO, lower_32_bits(data));
108 WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_HI, upper_32_bits(data));
109
110 WREG32_SOC15_UMSCH(regVCN_MES_MIBOUND_LO, 0x1FFFFF);
111
112 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_LO,
113 lower_32_bits(adev->umsch_mm.data_start_addr));
114 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_HI,
115 upper_32_bits(adev->umsch_mm.data_start_addr));
116
117 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_LO,
118 lower_32_bits(adev->umsch_mm.data_size - 1));
119 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_HI,
120 upper_32_bits(adev->umsch_mm.data_size - 1));
121
122 data = adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
123 0 : adev->umsch_mm.data_fw_gpu_addr;
124 WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_LO, lower_32_bits(data));
125 WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_HI, upper_32_bits(data));
126
127 WREG32_SOC15_UMSCH(regVCN_MES_MDBOUND_LO, 0x3FFFF);
128
129 data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE);
130 data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, IC_FORCE_GPUVM, 1);
131 data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, DC_FORCE_GPUVM, 1);
132 WREG32_SOC15_UMSCH(regUVD_UMSCH_FORCE, data);
133
134 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);
135 data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
136 data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
137 WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);
138
139 data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);
140 data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
141 WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);
142
143 WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, 0);
144 WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, 0);
145
146 WREG32_SOC15_UMSCH(regVCN_MES_GP1_LO, 0);
147 WREG32_SOC15_UMSCH(regVCN_MES_GP1_HI, 0);
148
149 data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
150 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 0);
151 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 0);
152 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 0);
153 data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 1);
154 WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);
155
156 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
157 amdgpu_umsch_mm_psp_execute_cmd_buf(umsch);
158
159 r = SOC15_WAIT_ON_RREG(VCN, 0, regVCN_MES_MSTATUS_LO, 0xAAAAAAAA, 0xFFFFFFFF);
160 if (r) {
161 dev_err(adev->dev, "UMSCH FW Load: Failed, regVCN_MES_MSTATUS_LO: 0x%08x\n",
162 RREG32_SOC15(VCN, 0, regVCN_MES_MSTATUS_LO));
163 goto err_free_data_bo;
164 }
165
166 return 0;
167
168err_free_data_bo:
169 amdgpu_bo_free_kernel(&adev->umsch_mm.data_fw_obj,
170 &adev->umsch_mm.data_fw_gpu_addr,
171 (void **)&adev->umsch_mm.data_fw_ptr);
172err_free_ucode_bo:
173 amdgpu_bo_free_kernel(&adev->umsch_mm.ucode_fw_obj,
174 &adev->umsch_mm.ucode_fw_gpu_addr,
175 (void **)&adev->umsch_mm.ucode_fw_ptr);
176 return r;
177}
178
179static void umsch_mm_v4_0_aggregated_doorbell_init(struct amdgpu_umsch_mm *umsch)
180{
181 struct amdgpu_device *adev = umsch->ring.adev;
182 uint32_t data;
183
184 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL0);
185 data = REG_SET_FIELD(data, VCN_AGDB_CTRL0, OFFSET,
186 umsch->agdb_index[CONTEXT_PRIORITY_LEVEL_REALTIME]);
187 data = REG_SET_FIELD(data, VCN_AGDB_CTRL0, EN, 1);
188 WREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL0, data);
189
190 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL1);
191 data = REG_SET_FIELD(data, VCN_AGDB_CTRL1, OFFSET,
192 umsch->agdb_index[CONTEXT_PRIORITY_LEVEL_FOCUS]);
193 data = REG_SET_FIELD(data, VCN_AGDB_CTRL1, EN, 1);
194 WREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL1, data);
195
196 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL2);
197 data = REG_SET_FIELD(data, VCN_AGDB_CTRL2, OFFSET,
198 umsch->agdb_index[CONTEXT_PRIORITY_LEVEL_NORMAL]);
199 data = REG_SET_FIELD(data, VCN_AGDB_CTRL2, EN, 1);
200 WREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL2, data);
201
202 data = RREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL3);
203 data = REG_SET_FIELD(data, VCN_AGDB_CTRL3, OFFSET,
204 umsch->agdb_index[CONTEXT_PRIORITY_LEVEL_IDLE]);
205 data = REG_SET_FIELD(data, VCN_AGDB_CTRL3, EN, 1);
206 WREG32_SOC15(VCN, 0, regVCN_AGDB_CTRL3, data);
207}
208
209static int umsch_mm_v4_0_ring_start(struct amdgpu_umsch_mm *umsch)
210{
211 struct amdgpu_ring *ring = &umsch->ring;
212 struct amdgpu_device *adev = ring->adev;
213 uint32_t data;
214
215 data = RREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL);
216 data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, OFFSET, ring->doorbell_index);
217 data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 1);
218 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
219
220 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
221 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
222
223 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_LO, lower_32_bits(ring->gpu_addr));
224 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
225
226 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_SIZE, ring->ring_size);
227
228 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE);
229 data &= ~(VCN_RB_ENABLE__AUDIO_RB_EN_MASK);
230 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data);
231
232 umsch_mm_v4_0_aggregated_doorbell_init(umsch);
233
234 return 0;
235}
236
237static int umsch_mm_v4_0_ring_stop(struct amdgpu_umsch_mm *umsch)
238{
239 struct amdgpu_ring *ring = &umsch->ring;
240 struct amdgpu_device *adev = ring->adev;
241 uint32_t data;
242
243 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE);
244 data = REG_SET_FIELD(data, VCN_RB_ENABLE, UMSCH_RB_EN, 0);
245 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data);
246
247 data = RREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL);
248 data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
249 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
250
251 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5)) {
252 WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
253 2 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
254 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
255 1 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
256 UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
257 }
258
259 return 0;
260}
261
262static int umsch_mm_v4_0_set_hw_resources(struct amdgpu_umsch_mm *umsch)
263{
264 union UMSCHAPI__SET_HW_RESOURCES set_hw_resources = {};
265 struct amdgpu_device *adev = umsch->ring.adev;
266 int r;
267
268 set_hw_resources.header.type = UMSCH_API_TYPE_SCHEDULER;
269 set_hw_resources.header.opcode = UMSCH_API_SET_HW_RSRC;
270 set_hw_resources.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
271
272 set_hw_resources.vmid_mask_mm_vcn = umsch->vmid_mask_mm_vcn;
273 set_hw_resources.vmid_mask_mm_vpe = umsch->vmid_mask_mm_vpe;
274 set_hw_resources.engine_mask = umsch->engine_mask;
275
276 set_hw_resources.vcn0_hqd_mask[0] = umsch->vcn0_hqd_mask;
277 set_hw_resources.vcn1_hqd_mask[0] = umsch->vcn1_hqd_mask;
278 set_hw_resources.vcn_hqd_mask[0] = umsch->vcn_hqd_mask[0];
279 set_hw_resources.vcn_hqd_mask[1] = umsch->vcn_hqd_mask[1];
280 set_hw_resources.vpe_hqd_mask[0] = umsch->vpe_hqd_mask;
281
282 set_hw_resources.g_sch_ctx_gpu_mc_ptr = umsch->sch_ctx_gpu_addr;
283
284 set_hw_resources.enable_level_process_quantum_check = 1;
285
286 memcpy(set_hw_resources.mmhub_base, adev->reg_offset[MMHUB_HWIP][0],
287 sizeof(uint32_t) * 5);
288 set_hw_resources.mmhub_version =
289 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, MMHUB_HWIP, 0));
290
291 memcpy(set_hw_resources.osssys_base, adev->reg_offset[OSSSYS_HWIP][0],
292 sizeof(uint32_t) * 5);
293 set_hw_resources.osssys_version =
294 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, OSSSYS_HWIP, 0));
295
296 set_hw_resources.vcn_version =
297 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCN_HWIP, 0));
298 set_hw_resources.vpe_version =
299 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0));
300
301 set_hw_resources.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr;
302 set_hw_resources.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq;
303
304 r = amdgpu_umsch_mm_submit_pkt(umsch, &set_hw_resources.max_dwords_in_api,
305 API_FRAME_SIZE_IN_DWORDS);
306 if (r)
307 return r;
308
309 r = amdgpu_umsch_mm_query_fence(umsch);
310 if (r) {
311 dev_err(adev->dev, "UMSCH SET_HW_RESOURCES: Failed\n");
312 return r;
313 }
314
315 return 0;
316}
317
318static int umsch_mm_v4_0_add_queue(struct amdgpu_umsch_mm *umsch,
319 struct umsch_mm_add_queue_input *input_ptr)
320{
321 struct amdgpu_device *adev = umsch->ring.adev;
322 union UMSCHAPI__ADD_QUEUE add_queue = {};
323 int r;
324
325 add_queue.header.type = UMSCH_API_TYPE_SCHEDULER;
326 add_queue.header.opcode = UMSCH_API_ADD_QUEUE;
327 add_queue.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
328
329 add_queue.process_id = input_ptr->process_id;
330 add_queue.page_table_base_addr = input_ptr->page_table_base_addr;
331 add_queue.process_va_start = input_ptr->process_va_start;
332 add_queue.process_va_end = input_ptr->process_va_end;
333 add_queue.process_quantum = input_ptr->process_quantum;
334 add_queue.process_csa_addr = input_ptr->process_csa_addr;
335 add_queue.context_quantum = input_ptr->context_quantum;
336 add_queue.context_csa_addr = input_ptr->context_csa_addr;
337 add_queue.inprocess_context_priority = input_ptr->inprocess_context_priority;
338 add_queue.context_global_priority_level =
339 (enum UMSCH_AMD_PRIORITY_LEVEL)input_ptr->context_global_priority_level;
340 add_queue.doorbell_offset_0 = input_ptr->doorbell_offset_0;
341 add_queue.doorbell_offset_1 = input_ptr->doorbell_offset_1;
342 add_queue.affinity.u32All = input_ptr->affinity;
343 add_queue.mqd_addr = input_ptr->mqd_addr;
344 add_queue.engine_type = (enum UMSCH_ENGINE_TYPE)input_ptr->engine_type;
345 add_queue.h_context = input_ptr->h_context;
346 add_queue.h_queue = input_ptr->h_queue;
347 add_queue.vm_context_cntl = input_ptr->vm_context_cntl;
348 add_queue.is_context_suspended = input_ptr->is_context_suspended;
349
350 add_queue.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr;
351 add_queue.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq;
352
353 r = amdgpu_umsch_mm_submit_pkt(umsch, &add_queue.max_dwords_in_api,
354 API_FRAME_SIZE_IN_DWORDS);
355 if (r)
356 return r;
357
358 r = amdgpu_umsch_mm_query_fence(umsch);
359 if (r) {
360 dev_err(adev->dev, "UMSCH ADD_QUEUE: Failed\n");
361 return r;
362 }
363
364 return 0;
365}
366
367static int umsch_mm_v4_0_remove_queue(struct amdgpu_umsch_mm *umsch,
368 struct umsch_mm_remove_queue_input *input_ptr)
369{
370 union UMSCHAPI__REMOVE_QUEUE remove_queue = {};
371 struct amdgpu_device *adev = umsch->ring.adev;
372 int r;
373
374 remove_queue.header.type = UMSCH_API_TYPE_SCHEDULER;
375 remove_queue.header.opcode = UMSCH_API_REMOVE_QUEUE;
376 remove_queue.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
377
378 remove_queue.doorbell_offset_0 = input_ptr->doorbell_offset_0;
379 remove_queue.doorbell_offset_1 = input_ptr->doorbell_offset_1;
380 remove_queue.context_csa_addr = input_ptr->context_csa_addr;
381
382 remove_queue.api_status.api_completion_fence_addr = umsch->ring.fence_drv.gpu_addr;
383 remove_queue.api_status.api_completion_fence_value = ++umsch->ring.fence_drv.sync_seq;
384
385 r = amdgpu_umsch_mm_submit_pkt(umsch, &remove_queue.max_dwords_in_api,
386 API_FRAME_SIZE_IN_DWORDS);
387 if (r)
388 return r;
389
390 r = amdgpu_umsch_mm_query_fence(umsch);
391 if (r) {
392 dev_err(adev->dev, "UMSCH REMOVE_QUEUE: Failed\n");
393 return r;
394 }
395
396 return 0;
397}
398
399static int umsch_mm_v4_0_set_regs(struct amdgpu_umsch_mm *umsch)
400{
401 struct amdgpu_device *adev = container_of(umsch, struct amdgpu_device, umsch_mm);
402
403 umsch->rb_wptr = SOC15_REG_OFFSET(VCN, 0, regVCN_UMSCH_RB_WPTR);
404 umsch->rb_rptr = SOC15_REG_OFFSET(VCN, 0, regVCN_UMSCH_RB_RPTR);
405
406 return 0;
407}
408
409static const struct umsch_mm_funcs umsch_mm_v4_0_funcs = {
410 .set_hw_resources = umsch_mm_v4_0_set_hw_resources,
411 .add_queue = umsch_mm_v4_0_add_queue,
412 .remove_queue = umsch_mm_v4_0_remove_queue,
413 .set_regs = umsch_mm_v4_0_set_regs,
414 .init_microcode = amdgpu_umsch_mm_init_microcode,
415 .load_microcode = umsch_mm_v4_0_load_microcode,
416 .ring_init = amdgpu_umsch_mm_ring_init,
417 .ring_start = umsch_mm_v4_0_ring_start,
418 .ring_stop = umsch_mm_v4_0_ring_stop,
419};
420
421void umsch_mm_v4_0_set_funcs(struct amdgpu_umsch_mm *umsch)
422{
423 umsch->funcs = &umsch_mm_v4_0_funcs;
424}