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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_11.h"
26
27#include "nbio/nbio_7_11_0_offset.h"
28#include "nbio/nbio_7_11_0_sh_mask.h"
29#include <uapi/linux/kfd_ioctl.h>
30
31static void nbio_v7_11_remap_hdp_registers(struct amdgpu_device *adev)
32{
33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
37}
38
39static u32 nbio_v7_11_get_rev_id(struct amdgpu_device *adev)
40{
41 u32 tmp;
42
43 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0);
44 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
45 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
46
47 return tmp;
48}
49
50static void nbio_v7_11_mc_access_enable(struct amdgpu_device *adev, bool enable)
51{
52 if (enable)
53 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN,
54 BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK |
55 BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK);
56 else
57 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0);
58}
59
60static u32 nbio_v7_11_get_memsize(struct amdgpu_device *adev)
61{
62 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
63}
64
65static void nbio_v7_11_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
66 bool use_doorbell, int doorbell_index,
67 int doorbell_size)
68{
69 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE);
70 u32 doorbell_range = RREG32_PCIE_PORT(reg);
71
72 if (use_doorbell) {
73 doorbell_range = REG_SET_FIELD(doorbell_range,
74 GDC0_BIF_CSDMA_DOORBELL_RANGE,
75 OFFSET, doorbell_index);
76 doorbell_range = REG_SET_FIELD(doorbell_range,
77 GDC0_BIF_CSDMA_DOORBELL_RANGE,
78 SIZE, doorbell_size);
79 } else {
80 doorbell_range = REG_SET_FIELD(doorbell_range,
81 GDC0_BIF_CSDMA_DOORBELL_RANGE,
82 SIZE, 0);
83 }
84
85 WREG32_PCIE_PORT(reg, doorbell_range);
86}
87
88static void nbio_v7_11_vpe_doorbell_range(struct amdgpu_device *adev, int instance,
89 bool use_doorbell, int doorbell_index,
90 int doorbell_size)
91{
92 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE_DOORBELL_RANGE);
93 u32 doorbell_range = RREG32_PCIE_PORT(reg);
94
95 if (use_doorbell) {
96 doorbell_range = REG_SET_FIELD(doorbell_range,
97 GDC0_BIF_VPE_DOORBELL_RANGE,
98 OFFSET, doorbell_index);
99 doorbell_range = REG_SET_FIELD(doorbell_range,
100 GDC0_BIF_VPE_DOORBELL_RANGE,
101 SIZE, doorbell_size);
102 } else {
103 doorbell_range = REG_SET_FIELD(doorbell_range,
104 GDC0_BIF_VPE_DOORBELL_RANGE,
105 SIZE, 0);
106 }
107
108 WREG32_PCIE_PORT(reg, doorbell_range);
109}
110
111static void nbio_v7_11_vcn_doorbell_range(struct amdgpu_device *adev,
112 bool use_doorbell,
113 int doorbell_index, int instance)
114{
115 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE);
116 u32 doorbell_range = RREG32_PCIE_PORT(reg);
117
118 if (use_doorbell) {
119 doorbell_range = REG_SET_FIELD(doorbell_range,
120 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
121 doorbell_index);
122 doorbell_range = REG_SET_FIELD(doorbell_range,
123 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
124 } else {
125 doorbell_range = REG_SET_FIELD(doorbell_range,
126 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
127 }
128
129 WREG32_PCIE_PORT(reg, doorbell_range);
130}
131
132static void nbio_v7_11_enable_doorbell_aperture(struct amdgpu_device *adev,
133 bool enable)
134{
135 u32 reg;
136
137
138 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
139 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
140 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
141
142 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
143}
144
145static void nbio_v7_11_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
146 bool enable)
147{
148 u32 tmp = 0;
149
150 if (enable) {
151 tmp = REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,
152 DOORBELL_SELFRING_GPA_APER_EN, 1) |
153 REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,
154 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
155 REG_SET_FIELD(tmp, BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL,
156 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
157
158 WREG32_SOC15(NBIO, 0,
159 regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
160 lower_32_bits(adev->doorbell.base));
161 WREG32_SOC15(NBIO, 0,
162 regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
163 upper_32_bits(adev->doorbell.base));
164 }
165
166 WREG32_SOC15(NBIO, 0, regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
167}
168
169
170static void nbio_v7_11_ih_doorbell_range(struct amdgpu_device *adev,
171 bool use_doorbell, int doorbell_index)
172{
173 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE);
174
175 if (use_doorbell) {
176 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
177 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
178 doorbell_index);
179 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
180 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
181 2);
182 } else {
183 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
184 GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
185 0);
186 }
187
188 WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE,
189 ih_doorbell_range);
190}
191
192static void nbio_v7_11_ih_control(struct amdgpu_device *adev)
193{
194 u32 interrupt_cntl;
195
196 /* setup interrupt control */
197 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2,
198 adev->dummy_page_addr >> 8);
199
200 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);
201 /*
202 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
203 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
204 */
205 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
206 IH_DUMMY_RD_OVERRIDE, 0);
207
208 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
209 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
210 IH_REQ_NONSNOOP_EN, 0);
211
212 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl);
213}
214
215static u32 nbio_v7_11_get_hdp_flush_req_offset(struct amdgpu_device *adev)
216{
217 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_REQ);
218}
219
220static u32 nbio_v7_11_get_hdp_flush_done_offset(struct amdgpu_device *adev)
221{
222 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_DONE);
223}
224
225static u32 nbio_v7_11_get_pcie_index_offset(struct amdgpu_device *adev)
226{
227 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_INDEX2);
228}
229
230static u32 nbio_v7_11_get_pcie_data_offset(struct amdgpu_device *adev)
231{
232 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_DATA2);
233}
234
235static u32 nbio_v7_11_get_pcie_port_index_offset(struct amdgpu_device *adev)
236{
237 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_RSMU_INDEX);
238}
239
240static u32 nbio_v7_11_get_pcie_port_data_offset(struct amdgpu_device *adev)
241{
242 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_RSMU_DATA);
243}
244
245const struct nbio_hdp_flush_reg nbio_v7_11_hdp_flush_reg = {
246 .ref_and_mask_cp0 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK,
247 .ref_and_mask_cp1 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK,
248 .ref_and_mask_cp2 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK,
249 .ref_and_mask_cp3 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK,
250 .ref_and_mask_cp4 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK,
251 .ref_and_mask_cp5 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK,
252 .ref_and_mask_cp6 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK,
253 .ref_and_mask_cp7 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK,
254 .ref_and_mask_cp8 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK,
255 .ref_and_mask_cp9 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK,
256 .ref_and_mask_sdma0 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
257 .ref_and_mask_sdma1 = BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
258};
259
260static void nbio_v7_11_init_registers(struct amdgpu_device *adev)
261{
262 uint32_t def, data;
263
264 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);
265 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
266 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
267 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
268 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
269
270 if (def != data)
271 WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);
272
273}
274
275static void nbio_v7_11_update_medium_grain_clock_gating(struct amdgpu_device *adev,
276 bool enable)
277{
278 uint32_t def, data;
279
280 if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
281 return;
282
283 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);
284 if (enable) {
285 data |= (BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
286 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
287 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
288 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
289 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
290 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
291 } else {
292 data &= ~(BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
293 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
294 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
295 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
296 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
297 BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
298 }
299
300 if (def != data)
301 WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL, data);
302}
303
304static void nbio_v7_11_update_medium_grain_light_sleep(struct amdgpu_device *adev,
305 bool enable)
306{
307 uint32_t def, data;
308
309 if (!(adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
310 return;
311
312 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);
313 if (enable)
314 data |= BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
315 else
316 data &= ~BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
317
318 if (def != data)
319 WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2, data);
320
321 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1);
322 if (enable) {
323 data |= (BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
324 BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
325 } else {
326 data &= ~(BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
327 BIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
328 }
329
330 if (def != data)
331 WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_TX_POWER_CTRL_1, data);
332}
333
334static void nbio_v7_11_get_clockgating_state(struct amdgpu_device *adev,
335 u64 *flags)
336{
337 uint32_t data;
338
339 /* AMD_CG_SUPPORT_BIF_MGCG */
340 data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL);
341 if (data & BIF_BIF256_CI256_RC3X4_USB4_CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
342 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
343
344 /* AMD_CG_SUPPORT_BIF_LS */
345 data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2);
346 if (data & BIF_BIF256_CI256_RC3X4_USB4_PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
347 *flags |= AMD_CG_SUPPORT_BIF_LS;
348}
349
350const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
351 .get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset,
352 .get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset,
353 .get_pcie_index_offset = nbio_v7_11_get_pcie_index_offset,
354 .get_pcie_data_offset = nbio_v7_11_get_pcie_data_offset,
355 .get_pcie_port_index_offset = nbio_v7_11_get_pcie_port_index_offset,
356 .get_pcie_port_data_offset = nbio_v7_11_get_pcie_port_data_offset,
357 .get_rev_id = nbio_v7_11_get_rev_id,
358 .mc_access_enable = nbio_v7_11_mc_access_enable,
359 .get_memsize = nbio_v7_11_get_memsize,
360 .sdma_doorbell_range = nbio_v7_11_sdma_doorbell_range,
361 .vcn_doorbell_range = nbio_v7_11_vcn_doorbell_range,
362 .vpe_doorbell_range = nbio_v7_11_vpe_doorbell_range,
363 .enable_doorbell_aperture = nbio_v7_11_enable_doorbell_aperture,
364 .enable_doorbell_selfring_aperture = nbio_v7_11_enable_doorbell_selfring_aperture,
365 .ih_doorbell_range = nbio_v7_11_ih_doorbell_range,
366 .update_medium_grain_clock_gating = nbio_v7_11_update_medium_grain_clock_gating,
367 .update_medium_grain_light_sleep = nbio_v7_11_update_medium_grain_light_sleep,
368 .get_clockgating_state = nbio_v7_11_get_clockgating_state,
369 .ih_control = nbio_v7_11_ih_control,
370 .init_registers = nbio_v7_11_init_registers,
371 .remap_hdp_registers = nbio_v7_11_remap_hdp_registers,
372};