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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29
30#include "amdgpu.h"
31#include "amdgpu_gfx.h"
32#include "amdgpu_ring.h"
33#include "vi.h"
34#include "vi_structs.h"
35#include "vid.h"
36#include "amdgpu_ucode.h"
37#include "amdgpu_atombios.h"
38#include "atombios_i2c.h"
39#include "clearstate_vi.h"
40
41#include "gmc/gmc_8_2_d.h"
42#include "gmc/gmc_8_2_sh_mask.h"
43
44#include "oss/oss_3_0_d.h"
45#include "oss/oss_3_0_sh_mask.h"
46
47#include "bif/bif_5_0_d.h"
48#include "bif/bif_5_0_sh_mask.h"
49#include "gca/gfx_8_0_d.h"
50#include "gca/gfx_8_0_enum.h"
51#include "gca/gfx_8_0_sh_mask.h"
52
53#include "dce/dce_10_0_d.h"
54#include "dce/dce_10_0_sh_mask.h"
55
56#include "smu/smu_7_1_3_d.h"
57
58#include "ivsrcid/ivsrcid_vislands30.h"
59
60#define GFX8_NUM_GFX_RINGS 1
61#define GFX8_MEC_HPD_SIZE 4096
62
63#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
67
68#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
69#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
70#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
71#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
72#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
73#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
74#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
75#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
76#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
77
78#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
79#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
80#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
81#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
82#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
83#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
84
85/* BPM SERDES CMD */
86#define SET_BPM_SERDES_CMD 1
87#define CLE_BPM_SERDES_CMD 0
88
89/* BPM Register Address*/
90enum {
91 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
92 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
93 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
94 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
95 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
96 BPM_REG_FGCG_MAX
97};
98
99#define RLC_FormatDirectRegListLength 14
100
101MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
102MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
103MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
104MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
105MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
106MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
107
108MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
109MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
110MODULE_FIRMWARE("amdgpu/stoney_me.bin");
111MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
112MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
113
114MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
115MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
116MODULE_FIRMWARE("amdgpu/tonga_me.bin");
117MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
118MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
119MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
120
121MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
122MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
123MODULE_FIRMWARE("amdgpu/topaz_me.bin");
124MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
125MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
126
127MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
128MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
129MODULE_FIRMWARE("amdgpu/fiji_me.bin");
130MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
131MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
132MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
133
134MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
135MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
136MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
137MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
138MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
139MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
140MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
141MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
142MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
143MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
144MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
145
146MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
147MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
148MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
149MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
150MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
151MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
152MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
153MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
154MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
155MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
156MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
157
158MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
159MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
160MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
161MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
162MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
163MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
164MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
165MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
166MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
167MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
168MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
169
170MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
171MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
172MODULE_FIRMWARE("amdgpu/vegam_me.bin");
173MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
174MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
175MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
176
177static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
178{
179 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
180 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
181 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
182 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
183 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
184 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
185 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
186 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
187 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
188 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
189 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
190 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
191 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
192 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
193 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
194 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
195};
196
197static const u32 golden_settings_tonga_a11[] =
198{
199 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
200 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
201 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
202 mmGB_GPU_ID, 0x0000000f, 0x00000000,
203 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
204 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
205 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
206 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
207 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
208 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
209 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
210 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
211 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
212 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
213 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
214 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
215};
216
217static const u32 tonga_golden_common_all[] =
218{
219 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
221 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
222 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
223 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
224 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
225 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
226 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
227};
228
229static const u32 tonga_mgcg_cgcg_init[] =
230{
231 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
232 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
233 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
234 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
235 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
236 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
237 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
238 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
239 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
240 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
241 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
242 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
243 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
244 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
245 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
246 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
247 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
248 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
249 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
250 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
251 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
252 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
253 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
254 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
255 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
256 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
257 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
258 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
260 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
261 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
262 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
265 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
270 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
275 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
280 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
285 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
290 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
295 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
298 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
299 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
300 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
301 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
302 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
303 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
304 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
305 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
306};
307
308static const u32 golden_settings_vegam_a11[] =
309{
310 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
311 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
312 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
313 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
314 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
315 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
317 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
318 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
319 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
320 mmSQ_CONFIG, 0x07f80000, 0x01180000,
321 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
322 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
323 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
324 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
325 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
326 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
327};
328
329static const u32 vegam_golden_common_all[] =
330{
331 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
333 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
335 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
336 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
337};
338
339static const u32 golden_settings_polaris11_a11[] =
340{
341 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
342 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
343 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
344 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
345 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
346 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
347 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
348 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
351 mmSQ_CONFIG, 0x07f80000, 0x01180000,
352 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
353 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
354 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
355 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
356 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
357 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
358};
359
360static const u32 polaris11_golden_common_all[] =
361{
362 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
363 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
364 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
368};
369
370static const u32 golden_settings_polaris10_a11[] =
371{
372 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
373 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
374 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
375 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
380 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
381 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
382 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
383 mmSQ_CONFIG, 0x07f80000, 0x07180000,
384 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
385 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
386 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
387 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
388 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
389};
390
391static const u32 polaris10_golden_common_all[] =
392{
393 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
394 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
395 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
396 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
397 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
398 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
399 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
400 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
401};
402
403static const u32 fiji_golden_common_all[] =
404{
405 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
406 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
407 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
408 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
409 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
410 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
411 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
412 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
413 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
414 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
415};
416
417static const u32 golden_settings_fiji_a10[] =
418{
419 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
420 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
422 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
423 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
424 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
426 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
427 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
428 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
429 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
430};
431
432static const u32 fiji_mgcg_cgcg_init[] =
433{
434 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
435 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
436 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
441 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
443 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
445 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
452 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
453 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
454 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
455 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
456 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
458 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
459 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
460 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
461 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
464 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
465 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
466 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
467 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
468 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
469};
470
471static const u32 golden_settings_iceland_a11[] =
472{
473 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
474 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
475 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
476 mmGB_GPU_ID, 0x0000000f, 0x00000000,
477 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
478 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
479 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
480 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
481 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
482 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
483 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
484 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
485 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
486 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
487 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
488 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
489};
490
491static const u32 iceland_golden_common_all[] =
492{
493 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
494 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
495 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
496 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
497 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
498 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
499 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
500 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
501};
502
503static const u32 iceland_mgcg_cgcg_init[] =
504{
505 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
506 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
507 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
508 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
509 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
510 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
511 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
512 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
513 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
514 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
515 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
516 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
517 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
518 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
519 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
520 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
521 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
522 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
523 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
524 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
525 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
526 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
527 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
528 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
529 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
530 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
531 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
532 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
534 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
535 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
539 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
544 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
549 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
554 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
559 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
562 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
563 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
564 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
565 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
566 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
567 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
568 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
569};
570
571static const u32 cz_golden_settings_a11[] =
572{
573 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
574 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
575 mmGB_GPU_ID, 0x0000000f, 0x00000000,
576 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
577 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
578 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
579 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
580 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
581 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
582 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
583 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
584 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
585};
586
587static const u32 cz_golden_common_all[] =
588{
589 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
590 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
591 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
592 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
593 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
594 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
595 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
596 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
597};
598
599static const u32 cz_mgcg_cgcg_init[] =
600{
601 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
602 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
603 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
604 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
605 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
606 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
607 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
608 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
609 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
610 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
611 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
612 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
613 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
614 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
615 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
616 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
617 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
618 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
619 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
620 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
621 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
622 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
623 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
624 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
625 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
626 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
627 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
628 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
630 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
631 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
632 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
635 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
640 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
645 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
650 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
655 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
660 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
665 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
668 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
669 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
670 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
671 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
672 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
673 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
674 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
675 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
676};
677
678static const u32 stoney_golden_settings_a11[] =
679{
680 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
681 mmGB_GPU_ID, 0x0000000f, 0x00000000,
682 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
683 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
684 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
685 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
686 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
687 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
688 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
689 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
690};
691
692static const u32 stoney_golden_common_all[] =
693{
694 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
695 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
696 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
697 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
698 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
699 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
700 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
701 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
702};
703
704static const u32 stoney_mgcg_cgcg_init[] =
705{
706 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
707 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
708 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
710 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
711};
712
713
714static const char * const sq_edc_source_names[] = {
715 "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
716 "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
717 "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
718 "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
719 "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
720 "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
721 "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
722};
723
724static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
725static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
726static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
727static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
728static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
729static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
730static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
731static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
732
733#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x0000007fL
734#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x00000000L
735
736static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
737{
738 uint32_t data;
739
740 switch (adev->asic_type) {
741 case CHIP_TOPAZ:
742 amdgpu_device_program_register_sequence(adev,
743 iceland_mgcg_cgcg_init,
744 ARRAY_SIZE(iceland_mgcg_cgcg_init));
745 amdgpu_device_program_register_sequence(adev,
746 golden_settings_iceland_a11,
747 ARRAY_SIZE(golden_settings_iceland_a11));
748 amdgpu_device_program_register_sequence(adev,
749 iceland_golden_common_all,
750 ARRAY_SIZE(iceland_golden_common_all));
751 break;
752 case CHIP_FIJI:
753 amdgpu_device_program_register_sequence(adev,
754 fiji_mgcg_cgcg_init,
755 ARRAY_SIZE(fiji_mgcg_cgcg_init));
756 amdgpu_device_program_register_sequence(adev,
757 golden_settings_fiji_a10,
758 ARRAY_SIZE(golden_settings_fiji_a10));
759 amdgpu_device_program_register_sequence(adev,
760 fiji_golden_common_all,
761 ARRAY_SIZE(fiji_golden_common_all));
762 break;
763
764 case CHIP_TONGA:
765 amdgpu_device_program_register_sequence(adev,
766 tonga_mgcg_cgcg_init,
767 ARRAY_SIZE(tonga_mgcg_cgcg_init));
768 amdgpu_device_program_register_sequence(adev,
769 golden_settings_tonga_a11,
770 ARRAY_SIZE(golden_settings_tonga_a11));
771 amdgpu_device_program_register_sequence(adev,
772 tonga_golden_common_all,
773 ARRAY_SIZE(tonga_golden_common_all));
774 break;
775 case CHIP_VEGAM:
776 amdgpu_device_program_register_sequence(adev,
777 golden_settings_vegam_a11,
778 ARRAY_SIZE(golden_settings_vegam_a11));
779 amdgpu_device_program_register_sequence(adev,
780 vegam_golden_common_all,
781 ARRAY_SIZE(vegam_golden_common_all));
782 break;
783 case CHIP_POLARIS11:
784 case CHIP_POLARIS12:
785 amdgpu_device_program_register_sequence(adev,
786 golden_settings_polaris11_a11,
787 ARRAY_SIZE(golden_settings_polaris11_a11));
788 amdgpu_device_program_register_sequence(adev,
789 polaris11_golden_common_all,
790 ARRAY_SIZE(polaris11_golden_common_all));
791 break;
792 case CHIP_POLARIS10:
793 amdgpu_device_program_register_sequence(adev,
794 golden_settings_polaris10_a11,
795 ARRAY_SIZE(golden_settings_polaris10_a11));
796 amdgpu_device_program_register_sequence(adev,
797 polaris10_golden_common_all,
798 ARRAY_SIZE(polaris10_golden_common_all));
799 data = RREG32_SMC(ixCG_ACLK_CNTL);
800 data &= ~CG_ACLK_CNTL__ACLK_DIVIDER_MASK;
801 data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;
802 WREG32_SMC(ixCG_ACLK_CNTL, data);
803 if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&
804 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
805 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
806 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {
807 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
808 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
809 }
810 break;
811 case CHIP_CARRIZO:
812 amdgpu_device_program_register_sequence(adev,
813 cz_mgcg_cgcg_init,
814 ARRAY_SIZE(cz_mgcg_cgcg_init));
815 amdgpu_device_program_register_sequence(adev,
816 cz_golden_settings_a11,
817 ARRAY_SIZE(cz_golden_settings_a11));
818 amdgpu_device_program_register_sequence(adev,
819 cz_golden_common_all,
820 ARRAY_SIZE(cz_golden_common_all));
821 break;
822 case CHIP_STONEY:
823 amdgpu_device_program_register_sequence(adev,
824 stoney_mgcg_cgcg_init,
825 ARRAY_SIZE(stoney_mgcg_cgcg_init));
826 amdgpu_device_program_register_sequence(adev,
827 stoney_golden_settings_a11,
828 ARRAY_SIZE(stoney_golden_settings_a11));
829 amdgpu_device_program_register_sequence(adev,
830 stoney_golden_common_all,
831 ARRAY_SIZE(stoney_golden_common_all));
832 break;
833 default:
834 break;
835 }
836}
837
838static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
839{
840 struct amdgpu_device *adev = ring->adev;
841 uint32_t tmp = 0;
842 unsigned i;
843 int r;
844
845 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
846 r = amdgpu_ring_alloc(ring, 3);
847 if (r)
848 return r;
849
850 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START);
852 amdgpu_ring_write(ring, 0xDEADBEEF);
853 amdgpu_ring_commit(ring);
854
855 for (i = 0; i < adev->usec_timeout; i++) {
856 tmp = RREG32(mmSCRATCH_REG0);
857 if (tmp == 0xDEADBEEF)
858 break;
859 udelay(1);
860 }
861
862 if (i >= adev->usec_timeout)
863 r = -ETIMEDOUT;
864
865 return r;
866}
867
868static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
869{
870 struct amdgpu_device *adev = ring->adev;
871 struct amdgpu_ib ib;
872 struct dma_fence *f = NULL;
873
874 unsigned int index;
875 uint64_t gpu_addr;
876 uint32_t tmp;
877 long r;
878
879 r = amdgpu_device_wb_get(adev, &index);
880 if (r)
881 return r;
882
883 gpu_addr = adev->wb.gpu_addr + (index * 4);
884 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
885 memset(&ib, 0, sizeof(ib));
886
887 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
888 if (r)
889 goto err1;
890
891 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
893 ib.ptr[2] = lower_32_bits(gpu_addr);
894 ib.ptr[3] = upper_32_bits(gpu_addr);
895 ib.ptr[4] = 0xDEADBEEF;
896 ib.length_dw = 5;
897
898 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
899 if (r)
900 goto err2;
901
902 r = dma_fence_wait_timeout(f, false, timeout);
903 if (r == 0) {
904 r = -ETIMEDOUT;
905 goto err2;
906 } else if (r < 0) {
907 goto err2;
908 }
909
910 tmp = adev->wb.wb[index];
911 if (tmp == 0xDEADBEEF)
912 r = 0;
913 else
914 r = -EINVAL;
915
916err2:
917 amdgpu_ib_free(adev, &ib, NULL);
918 dma_fence_put(f);
919err1:
920 amdgpu_device_wb_free(adev, index);
921 return r;
922}
923
924
925static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
926{
927 amdgpu_ucode_release(&adev->gfx.pfp_fw);
928 amdgpu_ucode_release(&adev->gfx.me_fw);
929 amdgpu_ucode_release(&adev->gfx.ce_fw);
930 amdgpu_ucode_release(&adev->gfx.rlc_fw);
931 amdgpu_ucode_release(&adev->gfx.mec_fw);
932 if ((adev->asic_type != CHIP_STONEY) &&
933 (adev->asic_type != CHIP_TOPAZ))
934 amdgpu_ucode_release(&adev->gfx.mec2_fw);
935
936 kfree(adev->gfx.rlc.register_list_format);
937}
938
939static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
940{
941 const char *chip_name;
942 char fw_name[30];
943 int err;
944 struct amdgpu_firmware_info *info = NULL;
945 const struct common_firmware_header *header = NULL;
946 const struct gfx_firmware_header_v1_0 *cp_hdr;
947 const struct rlc_firmware_header_v2_0 *rlc_hdr;
948 unsigned int *tmp = NULL, i;
949
950 DRM_DEBUG("\n");
951
952 switch (adev->asic_type) {
953 case CHIP_TOPAZ:
954 chip_name = "topaz";
955 break;
956 case CHIP_TONGA:
957 chip_name = "tonga";
958 break;
959 case CHIP_CARRIZO:
960 chip_name = "carrizo";
961 break;
962 case CHIP_FIJI:
963 chip_name = "fiji";
964 break;
965 case CHIP_STONEY:
966 chip_name = "stoney";
967 break;
968 case CHIP_POLARIS10:
969 chip_name = "polaris10";
970 break;
971 case CHIP_POLARIS11:
972 chip_name = "polaris11";
973 break;
974 case CHIP_POLARIS12:
975 chip_name = "polaris12";
976 break;
977 case CHIP_VEGAM:
978 chip_name = "vegam";
979 break;
980 default:
981 BUG();
982 }
983
984 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
985 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
986 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
987 if (err == -ENODEV) {
988 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
989 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
990 }
991 } else {
992 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
993 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
994 }
995 if (err)
996 goto out;
997 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
998 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
999 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1000
1001 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1002 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1003 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
1004 if (err == -ENODEV) {
1005 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1006 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
1007 }
1008 } else {
1009 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1010 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
1011 }
1012 if (err)
1013 goto out;
1014 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1015 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1016
1017 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1018
1019 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1020 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1021 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
1022 if (err == -ENODEV) {
1023 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1024 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
1025 }
1026 } else {
1027 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1028 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
1029 }
1030 if (err)
1031 goto out;
1032 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1033 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1034 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1035
1036 /*
1037 * Support for MCBP/Virtualization in combination with chained IBs is
1038 * formal released on feature version #46
1039 */
1040 if (adev->gfx.ce_feature_version >= 46 &&
1041 adev->gfx.pfp_feature_version >= 46) {
1042 adev->virt.chained_ib_support = true;
1043 DRM_INFO("Chained IB support enabled!\n");
1044 } else
1045 adev->virt.chained_ib_support = false;
1046
1047 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1048 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
1049 if (err)
1050 goto out;
1051 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1052 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1053 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1054
1055 adev->gfx.rlc.save_and_restore_offset =
1056 le32_to_cpu(rlc_hdr->save_and_restore_offset);
1057 adev->gfx.rlc.clear_state_descriptor_offset =
1058 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1059 adev->gfx.rlc.avail_scratch_ram_locations =
1060 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1061 adev->gfx.rlc.reg_restore_list_size =
1062 le32_to_cpu(rlc_hdr->reg_restore_list_size);
1063 adev->gfx.rlc.reg_list_format_start =
1064 le32_to_cpu(rlc_hdr->reg_list_format_start);
1065 adev->gfx.rlc.reg_list_format_separate_start =
1066 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1067 adev->gfx.rlc.starting_offsets_start =
1068 le32_to_cpu(rlc_hdr->starting_offsets_start);
1069 adev->gfx.rlc.reg_list_format_size_bytes =
1070 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1071 adev->gfx.rlc.reg_list_size_bytes =
1072 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1073
1074 adev->gfx.rlc.register_list_format =
1075 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1076 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1077
1078 if (!adev->gfx.rlc.register_list_format) {
1079 err = -ENOMEM;
1080 goto out;
1081 }
1082
1083 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1084 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1085 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1086 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1087
1088 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1089
1090 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1091 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1092 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1093 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1094
1095 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1096 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1097 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
1098 if (err == -ENODEV) {
1099 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1100 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
1101 }
1102 } else {
1103 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1104 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
1105 }
1106 if (err)
1107 goto out;
1108 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1109 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1110 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1111
1112 if ((adev->asic_type != CHIP_STONEY) &&
1113 (adev->asic_type != CHIP_TOPAZ)) {
1114 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1115 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1116 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
1117 if (err == -ENODEV) {
1118 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1119 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
1120 }
1121 } else {
1122 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1123 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
1124 }
1125 if (!err) {
1126 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1127 adev->gfx.mec2_fw->data;
1128 adev->gfx.mec2_fw_version =
1129 le32_to_cpu(cp_hdr->header.ucode_version);
1130 adev->gfx.mec2_feature_version =
1131 le32_to_cpu(cp_hdr->ucode_feature_version);
1132 } else {
1133 err = 0;
1134 adev->gfx.mec2_fw = NULL;
1135 }
1136 }
1137
1138 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1139 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1140 info->fw = adev->gfx.pfp_fw;
1141 header = (const struct common_firmware_header *)info->fw->data;
1142 adev->firmware.fw_size +=
1143 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1144
1145 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1146 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1147 info->fw = adev->gfx.me_fw;
1148 header = (const struct common_firmware_header *)info->fw->data;
1149 adev->firmware.fw_size +=
1150 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1151
1152 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1153 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1154 info->fw = adev->gfx.ce_fw;
1155 header = (const struct common_firmware_header *)info->fw->data;
1156 adev->firmware.fw_size +=
1157 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1158
1159 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1160 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1161 info->fw = adev->gfx.rlc_fw;
1162 header = (const struct common_firmware_header *)info->fw->data;
1163 adev->firmware.fw_size +=
1164 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1165
1166 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1167 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1168 info->fw = adev->gfx.mec_fw;
1169 header = (const struct common_firmware_header *)info->fw->data;
1170 adev->firmware.fw_size +=
1171 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1172
1173 /* we need account JT in */
1174 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1175 adev->firmware.fw_size +=
1176 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1177
1178 if (amdgpu_sriov_vf(adev)) {
1179 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1180 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1181 info->fw = adev->gfx.mec_fw;
1182 adev->firmware.fw_size +=
1183 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1184 }
1185
1186 if (adev->gfx.mec2_fw) {
1187 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1188 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1189 info->fw = adev->gfx.mec2_fw;
1190 header = (const struct common_firmware_header *)info->fw->data;
1191 adev->firmware.fw_size +=
1192 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1193 }
1194
1195out:
1196 if (err) {
1197 dev_err(adev->dev,
1198 "gfx8: Failed to load firmware \"%s\"\n",
1199 fw_name);
1200 amdgpu_ucode_release(&adev->gfx.pfp_fw);
1201 amdgpu_ucode_release(&adev->gfx.me_fw);
1202 amdgpu_ucode_release(&adev->gfx.ce_fw);
1203 amdgpu_ucode_release(&adev->gfx.rlc_fw);
1204 amdgpu_ucode_release(&adev->gfx.mec_fw);
1205 amdgpu_ucode_release(&adev->gfx.mec2_fw);
1206 }
1207 return err;
1208}
1209
1210static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1211 volatile u32 *buffer)
1212{
1213 u32 count = 0, i;
1214 const struct cs_section_def *sect = NULL;
1215 const struct cs_extent_def *ext = NULL;
1216
1217 if (adev->gfx.rlc.cs_data == NULL)
1218 return;
1219 if (buffer == NULL)
1220 return;
1221
1222 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1223 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1224
1225 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1226 buffer[count++] = cpu_to_le32(0x80000000);
1227 buffer[count++] = cpu_to_le32(0x80000000);
1228
1229 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1230 for (ext = sect->section; ext->extent != NULL; ++ext) {
1231 if (sect->id == SECT_CONTEXT) {
1232 buffer[count++] =
1233 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1234 buffer[count++] = cpu_to_le32(ext->reg_index -
1235 PACKET3_SET_CONTEXT_REG_START);
1236 for (i = 0; i < ext->reg_count; i++)
1237 buffer[count++] = cpu_to_le32(ext->extent[i]);
1238 } else {
1239 return;
1240 }
1241 }
1242 }
1243
1244 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1245 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1246 PACKET3_SET_CONTEXT_REG_START);
1247 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1248 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1249
1250 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1251 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1252
1253 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1254 buffer[count++] = cpu_to_le32(0);
1255}
1256
1257static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1258{
1259 if (adev->asic_type == CHIP_CARRIZO)
1260 return 5;
1261 else
1262 return 4;
1263}
1264
1265static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1266{
1267 const struct cs_section_def *cs_data;
1268 int r;
1269
1270 adev->gfx.rlc.cs_data = vi_cs_data;
1271
1272 cs_data = adev->gfx.rlc.cs_data;
1273
1274 if (cs_data) {
1275 /* init clear state block */
1276 r = amdgpu_gfx_rlc_init_csb(adev);
1277 if (r)
1278 return r;
1279 }
1280
1281 if ((adev->asic_type == CHIP_CARRIZO) ||
1282 (adev->asic_type == CHIP_STONEY)) {
1283 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1284 r = amdgpu_gfx_rlc_init_cpt(adev);
1285 if (r)
1286 return r;
1287 }
1288
1289 /* init spm vmid with 0xf */
1290 if (adev->gfx.rlc.funcs->update_spm_vmid)
1291 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1292
1293 return 0;
1294}
1295
1296static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1297{
1298 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1299}
1300
1301static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1302{
1303 int r;
1304 u32 *hpd;
1305 size_t mec_hpd_size;
1306
1307 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1308
1309 /* take ownership of the relevant compute queues */
1310 amdgpu_gfx_compute_queue_acquire(adev);
1311
1312 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1313 if (mec_hpd_size) {
1314 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1315 AMDGPU_GEM_DOMAIN_VRAM |
1316 AMDGPU_GEM_DOMAIN_GTT,
1317 &adev->gfx.mec.hpd_eop_obj,
1318 &adev->gfx.mec.hpd_eop_gpu_addr,
1319 (void **)&hpd);
1320 if (r) {
1321 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1322 return r;
1323 }
1324
1325 memset(hpd, 0, mec_hpd_size);
1326
1327 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1328 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1329 }
1330
1331 return 0;
1332}
1333
1334static const u32 vgpr_init_compute_shader[] =
1335{
1336 0x7e000209, 0x7e020208,
1337 0x7e040207, 0x7e060206,
1338 0x7e080205, 0x7e0a0204,
1339 0x7e0c0203, 0x7e0e0202,
1340 0x7e100201, 0x7e120200,
1341 0x7e140209, 0x7e160208,
1342 0x7e180207, 0x7e1a0206,
1343 0x7e1c0205, 0x7e1e0204,
1344 0x7e200203, 0x7e220202,
1345 0x7e240201, 0x7e260200,
1346 0x7e280209, 0x7e2a0208,
1347 0x7e2c0207, 0x7e2e0206,
1348 0x7e300205, 0x7e320204,
1349 0x7e340203, 0x7e360202,
1350 0x7e380201, 0x7e3a0200,
1351 0x7e3c0209, 0x7e3e0208,
1352 0x7e400207, 0x7e420206,
1353 0x7e440205, 0x7e460204,
1354 0x7e480203, 0x7e4a0202,
1355 0x7e4c0201, 0x7e4e0200,
1356 0x7e500209, 0x7e520208,
1357 0x7e540207, 0x7e560206,
1358 0x7e580205, 0x7e5a0204,
1359 0x7e5c0203, 0x7e5e0202,
1360 0x7e600201, 0x7e620200,
1361 0x7e640209, 0x7e660208,
1362 0x7e680207, 0x7e6a0206,
1363 0x7e6c0205, 0x7e6e0204,
1364 0x7e700203, 0x7e720202,
1365 0x7e740201, 0x7e760200,
1366 0x7e780209, 0x7e7a0208,
1367 0x7e7c0207, 0x7e7e0206,
1368 0xbf8a0000, 0xbf810000,
1369};
1370
1371static const u32 sgpr_init_compute_shader[] =
1372{
1373 0xbe8a0100, 0xbe8c0102,
1374 0xbe8e0104, 0xbe900106,
1375 0xbe920108, 0xbe940100,
1376 0xbe960102, 0xbe980104,
1377 0xbe9a0106, 0xbe9c0108,
1378 0xbe9e0100, 0xbea00102,
1379 0xbea20104, 0xbea40106,
1380 0xbea60108, 0xbea80100,
1381 0xbeaa0102, 0xbeac0104,
1382 0xbeae0106, 0xbeb00108,
1383 0xbeb20100, 0xbeb40102,
1384 0xbeb60104, 0xbeb80106,
1385 0xbeba0108, 0xbebc0100,
1386 0xbebe0102, 0xbec00104,
1387 0xbec20106, 0xbec40108,
1388 0xbec60100, 0xbec80102,
1389 0xbee60004, 0xbee70005,
1390 0xbeea0006, 0xbeeb0007,
1391 0xbee80008, 0xbee90009,
1392 0xbefc0000, 0xbf8a0000,
1393 0xbf810000, 0x00000000,
1394};
1395
1396static const u32 vgpr_init_regs[] =
1397{
1398 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1399 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1400 mmCOMPUTE_NUM_THREAD_X, 256*4,
1401 mmCOMPUTE_NUM_THREAD_Y, 1,
1402 mmCOMPUTE_NUM_THREAD_Z, 1,
1403 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1404 mmCOMPUTE_PGM_RSRC2, 20,
1405 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1406 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1407 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1408 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1409 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1410 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1411 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1412 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1413 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1414 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1415};
1416
1417static const u32 sgpr1_init_regs[] =
1418{
1419 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1420 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1421 mmCOMPUTE_NUM_THREAD_X, 256*5,
1422 mmCOMPUTE_NUM_THREAD_Y, 1,
1423 mmCOMPUTE_NUM_THREAD_Z, 1,
1424 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1425 mmCOMPUTE_PGM_RSRC2, 20,
1426 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1427 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1428 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1429 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1430 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1431 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1432 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1433 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1434 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1435 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1436};
1437
1438static const u32 sgpr2_init_regs[] =
1439{
1440 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1441 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1442 mmCOMPUTE_NUM_THREAD_X, 256*5,
1443 mmCOMPUTE_NUM_THREAD_Y, 1,
1444 mmCOMPUTE_NUM_THREAD_Z, 1,
1445 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1446 mmCOMPUTE_PGM_RSRC2, 20,
1447 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1448 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1449 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1450 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1451 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1452 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1453 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1454 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1455 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1456 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1457};
1458
1459static const u32 sec_ded_counter_registers[] =
1460{
1461 mmCPC_EDC_ATC_CNT,
1462 mmCPC_EDC_SCRATCH_CNT,
1463 mmCPC_EDC_UCODE_CNT,
1464 mmCPF_EDC_ATC_CNT,
1465 mmCPF_EDC_ROQ_CNT,
1466 mmCPF_EDC_TAG_CNT,
1467 mmCPG_EDC_ATC_CNT,
1468 mmCPG_EDC_DMA_CNT,
1469 mmCPG_EDC_TAG_CNT,
1470 mmDC_EDC_CSINVOC_CNT,
1471 mmDC_EDC_RESTORE_CNT,
1472 mmDC_EDC_STATE_CNT,
1473 mmGDS_EDC_CNT,
1474 mmGDS_EDC_GRBM_CNT,
1475 mmGDS_EDC_OA_DED,
1476 mmSPI_EDC_CNT,
1477 mmSQC_ATC_EDC_GATCL1_CNT,
1478 mmSQC_EDC_CNT,
1479 mmSQ_EDC_DED_CNT,
1480 mmSQ_EDC_INFO,
1481 mmSQ_EDC_SEC_CNT,
1482 mmTCC_EDC_CNT,
1483 mmTCP_ATC_EDC_GATCL1_CNT,
1484 mmTCP_EDC_CNT,
1485 mmTD_EDC_CNT
1486};
1487
1488static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1489{
1490 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1491 struct amdgpu_ib ib;
1492 struct dma_fence *f = NULL;
1493 int r, i;
1494 u32 tmp;
1495 unsigned total_size, vgpr_offset, sgpr_offset;
1496 u64 gpu_addr;
1497
1498 /* only supported on CZ */
1499 if (adev->asic_type != CHIP_CARRIZO)
1500 return 0;
1501
1502 /* bail if the compute ring is not ready */
1503 if (!ring->sched.ready)
1504 return 0;
1505
1506 tmp = RREG32(mmGB_EDC_MODE);
1507 WREG32(mmGB_EDC_MODE, 0);
1508
1509 total_size =
1510 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1511 total_size +=
1512 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1513 total_size +=
1514 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1515 total_size = ALIGN(total_size, 256);
1516 vgpr_offset = total_size;
1517 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1518 sgpr_offset = total_size;
1519 total_size += sizeof(sgpr_init_compute_shader);
1520
1521 /* allocate an indirect buffer to put the commands in */
1522 memset(&ib, 0, sizeof(ib));
1523 r = amdgpu_ib_get(adev, NULL, total_size,
1524 AMDGPU_IB_POOL_DIRECT, &ib);
1525 if (r) {
1526 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1527 return r;
1528 }
1529
1530 /* load the compute shaders */
1531 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1532 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1533
1534 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1535 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1536
1537 /* init the ib length to 0 */
1538 ib.length_dw = 0;
1539
1540 /* VGPR */
1541 /* write the register state for the compute dispatch */
1542 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1543 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1544 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1545 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1546 }
1547 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1548 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1549 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1550 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1551 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1552 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1553
1554 /* write dispatch packet */
1555 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1556 ib.ptr[ib.length_dw++] = 8; /* x */
1557 ib.ptr[ib.length_dw++] = 1; /* y */
1558 ib.ptr[ib.length_dw++] = 1; /* z */
1559 ib.ptr[ib.length_dw++] =
1560 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1561
1562 /* write CS partial flush packet */
1563 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1564 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1565
1566 /* SGPR1 */
1567 /* write the register state for the compute dispatch */
1568 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1569 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1570 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1571 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1572 }
1573 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1574 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1575 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1576 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1577 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1578 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1579
1580 /* write dispatch packet */
1581 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1582 ib.ptr[ib.length_dw++] = 8; /* x */
1583 ib.ptr[ib.length_dw++] = 1; /* y */
1584 ib.ptr[ib.length_dw++] = 1; /* z */
1585 ib.ptr[ib.length_dw++] =
1586 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1587
1588 /* write CS partial flush packet */
1589 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1590 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1591
1592 /* SGPR2 */
1593 /* write the register state for the compute dispatch */
1594 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1595 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1596 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1597 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1598 }
1599 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1600 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1601 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1602 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1603 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1604 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1605
1606 /* write dispatch packet */
1607 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1608 ib.ptr[ib.length_dw++] = 8; /* x */
1609 ib.ptr[ib.length_dw++] = 1; /* y */
1610 ib.ptr[ib.length_dw++] = 1; /* z */
1611 ib.ptr[ib.length_dw++] =
1612 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1613
1614 /* write CS partial flush packet */
1615 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1616 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1617
1618 /* shedule the ib on the ring */
1619 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1620 if (r) {
1621 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1622 goto fail;
1623 }
1624
1625 /* wait for the GPU to finish processing the IB */
1626 r = dma_fence_wait(f, false);
1627 if (r) {
1628 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1629 goto fail;
1630 }
1631
1632 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1633 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1634 WREG32(mmGB_EDC_MODE, tmp);
1635
1636 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1637 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1638 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1639
1640
1641 /* read back registers to clear the counters */
1642 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1643 RREG32(sec_ded_counter_registers[i]);
1644
1645fail:
1646 amdgpu_ib_free(adev, &ib, NULL);
1647 dma_fence_put(f);
1648
1649 return r;
1650}
1651
1652static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1653{
1654 u32 gb_addr_config;
1655 u32 mc_arb_ramcfg;
1656 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1657 u32 tmp;
1658 int ret;
1659
1660 switch (adev->asic_type) {
1661 case CHIP_TOPAZ:
1662 adev->gfx.config.max_shader_engines = 1;
1663 adev->gfx.config.max_tile_pipes = 2;
1664 adev->gfx.config.max_cu_per_sh = 6;
1665 adev->gfx.config.max_sh_per_se = 1;
1666 adev->gfx.config.max_backends_per_se = 2;
1667 adev->gfx.config.max_texture_channel_caches = 2;
1668 adev->gfx.config.max_gprs = 256;
1669 adev->gfx.config.max_gs_threads = 32;
1670 adev->gfx.config.max_hw_contexts = 8;
1671
1672 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1673 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1674 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1675 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1676 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1677 break;
1678 case CHIP_FIJI:
1679 adev->gfx.config.max_shader_engines = 4;
1680 adev->gfx.config.max_tile_pipes = 16;
1681 adev->gfx.config.max_cu_per_sh = 16;
1682 adev->gfx.config.max_sh_per_se = 1;
1683 adev->gfx.config.max_backends_per_se = 4;
1684 adev->gfx.config.max_texture_channel_caches = 16;
1685 adev->gfx.config.max_gprs = 256;
1686 adev->gfx.config.max_gs_threads = 32;
1687 adev->gfx.config.max_hw_contexts = 8;
1688
1689 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1690 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1691 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1692 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1693 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1694 break;
1695 case CHIP_POLARIS11:
1696 case CHIP_POLARIS12:
1697 ret = amdgpu_atombios_get_gfx_info(adev);
1698 if (ret)
1699 return ret;
1700 adev->gfx.config.max_gprs = 256;
1701 adev->gfx.config.max_gs_threads = 32;
1702 adev->gfx.config.max_hw_contexts = 8;
1703
1704 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1705 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1706 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1707 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1708 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1709 break;
1710 case CHIP_POLARIS10:
1711 case CHIP_VEGAM:
1712 ret = amdgpu_atombios_get_gfx_info(adev);
1713 if (ret)
1714 return ret;
1715 adev->gfx.config.max_gprs = 256;
1716 adev->gfx.config.max_gs_threads = 32;
1717 adev->gfx.config.max_hw_contexts = 8;
1718
1719 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1720 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1721 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1722 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1723 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1724 break;
1725 case CHIP_TONGA:
1726 adev->gfx.config.max_shader_engines = 4;
1727 adev->gfx.config.max_tile_pipes = 8;
1728 adev->gfx.config.max_cu_per_sh = 8;
1729 adev->gfx.config.max_sh_per_se = 1;
1730 adev->gfx.config.max_backends_per_se = 2;
1731 adev->gfx.config.max_texture_channel_caches = 8;
1732 adev->gfx.config.max_gprs = 256;
1733 adev->gfx.config.max_gs_threads = 32;
1734 adev->gfx.config.max_hw_contexts = 8;
1735
1736 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1737 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1738 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1739 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1740 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1741 break;
1742 case CHIP_CARRIZO:
1743 adev->gfx.config.max_shader_engines = 1;
1744 adev->gfx.config.max_tile_pipes = 2;
1745 adev->gfx.config.max_sh_per_se = 1;
1746 adev->gfx.config.max_backends_per_se = 2;
1747 adev->gfx.config.max_cu_per_sh = 8;
1748 adev->gfx.config.max_texture_channel_caches = 2;
1749 adev->gfx.config.max_gprs = 256;
1750 adev->gfx.config.max_gs_threads = 32;
1751 adev->gfx.config.max_hw_contexts = 8;
1752
1753 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1754 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1755 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1756 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1757 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1758 break;
1759 case CHIP_STONEY:
1760 adev->gfx.config.max_shader_engines = 1;
1761 adev->gfx.config.max_tile_pipes = 2;
1762 adev->gfx.config.max_sh_per_se = 1;
1763 adev->gfx.config.max_backends_per_se = 1;
1764 adev->gfx.config.max_cu_per_sh = 3;
1765 adev->gfx.config.max_texture_channel_caches = 2;
1766 adev->gfx.config.max_gprs = 256;
1767 adev->gfx.config.max_gs_threads = 16;
1768 adev->gfx.config.max_hw_contexts = 8;
1769
1770 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1771 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1772 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1773 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1774 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1775 break;
1776 default:
1777 adev->gfx.config.max_shader_engines = 2;
1778 adev->gfx.config.max_tile_pipes = 4;
1779 adev->gfx.config.max_cu_per_sh = 2;
1780 adev->gfx.config.max_sh_per_se = 1;
1781 adev->gfx.config.max_backends_per_se = 2;
1782 adev->gfx.config.max_texture_channel_caches = 4;
1783 adev->gfx.config.max_gprs = 256;
1784 adev->gfx.config.max_gs_threads = 32;
1785 adev->gfx.config.max_hw_contexts = 8;
1786
1787 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1788 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1789 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1790 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1791 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1792 break;
1793 }
1794
1795 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1796 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1797
1798 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
1799 MC_ARB_RAMCFG, NOOFBANK);
1800 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
1801 MC_ARB_RAMCFG, NOOFRANKS);
1802
1803 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1804 adev->gfx.config.mem_max_burst_length_bytes = 256;
1805 if (adev->flags & AMD_IS_APU) {
1806 /* Get memory bank mapping mode. */
1807 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1808 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1809 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1810
1811 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1812 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1813 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1814
1815 /* Validate settings in case only one DIMM installed. */
1816 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1817 dimm00_addr_map = 0;
1818 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1819 dimm01_addr_map = 0;
1820 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1821 dimm10_addr_map = 0;
1822 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1823 dimm11_addr_map = 0;
1824
1825 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1826 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1827 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1828 adev->gfx.config.mem_row_size_in_kb = 2;
1829 else
1830 adev->gfx.config.mem_row_size_in_kb = 1;
1831 } else {
1832 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1833 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1834 if (adev->gfx.config.mem_row_size_in_kb > 4)
1835 adev->gfx.config.mem_row_size_in_kb = 4;
1836 }
1837
1838 adev->gfx.config.shader_engine_tile_size = 32;
1839 adev->gfx.config.num_gpus = 1;
1840 adev->gfx.config.multi_gpu_tile_size = 64;
1841
1842 /* fix up row size */
1843 switch (adev->gfx.config.mem_row_size_in_kb) {
1844 case 1:
1845 default:
1846 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1847 break;
1848 case 2:
1849 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1850 break;
1851 case 4:
1852 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1853 break;
1854 }
1855 adev->gfx.config.gb_addr_config = gb_addr_config;
1856
1857 return 0;
1858}
1859
1860static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1861 int mec, int pipe, int queue)
1862{
1863 int r;
1864 unsigned irq_type;
1865 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1866 unsigned int hw_prio;
1867
1868 ring = &adev->gfx.compute_ring[ring_id];
1869
1870 /* mec0 is me1 */
1871 ring->me = mec + 1;
1872 ring->pipe = pipe;
1873 ring->queue = queue;
1874
1875 ring->ring_obj = NULL;
1876 ring->use_doorbell = true;
1877 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1878 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1879 + (ring_id * GFX8_MEC_HPD_SIZE);
1880 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1881
1882 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1883 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1884 + ring->pipe;
1885
1886 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1887 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
1888 /* type-2 packets are deprecated on MEC, use type-3 instead */
1889 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1890 hw_prio, NULL);
1891 if (r)
1892 return r;
1893
1894
1895 return 0;
1896}
1897
1898static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1899
1900static int gfx_v8_0_sw_init(void *handle)
1901{
1902 int i, j, k, r, ring_id;
1903 struct amdgpu_ring *ring;
1904 struct amdgpu_kiq *kiq;
1905 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1906
1907 switch (adev->asic_type) {
1908 case CHIP_TONGA:
1909 case CHIP_CARRIZO:
1910 case CHIP_FIJI:
1911 case CHIP_POLARIS10:
1912 case CHIP_POLARIS11:
1913 case CHIP_POLARIS12:
1914 case CHIP_VEGAM:
1915 adev->gfx.mec.num_mec = 2;
1916 break;
1917 case CHIP_TOPAZ:
1918 case CHIP_STONEY:
1919 default:
1920 adev->gfx.mec.num_mec = 1;
1921 break;
1922 }
1923
1924 adev->gfx.mec.num_pipe_per_mec = 4;
1925 adev->gfx.mec.num_queue_per_pipe = 8;
1926
1927 /* EOP Event */
1928 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1929 if (r)
1930 return r;
1931
1932 /* Privileged reg */
1933 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1934 &adev->gfx.priv_reg_irq);
1935 if (r)
1936 return r;
1937
1938 /* Privileged inst */
1939 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1940 &adev->gfx.priv_inst_irq);
1941 if (r)
1942 return r;
1943
1944 /* Add CP EDC/ECC irq */
1945 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1946 &adev->gfx.cp_ecc_error_irq);
1947 if (r)
1948 return r;
1949
1950 /* SQ interrupts. */
1951 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
1952 &adev->gfx.sq_irq);
1953 if (r) {
1954 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
1955 return r;
1956 }
1957
1958 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
1959
1960 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1961
1962 r = gfx_v8_0_init_microcode(adev);
1963 if (r) {
1964 DRM_ERROR("Failed to load gfx firmware!\n");
1965 return r;
1966 }
1967
1968 r = adev->gfx.rlc.funcs->init(adev);
1969 if (r) {
1970 DRM_ERROR("Failed to init rlc BOs!\n");
1971 return r;
1972 }
1973
1974 r = gfx_v8_0_mec_init(adev);
1975 if (r) {
1976 DRM_ERROR("Failed to init MEC BOs!\n");
1977 return r;
1978 }
1979
1980 /* set up the gfx ring */
1981 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1982 ring = &adev->gfx.gfx_ring[i];
1983 ring->ring_obj = NULL;
1984 sprintf(ring->name, "gfx");
1985 /* no gfx doorbells on iceland */
1986 if (adev->asic_type != CHIP_TOPAZ) {
1987 ring->use_doorbell = true;
1988 ring->doorbell_index = adev->doorbell_index.gfx_ring0;
1989 }
1990
1991 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
1992 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
1993 AMDGPU_RING_PRIO_DEFAULT, NULL);
1994 if (r)
1995 return r;
1996 }
1997
1998
1999 /* set up the compute queues - allocate horizontally across pipes */
2000 ring_id = 0;
2001 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2002 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2003 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2004 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
2005 k, j))
2006 continue;
2007
2008 r = gfx_v8_0_compute_ring_init(adev,
2009 ring_id,
2010 i, k, j);
2011 if (r)
2012 return r;
2013
2014 ring_id++;
2015 }
2016 }
2017 }
2018
2019 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE, 0);
2020 if (r) {
2021 DRM_ERROR("Failed to init KIQ BOs!\n");
2022 return r;
2023 }
2024
2025 kiq = &adev->gfx.kiq[0];
2026 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
2027 if (r)
2028 return r;
2029
2030 /* create MQD for all compute queues as well as KIQ for SRIOV case */
2031 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation), 0);
2032 if (r)
2033 return r;
2034
2035 adev->gfx.ce_ram_size = 0x8000;
2036
2037 r = gfx_v8_0_gpu_early_init(adev);
2038 if (r)
2039 return r;
2040
2041 return 0;
2042}
2043
2044static int gfx_v8_0_sw_fini(void *handle)
2045{
2046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2047 int i;
2048
2049 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2050 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2051 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2052 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2053
2054 amdgpu_gfx_mqd_sw_fini(adev, 0);
2055 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
2056 amdgpu_gfx_kiq_fini(adev, 0);
2057
2058 gfx_v8_0_mec_fini(adev);
2059 amdgpu_gfx_rlc_fini(adev);
2060 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2061 &adev->gfx.rlc.clear_state_gpu_addr,
2062 (void **)&adev->gfx.rlc.cs_ptr);
2063 if ((adev->asic_type == CHIP_CARRIZO) ||
2064 (adev->asic_type == CHIP_STONEY)) {
2065 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2066 &adev->gfx.rlc.cp_table_gpu_addr,
2067 (void **)&adev->gfx.rlc.cp_table_ptr);
2068 }
2069 gfx_v8_0_free_microcode(adev);
2070
2071 return 0;
2072}
2073
2074static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2075{
2076 uint32_t *modearray, *mod2array;
2077 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2078 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2079 u32 reg_offset;
2080
2081 modearray = adev->gfx.config.tile_mode_array;
2082 mod2array = adev->gfx.config.macrotile_mode_array;
2083
2084 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2085 modearray[reg_offset] = 0;
2086
2087 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2088 mod2array[reg_offset] = 0;
2089
2090 switch (adev->asic_type) {
2091 case CHIP_TOPAZ:
2092 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2093 PIPE_CONFIG(ADDR_SURF_P2) |
2094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2095 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2096 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2097 PIPE_CONFIG(ADDR_SURF_P2) |
2098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2099 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2100 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2101 PIPE_CONFIG(ADDR_SURF_P2) |
2102 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2103 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2104 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2105 PIPE_CONFIG(ADDR_SURF_P2) |
2106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2107 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2108 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2109 PIPE_CONFIG(ADDR_SURF_P2) |
2110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2111 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2112 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2113 PIPE_CONFIG(ADDR_SURF_P2) |
2114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2115 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2116 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2117 PIPE_CONFIG(ADDR_SURF_P2) |
2118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2119 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2120 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2121 PIPE_CONFIG(ADDR_SURF_P2));
2122 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2123 PIPE_CONFIG(ADDR_SURF_P2) |
2124 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2125 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2126 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2127 PIPE_CONFIG(ADDR_SURF_P2) |
2128 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2129 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2130 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2131 PIPE_CONFIG(ADDR_SURF_P2) |
2132 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2134 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2135 PIPE_CONFIG(ADDR_SURF_P2) |
2136 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2138 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2139 PIPE_CONFIG(ADDR_SURF_P2) |
2140 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2141 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2142 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2143 PIPE_CONFIG(ADDR_SURF_P2) |
2144 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2145 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2146 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2147 PIPE_CONFIG(ADDR_SURF_P2) |
2148 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2149 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2150 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2151 PIPE_CONFIG(ADDR_SURF_P2) |
2152 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2153 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2154 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2155 PIPE_CONFIG(ADDR_SURF_P2) |
2156 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2157 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2158 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2159 PIPE_CONFIG(ADDR_SURF_P2) |
2160 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2161 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2162 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2163 PIPE_CONFIG(ADDR_SURF_P2) |
2164 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2165 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2166 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2167 PIPE_CONFIG(ADDR_SURF_P2) |
2168 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2169 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2170 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2171 PIPE_CONFIG(ADDR_SURF_P2) |
2172 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2173 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2174 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2175 PIPE_CONFIG(ADDR_SURF_P2) |
2176 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2177 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2178 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2179 PIPE_CONFIG(ADDR_SURF_P2) |
2180 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2181 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2182 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2183 PIPE_CONFIG(ADDR_SURF_P2) |
2184 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2185 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2186 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2187 PIPE_CONFIG(ADDR_SURF_P2) |
2188 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2189 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2190 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2191 PIPE_CONFIG(ADDR_SURF_P2) |
2192 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2193 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2194
2195 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2198 NUM_BANKS(ADDR_SURF_8_BANK));
2199 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2200 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2201 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2202 NUM_BANKS(ADDR_SURF_8_BANK));
2203 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2206 NUM_BANKS(ADDR_SURF_8_BANK));
2207 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2208 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2209 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2210 NUM_BANKS(ADDR_SURF_8_BANK));
2211 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2214 NUM_BANKS(ADDR_SURF_8_BANK));
2215 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2216 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2217 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2218 NUM_BANKS(ADDR_SURF_8_BANK));
2219 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2222 NUM_BANKS(ADDR_SURF_8_BANK));
2223 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2226 NUM_BANKS(ADDR_SURF_16_BANK));
2227 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2230 NUM_BANKS(ADDR_SURF_16_BANK));
2231 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2232 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2234 NUM_BANKS(ADDR_SURF_16_BANK));
2235 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2238 NUM_BANKS(ADDR_SURF_16_BANK));
2239 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2242 NUM_BANKS(ADDR_SURF_16_BANK));
2243 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2246 NUM_BANKS(ADDR_SURF_16_BANK));
2247 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2250 NUM_BANKS(ADDR_SURF_8_BANK));
2251
2252 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2253 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2254 reg_offset != 23)
2255 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2256
2257 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2258 if (reg_offset != 7)
2259 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2260
2261 break;
2262 case CHIP_FIJI:
2263 case CHIP_VEGAM:
2264 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2267 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2268 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2269 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2270 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2271 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2272 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2274 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2275 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2276 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2278 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2279 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2280 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2281 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2282 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2283 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2284 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2285 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2286 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2287 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2288 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2289 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2290 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2291 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2292 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2293 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2294 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2295 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2296 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2297 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2298 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2299 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2300 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2302 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2303 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2304 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2306 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2307 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2308 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2310 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2311 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2312 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2314 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2316 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2318 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2320 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2322 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2324 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2325 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2326 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2328 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2329 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2330 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2331 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2332 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2333 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2334 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2335 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2336 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2337 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2338 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2339 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2340 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2341 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2342 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2343 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2344 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2345 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2346 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2347 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2348 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2349 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2350 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2351 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2352 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2353 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2354 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2355 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2356 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2357 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2358 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2359 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2360 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2361 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2362 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2363 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2364 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2365 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2366 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2367 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2368 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2369 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2370 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2371 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2372 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2373 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2374 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2375 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2376 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2377 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2378 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2379 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2380 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2381 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2382 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2383 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2384 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2385 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2386
2387 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2388 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2389 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2390 NUM_BANKS(ADDR_SURF_8_BANK));
2391 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2394 NUM_BANKS(ADDR_SURF_8_BANK));
2395 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2396 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2397 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2398 NUM_BANKS(ADDR_SURF_8_BANK));
2399 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2400 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2401 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2402 NUM_BANKS(ADDR_SURF_8_BANK));
2403 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2404 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2405 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2406 NUM_BANKS(ADDR_SURF_8_BANK));
2407 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2408 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2409 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2410 NUM_BANKS(ADDR_SURF_8_BANK));
2411 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2412 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2413 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2414 NUM_BANKS(ADDR_SURF_8_BANK));
2415 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2416 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2417 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2418 NUM_BANKS(ADDR_SURF_8_BANK));
2419 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2420 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2421 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2422 NUM_BANKS(ADDR_SURF_8_BANK));
2423 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2424 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2425 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2426 NUM_BANKS(ADDR_SURF_8_BANK));
2427 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2428 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2429 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2430 NUM_BANKS(ADDR_SURF_8_BANK));
2431 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2434 NUM_BANKS(ADDR_SURF_8_BANK));
2435 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2436 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2437 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2438 NUM_BANKS(ADDR_SURF_8_BANK));
2439 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2440 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2441 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2442 NUM_BANKS(ADDR_SURF_4_BANK));
2443
2444 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2445 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2446
2447 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2448 if (reg_offset != 7)
2449 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2450
2451 break;
2452 case CHIP_TONGA:
2453 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2454 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2456 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2457 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2458 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2459 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2460 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2461 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2462 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2464 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2465 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2466 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2467 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2468 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2469 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2470 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2472 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2473 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2474 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2475 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2476 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2477 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2478 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2479 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2480 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2481 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2482 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2484 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2485 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2486 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2487 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2488 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2489 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2491 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2492 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2493 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2494 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2495 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2496 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2497 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2498 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2499 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2500 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2501 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2502 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2503 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2504 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2505 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2506 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2507 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2508 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2509 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2510 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2511 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2513 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2514 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2515 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2516 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2517 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2518 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2519 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2520 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2521 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2522 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2523 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2524 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2525 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2526 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2527 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2529 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2530 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2531 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2532 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2533 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2534 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2535 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2536 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2537 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2538 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2539 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2540 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2541 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2542 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2543 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2544 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2545 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2546 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2547 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2548 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2549 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2550 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2551 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2552 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2553 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2554 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2555 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2556 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2557 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2558 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2559 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2560 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2561 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2562 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2563 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2564 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2565 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2566 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2567 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2568 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2569 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2570 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2571 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2572 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2573 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2574 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2575
2576 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2577 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2578 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2579 NUM_BANKS(ADDR_SURF_16_BANK));
2580 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2581 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2582 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2583 NUM_BANKS(ADDR_SURF_16_BANK));
2584 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2585 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2586 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2587 NUM_BANKS(ADDR_SURF_16_BANK));
2588 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2589 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2590 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2591 NUM_BANKS(ADDR_SURF_16_BANK));
2592 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2593 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2594 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2595 NUM_BANKS(ADDR_SURF_16_BANK));
2596 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2597 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2598 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2599 NUM_BANKS(ADDR_SURF_16_BANK));
2600 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2601 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2602 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2603 NUM_BANKS(ADDR_SURF_16_BANK));
2604 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2605 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2606 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2607 NUM_BANKS(ADDR_SURF_16_BANK));
2608 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2609 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2610 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2611 NUM_BANKS(ADDR_SURF_16_BANK));
2612 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2613 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2614 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2615 NUM_BANKS(ADDR_SURF_16_BANK));
2616 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2617 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2618 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2619 NUM_BANKS(ADDR_SURF_16_BANK));
2620 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2621 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2622 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2623 NUM_BANKS(ADDR_SURF_8_BANK));
2624 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2625 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2626 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2627 NUM_BANKS(ADDR_SURF_4_BANK));
2628 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2629 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2630 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2631 NUM_BANKS(ADDR_SURF_4_BANK));
2632
2633 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2634 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2635
2636 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2637 if (reg_offset != 7)
2638 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2639
2640 break;
2641 case CHIP_POLARIS11:
2642 case CHIP_POLARIS12:
2643 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2644 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2645 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2646 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2647 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2648 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2649 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2650 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2651 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2652 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2653 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2654 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2655 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2656 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2657 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2658 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2659 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2660 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2661 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2662 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2663 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2664 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2665 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2666 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2667 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2668 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2669 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2670 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2671 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2672 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2673 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2674 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2675 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2676 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2677 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2678 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2679 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2680 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2681 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2682 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2683 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2684 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2685 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2686 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2687 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2688 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2689 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2690 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2691 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2692 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2693 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2694 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2695 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2696 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2697 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2698 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2699 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2700 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2701 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2702 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2703 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2704 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2705 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2706 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2707 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2708 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2709 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2710 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2711 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2712 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2713 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2714 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2715 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2716 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2717 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2718 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2719 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2720 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2721 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2722 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2723 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2724 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2725 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2726 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2727 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2728 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2729 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2730 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2731 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2732 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2733 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2734 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2735 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2736 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2737 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2738 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2739 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2740 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2741 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2742 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2743 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2744 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2745 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2746 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2747 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2748 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2749 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2750 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2751 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2752 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2753 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2754 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2755 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2756 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2757 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2758 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2759 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2760 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2761 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2762 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2763 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2764 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2765
2766 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2769 NUM_BANKS(ADDR_SURF_16_BANK));
2770
2771 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2772 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2773 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2774 NUM_BANKS(ADDR_SURF_16_BANK));
2775
2776 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2777 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2778 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2779 NUM_BANKS(ADDR_SURF_16_BANK));
2780
2781 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2782 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2783 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2784 NUM_BANKS(ADDR_SURF_16_BANK));
2785
2786 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2787 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2788 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2789 NUM_BANKS(ADDR_SURF_16_BANK));
2790
2791 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2792 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2793 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2794 NUM_BANKS(ADDR_SURF_16_BANK));
2795
2796 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2797 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2798 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2799 NUM_BANKS(ADDR_SURF_16_BANK));
2800
2801 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2802 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2803 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2804 NUM_BANKS(ADDR_SURF_16_BANK));
2805
2806 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2809 NUM_BANKS(ADDR_SURF_16_BANK));
2810
2811 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2812 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2813 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2814 NUM_BANKS(ADDR_SURF_16_BANK));
2815
2816 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2817 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2818 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2819 NUM_BANKS(ADDR_SURF_16_BANK));
2820
2821 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2824 NUM_BANKS(ADDR_SURF_16_BANK));
2825
2826 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2827 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2828 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2829 NUM_BANKS(ADDR_SURF_8_BANK));
2830
2831 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2832 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2833 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2834 NUM_BANKS(ADDR_SURF_4_BANK));
2835
2836 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2837 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2838
2839 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2840 if (reg_offset != 7)
2841 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2842
2843 break;
2844 case CHIP_POLARIS10:
2845 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2846 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2848 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2849 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2850 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2851 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2852 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2853 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2854 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2855 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2856 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2857 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2858 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2859 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2860 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2861 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2862 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2863 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2864 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2865 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2866 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2867 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2868 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2869 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2870 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2871 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2872 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2873 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2874 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2875 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2876 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2877 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2878 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2879 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2880 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2881 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2882 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2883 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2884 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2885 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2886 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2887 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2888 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2889 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2890 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2891 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2892 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2893 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2894 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2895 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2896 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2897 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2898 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2899 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2900 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2901 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2902 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2903 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2904 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2905 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2906 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2907 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2908 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2909 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2910 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2911 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2912 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2913 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2914 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2915 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2916 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2917 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2918 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2919 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2920 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2921 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2922 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2923 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2924 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2925 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2926 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2927 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2928 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2929 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2930 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2931 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2932 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2933 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2934 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2935 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2936 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2937 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2938 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2939 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2940 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2941 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2942 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2943 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2944 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2945 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2946 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2947 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2948 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2949 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2950 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2951 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2952 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2953 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2954 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2955 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2956 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2957 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2958 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2959 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2960 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2961 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2962 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2963 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2964 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2965 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2966 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2967
2968 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2969 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2970 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2971 NUM_BANKS(ADDR_SURF_16_BANK));
2972
2973 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2974 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2975 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2976 NUM_BANKS(ADDR_SURF_16_BANK));
2977
2978 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2979 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2980 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2981 NUM_BANKS(ADDR_SURF_16_BANK));
2982
2983 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2984 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2985 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2986 NUM_BANKS(ADDR_SURF_16_BANK));
2987
2988 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2991 NUM_BANKS(ADDR_SURF_16_BANK));
2992
2993 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2994 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2995 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2996 NUM_BANKS(ADDR_SURF_16_BANK));
2997
2998 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2999 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3000 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3001 NUM_BANKS(ADDR_SURF_16_BANK));
3002
3003 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3004 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3005 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3006 NUM_BANKS(ADDR_SURF_16_BANK));
3007
3008 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3009 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3010 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3011 NUM_BANKS(ADDR_SURF_16_BANK));
3012
3013 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3014 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3015 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3016 NUM_BANKS(ADDR_SURF_16_BANK));
3017
3018 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3019 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3020 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3021 NUM_BANKS(ADDR_SURF_16_BANK));
3022
3023 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3024 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3025 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3026 NUM_BANKS(ADDR_SURF_8_BANK));
3027
3028 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3031 NUM_BANKS(ADDR_SURF_4_BANK));
3032
3033 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3034 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3035 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3036 NUM_BANKS(ADDR_SURF_4_BANK));
3037
3038 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3039 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3040
3041 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3042 if (reg_offset != 7)
3043 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3044
3045 break;
3046 case CHIP_STONEY:
3047 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3048 PIPE_CONFIG(ADDR_SURF_P2) |
3049 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3050 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3051 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3052 PIPE_CONFIG(ADDR_SURF_P2) |
3053 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3054 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3055 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3056 PIPE_CONFIG(ADDR_SURF_P2) |
3057 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3058 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3059 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3060 PIPE_CONFIG(ADDR_SURF_P2) |
3061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3063 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3064 PIPE_CONFIG(ADDR_SURF_P2) |
3065 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3066 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3067 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3068 PIPE_CONFIG(ADDR_SURF_P2) |
3069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3070 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3071 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3072 PIPE_CONFIG(ADDR_SURF_P2) |
3073 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3074 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3075 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3076 PIPE_CONFIG(ADDR_SURF_P2));
3077 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3078 PIPE_CONFIG(ADDR_SURF_P2) |
3079 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3080 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3081 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3082 PIPE_CONFIG(ADDR_SURF_P2) |
3083 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3084 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3085 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3086 PIPE_CONFIG(ADDR_SURF_P2) |
3087 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3088 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3089 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3090 PIPE_CONFIG(ADDR_SURF_P2) |
3091 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3092 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3093 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3094 PIPE_CONFIG(ADDR_SURF_P2) |
3095 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3096 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3097 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3098 PIPE_CONFIG(ADDR_SURF_P2) |
3099 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3100 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3101 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3102 PIPE_CONFIG(ADDR_SURF_P2) |
3103 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3104 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3105 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3106 PIPE_CONFIG(ADDR_SURF_P2) |
3107 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3108 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3109 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3110 PIPE_CONFIG(ADDR_SURF_P2) |
3111 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3112 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3113 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3114 PIPE_CONFIG(ADDR_SURF_P2) |
3115 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3116 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3117 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3118 PIPE_CONFIG(ADDR_SURF_P2) |
3119 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3120 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3121 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3122 PIPE_CONFIG(ADDR_SURF_P2) |
3123 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3124 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3125 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3126 PIPE_CONFIG(ADDR_SURF_P2) |
3127 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3128 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3129 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3130 PIPE_CONFIG(ADDR_SURF_P2) |
3131 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3132 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3133 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3134 PIPE_CONFIG(ADDR_SURF_P2) |
3135 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3136 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3137 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3138 PIPE_CONFIG(ADDR_SURF_P2) |
3139 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3140 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3141 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3142 PIPE_CONFIG(ADDR_SURF_P2) |
3143 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3144 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3145 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3146 PIPE_CONFIG(ADDR_SURF_P2) |
3147 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3148 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3149
3150 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3151 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3152 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3153 NUM_BANKS(ADDR_SURF_8_BANK));
3154 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3157 NUM_BANKS(ADDR_SURF_8_BANK));
3158 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3161 NUM_BANKS(ADDR_SURF_8_BANK));
3162 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3165 NUM_BANKS(ADDR_SURF_8_BANK));
3166 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3167 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3168 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3169 NUM_BANKS(ADDR_SURF_8_BANK));
3170 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3171 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3172 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3173 NUM_BANKS(ADDR_SURF_8_BANK));
3174 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3175 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3176 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3177 NUM_BANKS(ADDR_SURF_8_BANK));
3178 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3181 NUM_BANKS(ADDR_SURF_16_BANK));
3182 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3183 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3184 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3185 NUM_BANKS(ADDR_SURF_16_BANK));
3186 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3189 NUM_BANKS(ADDR_SURF_16_BANK));
3190 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3191 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3192 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3193 NUM_BANKS(ADDR_SURF_16_BANK));
3194 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3197 NUM_BANKS(ADDR_SURF_16_BANK));
3198 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3201 NUM_BANKS(ADDR_SURF_16_BANK));
3202 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3203 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3204 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3205 NUM_BANKS(ADDR_SURF_8_BANK));
3206
3207 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3208 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3209 reg_offset != 23)
3210 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3211
3212 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3213 if (reg_offset != 7)
3214 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3215
3216 break;
3217 default:
3218 dev_warn(adev->dev,
3219 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3220 adev->asic_type);
3221 fallthrough;
3222
3223 case CHIP_CARRIZO:
3224 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3225 PIPE_CONFIG(ADDR_SURF_P2) |
3226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3227 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3228 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3229 PIPE_CONFIG(ADDR_SURF_P2) |
3230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3231 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3232 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3233 PIPE_CONFIG(ADDR_SURF_P2) |
3234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3235 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3236 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3237 PIPE_CONFIG(ADDR_SURF_P2) |
3238 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3239 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3240 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3241 PIPE_CONFIG(ADDR_SURF_P2) |
3242 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3243 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3244 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3245 PIPE_CONFIG(ADDR_SURF_P2) |
3246 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3247 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3248 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3249 PIPE_CONFIG(ADDR_SURF_P2) |
3250 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3251 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3252 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3253 PIPE_CONFIG(ADDR_SURF_P2));
3254 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3255 PIPE_CONFIG(ADDR_SURF_P2) |
3256 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3257 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3258 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3259 PIPE_CONFIG(ADDR_SURF_P2) |
3260 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3261 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3262 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3263 PIPE_CONFIG(ADDR_SURF_P2) |
3264 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3265 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3266 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3267 PIPE_CONFIG(ADDR_SURF_P2) |
3268 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3269 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3270 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3271 PIPE_CONFIG(ADDR_SURF_P2) |
3272 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3273 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3274 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3275 PIPE_CONFIG(ADDR_SURF_P2) |
3276 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3277 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3278 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3279 PIPE_CONFIG(ADDR_SURF_P2) |
3280 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3281 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3282 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3283 PIPE_CONFIG(ADDR_SURF_P2) |
3284 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3285 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3286 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3287 PIPE_CONFIG(ADDR_SURF_P2) |
3288 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3289 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3290 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3291 PIPE_CONFIG(ADDR_SURF_P2) |
3292 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3293 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3294 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3295 PIPE_CONFIG(ADDR_SURF_P2) |
3296 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3297 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3298 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3299 PIPE_CONFIG(ADDR_SURF_P2) |
3300 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3302 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3303 PIPE_CONFIG(ADDR_SURF_P2) |
3304 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3305 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3306 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3307 PIPE_CONFIG(ADDR_SURF_P2) |
3308 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3309 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3310 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3311 PIPE_CONFIG(ADDR_SURF_P2) |
3312 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3314 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3315 PIPE_CONFIG(ADDR_SURF_P2) |
3316 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3318 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3319 PIPE_CONFIG(ADDR_SURF_P2) |
3320 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3322 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3323 PIPE_CONFIG(ADDR_SURF_P2) |
3324 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3325 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3326
3327 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3330 NUM_BANKS(ADDR_SURF_8_BANK));
3331 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3334 NUM_BANKS(ADDR_SURF_8_BANK));
3335 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3338 NUM_BANKS(ADDR_SURF_8_BANK));
3339 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3342 NUM_BANKS(ADDR_SURF_8_BANK));
3343 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3346 NUM_BANKS(ADDR_SURF_8_BANK));
3347 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3350 NUM_BANKS(ADDR_SURF_8_BANK));
3351 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3354 NUM_BANKS(ADDR_SURF_8_BANK));
3355 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3358 NUM_BANKS(ADDR_SURF_16_BANK));
3359 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3362 NUM_BANKS(ADDR_SURF_16_BANK));
3363 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3366 NUM_BANKS(ADDR_SURF_16_BANK));
3367 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3370 NUM_BANKS(ADDR_SURF_16_BANK));
3371 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3374 NUM_BANKS(ADDR_SURF_16_BANK));
3375 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3378 NUM_BANKS(ADDR_SURF_16_BANK));
3379 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3382 NUM_BANKS(ADDR_SURF_8_BANK));
3383
3384 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3385 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3386 reg_offset != 23)
3387 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3388
3389 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3390 if (reg_offset != 7)
3391 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3392
3393 break;
3394 }
3395}
3396
3397static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3398 u32 se_num, u32 sh_num, u32 instance,
3399 int xcc_id)
3400{
3401 u32 data;
3402
3403 if (instance == 0xffffffff)
3404 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3405 else
3406 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3407
3408 if (se_num == 0xffffffff)
3409 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3410 else
3411 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3412
3413 if (sh_num == 0xffffffff)
3414 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3415 else
3416 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3417
3418 WREG32(mmGRBM_GFX_INDEX, data);
3419}
3420
3421static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3422 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
3423{
3424 vi_srbm_select(adev, me, pipe, q, vm);
3425}
3426
3427static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3428{
3429 u32 data, mask;
3430
3431 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3432 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3433
3434 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3435
3436 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3437 adev->gfx.config.max_sh_per_se);
3438
3439 return (~data) & mask;
3440}
3441
3442static void
3443gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3444{
3445 switch (adev->asic_type) {
3446 case CHIP_FIJI:
3447 case CHIP_VEGAM:
3448 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3449 RB_XSEL2(1) | PKR_MAP(2) |
3450 PKR_XSEL(1) | PKR_YSEL(1) |
3451 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3452 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3453 SE_PAIR_YSEL(2);
3454 break;
3455 case CHIP_TONGA:
3456 case CHIP_POLARIS10:
3457 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3458 SE_XSEL(1) | SE_YSEL(1);
3459 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3460 SE_PAIR_YSEL(2);
3461 break;
3462 case CHIP_TOPAZ:
3463 case CHIP_CARRIZO:
3464 *rconf |= RB_MAP_PKR0(2);
3465 *rconf1 |= 0x0;
3466 break;
3467 case CHIP_POLARIS11:
3468 case CHIP_POLARIS12:
3469 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3470 SE_XSEL(1) | SE_YSEL(1);
3471 *rconf1 |= 0x0;
3472 break;
3473 case CHIP_STONEY:
3474 *rconf |= 0x0;
3475 *rconf1 |= 0x0;
3476 break;
3477 default:
3478 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3479 break;
3480 }
3481}
3482
3483static void
3484gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3485 u32 raster_config, u32 raster_config_1,
3486 unsigned rb_mask, unsigned num_rb)
3487{
3488 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3489 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3490 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3491 unsigned rb_per_se = num_rb / num_se;
3492 unsigned se_mask[4];
3493 unsigned se;
3494
3495 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3496 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3497 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3498 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3499
3500 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3501 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3502 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3503
3504 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3505 (!se_mask[2] && !se_mask[3]))) {
3506 raster_config_1 &= ~SE_PAIR_MAP_MASK;
3507
3508 if (!se_mask[0] && !se_mask[1]) {
3509 raster_config_1 |=
3510 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3511 } else {
3512 raster_config_1 |=
3513 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3514 }
3515 }
3516
3517 for (se = 0; se < num_se; se++) {
3518 unsigned raster_config_se = raster_config;
3519 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3520 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3521 int idx = (se / 2) * 2;
3522
3523 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3524 raster_config_se &= ~SE_MAP_MASK;
3525
3526 if (!se_mask[idx]) {
3527 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3528 } else {
3529 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3530 }
3531 }
3532
3533 pkr0_mask &= rb_mask;
3534 pkr1_mask &= rb_mask;
3535 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3536 raster_config_se &= ~PKR_MAP_MASK;
3537
3538 if (!pkr0_mask) {
3539 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3540 } else {
3541 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3542 }
3543 }
3544
3545 if (rb_per_se >= 2) {
3546 unsigned rb0_mask = 1 << (se * rb_per_se);
3547 unsigned rb1_mask = rb0_mask << 1;
3548
3549 rb0_mask &= rb_mask;
3550 rb1_mask &= rb_mask;
3551 if (!rb0_mask || !rb1_mask) {
3552 raster_config_se &= ~RB_MAP_PKR0_MASK;
3553
3554 if (!rb0_mask) {
3555 raster_config_se |=
3556 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3557 } else {
3558 raster_config_se |=
3559 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3560 }
3561 }
3562
3563 if (rb_per_se > 2) {
3564 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3565 rb1_mask = rb0_mask << 1;
3566 rb0_mask &= rb_mask;
3567 rb1_mask &= rb_mask;
3568 if (!rb0_mask || !rb1_mask) {
3569 raster_config_se &= ~RB_MAP_PKR1_MASK;
3570
3571 if (!rb0_mask) {
3572 raster_config_se |=
3573 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3574 } else {
3575 raster_config_se |=
3576 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3577 }
3578 }
3579 }
3580 }
3581
3582 /* GRBM_GFX_INDEX has a different offset on VI */
3583 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);
3584 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3585 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3586 }
3587
3588 /* GRBM_GFX_INDEX has a different offset on VI */
3589 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3590}
3591
3592static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3593{
3594 int i, j;
3595 u32 data;
3596 u32 raster_config = 0, raster_config_1 = 0;
3597 u32 active_rbs = 0;
3598 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3599 adev->gfx.config.max_sh_per_se;
3600 unsigned num_rb_pipes;
3601
3602 mutex_lock(&adev->grbm_idx_mutex);
3603 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3604 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3605 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3606 data = gfx_v8_0_get_rb_active_bitmap(adev);
3607 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3608 rb_bitmap_width_per_sh);
3609 }
3610 }
3611 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3612
3613 adev->gfx.config.backend_enable_mask = active_rbs;
3614 adev->gfx.config.num_rbs = hweight32(active_rbs);
3615
3616 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3617 adev->gfx.config.max_shader_engines, 16);
3618
3619 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3620
3621 if (!adev->gfx.config.backend_enable_mask ||
3622 adev->gfx.config.num_rbs >= num_rb_pipes) {
3623 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3624 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3625 } else {
3626 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3627 adev->gfx.config.backend_enable_mask,
3628 num_rb_pipes);
3629 }
3630
3631 /* cache the values for userspace */
3632 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3633 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3634 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3635 adev->gfx.config.rb_config[i][j].rb_backend_disable =
3636 RREG32(mmCC_RB_BACKEND_DISABLE);
3637 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3638 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3639 adev->gfx.config.rb_config[i][j].raster_config =
3640 RREG32(mmPA_SC_RASTER_CONFIG);
3641 adev->gfx.config.rb_config[i][j].raster_config_1 =
3642 RREG32(mmPA_SC_RASTER_CONFIG_1);
3643 }
3644 }
3645 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3646 mutex_unlock(&adev->grbm_idx_mutex);
3647}
3648
3649#define DEFAULT_SH_MEM_BASES (0x6000)
3650/**
3651 * gfx_v8_0_init_compute_vmid - gart enable
3652 *
3653 * @adev: amdgpu_device pointer
3654 *
3655 * Initialize compute vmid sh_mem registers
3656 *
3657 */
3658static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3659{
3660 int i;
3661 uint32_t sh_mem_config;
3662 uint32_t sh_mem_bases;
3663
3664 /*
3665 * Configure apertures:
3666 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3667 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3668 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3669 */
3670 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3671
3672 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3673 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3674 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3675 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3676 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3677 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3678
3679 mutex_lock(&adev->srbm_mutex);
3680 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3681 vi_srbm_select(adev, 0, 0, 0, i);
3682 /* CP and shaders */
3683 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3684 WREG32(mmSH_MEM_APE1_BASE, 1);
3685 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3686 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3687 }
3688 vi_srbm_select(adev, 0, 0, 0, 0);
3689 mutex_unlock(&adev->srbm_mutex);
3690
3691 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
3692 access. These should be enabled by FW for target VMIDs. */
3693 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3694 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
3695 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
3696 WREG32(amdgpu_gds_reg_offset[i].gws, 0);
3697 WREG32(amdgpu_gds_reg_offset[i].oa, 0);
3698 }
3699}
3700
3701static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
3702{
3703 int vmid;
3704
3705 /*
3706 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
3707 * access. Compute VMIDs should be enabled by FW for target VMIDs,
3708 * the driver can enable them for graphics. VMID0 should maintain
3709 * access so that HWS firmware can save/restore entries.
3710 */
3711 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
3712 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
3713 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
3714 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
3715 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
3716 }
3717}
3718
3719static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3720{
3721 switch (adev->asic_type) {
3722 default:
3723 adev->gfx.config.double_offchip_lds_buf = 1;
3724 break;
3725 case CHIP_CARRIZO:
3726 case CHIP_STONEY:
3727 adev->gfx.config.double_offchip_lds_buf = 0;
3728 break;
3729 }
3730}
3731
3732static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
3733{
3734 u32 tmp, sh_static_mem_cfg;
3735 int i;
3736
3737 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3738 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3739 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3740 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3741
3742 gfx_v8_0_tiling_mode_table_init(adev);
3743 gfx_v8_0_setup_rb(adev);
3744 gfx_v8_0_get_cu_info(adev);
3745 gfx_v8_0_config_init(adev);
3746
3747 /* XXX SH_MEM regs */
3748 /* where to put LDS, scratch, GPUVM in FSA64 space */
3749 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3750 SWIZZLE_ENABLE, 1);
3751 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3752 ELEMENT_SIZE, 1);
3753 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3754 INDEX_STRIDE, 3);
3755 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3756
3757 mutex_lock(&adev->srbm_mutex);
3758 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3759 vi_srbm_select(adev, 0, 0, 0, i);
3760 /* CP and shaders */
3761 if (i == 0) {
3762 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3763 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3764 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3765 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3766 WREG32(mmSH_MEM_CONFIG, tmp);
3767 WREG32(mmSH_MEM_BASES, 0);
3768 } else {
3769 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3770 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3771 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3772 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3773 WREG32(mmSH_MEM_CONFIG, tmp);
3774 tmp = adev->gmc.shared_aperture_start >> 48;
3775 WREG32(mmSH_MEM_BASES, tmp);
3776 }
3777
3778 WREG32(mmSH_MEM_APE1_BASE, 1);
3779 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3780 }
3781 vi_srbm_select(adev, 0, 0, 0, 0);
3782 mutex_unlock(&adev->srbm_mutex);
3783
3784 gfx_v8_0_init_compute_vmid(adev);
3785 gfx_v8_0_init_gds_vmid(adev);
3786
3787 mutex_lock(&adev->grbm_idx_mutex);
3788 /*
3789 * making sure that the following register writes will be broadcasted
3790 * to all the shaders
3791 */
3792 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3793
3794 WREG32(mmPA_SC_FIFO_SIZE,
3795 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3796 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3797 (adev->gfx.config.sc_prim_fifo_size_backend <<
3798 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3799 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3800 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3801 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3802 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3803
3804 tmp = RREG32(mmSPI_ARB_PRIORITY);
3805 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3806 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3807 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3808 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3809 WREG32(mmSPI_ARB_PRIORITY, tmp);
3810
3811 mutex_unlock(&adev->grbm_idx_mutex);
3812
3813}
3814
3815static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3816{
3817 u32 i, j, k;
3818 u32 mask;
3819
3820 mutex_lock(&adev->grbm_idx_mutex);
3821 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3822 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3823 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3824 for (k = 0; k < adev->usec_timeout; k++) {
3825 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3826 break;
3827 udelay(1);
3828 }
3829 if (k == adev->usec_timeout) {
3830 gfx_v8_0_select_se_sh(adev, 0xffffffff,
3831 0xffffffff, 0xffffffff, 0);
3832 mutex_unlock(&adev->grbm_idx_mutex);
3833 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3834 i, j);
3835 return;
3836 }
3837 }
3838 }
3839 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3840 mutex_unlock(&adev->grbm_idx_mutex);
3841
3842 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3843 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3844 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3845 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3846 for (k = 0; k < adev->usec_timeout; k++) {
3847 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3848 break;
3849 udelay(1);
3850 }
3851}
3852
3853static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3854 bool enable)
3855{
3856 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3857
3858 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3859 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3860 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3861 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3862
3863 WREG32(mmCP_INT_CNTL_RING0, tmp);
3864}
3865
3866static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3867{
3868 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
3869 /* csib */
3870 WREG32(mmRLC_CSIB_ADDR_HI,
3871 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3872 WREG32(mmRLC_CSIB_ADDR_LO,
3873 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3874 WREG32(mmRLC_CSIB_LENGTH,
3875 adev->gfx.rlc.clear_state_size);
3876}
3877
3878static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3879 int ind_offset,
3880 int list_size,
3881 int *unique_indices,
3882 int *indices_count,
3883 int max_indices,
3884 int *ind_start_offsets,
3885 int *offset_count,
3886 int max_offset)
3887{
3888 int indices;
3889 bool new_entry = true;
3890
3891 for (; ind_offset < list_size; ind_offset++) {
3892
3893 if (new_entry) {
3894 new_entry = false;
3895 ind_start_offsets[*offset_count] = ind_offset;
3896 *offset_count = *offset_count + 1;
3897 BUG_ON(*offset_count >= max_offset);
3898 }
3899
3900 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3901 new_entry = true;
3902 continue;
3903 }
3904
3905 ind_offset += 2;
3906
3907 /* look for the matching indice */
3908 for (indices = 0;
3909 indices < *indices_count;
3910 indices++) {
3911 if (unique_indices[indices] ==
3912 register_list_format[ind_offset])
3913 break;
3914 }
3915
3916 if (indices >= *indices_count) {
3917 unique_indices[*indices_count] =
3918 register_list_format[ind_offset];
3919 indices = *indices_count;
3920 *indices_count = *indices_count + 1;
3921 BUG_ON(*indices_count >= max_indices);
3922 }
3923
3924 register_list_format[ind_offset] = indices;
3925 }
3926}
3927
3928static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3929{
3930 int i, temp, data;
3931 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3932 int indices_count = 0;
3933 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3934 int offset_count = 0;
3935
3936 int list_size;
3937 unsigned int *register_list_format =
3938 kmemdup(adev->gfx.rlc.register_list_format,
3939 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3940 if (!register_list_format)
3941 return -ENOMEM;
3942
3943 gfx_v8_0_parse_ind_reg_list(register_list_format,
3944 RLC_FormatDirectRegListLength,
3945 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3946 unique_indices,
3947 &indices_count,
3948 ARRAY_SIZE(unique_indices),
3949 indirect_start_offsets,
3950 &offset_count,
3951 ARRAY_SIZE(indirect_start_offsets));
3952
3953 /* save and restore list */
3954 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3955
3956 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3957 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3958 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
3959
3960 /* indirect list */
3961 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
3962 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
3963 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3964
3965 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
3966 list_size = list_size >> 1;
3967 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
3968 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3969
3970 /* starting offsets starts */
3971 WREG32(mmRLC_GPM_SCRATCH_ADDR,
3972 adev->gfx.rlc.starting_offsets_start);
3973 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
3974 WREG32(mmRLC_GPM_SCRATCH_DATA,
3975 indirect_start_offsets[i]);
3976
3977 /* unique indices */
3978 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
3979 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
3980 for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
3981 if (unique_indices[i] != 0) {
3982 WREG32(temp + i, unique_indices[i] & 0x3FFFF);
3983 WREG32(data + i, unique_indices[i] >> 20);
3984 }
3985 }
3986 kfree(register_list_format);
3987
3988 return 0;
3989}
3990
3991static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
3992{
3993 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
3994}
3995
3996static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
3997{
3998 uint32_t data;
3999
4000 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
4001
4002 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
4003 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
4004 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
4005 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
4006 WREG32(mmRLC_PG_DELAY, data);
4007
4008 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4009 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4010
4011}
4012
4013static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
4014 bool enable)
4015{
4016 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4017}
4018
4019static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
4020 bool enable)
4021{
4022 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4023}
4024
4025static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
4026{
4027 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4028}
4029
4030static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4031{
4032 if ((adev->asic_type == CHIP_CARRIZO) ||
4033 (adev->asic_type == CHIP_STONEY)) {
4034 gfx_v8_0_init_csb(adev);
4035 gfx_v8_0_init_save_restore_list(adev);
4036 gfx_v8_0_enable_save_restore_machine(adev);
4037 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4038 gfx_v8_0_init_power_gating(adev);
4039 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4040 } else if ((adev->asic_type == CHIP_POLARIS11) ||
4041 (adev->asic_type == CHIP_POLARIS12) ||
4042 (adev->asic_type == CHIP_VEGAM)) {
4043 gfx_v8_0_init_csb(adev);
4044 gfx_v8_0_init_save_restore_list(adev);
4045 gfx_v8_0_enable_save_restore_machine(adev);
4046 gfx_v8_0_init_power_gating(adev);
4047 }
4048
4049}
4050
4051static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
4052{
4053 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4054
4055 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4056 gfx_v8_0_wait_for_rlc_serdes(adev);
4057}
4058
4059static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4060{
4061 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4062 udelay(50);
4063
4064 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4065 udelay(50);
4066}
4067
4068static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4069{
4070 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
4071
4072 /* carrizo do enable cp interrupt after cp inited */
4073 if (!(adev->flags & AMD_IS_APU))
4074 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4075
4076 udelay(50);
4077}
4078
4079static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4080{
4081 if (amdgpu_sriov_vf(adev)) {
4082 gfx_v8_0_init_csb(adev);
4083 return 0;
4084 }
4085
4086 adev->gfx.rlc.funcs->stop(adev);
4087 adev->gfx.rlc.funcs->reset(adev);
4088 gfx_v8_0_init_pg(adev);
4089 adev->gfx.rlc.funcs->start(adev);
4090
4091 return 0;
4092}
4093
4094static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4095{
4096 u32 tmp = RREG32(mmCP_ME_CNTL);
4097
4098 if (enable) {
4099 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4100 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4101 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4102 } else {
4103 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4104 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4105 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4106 }
4107 WREG32(mmCP_ME_CNTL, tmp);
4108 udelay(50);
4109}
4110
4111static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4112{
4113 u32 count = 0;
4114 const struct cs_section_def *sect = NULL;
4115 const struct cs_extent_def *ext = NULL;
4116
4117 /* begin clear state */
4118 count += 2;
4119 /* context control state */
4120 count += 3;
4121
4122 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4123 for (ext = sect->section; ext->extent != NULL; ++ext) {
4124 if (sect->id == SECT_CONTEXT)
4125 count += 2 + ext->reg_count;
4126 else
4127 return 0;
4128 }
4129 }
4130 /* pa_sc_raster_config/pa_sc_raster_config1 */
4131 count += 4;
4132 /* end clear state */
4133 count += 2;
4134 /* clear state */
4135 count += 2;
4136
4137 return count;
4138}
4139
4140static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4141{
4142 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4143 const struct cs_section_def *sect = NULL;
4144 const struct cs_extent_def *ext = NULL;
4145 int r, i;
4146
4147 /* init the CP */
4148 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4149 WREG32(mmCP_ENDIAN_SWAP, 0);
4150 WREG32(mmCP_DEVICE_ID, 1);
4151
4152 gfx_v8_0_cp_gfx_enable(adev, true);
4153
4154 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
4155 if (r) {
4156 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4157 return r;
4158 }
4159
4160 /* clear state buffer */
4161 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4162 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4163
4164 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4165 amdgpu_ring_write(ring, 0x80000000);
4166 amdgpu_ring_write(ring, 0x80000000);
4167
4168 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4169 for (ext = sect->section; ext->extent != NULL; ++ext) {
4170 if (sect->id == SECT_CONTEXT) {
4171 amdgpu_ring_write(ring,
4172 PACKET3(PACKET3_SET_CONTEXT_REG,
4173 ext->reg_count));
4174 amdgpu_ring_write(ring,
4175 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4176 for (i = 0; i < ext->reg_count; i++)
4177 amdgpu_ring_write(ring, ext->extent[i]);
4178 }
4179 }
4180 }
4181
4182 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4183 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4184 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
4185 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
4186
4187 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4188 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4189
4190 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4191 amdgpu_ring_write(ring, 0);
4192
4193 /* init the CE partitions */
4194 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4195 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4196 amdgpu_ring_write(ring, 0x8000);
4197 amdgpu_ring_write(ring, 0x8000);
4198
4199 amdgpu_ring_commit(ring);
4200
4201 return 0;
4202}
4203static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
4204{
4205 u32 tmp;
4206 /* no gfx doorbells on iceland */
4207 if (adev->asic_type == CHIP_TOPAZ)
4208 return;
4209
4210 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4211
4212 if (ring->use_doorbell) {
4213 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4214 DOORBELL_OFFSET, ring->doorbell_index);
4215 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4216 DOORBELL_HIT, 0);
4217 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4218 DOORBELL_EN, 1);
4219 } else {
4220 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
4221 }
4222
4223 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4224
4225 if (adev->flags & AMD_IS_APU)
4226 return;
4227
4228 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4229 DOORBELL_RANGE_LOWER,
4230 adev->doorbell_index.gfx_ring0);
4231 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4232
4233 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4234 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4235}
4236
4237static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4238{
4239 struct amdgpu_ring *ring;
4240 u32 tmp;
4241 u32 rb_bufsz;
4242 u64 rb_addr, rptr_addr, wptr_gpu_addr;
4243
4244 /* Set the write pointer delay */
4245 WREG32(mmCP_RB_WPTR_DELAY, 0);
4246
4247 /* set the RB to use vmid 0 */
4248 WREG32(mmCP_RB_VMID, 0);
4249
4250 /* Set ring buffer size */
4251 ring = &adev->gfx.gfx_ring[0];
4252 rb_bufsz = order_base_2(ring->ring_size / 8);
4253 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4254 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4255 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4256 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4257#ifdef __BIG_ENDIAN
4258 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4259#endif
4260 WREG32(mmCP_RB0_CNTL, tmp);
4261
4262 /* Initialize the ring buffer's read and write pointers */
4263 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4264 ring->wptr = 0;
4265 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4266
4267 /* set the wb address wether it's enabled or not */
4268 rptr_addr = ring->rptr_gpu_addr;
4269 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4270 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4271
4272 wptr_gpu_addr = ring->wptr_gpu_addr;
4273 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4274 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4275 mdelay(1);
4276 WREG32(mmCP_RB0_CNTL, tmp);
4277
4278 rb_addr = ring->gpu_addr >> 8;
4279 WREG32(mmCP_RB0_BASE, rb_addr);
4280 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4281
4282 gfx_v8_0_set_cpg_door_bell(adev, ring);
4283 /* start the ring */
4284 amdgpu_ring_clear_ring(ring);
4285 gfx_v8_0_cp_gfx_start(adev);
4286
4287 return 0;
4288}
4289
4290static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4291{
4292 if (enable) {
4293 WREG32(mmCP_MEC_CNTL, 0);
4294 } else {
4295 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4296 adev->gfx.kiq[0].ring.sched.ready = false;
4297 }
4298 udelay(50);
4299}
4300
4301/* KIQ functions */
4302static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
4303{
4304 uint32_t tmp;
4305 struct amdgpu_device *adev = ring->adev;
4306
4307 /* tell RLC which is KIQ queue */
4308 tmp = RREG32(mmRLC_CP_SCHEDULERS);
4309 tmp &= 0xffffff00;
4310 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
4311 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4312 tmp |= 0x80;
4313 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4314}
4315
4316static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
4317{
4318 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
4319 uint64_t queue_mask = 0;
4320 int r, i;
4321
4322 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4323 if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap))
4324 continue;
4325
4326 /* This situation may be hit in the future if a new HW
4327 * generation exposes more than 64 queues. If so, the
4328 * definition of queue_mask needs updating */
4329 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
4330 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
4331 break;
4332 }
4333
4334 queue_mask |= (1ull << i);
4335 }
4336
4337 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
4338 if (r) {
4339 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4340 return r;
4341 }
4342 /* set resources */
4343 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4344 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4345 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4346 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4347 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4348 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4349 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4350 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
4351 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4352 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4353 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
4354 uint64_t wptr_addr = ring->wptr_gpu_addr;
4355
4356 /* map queues */
4357 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
4358 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
4359 amdgpu_ring_write(kiq_ring,
4360 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
4361 amdgpu_ring_write(kiq_ring,
4362 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) |
4363 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
4364 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
4365 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */
4366 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
4367 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
4368 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
4369 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
4370 }
4371
4372 amdgpu_ring_commit(kiq_ring);
4373
4374 return 0;
4375}
4376
4377static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
4378{
4379 int i, r = 0;
4380
4381 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4382 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
4383 for (i = 0; i < adev->usec_timeout; i++) {
4384 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4385 break;
4386 udelay(1);
4387 }
4388 if (i == adev->usec_timeout)
4389 r = -ETIMEDOUT;
4390 }
4391 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
4392 WREG32(mmCP_HQD_PQ_RPTR, 0);
4393 WREG32(mmCP_HQD_PQ_WPTR, 0);
4394
4395 return r;
4396}
4397
4398static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd)
4399{
4400 struct amdgpu_device *adev = ring->adev;
4401
4402 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4403 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
4404 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
4405 mqd->cp_hqd_queue_priority =
4406 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
4407 }
4408 }
4409}
4410
4411static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4412{
4413 struct amdgpu_device *adev = ring->adev;
4414 struct vi_mqd *mqd = ring->mqd_ptr;
4415 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4416 uint32_t tmp;
4417
4418 mqd->header = 0xC0310800;
4419 mqd->compute_pipelinestat_enable = 0x00000001;
4420 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4421 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4422 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4423 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4424 mqd->compute_misc_reserved = 0x00000003;
4425 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4426 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4427 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4428 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4429 eop_base_addr = ring->eop_gpu_addr >> 8;
4430 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4431 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4432
4433 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4434 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4435 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4436 (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1));
4437
4438 mqd->cp_hqd_eop_control = tmp;
4439
4440 /* enable doorbell? */
4441 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
4442 CP_HQD_PQ_DOORBELL_CONTROL,
4443 DOORBELL_EN,
4444 ring->use_doorbell ? 1 : 0);
4445
4446 mqd->cp_hqd_pq_doorbell_control = tmp;
4447
4448 /* set the pointer to the MQD */
4449 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4450 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4451
4452 /* set MQD vmid to 0 */
4453 tmp = RREG32(mmCP_MQD_CONTROL);
4454 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4455 mqd->cp_mqd_control = tmp;
4456
4457 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4458 hqd_gpu_addr = ring->gpu_addr >> 8;
4459 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4460 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4461
4462 /* set up the HQD, this is similar to CP_RB0_CNTL */
4463 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4464 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4465 (order_base_2(ring->ring_size / 4) - 1));
4466 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4467 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
4468#ifdef __BIG_ENDIAN
4469 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4470#endif
4471 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4472 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4473 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4474 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4475 mqd->cp_hqd_pq_control = tmp;
4476
4477 /* set the wb address whether it's enabled or not */
4478 wb_gpu_addr = ring->rptr_gpu_addr;
4479 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4480 mqd->cp_hqd_pq_rptr_report_addr_hi =
4481 upper_32_bits(wb_gpu_addr) & 0xffff;
4482
4483 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4484 wb_gpu_addr = ring->wptr_gpu_addr;
4485 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4486 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4487
4488 tmp = 0;
4489 /* enable the doorbell if requested */
4490 if (ring->use_doorbell) {
4491 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4492 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4493 DOORBELL_OFFSET, ring->doorbell_index);
4494
4495 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4496 DOORBELL_EN, 1);
4497 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4498 DOORBELL_SOURCE, 0);
4499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4500 DOORBELL_HIT, 0);
4501 }
4502
4503 mqd->cp_hqd_pq_doorbell_control = tmp;
4504
4505 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4506 ring->wptr = 0;
4507 mqd->cp_hqd_pq_wptr = ring->wptr;
4508 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4509
4510 /* set the vmid for the queue */
4511 mqd->cp_hqd_vmid = 0;
4512
4513 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4514 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4515 mqd->cp_hqd_persistent_state = tmp;
4516
4517 /* set MTYPE */
4518 tmp = RREG32(mmCP_HQD_IB_CONTROL);
4519 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4520 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
4521 mqd->cp_hqd_ib_control = tmp;
4522
4523 tmp = RREG32(mmCP_HQD_IQ_TIMER);
4524 tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
4525 mqd->cp_hqd_iq_timer = tmp;
4526
4527 tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
4528 tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4529 mqd->cp_hqd_ctx_save_control = tmp;
4530
4531 /* defaults */
4532 mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4533 mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4534 mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4535 mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4536 mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4537 mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4538 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4539 mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4540 mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4541 mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4542 mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4543 mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4544
4545 /* set static priority for a queue/ring */
4546 gfx_v8_0_mqd_set_priority(ring, mqd);
4547 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4548
4549 /* map_queues packet doesn't need activate the queue,
4550 * so only kiq need set this field.
4551 */
4552 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
4553 mqd->cp_hqd_active = 1;
4554
4555 return 0;
4556}
4557
4558static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4559 struct vi_mqd *mqd)
4560{
4561 uint32_t mqd_reg;
4562 uint32_t *mqd_data;
4563
4564 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4565 mqd_data = &mqd->cp_mqd_base_addr_lo;
4566
4567 /* disable wptr polling */
4568 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4569
4570 /* program all HQD registers */
4571 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
4572 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4573
4574 /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
4575 * This is safe since EOP RPTR==WPTR for any inactive HQD
4576 * on ASICs that do not support context-save.
4577 * EOP writes/reads can start anywhere in the ring.
4578 */
4579 if (adev->asic_type != CHIP_TONGA) {
4580 WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4581 WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4582 WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4583 }
4584
4585 for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
4586 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4587
4588 /* activate the HQD */
4589 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4590 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4591
4592 return 0;
4593}
4594
4595static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4596{
4597 struct amdgpu_device *adev = ring->adev;
4598 struct vi_mqd *mqd = ring->mqd_ptr;
4599
4600 gfx_v8_0_kiq_setting(ring);
4601
4602 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4603 /* reset MQD to a clean status */
4604 if (adev->gfx.kiq[0].mqd_backup)
4605 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct vi_mqd_allocation));
4606
4607 /* reset ring buffer */
4608 ring->wptr = 0;
4609 amdgpu_ring_clear_ring(ring);
4610 mutex_lock(&adev->srbm_mutex);
4611 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4612 gfx_v8_0_mqd_commit(adev, mqd);
4613 vi_srbm_select(adev, 0, 0, 0, 0);
4614 mutex_unlock(&adev->srbm_mutex);
4615 } else {
4616 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4617 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4618 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4619 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
4620 amdgpu_ring_clear_ring(ring);
4621 mutex_lock(&adev->srbm_mutex);
4622 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4623 gfx_v8_0_mqd_init(ring);
4624 gfx_v8_0_mqd_commit(adev, mqd);
4625 vi_srbm_select(adev, 0, 0, 0, 0);
4626 mutex_unlock(&adev->srbm_mutex);
4627
4628 if (adev->gfx.kiq[0].mqd_backup)
4629 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct vi_mqd_allocation));
4630 }
4631
4632 return 0;
4633}
4634
4635static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4636{
4637 struct amdgpu_device *adev = ring->adev;
4638 struct vi_mqd *mqd = ring->mqd_ptr;
4639 int mqd_idx = ring - &adev->gfx.compute_ring[0];
4640
4641 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4642 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4643 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4644 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4645 mutex_lock(&adev->srbm_mutex);
4646 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4647 gfx_v8_0_mqd_init(ring);
4648 vi_srbm_select(adev, 0, 0, 0, 0);
4649 mutex_unlock(&adev->srbm_mutex);
4650
4651 if (adev->gfx.mec.mqd_backup[mqd_idx])
4652 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4653 } else {
4654 /* restore MQD to a clean status */
4655 if (adev->gfx.mec.mqd_backup[mqd_idx])
4656 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4657 /* reset ring buffer */
4658 ring->wptr = 0;
4659 amdgpu_ring_clear_ring(ring);
4660 }
4661 return 0;
4662}
4663
4664static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
4665{
4666 if (adev->asic_type > CHIP_TONGA) {
4667 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
4668 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
4669 }
4670 /* enable doorbells */
4671 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4672}
4673
4674static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4675{
4676 struct amdgpu_ring *ring;
4677 int r;
4678
4679 ring = &adev->gfx.kiq[0].ring;
4680
4681 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4682 if (unlikely(r != 0))
4683 return r;
4684
4685 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4686 if (unlikely(r != 0)) {
4687 amdgpu_bo_unreserve(ring->mqd_obj);
4688 return r;
4689 }
4690
4691 gfx_v8_0_kiq_init_queue(ring);
4692 amdgpu_bo_kunmap(ring->mqd_obj);
4693 ring->mqd_ptr = NULL;
4694 amdgpu_bo_unreserve(ring->mqd_obj);
4695 return 0;
4696}
4697
4698static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
4699{
4700 struct amdgpu_ring *ring = NULL;
4701 int r = 0, i;
4702
4703 gfx_v8_0_cp_compute_enable(adev, true);
4704
4705 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4706 ring = &adev->gfx.compute_ring[i];
4707
4708 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4709 if (unlikely(r != 0))
4710 goto done;
4711 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4712 if (!r) {
4713 r = gfx_v8_0_kcq_init_queue(ring);
4714 amdgpu_bo_kunmap(ring->mqd_obj);
4715 ring->mqd_ptr = NULL;
4716 }
4717 amdgpu_bo_unreserve(ring->mqd_obj);
4718 if (r)
4719 goto done;
4720 }
4721
4722 gfx_v8_0_set_mec_doorbell_range(adev);
4723
4724 r = gfx_v8_0_kiq_kcq_enable(adev);
4725 if (r)
4726 goto done;
4727
4728done:
4729 return r;
4730}
4731
4732static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
4733{
4734 int r, i;
4735 struct amdgpu_ring *ring;
4736
4737 /* collect all the ring_tests here, gfx, kiq, compute */
4738 ring = &adev->gfx.gfx_ring[0];
4739 r = amdgpu_ring_test_helper(ring);
4740 if (r)
4741 return r;
4742
4743 ring = &adev->gfx.kiq[0].ring;
4744 r = amdgpu_ring_test_helper(ring);
4745 if (r)
4746 return r;
4747
4748 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4749 ring = &adev->gfx.compute_ring[i];
4750 amdgpu_ring_test_helper(ring);
4751 }
4752
4753 return 0;
4754}
4755
4756static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4757{
4758 int r;
4759
4760 if (!(adev->flags & AMD_IS_APU))
4761 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4762
4763 r = gfx_v8_0_kiq_resume(adev);
4764 if (r)
4765 return r;
4766
4767 r = gfx_v8_0_cp_gfx_resume(adev);
4768 if (r)
4769 return r;
4770
4771 r = gfx_v8_0_kcq_resume(adev);
4772 if (r)
4773 return r;
4774
4775 r = gfx_v8_0_cp_test_all_rings(adev);
4776 if (r)
4777 return r;
4778
4779 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4780
4781 return 0;
4782}
4783
4784static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4785{
4786 gfx_v8_0_cp_gfx_enable(adev, enable);
4787 gfx_v8_0_cp_compute_enable(adev, enable);
4788}
4789
4790static int gfx_v8_0_hw_init(void *handle)
4791{
4792 int r;
4793 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4794
4795 gfx_v8_0_init_golden_registers(adev);
4796 gfx_v8_0_constants_init(adev);
4797
4798 r = adev->gfx.rlc.funcs->resume(adev);
4799 if (r)
4800 return r;
4801
4802 r = gfx_v8_0_cp_resume(adev);
4803
4804 return r;
4805}
4806
4807static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
4808{
4809 int r, i;
4810 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
4811
4812 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
4813 if (r)
4814 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4815
4816 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4817 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4818
4819 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
4820 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
4821 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
4822 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
4823 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
4824 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
4825 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
4826 amdgpu_ring_write(kiq_ring, 0);
4827 amdgpu_ring_write(kiq_ring, 0);
4828 amdgpu_ring_write(kiq_ring, 0);
4829 }
4830 r = amdgpu_ring_test_helper(kiq_ring);
4831 if (r)
4832 DRM_ERROR("KCQ disable failed\n");
4833
4834 return r;
4835}
4836
4837static bool gfx_v8_0_is_idle(void *handle)
4838{
4839 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4840
4841 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
4842 || RREG32(mmGRBM_STATUS2) != 0x8)
4843 return false;
4844 else
4845 return true;
4846}
4847
4848static bool gfx_v8_0_rlc_is_idle(void *handle)
4849{
4850 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4851
4852 if (RREG32(mmGRBM_STATUS2) != 0x8)
4853 return false;
4854 else
4855 return true;
4856}
4857
4858static int gfx_v8_0_wait_for_rlc_idle(void *handle)
4859{
4860 unsigned int i;
4861 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4862
4863 for (i = 0; i < adev->usec_timeout; i++) {
4864 if (gfx_v8_0_rlc_is_idle(handle))
4865 return 0;
4866
4867 udelay(1);
4868 }
4869 return -ETIMEDOUT;
4870}
4871
4872static int gfx_v8_0_wait_for_idle(void *handle)
4873{
4874 unsigned int i;
4875 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4876
4877 for (i = 0; i < adev->usec_timeout; i++) {
4878 if (gfx_v8_0_is_idle(handle))
4879 return 0;
4880
4881 udelay(1);
4882 }
4883 return -ETIMEDOUT;
4884}
4885
4886static int gfx_v8_0_hw_fini(void *handle)
4887{
4888 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4889
4890 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4891 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4892
4893 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4894
4895 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);
4896
4897 /* disable KCQ to avoid CPC touch memory not valid anymore */
4898 gfx_v8_0_kcq_disable(adev);
4899
4900 if (amdgpu_sriov_vf(adev)) {
4901 pr_debug("For SRIOV client, shouldn't do anything.\n");
4902 return 0;
4903 }
4904 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4905 if (!gfx_v8_0_wait_for_idle(adev))
4906 gfx_v8_0_cp_enable(adev, false);
4907 else
4908 pr_err("cp is busy, skip halt cp\n");
4909 if (!gfx_v8_0_wait_for_rlc_idle(adev))
4910 adev->gfx.rlc.funcs->stop(adev);
4911 else
4912 pr_err("rlc is busy, skip halt rlc\n");
4913 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4914
4915 return 0;
4916}
4917
4918static int gfx_v8_0_suspend(void *handle)
4919{
4920 return gfx_v8_0_hw_fini(handle);
4921}
4922
4923static int gfx_v8_0_resume(void *handle)
4924{
4925 return gfx_v8_0_hw_init(handle);
4926}
4927
4928static bool gfx_v8_0_check_soft_reset(void *handle)
4929{
4930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4931 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4932 u32 tmp;
4933
4934 /* GRBM_STATUS */
4935 tmp = RREG32(mmGRBM_STATUS);
4936 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4937 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4938 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4939 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4940 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4941 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
4942 GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4943 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4944 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4945 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4946 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4947 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4948 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4949 }
4950
4951 /* GRBM_STATUS2 */
4952 tmp = RREG32(mmGRBM_STATUS2);
4953 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4954 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4955 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4956
4957 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
4958 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
4959 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
4960 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4961 SOFT_RESET_CPF, 1);
4962 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4963 SOFT_RESET_CPC, 1);
4964 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4965 SOFT_RESET_CPG, 1);
4966 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
4967 SOFT_RESET_GRBM, 1);
4968 }
4969
4970 /* SRBM_STATUS */
4971 tmp = RREG32(mmSRBM_STATUS);
4972 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4973 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4974 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4975 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
4976 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4977 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
4978
4979 if (grbm_soft_reset || srbm_soft_reset) {
4980 adev->gfx.grbm_soft_reset = grbm_soft_reset;
4981 adev->gfx.srbm_soft_reset = srbm_soft_reset;
4982 return true;
4983 } else {
4984 adev->gfx.grbm_soft_reset = 0;
4985 adev->gfx.srbm_soft_reset = 0;
4986 return false;
4987 }
4988}
4989
4990static int gfx_v8_0_pre_soft_reset(void *handle)
4991{
4992 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4993 u32 grbm_soft_reset = 0;
4994
4995 if ((!adev->gfx.grbm_soft_reset) &&
4996 (!adev->gfx.srbm_soft_reset))
4997 return 0;
4998
4999 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5000
5001 /* stop the rlc */
5002 adev->gfx.rlc.funcs->stop(adev);
5003
5004 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5005 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5006 /* Disable GFX parsing/prefetching */
5007 gfx_v8_0_cp_gfx_enable(adev, false);
5008
5009 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5010 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5011 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5012 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5013 int i;
5014
5015 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5016 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5017
5018 mutex_lock(&adev->srbm_mutex);
5019 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5020 gfx_v8_0_deactivate_hqd(adev, 2);
5021 vi_srbm_select(adev, 0, 0, 0, 0);
5022 mutex_unlock(&adev->srbm_mutex);
5023 }
5024 /* Disable MEC parsing/prefetching */
5025 gfx_v8_0_cp_compute_enable(adev, false);
5026 }
5027
5028 return 0;
5029}
5030
5031static int gfx_v8_0_soft_reset(void *handle)
5032{
5033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5034 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5035 u32 tmp;
5036
5037 if ((!adev->gfx.grbm_soft_reset) &&
5038 (!adev->gfx.srbm_soft_reset))
5039 return 0;
5040
5041 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5042 srbm_soft_reset = adev->gfx.srbm_soft_reset;
5043
5044 if (grbm_soft_reset || srbm_soft_reset) {
5045 tmp = RREG32(mmGMCON_DEBUG);
5046 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5047 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5048 WREG32(mmGMCON_DEBUG, tmp);
5049 udelay(50);
5050 }
5051
5052 if (grbm_soft_reset) {
5053 tmp = RREG32(mmGRBM_SOFT_RESET);
5054 tmp |= grbm_soft_reset;
5055 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5056 WREG32(mmGRBM_SOFT_RESET, tmp);
5057 tmp = RREG32(mmGRBM_SOFT_RESET);
5058
5059 udelay(50);
5060
5061 tmp &= ~grbm_soft_reset;
5062 WREG32(mmGRBM_SOFT_RESET, tmp);
5063 tmp = RREG32(mmGRBM_SOFT_RESET);
5064 }
5065
5066 if (srbm_soft_reset) {
5067 tmp = RREG32(mmSRBM_SOFT_RESET);
5068 tmp |= srbm_soft_reset;
5069 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5070 WREG32(mmSRBM_SOFT_RESET, tmp);
5071 tmp = RREG32(mmSRBM_SOFT_RESET);
5072
5073 udelay(50);
5074
5075 tmp &= ~srbm_soft_reset;
5076 WREG32(mmSRBM_SOFT_RESET, tmp);
5077 tmp = RREG32(mmSRBM_SOFT_RESET);
5078 }
5079
5080 if (grbm_soft_reset || srbm_soft_reset) {
5081 tmp = RREG32(mmGMCON_DEBUG);
5082 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5083 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5084 WREG32(mmGMCON_DEBUG, tmp);
5085 }
5086
5087 /* Wait a little for things to settle down */
5088 udelay(50);
5089
5090 return 0;
5091}
5092
5093static int gfx_v8_0_post_soft_reset(void *handle)
5094{
5095 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5096 u32 grbm_soft_reset = 0;
5097
5098 if ((!adev->gfx.grbm_soft_reset) &&
5099 (!adev->gfx.srbm_soft_reset))
5100 return 0;
5101
5102 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5103
5104 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5105 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5106 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5107 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5108 int i;
5109
5110 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5111 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5112
5113 mutex_lock(&adev->srbm_mutex);
5114 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5115 gfx_v8_0_deactivate_hqd(adev, 2);
5116 vi_srbm_select(adev, 0, 0, 0, 0);
5117 mutex_unlock(&adev->srbm_mutex);
5118 }
5119 gfx_v8_0_kiq_resume(adev);
5120 gfx_v8_0_kcq_resume(adev);
5121 }
5122
5123 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5124 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5125 gfx_v8_0_cp_gfx_resume(adev);
5126
5127 gfx_v8_0_cp_test_all_rings(adev);
5128
5129 adev->gfx.rlc.funcs->start(adev);
5130
5131 return 0;
5132}
5133
5134/**
5135 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5136 *
5137 * @adev: amdgpu_device pointer
5138 *
5139 * Fetches a GPU clock counter snapshot.
5140 * Returns the 64 bit clock counter snapshot.
5141 */
5142static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5143{
5144 uint64_t clock;
5145
5146 mutex_lock(&adev->gfx.gpu_clock_mutex);
5147 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5148 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5149 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5150 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5151 return clock;
5152}
5153
5154static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5155 uint32_t vmid,
5156 uint32_t gds_base, uint32_t gds_size,
5157 uint32_t gws_base, uint32_t gws_size,
5158 uint32_t oa_base, uint32_t oa_size)
5159{
5160 /* GDS Base */
5161 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5162 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5163 WRITE_DATA_DST_SEL(0)));
5164 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5165 amdgpu_ring_write(ring, 0);
5166 amdgpu_ring_write(ring, gds_base);
5167
5168 /* GDS Size */
5169 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5170 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5171 WRITE_DATA_DST_SEL(0)));
5172 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5173 amdgpu_ring_write(ring, 0);
5174 amdgpu_ring_write(ring, gds_size);
5175
5176 /* GWS */
5177 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5178 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5179 WRITE_DATA_DST_SEL(0)));
5180 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5181 amdgpu_ring_write(ring, 0);
5182 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5183
5184 /* OA */
5185 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5186 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5187 WRITE_DATA_DST_SEL(0)));
5188 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5189 amdgpu_ring_write(ring, 0);
5190 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5191}
5192
5193static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5194{
5195 WREG32(mmSQ_IND_INDEX,
5196 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5197 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5198 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5199 (SQ_IND_INDEX__FORCE_READ_MASK));
5200 return RREG32(mmSQ_IND_DATA);
5201}
5202
5203static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5204 uint32_t wave, uint32_t thread,
5205 uint32_t regno, uint32_t num, uint32_t *out)
5206{
5207 WREG32(mmSQ_IND_INDEX,
5208 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5209 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5210 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5211 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5212 (SQ_IND_INDEX__FORCE_READ_MASK) |
5213 (SQ_IND_INDEX__AUTO_INCR_MASK));
5214 while (num--)
5215 *(out++) = RREG32(mmSQ_IND_DATA);
5216}
5217
5218static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5219{
5220 /* type 0 wave data */
5221 dst[(*no_fields)++] = 0;
5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5226 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5227 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5228 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5229 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5230 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5231 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5232 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5233 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
5234 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5235 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5236 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5237 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5238 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5239 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
5240 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
5241}
5242
5243static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
5244 uint32_t wave, uint32_t start,
5245 uint32_t size, uint32_t *dst)
5246{
5247 wave_read_regs(
5248 adev, simd, wave, 0,
5249 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5250}
5251
5252
5253static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5254 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5255 .select_se_sh = &gfx_v8_0_select_se_sh,
5256 .read_wave_data = &gfx_v8_0_read_wave_data,
5257 .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5258 .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
5259};
5260
5261static int gfx_v8_0_early_init(void *handle)
5262{
5263 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5264
5265 adev->gfx.xcc_mask = 1;
5266 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5267 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
5268 AMDGPU_MAX_COMPUTE_RINGS);
5269 adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
5270 gfx_v8_0_set_ring_funcs(adev);
5271 gfx_v8_0_set_irq_funcs(adev);
5272 gfx_v8_0_set_gds_init(adev);
5273 gfx_v8_0_set_rlc_funcs(adev);
5274
5275 return 0;
5276}
5277
5278static int gfx_v8_0_late_init(void *handle)
5279{
5280 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5281 int r;
5282
5283 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5284 if (r)
5285 return r;
5286
5287 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5288 if (r)
5289 return r;
5290
5291 /* requires IBs so do in late init after IB pool is initialized */
5292 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5293 if (r)
5294 return r;
5295
5296 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
5297 if (r) {
5298 DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r);
5299 return r;
5300 }
5301
5302 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);
5303 if (r) {
5304 DRM_ERROR(
5305 "amdgpu_irq_get() failed to get IRQ for SQ, r: %d.\n",
5306 r);
5307 return r;
5308 }
5309
5310 return 0;
5311}
5312
5313static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5314 bool enable)
5315{
5316 if ((adev->asic_type == CHIP_POLARIS11) ||
5317 (adev->asic_type == CHIP_POLARIS12) ||
5318 (adev->asic_type == CHIP_VEGAM))
5319 /* Send msg to SMU via Powerplay */
5320 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
5321
5322 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5323}
5324
5325static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5326 bool enable)
5327{
5328 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5329}
5330
5331static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5332 bool enable)
5333{
5334 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5335}
5336
5337static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5338 bool enable)
5339{
5340 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5341}
5342
5343static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5344 bool enable)
5345{
5346 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
5347
5348 /* Read any GFX register to wake up GFX. */
5349 if (!enable)
5350 RREG32(mmDB_RENDER_CONTROL);
5351}
5352
5353static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5354 bool enable)
5355{
5356 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5357 cz_enable_gfx_cg_power_gating(adev, true);
5358 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5359 cz_enable_gfx_pipeline_power_gating(adev, true);
5360 } else {
5361 cz_enable_gfx_cg_power_gating(adev, false);
5362 cz_enable_gfx_pipeline_power_gating(adev, false);
5363 }
5364}
5365
5366static int gfx_v8_0_set_powergating_state(void *handle,
5367 enum amd_powergating_state state)
5368{
5369 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5370 bool enable = (state == AMD_PG_STATE_GATE);
5371
5372 if (amdgpu_sriov_vf(adev))
5373 return 0;
5374
5375 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5376 AMD_PG_SUPPORT_RLC_SMU_HS |
5377 AMD_PG_SUPPORT_CP |
5378 AMD_PG_SUPPORT_GFX_DMG))
5379 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5380 switch (adev->asic_type) {
5381 case CHIP_CARRIZO:
5382 case CHIP_STONEY:
5383
5384 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5385 cz_enable_sck_slow_down_on_power_up(adev, true);
5386 cz_enable_sck_slow_down_on_power_down(adev, true);
5387 } else {
5388 cz_enable_sck_slow_down_on_power_up(adev, false);
5389 cz_enable_sck_slow_down_on_power_down(adev, false);
5390 }
5391 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5392 cz_enable_cp_power_gating(adev, true);
5393 else
5394 cz_enable_cp_power_gating(adev, false);
5395
5396 cz_update_gfx_cg_power_gating(adev, enable);
5397
5398 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5399 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5400 else
5401 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5402
5403 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5404 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5405 else
5406 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5407 break;
5408 case CHIP_POLARIS11:
5409 case CHIP_POLARIS12:
5410 case CHIP_VEGAM:
5411 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5412 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5413 else
5414 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5415
5416 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5417 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5418 else
5419 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5420
5421 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5422 polaris11_enable_gfx_quick_mg_power_gating(adev, true);
5423 else
5424 polaris11_enable_gfx_quick_mg_power_gating(adev, false);
5425 break;
5426 default:
5427 break;
5428 }
5429 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5430 AMD_PG_SUPPORT_RLC_SMU_HS |
5431 AMD_PG_SUPPORT_CP |
5432 AMD_PG_SUPPORT_GFX_DMG))
5433 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5434 return 0;
5435}
5436
5437static void gfx_v8_0_get_clockgating_state(void *handle, u64 *flags)
5438{
5439 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5440 int data;
5441
5442 if (amdgpu_sriov_vf(adev))
5443 *flags = 0;
5444
5445 /* AMD_CG_SUPPORT_GFX_MGCG */
5446 data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5447 if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
5448 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5449
5450 /* AMD_CG_SUPPORT_GFX_CGLG */
5451 data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5452 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5453 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5454
5455 /* AMD_CG_SUPPORT_GFX_CGLS */
5456 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5457 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5458
5459 /* AMD_CG_SUPPORT_GFX_CGTS */
5460 data = RREG32(mmCGTS_SM_CTRL_REG);
5461 if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
5462 *flags |= AMD_CG_SUPPORT_GFX_CGTS;
5463
5464 /* AMD_CG_SUPPORT_GFX_CGTS_LS */
5465 if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
5466 *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
5467
5468 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5469 data = RREG32(mmRLC_MEM_SLP_CNTL);
5470 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5471 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5472
5473 /* AMD_CG_SUPPORT_GFX_CP_LS */
5474 data = RREG32(mmCP_MEM_SLP_CNTL);
5475 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5476 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5477}
5478
5479static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
5480 uint32_t reg_addr, uint32_t cmd)
5481{
5482 uint32_t data;
5483
5484 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5485
5486 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5487 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5488
5489 data = RREG32(mmRLC_SERDES_WR_CTRL);
5490 if (adev->asic_type == CHIP_STONEY)
5491 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5492 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5493 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5494 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5495 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5496 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5497 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5498 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5499 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5500 else
5501 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5502 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5503 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5504 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5505 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5506 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5507 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5508 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5509 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5510 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5511 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5512 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
5513 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5514 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5515 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
5516
5517 WREG32(mmRLC_SERDES_WR_CTRL, data);
5518}
5519
5520#define MSG_ENTER_RLC_SAFE_MODE 1
5521#define MSG_EXIT_RLC_SAFE_MODE 0
5522#define RLC_GPR_REG2__REQ_MASK 0x00000001
5523#define RLC_GPR_REG2__REQ__SHIFT 0
5524#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5525#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5526
5527static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
5528{
5529 uint32_t rlc_setting;
5530
5531 rlc_setting = RREG32(mmRLC_CNTL);
5532 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
5533 return false;
5534
5535 return true;
5536}
5537
5538static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
5539{
5540 uint32_t data;
5541 unsigned i;
5542 data = RREG32(mmRLC_CNTL);
5543 data |= RLC_SAFE_MODE__CMD_MASK;
5544 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5545 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5546 WREG32(mmRLC_SAFE_MODE, data);
5547
5548 /* wait for RLC_SAFE_MODE */
5549 for (i = 0; i < adev->usec_timeout; i++) {
5550 if ((RREG32(mmRLC_GPM_STAT) &
5551 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5552 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5553 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5554 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5555 break;
5556 udelay(1);
5557 }
5558 for (i = 0; i < adev->usec_timeout; i++) {
5559 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5560 break;
5561 udelay(1);
5562 }
5563}
5564
5565static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
5566{
5567 uint32_t data;
5568 unsigned i;
5569
5570 data = RREG32(mmRLC_CNTL);
5571 data |= RLC_SAFE_MODE__CMD_MASK;
5572 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5573 WREG32(mmRLC_SAFE_MODE, data);
5574
5575 for (i = 0; i < adev->usec_timeout; i++) {
5576 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5577 break;
5578 udelay(1);
5579 }
5580}
5581
5582static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5583{
5584 u32 data;
5585
5586 amdgpu_gfx_off_ctrl(adev, false);
5587
5588 if (amdgpu_sriov_is_pp_one_vf(adev))
5589 data = RREG32_NO_KIQ(mmRLC_SPM_VMID);
5590 else
5591 data = RREG32(mmRLC_SPM_VMID);
5592
5593 data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
5594 data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
5595
5596 if (amdgpu_sriov_is_pp_one_vf(adev))
5597 WREG32_NO_KIQ(mmRLC_SPM_VMID, data);
5598 else
5599 WREG32(mmRLC_SPM_VMID, data);
5600
5601 amdgpu_gfx_off_ctrl(adev, true);
5602}
5603
5604static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5605 .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
5606 .set_safe_mode = gfx_v8_0_set_safe_mode,
5607 .unset_safe_mode = gfx_v8_0_unset_safe_mode,
5608 .init = gfx_v8_0_rlc_init,
5609 .get_csb_size = gfx_v8_0_get_csb_size,
5610 .get_csb_buffer = gfx_v8_0_get_csb_buffer,
5611 .get_cp_table_num = gfx_v8_0_cp_jump_table_num,
5612 .resume = gfx_v8_0_rlc_resume,
5613 .stop = gfx_v8_0_rlc_stop,
5614 .reset = gfx_v8_0_rlc_reset,
5615 .start = gfx_v8_0_rlc_start,
5616 .update_spm_vmid = gfx_v8_0_update_spm_vmid
5617};
5618
5619static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5620 bool enable)
5621{
5622 uint32_t temp, data;
5623
5624 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5625
5626 /* It is disabled by HW by default */
5627 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5628 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5629 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
5630 /* 1 - RLC memory Light sleep */
5631 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
5632
5633 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5634 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
5635 }
5636
5637 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5638 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5639 if (adev->flags & AMD_IS_APU)
5640 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5641 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5642 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5643 else
5644 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5645 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5646 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5647 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5648
5649 if (temp != data)
5650 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5651
5652 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5653 gfx_v8_0_wait_for_rlc_serdes(adev);
5654
5655 /* 5 - clear mgcg override */
5656 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5657
5658 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5659 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5660 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5661 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5662 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5663 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5664 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5665 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5666 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5667 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5668 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5669 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5670 if (temp != data)
5671 WREG32(mmCGTS_SM_CTRL_REG, data);
5672 }
5673 udelay(50);
5674
5675 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5676 gfx_v8_0_wait_for_rlc_serdes(adev);
5677 } else {
5678 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5679 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5680 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5681 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5682 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5683 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5684 if (temp != data)
5685 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5686
5687 /* 2 - disable MGLS in RLC */
5688 data = RREG32(mmRLC_MEM_SLP_CNTL);
5689 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5690 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5691 WREG32(mmRLC_MEM_SLP_CNTL, data);
5692 }
5693
5694 /* 3 - disable MGLS in CP */
5695 data = RREG32(mmCP_MEM_SLP_CNTL);
5696 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5697 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5698 WREG32(mmCP_MEM_SLP_CNTL, data);
5699 }
5700
5701 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5702 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5703 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5704 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5705 if (temp != data)
5706 WREG32(mmCGTS_SM_CTRL_REG, data);
5707
5708 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5709 gfx_v8_0_wait_for_rlc_serdes(adev);
5710
5711 /* 6 - set mgcg override */
5712 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5713
5714 udelay(50);
5715
5716 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5717 gfx_v8_0_wait_for_rlc_serdes(adev);
5718 }
5719
5720 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5721}
5722
5723static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5724 bool enable)
5725{
5726 uint32_t temp, temp1, data, data1;
5727
5728 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5729
5730 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5731
5732 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5733 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5734 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5735 if (temp1 != data1)
5736 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5737
5738 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5739 gfx_v8_0_wait_for_rlc_serdes(adev);
5740
5741 /* 2 - clear cgcg override */
5742 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5743
5744 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5745 gfx_v8_0_wait_for_rlc_serdes(adev);
5746
5747 /* 3 - write cmd to set CGLS */
5748 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5749
5750 /* 4 - enable cgcg */
5751 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5752
5753 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5754 /* enable cgls*/
5755 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5756
5757 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5758 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
5759
5760 if (temp1 != data1)
5761 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5762 } else {
5763 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5764 }
5765
5766 if (temp != data)
5767 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5768
5769 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5770 * Cmp_busy/GFX_Idle interrupts
5771 */
5772 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5773 } else {
5774 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5775 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5776
5777 /* TEST CGCG */
5778 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5779 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5780 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5781 if (temp1 != data1)
5782 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5783
5784 /* read gfx register to wake up cgcg */
5785 RREG32(mmCB_CGTT_SCLK_CTRL);
5786 RREG32(mmCB_CGTT_SCLK_CTRL);
5787 RREG32(mmCB_CGTT_SCLK_CTRL);
5788 RREG32(mmCB_CGTT_SCLK_CTRL);
5789
5790 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5791 gfx_v8_0_wait_for_rlc_serdes(adev);
5792
5793 /* write cmd to Set CGCG Override */
5794 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5795
5796 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5797 gfx_v8_0_wait_for_rlc_serdes(adev);
5798
5799 /* write cmd to Clear CGLS */
5800 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
5801
5802 /* disable cgcg, cgls should be disabled too. */
5803 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
5804 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
5805 if (temp != data)
5806 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5807 /* enable interrupts again for PG */
5808 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5809 }
5810
5811 gfx_v8_0_wait_for_rlc_serdes(adev);
5812
5813 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5814}
5815static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5816 bool enable)
5817{
5818 if (enable) {
5819 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5820 * === MGCG + MGLS + TS(CG/LS) ===
5821 */
5822 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5823 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5824 } else {
5825 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5826 * === CGCG + CGLS ===
5827 */
5828 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5829 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5830 }
5831 return 0;
5832}
5833
5834static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5835 enum amd_clockgating_state state)
5836{
5837 uint32_t msg_id, pp_state = 0;
5838 uint32_t pp_support_state = 0;
5839
5840 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5841 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5842 pp_support_state = PP_STATE_SUPPORT_LS;
5843 pp_state = PP_STATE_LS;
5844 }
5845 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5846 pp_support_state |= PP_STATE_SUPPORT_CG;
5847 pp_state |= PP_STATE_CG;
5848 }
5849 if (state == AMD_CG_STATE_UNGATE)
5850 pp_state = 0;
5851
5852 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5853 PP_BLOCK_GFX_CG,
5854 pp_support_state,
5855 pp_state);
5856 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5857 }
5858
5859 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5860 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5861 pp_support_state = PP_STATE_SUPPORT_LS;
5862 pp_state = PP_STATE_LS;
5863 }
5864
5865 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5866 pp_support_state |= PP_STATE_SUPPORT_CG;
5867 pp_state |= PP_STATE_CG;
5868 }
5869
5870 if (state == AMD_CG_STATE_UNGATE)
5871 pp_state = 0;
5872
5873 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5874 PP_BLOCK_GFX_MG,
5875 pp_support_state,
5876 pp_state);
5877 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5878 }
5879
5880 return 0;
5881}
5882
5883static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5884 enum amd_clockgating_state state)
5885{
5886
5887 uint32_t msg_id, pp_state = 0;
5888 uint32_t pp_support_state = 0;
5889
5890 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5891 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5892 pp_support_state = PP_STATE_SUPPORT_LS;
5893 pp_state = PP_STATE_LS;
5894 }
5895 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5896 pp_support_state |= PP_STATE_SUPPORT_CG;
5897 pp_state |= PP_STATE_CG;
5898 }
5899 if (state == AMD_CG_STATE_UNGATE)
5900 pp_state = 0;
5901
5902 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5903 PP_BLOCK_GFX_CG,
5904 pp_support_state,
5905 pp_state);
5906 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5907 }
5908
5909 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5910 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5911 pp_support_state = PP_STATE_SUPPORT_LS;
5912 pp_state = PP_STATE_LS;
5913 }
5914 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5915 pp_support_state |= PP_STATE_SUPPORT_CG;
5916 pp_state |= PP_STATE_CG;
5917 }
5918 if (state == AMD_CG_STATE_UNGATE)
5919 pp_state = 0;
5920
5921 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5922 PP_BLOCK_GFX_3D,
5923 pp_support_state,
5924 pp_state);
5925 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5926 }
5927
5928 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5929 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5930 pp_support_state = PP_STATE_SUPPORT_LS;
5931 pp_state = PP_STATE_LS;
5932 }
5933
5934 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5935 pp_support_state |= PP_STATE_SUPPORT_CG;
5936 pp_state |= PP_STATE_CG;
5937 }
5938
5939 if (state == AMD_CG_STATE_UNGATE)
5940 pp_state = 0;
5941
5942 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5943 PP_BLOCK_GFX_MG,
5944 pp_support_state,
5945 pp_state);
5946 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5947 }
5948
5949 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5950 pp_support_state = PP_STATE_SUPPORT_LS;
5951
5952 if (state == AMD_CG_STATE_UNGATE)
5953 pp_state = 0;
5954 else
5955 pp_state = PP_STATE_LS;
5956
5957 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5958 PP_BLOCK_GFX_RLC,
5959 pp_support_state,
5960 pp_state);
5961 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5962 }
5963
5964 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5965 pp_support_state = PP_STATE_SUPPORT_LS;
5966
5967 if (state == AMD_CG_STATE_UNGATE)
5968 pp_state = 0;
5969 else
5970 pp_state = PP_STATE_LS;
5971 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5972 PP_BLOCK_GFX_CP,
5973 pp_support_state,
5974 pp_state);
5975 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5976 }
5977
5978 return 0;
5979}
5980
5981static int gfx_v8_0_set_clockgating_state(void *handle,
5982 enum amd_clockgating_state state)
5983{
5984 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5985
5986 if (amdgpu_sriov_vf(adev))
5987 return 0;
5988
5989 switch (adev->asic_type) {
5990 case CHIP_FIJI:
5991 case CHIP_CARRIZO:
5992 case CHIP_STONEY:
5993 gfx_v8_0_update_gfx_clock_gating(adev,
5994 state == AMD_CG_STATE_GATE);
5995 break;
5996 case CHIP_TONGA:
5997 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
5998 break;
5999 case CHIP_POLARIS10:
6000 case CHIP_POLARIS11:
6001 case CHIP_POLARIS12:
6002 case CHIP_VEGAM:
6003 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
6004 break;
6005 default:
6006 break;
6007 }
6008 return 0;
6009}
6010
6011static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
6012{
6013 return *ring->rptr_cpu_addr;
6014}
6015
6016static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
6017{
6018 struct amdgpu_device *adev = ring->adev;
6019
6020 if (ring->use_doorbell)
6021 /* XXX check if swapping is necessary on BE */
6022 return *ring->wptr_cpu_addr;
6023 else
6024 return RREG32(mmCP_RB0_WPTR);
6025}
6026
6027static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
6028{
6029 struct amdgpu_device *adev = ring->adev;
6030
6031 if (ring->use_doorbell) {
6032 /* XXX check if swapping is necessary on BE */
6033 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
6034 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6035 } else {
6036 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6037 (void)RREG32(mmCP_RB0_WPTR);
6038 }
6039}
6040
6041static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6042{
6043 u32 ref_and_mask, reg_mem_engine;
6044
6045 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||
6046 (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {
6047 switch (ring->me) {
6048 case 1:
6049 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6050 break;
6051 case 2:
6052 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6053 break;
6054 default:
6055 return;
6056 }
6057 reg_mem_engine = 0;
6058 } else {
6059 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6060 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
6061 }
6062
6063 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6064 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
6065 WAIT_REG_MEM_FUNCTION(3) | /* == */
6066 reg_mem_engine));
6067 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
6068 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
6069 amdgpu_ring_write(ring, ref_and_mask);
6070 amdgpu_ring_write(ring, ref_and_mask);
6071 amdgpu_ring_write(ring, 0x20); /* poll interval */
6072}
6073
6074static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6075{
6076 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6077 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6078 EVENT_INDEX(4));
6079
6080 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6081 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6082 EVENT_INDEX(0));
6083}
6084
6085static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6086 struct amdgpu_job *job,
6087 struct amdgpu_ib *ib,
6088 uint32_t flags)
6089{
6090 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6091 u32 header, control = 0;
6092
6093 if (ib->flags & AMDGPU_IB_FLAG_CE)
6094 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
6095 else
6096 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6097
6098 control |= ib->length_dw | (vmid << 24);
6099
6100 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6101 control |= INDIRECT_BUFFER_PRE_ENB(1);
6102
6103 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
6104 gfx_v8_0_ring_emit_de_meta(ring);
6105 }
6106
6107 amdgpu_ring_write(ring, header);
6108 amdgpu_ring_write(ring,
6109#ifdef __BIG_ENDIAN
6110 (2 << 0) |
6111#endif
6112 (ib->gpu_addr & 0xFFFFFFFC));
6113 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6114 amdgpu_ring_write(ring, control);
6115}
6116
6117static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6118 struct amdgpu_job *job,
6119 struct amdgpu_ib *ib,
6120 uint32_t flags)
6121{
6122 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6123 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6124
6125 /* Currently, there is a high possibility to get wave ID mismatch
6126 * between ME and GDS, leading to a hw deadlock, because ME generates
6127 * different wave IDs than the GDS expects. This situation happens
6128 * randomly when at least 5 compute pipes use GDS ordered append.
6129 * The wave IDs generated by ME are also wrong after suspend/resume.
6130 * Those are probably bugs somewhere else in the kernel driver.
6131 *
6132 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
6133 * GDS to 0 for this ring (me/pipe).
6134 */
6135 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
6136 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
6137 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
6138 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
6139 }
6140
6141 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6142 amdgpu_ring_write(ring,
6143#ifdef __BIG_ENDIAN
6144 (2 << 0) |
6145#endif
6146 (ib->gpu_addr & 0xFFFFFFFC));
6147 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6148 amdgpu_ring_write(ring, control);
6149}
6150
6151static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
6152 u64 seq, unsigned flags)
6153{
6154 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6155 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6156
6157 /* Workaround for cache flush problems. First send a dummy EOP
6158 * event down the pipe with seq one below.
6159 */
6160 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6161 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6162 EOP_TC_ACTION_EN |
6163 EOP_TC_WB_ACTION_EN |
6164 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6165 EVENT_INDEX(5)));
6166 amdgpu_ring_write(ring, addr & 0xfffffffc);
6167 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6168 DATA_SEL(1) | INT_SEL(0));
6169 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
6170 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
6171
6172 /* Then send the real EOP event down the pipe:
6173 * EVENT_WRITE_EOP - flush caches, send int */
6174 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6175 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6176 EOP_TC_ACTION_EN |
6177 EOP_TC_WB_ACTION_EN |
6178 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6179 EVENT_INDEX(5)));
6180 amdgpu_ring_write(ring, addr & 0xfffffffc);
6181 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6182 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6183 amdgpu_ring_write(ring, lower_32_bits(seq));
6184 amdgpu_ring_write(ring, upper_32_bits(seq));
6185
6186}
6187
6188static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6189{
6190 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6191 uint32_t seq = ring->fence_drv.sync_seq;
6192 uint64_t addr = ring->fence_drv.gpu_addr;
6193
6194 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6195 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
6196 WAIT_REG_MEM_FUNCTION(3) | /* equal */
6197 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
6198 amdgpu_ring_write(ring, addr & 0xfffffffc);
6199 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6200 amdgpu_ring_write(ring, seq);
6201 amdgpu_ring_write(ring, 0xffffffff);
6202 amdgpu_ring_write(ring, 4); /* poll interval */
6203}
6204
6205static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6206 unsigned vmid, uint64_t pd_addr)
6207{
6208 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6209
6210 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6211
6212 /* wait for the invalidate to complete */
6213 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6214 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6215 WAIT_REG_MEM_FUNCTION(0) | /* always */
6216 WAIT_REG_MEM_ENGINE(0))); /* me */
6217 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6218 amdgpu_ring_write(ring, 0);
6219 amdgpu_ring_write(ring, 0); /* ref */
6220 amdgpu_ring_write(ring, 0); /* mask */
6221 amdgpu_ring_write(ring, 0x20); /* poll interval */
6222
6223 /* compute doesn't have PFP */
6224 if (usepfp) {
6225 /* sync PFP to ME, otherwise we might get invalid PFP reads */
6226 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6227 amdgpu_ring_write(ring, 0x0);
6228 }
6229}
6230
6231static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6232{
6233 return *ring->wptr_cpu_addr;
6234}
6235
6236static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6237{
6238 struct amdgpu_device *adev = ring->adev;
6239
6240 /* XXX check if swapping is necessary on BE */
6241 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
6242 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6243}
6244
6245static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6246 u64 addr, u64 seq,
6247 unsigned flags)
6248{
6249 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6250 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6251
6252 /* RELEASE_MEM - flush caches, send int */
6253 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6254 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6255 EOP_TC_ACTION_EN |
6256 EOP_TC_WB_ACTION_EN |
6257 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6258 EVENT_INDEX(5)));
6259 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6260 amdgpu_ring_write(ring, addr & 0xfffffffc);
6261 amdgpu_ring_write(ring, upper_32_bits(addr));
6262 amdgpu_ring_write(ring, lower_32_bits(seq));
6263 amdgpu_ring_write(ring, upper_32_bits(seq));
6264}
6265
6266static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
6267 u64 seq, unsigned int flags)
6268{
6269 /* we only allocate 32bit for each seq wb address */
6270 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
6271
6272 /* write fence seq to the "addr" */
6273 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6274 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6275 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
6276 amdgpu_ring_write(ring, lower_32_bits(addr));
6277 amdgpu_ring_write(ring, upper_32_bits(addr));
6278 amdgpu_ring_write(ring, lower_32_bits(seq));
6279
6280 if (flags & AMDGPU_FENCE_FLAG_INT) {
6281 /* set register to trigger INT */
6282 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6283 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6284 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
6285 amdgpu_ring_write(ring, mmCPC_INT_STATUS);
6286 amdgpu_ring_write(ring, 0);
6287 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
6288 }
6289}
6290
6291static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6292{
6293 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6294 amdgpu_ring_write(ring, 0);
6295}
6296
6297static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6298{
6299 uint32_t dw2 = 0;
6300
6301 if (amdgpu_sriov_vf(ring->adev))
6302 gfx_v8_0_ring_emit_ce_meta(ring);
6303
6304 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6305 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6306 gfx_v8_0_ring_emit_vgt_flush(ring);
6307 /* set load_global_config & load_global_uconfig */
6308 dw2 |= 0x8001;
6309 /* set load_cs_sh_regs */
6310 dw2 |= 0x01000000;
6311 /* set load_per_context_state & load_gfx_sh_regs for GFX */
6312 dw2 |= 0x10002;
6313
6314 /* set load_ce_ram if preamble presented */
6315 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6316 dw2 |= 0x10000000;
6317 } else {
6318 /* still load_ce_ram if this is the first time preamble presented
6319 * although there is no context switch happens.
6320 */
6321 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6322 dw2 |= 0x10000000;
6323 }
6324
6325 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6326 amdgpu_ring_write(ring, dw2);
6327 amdgpu_ring_write(ring, 0);
6328}
6329
6330static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
6331{
6332 unsigned ret;
6333
6334 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
6335 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
6336 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
6337 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
6338 ret = ring->wptr & ring->buf_mask;
6339 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
6340 return ret;
6341}
6342
6343static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
6344{
6345 unsigned cur;
6346
6347 BUG_ON(offset > ring->buf_mask);
6348 BUG_ON(ring->ring[offset] != 0x55aa55aa);
6349
6350 cur = (ring->wptr & ring->buf_mask) - 1;
6351 if (likely(cur > offset))
6352 ring->ring[offset] = cur - offset;
6353 else
6354 ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
6355}
6356
6357static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
6358 uint32_t reg_val_offs)
6359{
6360 struct amdgpu_device *adev = ring->adev;
6361
6362 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6363 amdgpu_ring_write(ring, 0 | /* src: register*/
6364 (5 << 8) | /* dst: memory */
6365 (1 << 20)); /* write confirm */
6366 amdgpu_ring_write(ring, reg);
6367 amdgpu_ring_write(ring, 0);
6368 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6369 reg_val_offs * 4));
6370 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6371 reg_val_offs * 4));
6372}
6373
6374static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6375 uint32_t val)
6376{
6377 uint32_t cmd;
6378
6379 switch (ring->funcs->type) {
6380 case AMDGPU_RING_TYPE_GFX:
6381 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6382 break;
6383 case AMDGPU_RING_TYPE_KIQ:
6384 cmd = 1 << 16; /* no inc addr */
6385 break;
6386 default:
6387 cmd = WR_CONFIRM;
6388 break;
6389 }
6390
6391 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6392 amdgpu_ring_write(ring, cmd);
6393 amdgpu_ring_write(ring, reg);
6394 amdgpu_ring_write(ring, 0);
6395 amdgpu_ring_write(ring, val);
6396}
6397
6398static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
6399{
6400 struct amdgpu_device *adev = ring->adev;
6401 uint32_t value = 0;
6402
6403 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6404 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6405 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6406 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6407 WREG32(mmSQ_CMD, value);
6408}
6409
6410static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6411 enum amdgpu_interrupt_state state)
6412{
6413 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6414 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6415}
6416
6417static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6418 int me, int pipe,
6419 enum amdgpu_interrupt_state state)
6420{
6421 u32 mec_int_cntl, mec_int_cntl_reg;
6422
6423 /*
6424 * amdgpu controls only the first MEC. That's why this function only
6425 * handles the setting of interrupts for this specific MEC. All other
6426 * pipes' interrupts are set by amdkfd.
6427 */
6428
6429 if (me == 1) {
6430 switch (pipe) {
6431 case 0:
6432 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6433 break;
6434 case 1:
6435 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6436 break;
6437 case 2:
6438 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6439 break;
6440 case 3:
6441 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6442 break;
6443 default:
6444 DRM_DEBUG("invalid pipe %d\n", pipe);
6445 return;
6446 }
6447 } else {
6448 DRM_DEBUG("invalid me %d\n", me);
6449 return;
6450 }
6451
6452 switch (state) {
6453 case AMDGPU_IRQ_STATE_DISABLE:
6454 mec_int_cntl = RREG32(mec_int_cntl_reg);
6455 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6456 WREG32(mec_int_cntl_reg, mec_int_cntl);
6457 break;
6458 case AMDGPU_IRQ_STATE_ENABLE:
6459 mec_int_cntl = RREG32(mec_int_cntl_reg);
6460 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6461 WREG32(mec_int_cntl_reg, mec_int_cntl);
6462 break;
6463 default:
6464 break;
6465 }
6466}
6467
6468static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6469 struct amdgpu_irq_src *source,
6470 unsigned type,
6471 enum amdgpu_interrupt_state state)
6472{
6473 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6474 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6475
6476 return 0;
6477}
6478
6479static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6480 struct amdgpu_irq_src *source,
6481 unsigned type,
6482 enum amdgpu_interrupt_state state)
6483{
6484 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6485 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6486
6487 return 0;
6488}
6489
6490static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6491 struct amdgpu_irq_src *src,
6492 unsigned type,
6493 enum amdgpu_interrupt_state state)
6494{
6495 switch (type) {
6496 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
6497 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6498 break;
6499 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6500 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6501 break;
6502 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6503 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6504 break;
6505 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6506 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6507 break;
6508 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6509 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6510 break;
6511 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6512 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6513 break;
6514 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6515 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6516 break;
6517 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6518 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6519 break;
6520 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6521 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6522 break;
6523 default:
6524 break;
6525 }
6526 return 0;
6527}
6528
6529static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev,
6530 struct amdgpu_irq_src *source,
6531 unsigned int type,
6532 enum amdgpu_interrupt_state state)
6533{
6534 int enable_flag;
6535
6536 switch (state) {
6537 case AMDGPU_IRQ_STATE_DISABLE:
6538 enable_flag = 0;
6539 break;
6540
6541 case AMDGPU_IRQ_STATE_ENABLE:
6542 enable_flag = 1;
6543 break;
6544
6545 default:
6546 return -EINVAL;
6547 }
6548
6549 WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6550 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6551 WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6552 WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6553 WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6554 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6555 enable_flag);
6556 WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6557 enable_flag);
6558 WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6559 enable_flag);
6560 WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6561 enable_flag);
6562 WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6563 enable_flag);
6564 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6565 enable_flag);
6566 WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6567 enable_flag);
6568 WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6569 enable_flag);
6570
6571 return 0;
6572}
6573
6574static int gfx_v8_0_set_sq_int_state(struct amdgpu_device *adev,
6575 struct amdgpu_irq_src *source,
6576 unsigned int type,
6577 enum amdgpu_interrupt_state state)
6578{
6579 int enable_flag;
6580
6581 switch (state) {
6582 case AMDGPU_IRQ_STATE_DISABLE:
6583 enable_flag = 1;
6584 break;
6585
6586 case AMDGPU_IRQ_STATE_ENABLE:
6587 enable_flag = 0;
6588 break;
6589
6590 default:
6591 return -EINVAL;
6592 }
6593
6594 WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,
6595 enable_flag);
6596
6597 return 0;
6598}
6599
6600static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6601 struct amdgpu_irq_src *source,
6602 struct amdgpu_iv_entry *entry)
6603{
6604 int i;
6605 u8 me_id, pipe_id, queue_id;
6606 struct amdgpu_ring *ring;
6607
6608 DRM_DEBUG("IH: CP EOP\n");
6609 me_id = (entry->ring_id & 0x0c) >> 2;
6610 pipe_id = (entry->ring_id & 0x03) >> 0;
6611 queue_id = (entry->ring_id & 0x70) >> 4;
6612
6613 switch (me_id) {
6614 case 0:
6615 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6616 break;
6617 case 1:
6618 case 2:
6619 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6620 ring = &adev->gfx.compute_ring[i];
6621 /* Per-queue interrupt is supported for MEC starting from VI.
6622 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6623 */
6624 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6625 amdgpu_fence_process(ring);
6626 }
6627 break;
6628 }
6629 return 0;
6630}
6631
6632static void gfx_v8_0_fault(struct amdgpu_device *adev,
6633 struct amdgpu_iv_entry *entry)
6634{
6635 u8 me_id, pipe_id, queue_id;
6636 struct amdgpu_ring *ring;
6637 int i;
6638
6639 me_id = (entry->ring_id & 0x0c) >> 2;
6640 pipe_id = (entry->ring_id & 0x03) >> 0;
6641 queue_id = (entry->ring_id & 0x70) >> 4;
6642
6643 switch (me_id) {
6644 case 0:
6645 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
6646 break;
6647 case 1:
6648 case 2:
6649 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6650 ring = &adev->gfx.compute_ring[i];
6651 if (ring->me == me_id && ring->pipe == pipe_id &&
6652 ring->queue == queue_id)
6653 drm_sched_fault(&ring->sched);
6654 }
6655 break;
6656 }
6657}
6658
6659static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6660 struct amdgpu_irq_src *source,
6661 struct amdgpu_iv_entry *entry)
6662{
6663 DRM_ERROR("Illegal register access in command stream\n");
6664 gfx_v8_0_fault(adev, entry);
6665 return 0;
6666}
6667
6668static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6669 struct amdgpu_irq_src *source,
6670 struct amdgpu_iv_entry *entry)
6671{
6672 DRM_ERROR("Illegal instruction in command stream\n");
6673 gfx_v8_0_fault(adev, entry);
6674 return 0;
6675}
6676
6677static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev,
6678 struct amdgpu_irq_src *source,
6679 struct amdgpu_iv_entry *entry)
6680{
6681 DRM_ERROR("CP EDC/ECC error detected.");
6682 return 0;
6683}
6684
6685static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data,
6686 bool from_wq)
6687{
6688 u32 enc, se_id, sh_id, cu_id;
6689 char type[20];
6690 int sq_edc_source = -1;
6691
6692 enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
6693 se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
6694
6695 switch (enc) {
6696 case 0:
6697 DRM_INFO("SQ general purpose intr detected:"
6698 "se_id %d, immed_overflow %d, host_reg_overflow %d,"
6699 "host_cmd_overflow %d, cmd_timestamp %d,"
6700 "reg_timestamp %d, thread_trace_buff_full %d,"
6701 "wlt %d, thread_trace %d.\n",
6702 se_id,
6703 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
6704 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
6705 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
6706 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
6707 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
6708 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
6709 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
6710 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
6711 );
6712 break;
6713 case 1:
6714 case 2:
6715
6716 cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
6717 sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
6718
6719 /*
6720 * This function can be called either directly from ISR
6721 * or from BH in which case we can access SQ_EDC_INFO
6722 * instance
6723 */
6724 if (from_wq) {
6725 mutex_lock(&adev->grbm_idx_mutex);
6726 gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id, 0);
6727
6728 sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
6729
6730 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
6731 mutex_unlock(&adev->grbm_idx_mutex);
6732 }
6733
6734 if (enc == 1)
6735 sprintf(type, "instruction intr");
6736 else
6737 sprintf(type, "EDC/ECC error");
6738
6739 DRM_INFO(
6740 "SQ %s detected: "
6741 "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d "
6742 "trap %s, sq_ed_info.source %s.\n",
6743 type, se_id, sh_id, cu_id,
6744 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
6745 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
6746 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
6747 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
6748 (sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable"
6749 );
6750 break;
6751 default:
6752 DRM_ERROR("SQ invalid encoding type\n.");
6753 }
6754}
6755
6756static void gfx_v8_0_sq_irq_work_func(struct work_struct *work)
6757{
6758
6759 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work);
6760 struct sq_work *sq_work = container_of(work, struct sq_work, work);
6761
6762 gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data, true);
6763}
6764
6765static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
6766 struct amdgpu_irq_src *source,
6767 struct amdgpu_iv_entry *entry)
6768{
6769 unsigned ih_data = entry->src_data[0];
6770
6771 /*
6772 * Try to submit work so SQ_EDC_INFO can be accessed from
6773 * BH. If previous work submission hasn't finished yet
6774 * just print whatever info is possible directly from the ISR.
6775 */
6776 if (work_pending(&adev->gfx.sq_work.work)) {
6777 gfx_v8_0_parse_sq_irq(adev, ih_data, false);
6778 } else {
6779 adev->gfx.sq_work.ih_data = ih_data;
6780 schedule_work(&adev->gfx.sq_work.work);
6781 }
6782
6783 return 0;
6784}
6785
6786static void gfx_v8_0_emit_mem_sync(struct amdgpu_ring *ring)
6787{
6788 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
6789 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6790 PACKET3_TC_ACTION_ENA |
6791 PACKET3_SH_KCACHE_ACTION_ENA |
6792 PACKET3_SH_ICACHE_ACTION_ENA |
6793 PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6794 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6795 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6796 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6797}
6798
6799static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
6800{
6801 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
6802 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6803 PACKET3_TC_ACTION_ENA |
6804 PACKET3_SH_KCACHE_ACTION_ENA |
6805 PACKET3_SH_ICACHE_ACTION_ENA |
6806 PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6807 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6808 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */
6809 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6810 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
6811 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6812}
6813
6814
6815/* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
6816#define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f
6817static void gfx_v8_0_emit_wave_limit_cs(struct amdgpu_ring *ring,
6818 uint32_t pipe, bool enable)
6819{
6820 uint32_t val;
6821 uint32_t wcl_cs_reg;
6822
6823 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;
6824
6825 switch (pipe) {
6826 case 0:
6827 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0;
6828 break;
6829 case 1:
6830 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1;
6831 break;
6832 case 2:
6833 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2;
6834 break;
6835 case 3:
6836 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3;
6837 break;
6838 default:
6839 DRM_DEBUG("invalid pipe %d\n", pipe);
6840 return;
6841 }
6842
6843 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
6844
6845}
6846
6847#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
6848static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
6849{
6850 struct amdgpu_device *adev = ring->adev;
6851 uint32_t val;
6852 int i;
6853
6854 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
6855 * number of gfx waves. Setting 5 bit will make sure gfx only gets
6856 * around 25% of gpu resources.
6857 */
6858 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
6859 amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
6860
6861 /* Restrict waves for normal/low priority compute queues as well
6862 * to get best QoS for high priority compute jobs.
6863 *
6864 * amdgpu controls only 1st ME(0-3 CS pipes).
6865 */
6866 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
6867 if (i != ring->pipe)
6868 gfx_v8_0_emit_wave_limit_cs(ring, i, enable);
6869
6870 }
6871
6872}
6873
6874static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6875 .name = "gfx_v8_0",
6876 .early_init = gfx_v8_0_early_init,
6877 .late_init = gfx_v8_0_late_init,
6878 .sw_init = gfx_v8_0_sw_init,
6879 .sw_fini = gfx_v8_0_sw_fini,
6880 .hw_init = gfx_v8_0_hw_init,
6881 .hw_fini = gfx_v8_0_hw_fini,
6882 .suspend = gfx_v8_0_suspend,
6883 .resume = gfx_v8_0_resume,
6884 .is_idle = gfx_v8_0_is_idle,
6885 .wait_for_idle = gfx_v8_0_wait_for_idle,
6886 .check_soft_reset = gfx_v8_0_check_soft_reset,
6887 .pre_soft_reset = gfx_v8_0_pre_soft_reset,
6888 .soft_reset = gfx_v8_0_soft_reset,
6889 .post_soft_reset = gfx_v8_0_post_soft_reset,
6890 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6891 .set_powergating_state = gfx_v8_0_set_powergating_state,
6892 .get_clockgating_state = gfx_v8_0_get_clockgating_state,
6893};
6894
6895static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6896 .type = AMDGPU_RING_TYPE_GFX,
6897 .align_mask = 0xff,
6898 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6899 .support_64bit_ptrs = false,
6900 .get_rptr = gfx_v8_0_ring_get_rptr,
6901 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6902 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6903 .emit_frame_size = /* maximum 215dw if count 16 IBs in */
6904 5 + /* COND_EXEC */
6905 7 + /* PIPELINE_SYNC */
6906 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
6907 12 + /* FENCE for VM_FLUSH */
6908 20 + /* GDS switch */
6909 4 + /* double SWITCH_BUFFER,
6910 the first COND_EXEC jump to the place just
6911 prior to this double SWITCH_BUFFER */
6912 5 + /* COND_EXEC */
6913 7 + /* HDP_flush */
6914 4 + /* VGT_flush */
6915 14 + /* CE_META */
6916 31 + /* DE_META */
6917 3 + /* CNTX_CTRL */
6918 5 + /* HDP_INVL */
6919 12 + 12 + /* FENCE x2 */
6920 2 + /* SWITCH_BUFFER */
6921 5, /* SURFACE_SYNC */
6922 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6923 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6924 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
6925 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6926 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6927 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6928 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6929 .test_ring = gfx_v8_0_ring_test_ring,
6930 .test_ib = gfx_v8_0_ring_test_ib,
6931 .insert_nop = amdgpu_ring_insert_nop,
6932 .pad_ib = amdgpu_ring_generic_pad_ib,
6933 .emit_switch_buffer = gfx_v8_ring_emit_sb,
6934 .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
6935 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
6936 .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
6937 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6938 .soft_recovery = gfx_v8_0_ring_soft_recovery,
6939 .emit_mem_sync = gfx_v8_0_emit_mem_sync,
6940};
6941
6942static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6943 .type = AMDGPU_RING_TYPE_COMPUTE,
6944 .align_mask = 0xff,
6945 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6946 .support_64bit_ptrs = false,
6947 .get_rptr = gfx_v8_0_ring_get_rptr,
6948 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6949 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6950 .emit_frame_size =
6951 20 + /* gfx_v8_0_ring_emit_gds_switch */
6952 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6953 5 + /* hdp_invalidate */
6954 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6955 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6956 7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6957 7 + /* gfx_v8_0_emit_mem_sync_compute */
6958 5 + /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
6959 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
6960 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6961 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6962 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
6963 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6964 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6965 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6966 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6967 .test_ring = gfx_v8_0_ring_test_ring,
6968 .test_ib = gfx_v8_0_ring_test_ib,
6969 .insert_nop = amdgpu_ring_insert_nop,
6970 .pad_ib = amdgpu_ring_generic_pad_ib,
6971 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6972 .emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
6973 .emit_wave_limit = gfx_v8_0_emit_wave_limit,
6974};
6975
6976static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
6977 .type = AMDGPU_RING_TYPE_KIQ,
6978 .align_mask = 0xff,
6979 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6980 .support_64bit_ptrs = false,
6981 .get_rptr = gfx_v8_0_ring_get_rptr,
6982 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6983 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6984 .emit_frame_size =
6985 20 + /* gfx_v8_0_ring_emit_gds_switch */
6986 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6987 5 + /* hdp_invalidate */
6988 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6989 17 + /* gfx_v8_0_ring_emit_vm_flush */
6990 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6991 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6992 .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
6993 .test_ring = gfx_v8_0_ring_test_ring,
6994 .insert_nop = amdgpu_ring_insert_nop,
6995 .pad_ib = amdgpu_ring_generic_pad_ib,
6996 .emit_rreg = gfx_v8_0_ring_emit_rreg,
6997 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6998};
6999
7000static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
7001{
7002 int i;
7003
7004 adev->gfx.kiq[0].ring.funcs = &gfx_v8_0_ring_funcs_kiq;
7005
7006 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7007 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
7008
7009 for (i = 0; i < adev->gfx.num_compute_rings; i++)
7010 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
7011}
7012
7013static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
7014 .set = gfx_v8_0_set_eop_interrupt_state,
7015 .process = gfx_v8_0_eop_irq,
7016};
7017
7018static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
7019 .set = gfx_v8_0_set_priv_reg_fault_state,
7020 .process = gfx_v8_0_priv_reg_irq,
7021};
7022
7023static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
7024 .set = gfx_v8_0_set_priv_inst_fault_state,
7025 .process = gfx_v8_0_priv_inst_irq,
7026};
7027
7028static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = {
7029 .set = gfx_v8_0_set_cp_ecc_int_state,
7030 .process = gfx_v8_0_cp_ecc_error_irq,
7031};
7032
7033static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = {
7034 .set = gfx_v8_0_set_sq_int_state,
7035 .process = gfx_v8_0_sq_irq,
7036};
7037
7038static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
7039{
7040 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7041 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
7042
7043 adev->gfx.priv_reg_irq.num_types = 1;
7044 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
7045
7046 adev->gfx.priv_inst_irq.num_types = 1;
7047 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
7048
7049 adev->gfx.cp_ecc_error_irq.num_types = 1;
7050 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;
7051
7052 adev->gfx.sq_irq.num_types = 1;
7053 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs;
7054}
7055
7056static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
7057{
7058 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
7059}
7060
7061static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
7062{
7063 /* init asci gds info */
7064 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
7065 adev->gds.gws_size = 64;
7066 adev->gds.oa_size = 16;
7067 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
7068}
7069
7070static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7071 u32 bitmap)
7072{
7073 u32 data;
7074
7075 if (!bitmap)
7076 return;
7077
7078 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7079 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7080
7081 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
7082}
7083
7084static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7085{
7086 u32 data, mask;
7087
7088 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
7089 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
7090
7091 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7092
7093 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
7094}
7095
7096static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
7097{
7098 int i, j, k, counter, active_cu_number = 0;
7099 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7100 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
7101 unsigned disable_masks[4 * 2];
7102 u32 ao_cu_num;
7103
7104 memset(cu_info, 0, sizeof(*cu_info));
7105
7106 if (adev->flags & AMD_IS_APU)
7107 ao_cu_num = 2;
7108 else
7109 ao_cu_num = adev->gfx.config.max_cu_per_sh;
7110
7111 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
7112
7113 mutex_lock(&adev->grbm_idx_mutex);
7114 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7115 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7116 mask = 1;
7117 ao_bitmap = 0;
7118 counter = 0;
7119 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0);
7120 if (i < 4 && j < 2)
7121 gfx_v8_0_set_user_cu_inactive_bitmap(
7122 adev, disable_masks[i * 2 + j]);
7123 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7124 cu_info->bitmap[0][i][j] = bitmap;
7125
7126 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7127 if (bitmap & mask) {
7128 if (counter < ao_cu_num)
7129 ao_bitmap |= mask;
7130 counter ++;
7131 }
7132 mask <<= 1;
7133 }
7134 active_cu_number += counter;
7135 if (i < 2 && j < 2)
7136 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7137 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
7138 }
7139 }
7140 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
7141 mutex_unlock(&adev->grbm_idx_mutex);
7142
7143 cu_info->number = active_cu_number;
7144 cu_info->ao_cu_mask = ao_cu_mask;
7145 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7146 cu_info->max_waves_per_simd = 10;
7147 cu_info->max_scratch_slots_per_cu = 32;
7148 cu_info->wave_front_size = 64;
7149 cu_info->lds_size = 64;
7150}
7151
7152const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
7153{
7154 .type = AMD_IP_BLOCK_TYPE_GFX,
7155 .major = 8,
7156 .minor = 0,
7157 .rev = 0,
7158 .funcs = &gfx_v8_0_ip_funcs,
7159};
7160
7161const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
7162{
7163 .type = AMD_IP_BLOCK_TYPE_GFX,
7164 .major = 8,
7165 .minor = 1,
7166 .rev = 0,
7167 .funcs = &gfx_v8_0_ip_funcs,
7168};
7169
7170static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
7171{
7172 uint64_t ce_payload_addr;
7173 int cnt_ce;
7174 union {
7175 struct vi_ce_ib_state regular;
7176 struct vi_ce_ib_state_chained_ib chained;
7177 } ce_payload = {};
7178
7179 if (ring->adev->virt.chained_ib_support) {
7180 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7181 offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
7182 cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
7183 } else {
7184 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7185 offsetof(struct vi_gfx_meta_data, ce_payload);
7186 cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
7187 }
7188
7189 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));
7190 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7191 WRITE_DATA_DST_SEL(8) |
7192 WR_CONFIRM) |
7193 WRITE_DATA_CACHE_POLICY(0));
7194 amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
7195 amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));
7196 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
7197}
7198
7199static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
7200{
7201 uint64_t de_payload_addr, gds_addr, csa_addr;
7202 int cnt_de;
7203 union {
7204 struct vi_de_ib_state regular;
7205 struct vi_de_ib_state_chained_ib chained;
7206 } de_payload = {};
7207
7208 csa_addr = amdgpu_csa_vaddr(ring->adev);
7209 gds_addr = csa_addr + 4096;
7210 if (ring->adev->virt.chained_ib_support) {
7211 de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
7212 de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
7213 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload);
7214 cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2;
7215 } else {
7216 de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
7217 de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);
7218 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload);
7219 cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2;
7220 }
7221
7222 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));
7223 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7224 WRITE_DATA_DST_SEL(8) |
7225 WR_CONFIRM) |
7226 WRITE_DATA_CACHE_POLICY(0));
7227 amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
7228 amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));
7229 amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2);
7230}
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29
30#include "amdgpu.h"
31#include "amdgpu_gfx.h"
32#include "amdgpu_ring.h"
33#include "vi.h"
34#include "vi_structs.h"
35#include "vid.h"
36#include "amdgpu_ucode.h"
37#include "amdgpu_atombios.h"
38#include "atombios_i2c.h"
39#include "clearstate_vi.h"
40
41#include "gmc/gmc_8_2_d.h"
42#include "gmc/gmc_8_2_sh_mask.h"
43
44#include "oss/oss_3_0_d.h"
45#include "oss/oss_3_0_sh_mask.h"
46
47#include "bif/bif_5_0_d.h"
48#include "bif/bif_5_0_sh_mask.h"
49#include "gca/gfx_8_0_d.h"
50#include "gca/gfx_8_0_enum.h"
51#include "gca/gfx_8_0_sh_mask.h"
52
53#include "dce/dce_10_0_d.h"
54#include "dce/dce_10_0_sh_mask.h"
55
56#include "smu/smu_7_1_3_d.h"
57
58#include "ivsrcid/ivsrcid_vislands30.h"
59
60#define GFX8_NUM_GFX_RINGS 1
61#define GFX8_MEC_HPD_SIZE 4096
62
63#define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64#define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66#define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
67
68#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
69#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
70#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
71#define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
72#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
73#define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
74#define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
75#define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
76#define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
77
78#define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
79#define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
80#define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
81#define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
82#define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
83#define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
84
85/* BPM SERDES CMD */
86#define SET_BPM_SERDES_CMD 1
87#define CLE_BPM_SERDES_CMD 0
88
89/* BPM Register Address*/
90enum {
91 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
92 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
93 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
94 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
95 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
96 BPM_REG_FGCG_MAX
97};
98
99#define RLC_FormatDirectRegListLength 14
100
101MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
102MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
103MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
104MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
105MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
106MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
107
108MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
109MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
110MODULE_FIRMWARE("amdgpu/stoney_me.bin");
111MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
112MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
113
114MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
115MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
116MODULE_FIRMWARE("amdgpu/tonga_me.bin");
117MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
118MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
119MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
120
121MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
122MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
123MODULE_FIRMWARE("amdgpu/topaz_me.bin");
124MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
125MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
126
127MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
128MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
129MODULE_FIRMWARE("amdgpu/fiji_me.bin");
130MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
131MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
132MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
133
134MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
135MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
136MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
137MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
138MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
139MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
140MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
141MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
142MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
143MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
144MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
145
146MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
147MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
148MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
149MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
150MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
151MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
152MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
153MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
154MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
155MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
156MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
157
158MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
159MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
160MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
161MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
162MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
163MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
164MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
165MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
166MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
167MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
168MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
169
170MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
171MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
172MODULE_FIRMWARE("amdgpu/vegam_me.bin");
173MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
174MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
175MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
176
177static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
178{
179 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
180 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
181 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
182 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
183 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
184 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
185 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
186 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
187 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
188 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
189 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
190 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
191 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
192 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
193 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
194 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
195};
196
197static const u32 golden_settings_tonga_a11[] =
198{
199 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
200 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
201 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
202 mmGB_GPU_ID, 0x0000000f, 0x00000000,
203 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
204 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
205 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
206 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
207 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
208 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
209 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
210 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
211 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
212 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
213 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
214 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
215};
216
217static const u32 tonga_golden_common_all[] =
218{
219 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
220 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
221 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
222 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
223 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
224 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
225 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
226 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
227};
228
229static const u32 tonga_mgcg_cgcg_init[] =
230{
231 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
232 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
233 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
234 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
235 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
236 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
237 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
238 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
239 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
240 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
241 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
242 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
243 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
244 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
245 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
246 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
247 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
248 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
249 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
250 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
251 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
252 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
253 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
254 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
255 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
256 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
257 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
258 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
260 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
261 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
262 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
263 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
264 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
265 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
266 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
267 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
268 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
269 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
270 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
271 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
272 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
273 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
274 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
275 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
276 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
277 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
278 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
279 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
280 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
281 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
282 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
283 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
284 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
285 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
286 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
287 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
288 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
289 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
290 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
291 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
292 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
293 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
294 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
295 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
296 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
297 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
298 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
299 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
300 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
301 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
302 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
303 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
304 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
305 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
306};
307
308static const u32 golden_settings_vegam_a11[] =
309{
310 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
311 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
312 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
313 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
314 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
315 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
316 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
317 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
318 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
319 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
320 mmSQ_CONFIG, 0x07f80000, 0x01180000,
321 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
322 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
323 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
324 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
325 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
326 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
327};
328
329static const u32 vegam_golden_common_all[] =
330{
331 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
332 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
333 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
335 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
336 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
337};
338
339static const u32 golden_settings_polaris11_a11[] =
340{
341 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
342 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
343 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
344 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
345 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
346 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
347 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
348 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
350 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
351 mmSQ_CONFIG, 0x07f80000, 0x01180000,
352 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
353 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
354 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
355 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
356 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
357 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
358};
359
360static const u32 polaris11_golden_common_all[] =
361{
362 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
363 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
364 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
365 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
366 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
367 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
368};
369
370static const u32 golden_settings_polaris10_a11[] =
371{
372 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
373 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
374 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
375 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
376 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
377 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
378 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
379 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
380 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
381 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
382 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
383 mmSQ_CONFIG, 0x07f80000, 0x07180000,
384 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
385 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
386 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
387 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
388 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
389};
390
391static const u32 polaris10_golden_common_all[] =
392{
393 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
394 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
395 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
396 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
397 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
398 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
399 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
400 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
401};
402
403static const u32 fiji_golden_common_all[] =
404{
405 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
406 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
407 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
408 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
409 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
410 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
411 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
412 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
413 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
414 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
415};
416
417static const u32 golden_settings_fiji_a10[] =
418{
419 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
420 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
421 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
422 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
423 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
424 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
425 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
426 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
427 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
428 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
429 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
430};
431
432static const u32 fiji_mgcg_cgcg_init[] =
433{
434 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
435 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
436 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
441 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
443 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
445 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
452 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
453 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
454 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
455 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
456 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
458 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
459 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
460 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
461 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
463 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
464 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
465 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
466 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
467 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
468 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
469};
470
471static const u32 golden_settings_iceland_a11[] =
472{
473 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
474 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
475 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
476 mmGB_GPU_ID, 0x0000000f, 0x00000000,
477 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
478 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
479 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
480 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
481 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
482 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
483 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
484 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
485 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
486 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
487 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
488 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
489};
490
491static const u32 iceland_golden_common_all[] =
492{
493 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
494 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
495 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
496 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
497 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
498 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
499 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
500 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
501};
502
503static const u32 iceland_mgcg_cgcg_init[] =
504{
505 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
506 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
507 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
508 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
509 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
510 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
511 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
512 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
513 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
514 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
515 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
516 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
517 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
518 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
519 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
520 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
521 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
522 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
523 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
524 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
525 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
526 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
527 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
528 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
529 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
530 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
531 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
532 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
534 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
535 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
536 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
537 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
538 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
539 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
540 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
541 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
542 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
543 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
544 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
545 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
546 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
547 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
548 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
549 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
550 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
551 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
552 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
553 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
554 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
555 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
556 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
557 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
558 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
559 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
560 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
561 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
562 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
563 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
564 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
565 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
566 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
567 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
568 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
569};
570
571static const u32 cz_golden_settings_a11[] =
572{
573 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
574 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
575 mmGB_GPU_ID, 0x0000000f, 0x00000000,
576 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
577 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
578 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
579 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
580 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
581 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
582 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
583 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
584 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
585};
586
587static const u32 cz_golden_common_all[] =
588{
589 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
590 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
591 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
592 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
593 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
594 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
595 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
596 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
597};
598
599static const u32 cz_mgcg_cgcg_init[] =
600{
601 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
602 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
603 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
604 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
605 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
606 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
607 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
608 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
609 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
610 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
611 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
612 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
613 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
614 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
615 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
616 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
617 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
618 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
619 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
620 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
621 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
622 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
623 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
624 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
625 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
626 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
627 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
628 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
630 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
631 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
632 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
633 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
634 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
635 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
636 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
637 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
638 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
639 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
640 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
641 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
642 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
643 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
644 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
645 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
646 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
647 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
648 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
649 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
650 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
651 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
652 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
653 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
654 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
655 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
656 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
657 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
658 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
659 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
660 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
661 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
662 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
663 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
664 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
665 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
666 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
667 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
668 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
669 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
670 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
671 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
672 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
673 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
674 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
675 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
676};
677
678static const u32 stoney_golden_settings_a11[] =
679{
680 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
681 mmGB_GPU_ID, 0x0000000f, 0x00000000,
682 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
683 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
684 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
685 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
686 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
687 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
688 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
689 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
690};
691
692static const u32 stoney_golden_common_all[] =
693{
694 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
695 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
696 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
697 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
698 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
699 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
700 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
701 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
702};
703
704static const u32 stoney_mgcg_cgcg_init[] =
705{
706 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
707 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
708 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
710 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
711};
712
713
714static const char * const sq_edc_source_names[] = {
715 "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
716 "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
717 "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
718 "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
719 "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
720 "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
721 "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
722};
723
724static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
725static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
726static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
727static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
728static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
729static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
730static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
731static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
732
733#define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x0000007fL
734#define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x00000000L
735
736static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
737{
738 uint32_t data;
739
740 switch (adev->asic_type) {
741 case CHIP_TOPAZ:
742 amdgpu_device_program_register_sequence(adev,
743 iceland_mgcg_cgcg_init,
744 ARRAY_SIZE(iceland_mgcg_cgcg_init));
745 amdgpu_device_program_register_sequence(adev,
746 golden_settings_iceland_a11,
747 ARRAY_SIZE(golden_settings_iceland_a11));
748 amdgpu_device_program_register_sequence(adev,
749 iceland_golden_common_all,
750 ARRAY_SIZE(iceland_golden_common_all));
751 break;
752 case CHIP_FIJI:
753 amdgpu_device_program_register_sequence(adev,
754 fiji_mgcg_cgcg_init,
755 ARRAY_SIZE(fiji_mgcg_cgcg_init));
756 amdgpu_device_program_register_sequence(adev,
757 golden_settings_fiji_a10,
758 ARRAY_SIZE(golden_settings_fiji_a10));
759 amdgpu_device_program_register_sequence(adev,
760 fiji_golden_common_all,
761 ARRAY_SIZE(fiji_golden_common_all));
762 break;
763
764 case CHIP_TONGA:
765 amdgpu_device_program_register_sequence(adev,
766 tonga_mgcg_cgcg_init,
767 ARRAY_SIZE(tonga_mgcg_cgcg_init));
768 amdgpu_device_program_register_sequence(adev,
769 golden_settings_tonga_a11,
770 ARRAY_SIZE(golden_settings_tonga_a11));
771 amdgpu_device_program_register_sequence(adev,
772 tonga_golden_common_all,
773 ARRAY_SIZE(tonga_golden_common_all));
774 break;
775 case CHIP_VEGAM:
776 amdgpu_device_program_register_sequence(adev,
777 golden_settings_vegam_a11,
778 ARRAY_SIZE(golden_settings_vegam_a11));
779 amdgpu_device_program_register_sequence(adev,
780 vegam_golden_common_all,
781 ARRAY_SIZE(vegam_golden_common_all));
782 break;
783 case CHIP_POLARIS11:
784 case CHIP_POLARIS12:
785 amdgpu_device_program_register_sequence(adev,
786 golden_settings_polaris11_a11,
787 ARRAY_SIZE(golden_settings_polaris11_a11));
788 amdgpu_device_program_register_sequence(adev,
789 polaris11_golden_common_all,
790 ARRAY_SIZE(polaris11_golden_common_all));
791 break;
792 case CHIP_POLARIS10:
793 amdgpu_device_program_register_sequence(adev,
794 golden_settings_polaris10_a11,
795 ARRAY_SIZE(golden_settings_polaris10_a11));
796 amdgpu_device_program_register_sequence(adev,
797 polaris10_golden_common_all,
798 ARRAY_SIZE(polaris10_golden_common_all));
799 data = RREG32_SMC(ixCG_ACLK_CNTL);
800 data &= ~CG_ACLK_CNTL__ACLK_DIVIDER_MASK;
801 data |= 0x18 << CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT;
802 WREG32_SMC(ixCG_ACLK_CNTL, data);
803 if ((adev->pdev->device == 0x67DF) && (adev->pdev->revision == 0xc7) &&
804 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
805 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
806 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1680))) {
807 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
808 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
809 }
810 break;
811 case CHIP_CARRIZO:
812 amdgpu_device_program_register_sequence(adev,
813 cz_mgcg_cgcg_init,
814 ARRAY_SIZE(cz_mgcg_cgcg_init));
815 amdgpu_device_program_register_sequence(adev,
816 cz_golden_settings_a11,
817 ARRAY_SIZE(cz_golden_settings_a11));
818 amdgpu_device_program_register_sequence(adev,
819 cz_golden_common_all,
820 ARRAY_SIZE(cz_golden_common_all));
821 break;
822 case CHIP_STONEY:
823 amdgpu_device_program_register_sequence(adev,
824 stoney_mgcg_cgcg_init,
825 ARRAY_SIZE(stoney_mgcg_cgcg_init));
826 amdgpu_device_program_register_sequence(adev,
827 stoney_golden_settings_a11,
828 ARRAY_SIZE(stoney_golden_settings_a11));
829 amdgpu_device_program_register_sequence(adev,
830 stoney_golden_common_all,
831 ARRAY_SIZE(stoney_golden_common_all));
832 break;
833 default:
834 break;
835 }
836}
837
838static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
839{
840 adev->gfx.scratch.num_reg = 8;
841 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
842 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
843}
844
845static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
846{
847 struct amdgpu_device *adev = ring->adev;
848 uint32_t scratch;
849 uint32_t tmp = 0;
850 unsigned i;
851 int r;
852
853 r = amdgpu_gfx_scratch_get(adev, &scratch);
854 if (r)
855 return r;
856
857 WREG32(scratch, 0xCAFEDEAD);
858 r = amdgpu_ring_alloc(ring, 3);
859 if (r)
860 goto error_free_scratch;
861
862 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
863 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
864 amdgpu_ring_write(ring, 0xDEADBEEF);
865 amdgpu_ring_commit(ring);
866
867 for (i = 0; i < adev->usec_timeout; i++) {
868 tmp = RREG32(scratch);
869 if (tmp == 0xDEADBEEF)
870 break;
871 udelay(1);
872 }
873
874 if (i >= adev->usec_timeout)
875 r = -ETIMEDOUT;
876
877error_free_scratch:
878 amdgpu_gfx_scratch_free(adev, scratch);
879 return r;
880}
881
882static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
883{
884 struct amdgpu_device *adev = ring->adev;
885 struct amdgpu_ib ib;
886 struct dma_fence *f = NULL;
887
888 unsigned int index;
889 uint64_t gpu_addr;
890 uint32_t tmp;
891 long r;
892
893 r = amdgpu_device_wb_get(adev, &index);
894 if (r)
895 return r;
896
897 gpu_addr = adev->wb.gpu_addr + (index * 4);
898 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
899 memset(&ib, 0, sizeof(ib));
900 r = amdgpu_ib_get(adev, NULL, 16,
901 AMDGPU_IB_POOL_DIRECT, &ib);
902 if (r)
903 goto err1;
904
905 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
906 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
907 ib.ptr[2] = lower_32_bits(gpu_addr);
908 ib.ptr[3] = upper_32_bits(gpu_addr);
909 ib.ptr[4] = 0xDEADBEEF;
910 ib.length_dw = 5;
911
912 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
913 if (r)
914 goto err2;
915
916 r = dma_fence_wait_timeout(f, false, timeout);
917 if (r == 0) {
918 r = -ETIMEDOUT;
919 goto err2;
920 } else if (r < 0) {
921 goto err2;
922 }
923
924 tmp = adev->wb.wb[index];
925 if (tmp == 0xDEADBEEF)
926 r = 0;
927 else
928 r = -EINVAL;
929
930err2:
931 amdgpu_ib_free(adev, &ib, NULL);
932 dma_fence_put(f);
933err1:
934 amdgpu_device_wb_free(adev, index);
935 return r;
936}
937
938
939static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
940{
941 release_firmware(adev->gfx.pfp_fw);
942 adev->gfx.pfp_fw = NULL;
943 release_firmware(adev->gfx.me_fw);
944 adev->gfx.me_fw = NULL;
945 release_firmware(adev->gfx.ce_fw);
946 adev->gfx.ce_fw = NULL;
947 release_firmware(adev->gfx.rlc_fw);
948 adev->gfx.rlc_fw = NULL;
949 release_firmware(adev->gfx.mec_fw);
950 adev->gfx.mec_fw = NULL;
951 if ((adev->asic_type != CHIP_STONEY) &&
952 (adev->asic_type != CHIP_TOPAZ))
953 release_firmware(adev->gfx.mec2_fw);
954 adev->gfx.mec2_fw = NULL;
955
956 kfree(adev->gfx.rlc.register_list_format);
957}
958
959static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
960{
961 const char *chip_name;
962 char fw_name[30];
963 int err;
964 struct amdgpu_firmware_info *info = NULL;
965 const struct common_firmware_header *header = NULL;
966 const struct gfx_firmware_header_v1_0 *cp_hdr;
967 const struct rlc_firmware_header_v2_0 *rlc_hdr;
968 unsigned int *tmp = NULL, i;
969
970 DRM_DEBUG("\n");
971
972 switch (adev->asic_type) {
973 case CHIP_TOPAZ:
974 chip_name = "topaz";
975 break;
976 case CHIP_TONGA:
977 chip_name = "tonga";
978 break;
979 case CHIP_CARRIZO:
980 chip_name = "carrizo";
981 break;
982 case CHIP_FIJI:
983 chip_name = "fiji";
984 break;
985 case CHIP_STONEY:
986 chip_name = "stoney";
987 break;
988 case CHIP_POLARIS10:
989 chip_name = "polaris10";
990 break;
991 case CHIP_POLARIS11:
992 chip_name = "polaris11";
993 break;
994 case CHIP_POLARIS12:
995 chip_name = "polaris12";
996 break;
997 case CHIP_VEGAM:
998 chip_name = "vegam";
999 break;
1000 default:
1001 BUG();
1002 }
1003
1004 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1005 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
1006 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1007 if (err == -ENOENT) {
1008 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1009 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1010 }
1011 } else {
1012 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1013 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1014 }
1015 if (err)
1016 goto out;
1017 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1018 if (err)
1019 goto out;
1020 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1021 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1022 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1023
1024 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1025 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1026 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1027 if (err == -ENOENT) {
1028 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1029 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1030 }
1031 } else {
1032 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1033 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1034 }
1035 if (err)
1036 goto out;
1037 err = amdgpu_ucode_validate(adev->gfx.me_fw);
1038 if (err)
1039 goto out;
1040 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1041 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1042
1043 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1044
1045 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1046 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1047 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1048 if (err == -ENOENT) {
1049 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1050 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1051 }
1052 } else {
1053 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1054 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1055 }
1056 if (err)
1057 goto out;
1058 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1059 if (err)
1060 goto out;
1061 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1062 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1063 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1064
1065 /*
1066 * Support for MCBP/Virtualization in combination with chained IBs is
1067 * formal released on feature version #46
1068 */
1069 if (adev->gfx.ce_feature_version >= 46 &&
1070 adev->gfx.pfp_feature_version >= 46) {
1071 adev->virt.chained_ib_support = true;
1072 DRM_INFO("Chained IB support enabled!\n");
1073 } else
1074 adev->virt.chained_ib_support = false;
1075
1076 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1077 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1078 if (err)
1079 goto out;
1080 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1081 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1082 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1083 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1084
1085 adev->gfx.rlc.save_and_restore_offset =
1086 le32_to_cpu(rlc_hdr->save_and_restore_offset);
1087 adev->gfx.rlc.clear_state_descriptor_offset =
1088 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1089 adev->gfx.rlc.avail_scratch_ram_locations =
1090 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1091 adev->gfx.rlc.reg_restore_list_size =
1092 le32_to_cpu(rlc_hdr->reg_restore_list_size);
1093 adev->gfx.rlc.reg_list_format_start =
1094 le32_to_cpu(rlc_hdr->reg_list_format_start);
1095 adev->gfx.rlc.reg_list_format_separate_start =
1096 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1097 adev->gfx.rlc.starting_offsets_start =
1098 le32_to_cpu(rlc_hdr->starting_offsets_start);
1099 adev->gfx.rlc.reg_list_format_size_bytes =
1100 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1101 adev->gfx.rlc.reg_list_size_bytes =
1102 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1103
1104 adev->gfx.rlc.register_list_format =
1105 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1106 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1107
1108 if (!adev->gfx.rlc.register_list_format) {
1109 err = -ENOMEM;
1110 goto out;
1111 }
1112
1113 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1114 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1115 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1116 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1117
1118 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1119
1120 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1121 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1122 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1123 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1124
1125 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1126 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1127 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1128 if (err == -ENOENT) {
1129 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1130 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1131 }
1132 } else {
1133 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1134 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1135 }
1136 if (err)
1137 goto out;
1138 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1139 if (err)
1140 goto out;
1141 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1142 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1143 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1144
1145 if ((adev->asic_type != CHIP_STONEY) &&
1146 (adev->asic_type != CHIP_TOPAZ)) {
1147 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1148 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1149 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1150 if (err == -ENOENT) {
1151 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1152 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1153 }
1154 } else {
1155 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1156 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1157 }
1158 if (!err) {
1159 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1160 if (err)
1161 goto out;
1162 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1163 adev->gfx.mec2_fw->data;
1164 adev->gfx.mec2_fw_version =
1165 le32_to_cpu(cp_hdr->header.ucode_version);
1166 adev->gfx.mec2_feature_version =
1167 le32_to_cpu(cp_hdr->ucode_feature_version);
1168 } else {
1169 err = 0;
1170 adev->gfx.mec2_fw = NULL;
1171 }
1172 }
1173
1174 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1175 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1176 info->fw = adev->gfx.pfp_fw;
1177 header = (const struct common_firmware_header *)info->fw->data;
1178 adev->firmware.fw_size +=
1179 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1180
1181 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1182 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1183 info->fw = adev->gfx.me_fw;
1184 header = (const struct common_firmware_header *)info->fw->data;
1185 adev->firmware.fw_size +=
1186 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1187
1188 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1189 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1190 info->fw = adev->gfx.ce_fw;
1191 header = (const struct common_firmware_header *)info->fw->data;
1192 adev->firmware.fw_size +=
1193 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1194
1195 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1196 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1197 info->fw = adev->gfx.rlc_fw;
1198 header = (const struct common_firmware_header *)info->fw->data;
1199 adev->firmware.fw_size +=
1200 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1201
1202 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1203 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1204 info->fw = adev->gfx.mec_fw;
1205 header = (const struct common_firmware_header *)info->fw->data;
1206 adev->firmware.fw_size +=
1207 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1208
1209 /* we need account JT in */
1210 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1211 adev->firmware.fw_size +=
1212 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1213
1214 if (amdgpu_sriov_vf(adev)) {
1215 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1216 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1217 info->fw = adev->gfx.mec_fw;
1218 adev->firmware.fw_size +=
1219 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1220 }
1221
1222 if (adev->gfx.mec2_fw) {
1223 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1224 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1225 info->fw = adev->gfx.mec2_fw;
1226 header = (const struct common_firmware_header *)info->fw->data;
1227 adev->firmware.fw_size +=
1228 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1229 }
1230
1231out:
1232 if (err) {
1233 dev_err(adev->dev,
1234 "gfx8: Failed to load firmware \"%s\"\n",
1235 fw_name);
1236 release_firmware(adev->gfx.pfp_fw);
1237 adev->gfx.pfp_fw = NULL;
1238 release_firmware(adev->gfx.me_fw);
1239 adev->gfx.me_fw = NULL;
1240 release_firmware(adev->gfx.ce_fw);
1241 adev->gfx.ce_fw = NULL;
1242 release_firmware(adev->gfx.rlc_fw);
1243 adev->gfx.rlc_fw = NULL;
1244 release_firmware(adev->gfx.mec_fw);
1245 adev->gfx.mec_fw = NULL;
1246 release_firmware(adev->gfx.mec2_fw);
1247 adev->gfx.mec2_fw = NULL;
1248 }
1249 return err;
1250}
1251
1252static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1253 volatile u32 *buffer)
1254{
1255 u32 count = 0, i;
1256 const struct cs_section_def *sect = NULL;
1257 const struct cs_extent_def *ext = NULL;
1258
1259 if (adev->gfx.rlc.cs_data == NULL)
1260 return;
1261 if (buffer == NULL)
1262 return;
1263
1264 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1265 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1266
1267 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1268 buffer[count++] = cpu_to_le32(0x80000000);
1269 buffer[count++] = cpu_to_le32(0x80000000);
1270
1271 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1272 for (ext = sect->section; ext->extent != NULL; ++ext) {
1273 if (sect->id == SECT_CONTEXT) {
1274 buffer[count++] =
1275 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1276 buffer[count++] = cpu_to_le32(ext->reg_index -
1277 PACKET3_SET_CONTEXT_REG_START);
1278 for (i = 0; i < ext->reg_count; i++)
1279 buffer[count++] = cpu_to_le32(ext->extent[i]);
1280 } else {
1281 return;
1282 }
1283 }
1284 }
1285
1286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1287 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1288 PACKET3_SET_CONTEXT_REG_START);
1289 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1290 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1291
1292 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1293 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1294
1295 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1296 buffer[count++] = cpu_to_le32(0);
1297}
1298
1299static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1300{
1301 if (adev->asic_type == CHIP_CARRIZO)
1302 return 5;
1303 else
1304 return 4;
1305}
1306
1307static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1308{
1309 const struct cs_section_def *cs_data;
1310 int r;
1311
1312 adev->gfx.rlc.cs_data = vi_cs_data;
1313
1314 cs_data = adev->gfx.rlc.cs_data;
1315
1316 if (cs_data) {
1317 /* init clear state block */
1318 r = amdgpu_gfx_rlc_init_csb(adev);
1319 if (r)
1320 return r;
1321 }
1322
1323 if ((adev->asic_type == CHIP_CARRIZO) ||
1324 (adev->asic_type == CHIP_STONEY)) {
1325 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1326 r = amdgpu_gfx_rlc_init_cpt(adev);
1327 if (r)
1328 return r;
1329 }
1330
1331 /* init spm vmid with 0xf */
1332 if (adev->gfx.rlc.funcs->update_spm_vmid)
1333 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1334
1335 return 0;
1336}
1337
1338static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1339{
1340 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1341}
1342
1343static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1344{
1345 int r;
1346 u32 *hpd;
1347 size_t mec_hpd_size;
1348
1349 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1350
1351 /* take ownership of the relevant compute queues */
1352 amdgpu_gfx_compute_queue_acquire(adev);
1353
1354 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1355 if (mec_hpd_size) {
1356 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1357 AMDGPU_GEM_DOMAIN_VRAM,
1358 &adev->gfx.mec.hpd_eop_obj,
1359 &adev->gfx.mec.hpd_eop_gpu_addr,
1360 (void **)&hpd);
1361 if (r) {
1362 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1363 return r;
1364 }
1365
1366 memset(hpd, 0, mec_hpd_size);
1367
1368 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1369 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1370 }
1371
1372 return 0;
1373}
1374
1375static const u32 vgpr_init_compute_shader[] =
1376{
1377 0x7e000209, 0x7e020208,
1378 0x7e040207, 0x7e060206,
1379 0x7e080205, 0x7e0a0204,
1380 0x7e0c0203, 0x7e0e0202,
1381 0x7e100201, 0x7e120200,
1382 0x7e140209, 0x7e160208,
1383 0x7e180207, 0x7e1a0206,
1384 0x7e1c0205, 0x7e1e0204,
1385 0x7e200203, 0x7e220202,
1386 0x7e240201, 0x7e260200,
1387 0x7e280209, 0x7e2a0208,
1388 0x7e2c0207, 0x7e2e0206,
1389 0x7e300205, 0x7e320204,
1390 0x7e340203, 0x7e360202,
1391 0x7e380201, 0x7e3a0200,
1392 0x7e3c0209, 0x7e3e0208,
1393 0x7e400207, 0x7e420206,
1394 0x7e440205, 0x7e460204,
1395 0x7e480203, 0x7e4a0202,
1396 0x7e4c0201, 0x7e4e0200,
1397 0x7e500209, 0x7e520208,
1398 0x7e540207, 0x7e560206,
1399 0x7e580205, 0x7e5a0204,
1400 0x7e5c0203, 0x7e5e0202,
1401 0x7e600201, 0x7e620200,
1402 0x7e640209, 0x7e660208,
1403 0x7e680207, 0x7e6a0206,
1404 0x7e6c0205, 0x7e6e0204,
1405 0x7e700203, 0x7e720202,
1406 0x7e740201, 0x7e760200,
1407 0x7e780209, 0x7e7a0208,
1408 0x7e7c0207, 0x7e7e0206,
1409 0xbf8a0000, 0xbf810000,
1410};
1411
1412static const u32 sgpr_init_compute_shader[] =
1413{
1414 0xbe8a0100, 0xbe8c0102,
1415 0xbe8e0104, 0xbe900106,
1416 0xbe920108, 0xbe940100,
1417 0xbe960102, 0xbe980104,
1418 0xbe9a0106, 0xbe9c0108,
1419 0xbe9e0100, 0xbea00102,
1420 0xbea20104, 0xbea40106,
1421 0xbea60108, 0xbea80100,
1422 0xbeaa0102, 0xbeac0104,
1423 0xbeae0106, 0xbeb00108,
1424 0xbeb20100, 0xbeb40102,
1425 0xbeb60104, 0xbeb80106,
1426 0xbeba0108, 0xbebc0100,
1427 0xbebe0102, 0xbec00104,
1428 0xbec20106, 0xbec40108,
1429 0xbec60100, 0xbec80102,
1430 0xbee60004, 0xbee70005,
1431 0xbeea0006, 0xbeeb0007,
1432 0xbee80008, 0xbee90009,
1433 0xbefc0000, 0xbf8a0000,
1434 0xbf810000, 0x00000000,
1435};
1436
1437static const u32 vgpr_init_regs[] =
1438{
1439 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1440 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1441 mmCOMPUTE_NUM_THREAD_X, 256*4,
1442 mmCOMPUTE_NUM_THREAD_Y, 1,
1443 mmCOMPUTE_NUM_THREAD_Z, 1,
1444 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1445 mmCOMPUTE_PGM_RSRC2, 20,
1446 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1447 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1448 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1449 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1450 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1451 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1452 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1453 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1454 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1455 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1456};
1457
1458static const u32 sgpr1_init_regs[] =
1459{
1460 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1461 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1462 mmCOMPUTE_NUM_THREAD_X, 256*5,
1463 mmCOMPUTE_NUM_THREAD_Y, 1,
1464 mmCOMPUTE_NUM_THREAD_Z, 1,
1465 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1466 mmCOMPUTE_PGM_RSRC2, 20,
1467 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1468 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1469 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1470 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1471 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1472 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1473 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1474 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1475 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1476 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1477};
1478
1479static const u32 sgpr2_init_regs[] =
1480{
1481 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1482 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1483 mmCOMPUTE_NUM_THREAD_X, 256*5,
1484 mmCOMPUTE_NUM_THREAD_Y, 1,
1485 mmCOMPUTE_NUM_THREAD_Z, 1,
1486 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1487 mmCOMPUTE_PGM_RSRC2, 20,
1488 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1489 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1490 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1491 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1492 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1493 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1494 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1495 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1496 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1497 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1498};
1499
1500static const u32 sec_ded_counter_registers[] =
1501{
1502 mmCPC_EDC_ATC_CNT,
1503 mmCPC_EDC_SCRATCH_CNT,
1504 mmCPC_EDC_UCODE_CNT,
1505 mmCPF_EDC_ATC_CNT,
1506 mmCPF_EDC_ROQ_CNT,
1507 mmCPF_EDC_TAG_CNT,
1508 mmCPG_EDC_ATC_CNT,
1509 mmCPG_EDC_DMA_CNT,
1510 mmCPG_EDC_TAG_CNT,
1511 mmDC_EDC_CSINVOC_CNT,
1512 mmDC_EDC_RESTORE_CNT,
1513 mmDC_EDC_STATE_CNT,
1514 mmGDS_EDC_CNT,
1515 mmGDS_EDC_GRBM_CNT,
1516 mmGDS_EDC_OA_DED,
1517 mmSPI_EDC_CNT,
1518 mmSQC_ATC_EDC_GATCL1_CNT,
1519 mmSQC_EDC_CNT,
1520 mmSQ_EDC_DED_CNT,
1521 mmSQ_EDC_INFO,
1522 mmSQ_EDC_SEC_CNT,
1523 mmTCC_EDC_CNT,
1524 mmTCP_ATC_EDC_GATCL1_CNT,
1525 mmTCP_EDC_CNT,
1526 mmTD_EDC_CNT
1527};
1528
1529static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1530{
1531 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1532 struct amdgpu_ib ib;
1533 struct dma_fence *f = NULL;
1534 int r, i;
1535 u32 tmp;
1536 unsigned total_size, vgpr_offset, sgpr_offset;
1537 u64 gpu_addr;
1538
1539 /* only supported on CZ */
1540 if (adev->asic_type != CHIP_CARRIZO)
1541 return 0;
1542
1543 /* bail if the compute ring is not ready */
1544 if (!ring->sched.ready)
1545 return 0;
1546
1547 tmp = RREG32(mmGB_EDC_MODE);
1548 WREG32(mmGB_EDC_MODE, 0);
1549
1550 total_size =
1551 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1552 total_size +=
1553 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1554 total_size +=
1555 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1556 total_size = ALIGN(total_size, 256);
1557 vgpr_offset = total_size;
1558 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1559 sgpr_offset = total_size;
1560 total_size += sizeof(sgpr_init_compute_shader);
1561
1562 /* allocate an indirect buffer to put the commands in */
1563 memset(&ib, 0, sizeof(ib));
1564 r = amdgpu_ib_get(adev, NULL, total_size,
1565 AMDGPU_IB_POOL_DIRECT, &ib);
1566 if (r) {
1567 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1568 return r;
1569 }
1570
1571 /* load the compute shaders */
1572 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1573 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1574
1575 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1576 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1577
1578 /* init the ib length to 0 */
1579 ib.length_dw = 0;
1580
1581 /* VGPR */
1582 /* write the register state for the compute dispatch */
1583 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1584 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1585 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1586 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1587 }
1588 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1589 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1590 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1591 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1592 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1593 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1594
1595 /* write dispatch packet */
1596 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1597 ib.ptr[ib.length_dw++] = 8; /* x */
1598 ib.ptr[ib.length_dw++] = 1; /* y */
1599 ib.ptr[ib.length_dw++] = 1; /* z */
1600 ib.ptr[ib.length_dw++] =
1601 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1602
1603 /* write CS partial flush packet */
1604 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1605 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1606
1607 /* SGPR1 */
1608 /* write the register state for the compute dispatch */
1609 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1610 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1611 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1612 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1613 }
1614 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1615 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1616 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1617 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1618 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1619 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1620
1621 /* write dispatch packet */
1622 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1623 ib.ptr[ib.length_dw++] = 8; /* x */
1624 ib.ptr[ib.length_dw++] = 1; /* y */
1625 ib.ptr[ib.length_dw++] = 1; /* z */
1626 ib.ptr[ib.length_dw++] =
1627 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1628
1629 /* write CS partial flush packet */
1630 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1631 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1632
1633 /* SGPR2 */
1634 /* write the register state for the compute dispatch */
1635 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1636 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1637 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1638 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1639 }
1640 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1641 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1642 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1643 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1644 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1645 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1646
1647 /* write dispatch packet */
1648 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1649 ib.ptr[ib.length_dw++] = 8; /* x */
1650 ib.ptr[ib.length_dw++] = 1; /* y */
1651 ib.ptr[ib.length_dw++] = 1; /* z */
1652 ib.ptr[ib.length_dw++] =
1653 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1654
1655 /* write CS partial flush packet */
1656 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1657 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1658
1659 /* shedule the ib on the ring */
1660 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1661 if (r) {
1662 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1663 goto fail;
1664 }
1665
1666 /* wait for the GPU to finish processing the IB */
1667 r = dma_fence_wait(f, false);
1668 if (r) {
1669 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1670 goto fail;
1671 }
1672
1673 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1674 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1675 WREG32(mmGB_EDC_MODE, tmp);
1676
1677 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1678 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1679 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1680
1681
1682 /* read back registers to clear the counters */
1683 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1684 RREG32(sec_ded_counter_registers[i]);
1685
1686fail:
1687 amdgpu_ib_free(adev, &ib, NULL);
1688 dma_fence_put(f);
1689
1690 return r;
1691}
1692
1693static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1694{
1695 u32 gb_addr_config;
1696 u32 mc_arb_ramcfg;
1697 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1698 u32 tmp;
1699 int ret;
1700
1701 switch (adev->asic_type) {
1702 case CHIP_TOPAZ:
1703 adev->gfx.config.max_shader_engines = 1;
1704 adev->gfx.config.max_tile_pipes = 2;
1705 adev->gfx.config.max_cu_per_sh = 6;
1706 adev->gfx.config.max_sh_per_se = 1;
1707 adev->gfx.config.max_backends_per_se = 2;
1708 adev->gfx.config.max_texture_channel_caches = 2;
1709 adev->gfx.config.max_gprs = 256;
1710 adev->gfx.config.max_gs_threads = 32;
1711 adev->gfx.config.max_hw_contexts = 8;
1712
1713 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1714 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1715 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1716 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1717 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1718 break;
1719 case CHIP_FIJI:
1720 adev->gfx.config.max_shader_engines = 4;
1721 adev->gfx.config.max_tile_pipes = 16;
1722 adev->gfx.config.max_cu_per_sh = 16;
1723 adev->gfx.config.max_sh_per_se = 1;
1724 adev->gfx.config.max_backends_per_se = 4;
1725 adev->gfx.config.max_texture_channel_caches = 16;
1726 adev->gfx.config.max_gprs = 256;
1727 adev->gfx.config.max_gs_threads = 32;
1728 adev->gfx.config.max_hw_contexts = 8;
1729
1730 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1731 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1732 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1733 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1734 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1735 break;
1736 case CHIP_POLARIS11:
1737 case CHIP_POLARIS12:
1738 ret = amdgpu_atombios_get_gfx_info(adev);
1739 if (ret)
1740 return ret;
1741 adev->gfx.config.max_gprs = 256;
1742 adev->gfx.config.max_gs_threads = 32;
1743 adev->gfx.config.max_hw_contexts = 8;
1744
1745 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1746 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1747 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1748 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1749 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1750 break;
1751 case CHIP_POLARIS10:
1752 case CHIP_VEGAM:
1753 ret = amdgpu_atombios_get_gfx_info(adev);
1754 if (ret)
1755 return ret;
1756 adev->gfx.config.max_gprs = 256;
1757 adev->gfx.config.max_gs_threads = 32;
1758 adev->gfx.config.max_hw_contexts = 8;
1759
1760 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1761 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1762 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1763 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1764 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1765 break;
1766 case CHIP_TONGA:
1767 adev->gfx.config.max_shader_engines = 4;
1768 adev->gfx.config.max_tile_pipes = 8;
1769 adev->gfx.config.max_cu_per_sh = 8;
1770 adev->gfx.config.max_sh_per_se = 1;
1771 adev->gfx.config.max_backends_per_se = 2;
1772 adev->gfx.config.max_texture_channel_caches = 8;
1773 adev->gfx.config.max_gprs = 256;
1774 adev->gfx.config.max_gs_threads = 32;
1775 adev->gfx.config.max_hw_contexts = 8;
1776
1777 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1778 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1779 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1780 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1781 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1782 break;
1783 case CHIP_CARRIZO:
1784 adev->gfx.config.max_shader_engines = 1;
1785 adev->gfx.config.max_tile_pipes = 2;
1786 adev->gfx.config.max_sh_per_se = 1;
1787 adev->gfx.config.max_backends_per_se = 2;
1788 adev->gfx.config.max_cu_per_sh = 8;
1789 adev->gfx.config.max_texture_channel_caches = 2;
1790 adev->gfx.config.max_gprs = 256;
1791 adev->gfx.config.max_gs_threads = 32;
1792 adev->gfx.config.max_hw_contexts = 8;
1793
1794 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1795 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1796 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1797 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1798 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1799 break;
1800 case CHIP_STONEY:
1801 adev->gfx.config.max_shader_engines = 1;
1802 adev->gfx.config.max_tile_pipes = 2;
1803 adev->gfx.config.max_sh_per_se = 1;
1804 adev->gfx.config.max_backends_per_se = 1;
1805 adev->gfx.config.max_cu_per_sh = 3;
1806 adev->gfx.config.max_texture_channel_caches = 2;
1807 adev->gfx.config.max_gprs = 256;
1808 adev->gfx.config.max_gs_threads = 16;
1809 adev->gfx.config.max_hw_contexts = 8;
1810
1811 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1812 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1813 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1814 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1815 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1816 break;
1817 default:
1818 adev->gfx.config.max_shader_engines = 2;
1819 adev->gfx.config.max_tile_pipes = 4;
1820 adev->gfx.config.max_cu_per_sh = 2;
1821 adev->gfx.config.max_sh_per_se = 1;
1822 adev->gfx.config.max_backends_per_se = 2;
1823 adev->gfx.config.max_texture_channel_caches = 4;
1824 adev->gfx.config.max_gprs = 256;
1825 adev->gfx.config.max_gs_threads = 32;
1826 adev->gfx.config.max_hw_contexts = 8;
1827
1828 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1829 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1830 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1831 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1832 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1833 break;
1834 }
1835
1836 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1837 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1838
1839 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
1840 MC_ARB_RAMCFG, NOOFBANK);
1841 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
1842 MC_ARB_RAMCFG, NOOFRANKS);
1843
1844 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1845 adev->gfx.config.mem_max_burst_length_bytes = 256;
1846 if (adev->flags & AMD_IS_APU) {
1847 /* Get memory bank mapping mode. */
1848 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1849 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1850 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1851
1852 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1853 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1854 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1855
1856 /* Validate settings in case only one DIMM installed. */
1857 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1858 dimm00_addr_map = 0;
1859 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1860 dimm01_addr_map = 0;
1861 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1862 dimm10_addr_map = 0;
1863 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1864 dimm11_addr_map = 0;
1865
1866 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1867 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1868 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1869 adev->gfx.config.mem_row_size_in_kb = 2;
1870 else
1871 adev->gfx.config.mem_row_size_in_kb = 1;
1872 } else {
1873 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1874 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1875 if (adev->gfx.config.mem_row_size_in_kb > 4)
1876 adev->gfx.config.mem_row_size_in_kb = 4;
1877 }
1878
1879 adev->gfx.config.shader_engine_tile_size = 32;
1880 adev->gfx.config.num_gpus = 1;
1881 adev->gfx.config.multi_gpu_tile_size = 64;
1882
1883 /* fix up row size */
1884 switch (adev->gfx.config.mem_row_size_in_kb) {
1885 case 1:
1886 default:
1887 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1888 break;
1889 case 2:
1890 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1891 break;
1892 case 4:
1893 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1894 break;
1895 }
1896 adev->gfx.config.gb_addr_config = gb_addr_config;
1897
1898 return 0;
1899}
1900
1901static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1902 int mec, int pipe, int queue)
1903{
1904 int r;
1905 unsigned irq_type;
1906 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1907 unsigned int hw_prio;
1908
1909 ring = &adev->gfx.compute_ring[ring_id];
1910
1911 /* mec0 is me1 */
1912 ring->me = mec + 1;
1913 ring->pipe = pipe;
1914 ring->queue = queue;
1915
1916 ring->ring_obj = NULL;
1917 ring->use_doorbell = true;
1918 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1919 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1920 + (ring_id * GFX8_MEC_HPD_SIZE);
1921 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1922
1923 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1924 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1925 + ring->pipe;
1926
1927 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1928 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT;
1929 /* type-2 packets are deprecated on MEC, use type-3 instead */
1930 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1931 hw_prio, NULL);
1932 if (r)
1933 return r;
1934
1935
1936 return 0;
1937}
1938
1939static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1940
1941static int gfx_v8_0_sw_init(void *handle)
1942{
1943 int i, j, k, r, ring_id;
1944 struct amdgpu_ring *ring;
1945 struct amdgpu_kiq *kiq;
1946 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1947
1948 switch (adev->asic_type) {
1949 case CHIP_TONGA:
1950 case CHIP_CARRIZO:
1951 case CHIP_FIJI:
1952 case CHIP_POLARIS10:
1953 case CHIP_POLARIS11:
1954 case CHIP_POLARIS12:
1955 case CHIP_VEGAM:
1956 adev->gfx.mec.num_mec = 2;
1957 break;
1958 case CHIP_TOPAZ:
1959 case CHIP_STONEY:
1960 default:
1961 adev->gfx.mec.num_mec = 1;
1962 break;
1963 }
1964
1965 adev->gfx.mec.num_pipe_per_mec = 4;
1966 adev->gfx.mec.num_queue_per_pipe = 8;
1967
1968 /* EOP Event */
1969 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1970 if (r)
1971 return r;
1972
1973 /* Privileged reg */
1974 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1975 &adev->gfx.priv_reg_irq);
1976 if (r)
1977 return r;
1978
1979 /* Privileged inst */
1980 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1981 &adev->gfx.priv_inst_irq);
1982 if (r)
1983 return r;
1984
1985 /* Add CP EDC/ECC irq */
1986 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1987 &adev->gfx.cp_ecc_error_irq);
1988 if (r)
1989 return r;
1990
1991 /* SQ interrupts. */
1992 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
1993 &adev->gfx.sq_irq);
1994 if (r) {
1995 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
1996 return r;
1997 }
1998
1999 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
2000
2001 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2002
2003 gfx_v8_0_scratch_init(adev);
2004
2005 r = gfx_v8_0_init_microcode(adev);
2006 if (r) {
2007 DRM_ERROR("Failed to load gfx firmware!\n");
2008 return r;
2009 }
2010
2011 r = adev->gfx.rlc.funcs->init(adev);
2012 if (r) {
2013 DRM_ERROR("Failed to init rlc BOs!\n");
2014 return r;
2015 }
2016
2017 r = gfx_v8_0_mec_init(adev);
2018 if (r) {
2019 DRM_ERROR("Failed to init MEC BOs!\n");
2020 return r;
2021 }
2022
2023 /* set up the gfx ring */
2024 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2025 ring = &adev->gfx.gfx_ring[i];
2026 ring->ring_obj = NULL;
2027 sprintf(ring->name, "gfx");
2028 /* no gfx doorbells on iceland */
2029 if (adev->asic_type != CHIP_TOPAZ) {
2030 ring->use_doorbell = true;
2031 ring->doorbell_index = adev->doorbell_index.gfx_ring0;
2032 }
2033
2034 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2035 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
2036 AMDGPU_RING_PRIO_DEFAULT, NULL);
2037 if (r)
2038 return r;
2039 }
2040
2041
2042 /* set up the compute queues - allocate horizontally across pipes */
2043 ring_id = 0;
2044 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2045 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2046 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2047 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2048 continue;
2049
2050 r = gfx_v8_0_compute_ring_init(adev,
2051 ring_id,
2052 i, k, j);
2053 if (r)
2054 return r;
2055
2056 ring_id++;
2057 }
2058 }
2059 }
2060
2061 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2062 if (r) {
2063 DRM_ERROR("Failed to init KIQ BOs!\n");
2064 return r;
2065 }
2066
2067 kiq = &adev->gfx.kiq;
2068 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2069 if (r)
2070 return r;
2071
2072 /* create MQD for all compute queues as well as KIQ for SRIOV case */
2073 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2074 if (r)
2075 return r;
2076
2077 adev->gfx.ce_ram_size = 0x8000;
2078
2079 r = gfx_v8_0_gpu_early_init(adev);
2080 if (r)
2081 return r;
2082
2083 return 0;
2084}
2085
2086static int gfx_v8_0_sw_fini(void *handle)
2087{
2088 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2089 int i;
2090
2091 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2092 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2093 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2094 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2095
2096 amdgpu_gfx_mqd_sw_fini(adev);
2097 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
2098 amdgpu_gfx_kiq_fini(adev);
2099
2100 gfx_v8_0_mec_fini(adev);
2101 amdgpu_gfx_rlc_fini(adev);
2102 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2103 &adev->gfx.rlc.clear_state_gpu_addr,
2104 (void **)&adev->gfx.rlc.cs_ptr);
2105 if ((adev->asic_type == CHIP_CARRIZO) ||
2106 (adev->asic_type == CHIP_STONEY)) {
2107 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2108 &adev->gfx.rlc.cp_table_gpu_addr,
2109 (void **)&adev->gfx.rlc.cp_table_ptr);
2110 }
2111 gfx_v8_0_free_microcode(adev);
2112
2113 return 0;
2114}
2115
2116static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2117{
2118 uint32_t *modearray, *mod2array;
2119 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2120 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2121 u32 reg_offset;
2122
2123 modearray = adev->gfx.config.tile_mode_array;
2124 mod2array = adev->gfx.config.macrotile_mode_array;
2125
2126 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2127 modearray[reg_offset] = 0;
2128
2129 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2130 mod2array[reg_offset] = 0;
2131
2132 switch (adev->asic_type) {
2133 case CHIP_TOPAZ:
2134 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2135 PIPE_CONFIG(ADDR_SURF_P2) |
2136 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2137 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2138 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2139 PIPE_CONFIG(ADDR_SURF_P2) |
2140 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2141 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2142 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2143 PIPE_CONFIG(ADDR_SURF_P2) |
2144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2145 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2146 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2147 PIPE_CONFIG(ADDR_SURF_P2) |
2148 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2149 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2150 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2151 PIPE_CONFIG(ADDR_SURF_P2) |
2152 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2153 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2154 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2155 PIPE_CONFIG(ADDR_SURF_P2) |
2156 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2157 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2158 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2159 PIPE_CONFIG(ADDR_SURF_P2) |
2160 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2161 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2162 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2163 PIPE_CONFIG(ADDR_SURF_P2));
2164 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2165 PIPE_CONFIG(ADDR_SURF_P2) |
2166 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2167 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2168 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2169 PIPE_CONFIG(ADDR_SURF_P2) |
2170 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2171 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2172 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2173 PIPE_CONFIG(ADDR_SURF_P2) |
2174 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2175 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2176 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2177 PIPE_CONFIG(ADDR_SURF_P2) |
2178 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2179 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2180 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2181 PIPE_CONFIG(ADDR_SURF_P2) |
2182 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2183 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2184 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2185 PIPE_CONFIG(ADDR_SURF_P2) |
2186 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2187 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2188 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2189 PIPE_CONFIG(ADDR_SURF_P2) |
2190 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2191 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2192 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2193 PIPE_CONFIG(ADDR_SURF_P2) |
2194 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2195 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2196 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2197 PIPE_CONFIG(ADDR_SURF_P2) |
2198 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2199 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2200 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2201 PIPE_CONFIG(ADDR_SURF_P2) |
2202 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2203 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2204 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2205 PIPE_CONFIG(ADDR_SURF_P2) |
2206 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2207 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2208 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2209 PIPE_CONFIG(ADDR_SURF_P2) |
2210 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2211 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2212 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2213 PIPE_CONFIG(ADDR_SURF_P2) |
2214 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2215 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2216 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2217 PIPE_CONFIG(ADDR_SURF_P2) |
2218 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2219 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2220 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2221 PIPE_CONFIG(ADDR_SURF_P2) |
2222 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2223 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2224 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2225 PIPE_CONFIG(ADDR_SURF_P2) |
2226 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2227 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2228 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2229 PIPE_CONFIG(ADDR_SURF_P2) |
2230 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2231 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2232 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2233 PIPE_CONFIG(ADDR_SURF_P2) |
2234 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2235 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2236
2237 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2240 NUM_BANKS(ADDR_SURF_8_BANK));
2241 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2242 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2243 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2244 NUM_BANKS(ADDR_SURF_8_BANK));
2245 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2248 NUM_BANKS(ADDR_SURF_8_BANK));
2249 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2252 NUM_BANKS(ADDR_SURF_8_BANK));
2253 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2256 NUM_BANKS(ADDR_SURF_8_BANK));
2257 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2258 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2259 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2260 NUM_BANKS(ADDR_SURF_8_BANK));
2261 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2264 NUM_BANKS(ADDR_SURF_8_BANK));
2265 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2266 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2267 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2268 NUM_BANKS(ADDR_SURF_16_BANK));
2269 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2272 NUM_BANKS(ADDR_SURF_16_BANK));
2273 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2274 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2275 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2276 NUM_BANKS(ADDR_SURF_16_BANK));
2277 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2278 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2279 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2280 NUM_BANKS(ADDR_SURF_16_BANK));
2281 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2282 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2283 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2284 NUM_BANKS(ADDR_SURF_16_BANK));
2285 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2286 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2287 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2288 NUM_BANKS(ADDR_SURF_16_BANK));
2289 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2290 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2291 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2292 NUM_BANKS(ADDR_SURF_8_BANK));
2293
2294 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2295 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2296 reg_offset != 23)
2297 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2298
2299 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2300 if (reg_offset != 7)
2301 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2302
2303 break;
2304 case CHIP_FIJI:
2305 case CHIP_VEGAM:
2306 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2307 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2308 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2309 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2310 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2312 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2313 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2314 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2316 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2317 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2318 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2319 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2320 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2321 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2322 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2323 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2324 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2325 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2326 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2327 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2328 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2329 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2330 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2331 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2332 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2333 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2334 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2335 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2336 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2337 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2338 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2339 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2340 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2341 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2342 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2343 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2344 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2345 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2346 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2348 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2349 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2350 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2351 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2352 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2353 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2354 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2355 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2356 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2357 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2358 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2359 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2360 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2361 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2362 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2364 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2365 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2366 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2368 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2369 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2370 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2371 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2372 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2373 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2374 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2375 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2376 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2377 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2378 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2379 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2380 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2381 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2382 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2383 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2384 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2385 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2387 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2388 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2389 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2390 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2391 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2392 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2393 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2394 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2395 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2396 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2397 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2398 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2399 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2400 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2401 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2402 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2404 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2405 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2406 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2407 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2408 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2409 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2410 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2411 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2412 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2413 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2414 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2416 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2417 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2418 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2419 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2420 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2421 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2422 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2423 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2424 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2425 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2426 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2428
2429 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2432 NUM_BANKS(ADDR_SURF_8_BANK));
2433 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2434 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2435 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2436 NUM_BANKS(ADDR_SURF_8_BANK));
2437 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2440 NUM_BANKS(ADDR_SURF_8_BANK));
2441 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2442 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2443 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2444 NUM_BANKS(ADDR_SURF_8_BANK));
2445 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2446 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2447 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2448 NUM_BANKS(ADDR_SURF_8_BANK));
2449 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2450 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2451 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2452 NUM_BANKS(ADDR_SURF_8_BANK));
2453 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2454 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2455 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2456 NUM_BANKS(ADDR_SURF_8_BANK));
2457 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2458 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2459 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2460 NUM_BANKS(ADDR_SURF_8_BANK));
2461 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2462 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2463 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2464 NUM_BANKS(ADDR_SURF_8_BANK));
2465 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2466 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2467 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2468 NUM_BANKS(ADDR_SURF_8_BANK));
2469 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2470 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2471 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2472 NUM_BANKS(ADDR_SURF_8_BANK));
2473 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2474 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2475 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2476 NUM_BANKS(ADDR_SURF_8_BANK));
2477 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2478 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2479 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2480 NUM_BANKS(ADDR_SURF_8_BANK));
2481 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2482 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2483 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2484 NUM_BANKS(ADDR_SURF_4_BANK));
2485
2486 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2487 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2488
2489 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2490 if (reg_offset != 7)
2491 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2492
2493 break;
2494 case CHIP_TONGA:
2495 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2496 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2498 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2499 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2500 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2501 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2502 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2503 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2504 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2506 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2507 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2508 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2509 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2510 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2511 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2512 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2514 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2515 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2516 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2518 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2519 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2520 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2521 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2522 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2523 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2524 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2526 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2527 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2529 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2530 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2531 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2532 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2533 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2534 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2535 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2536 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2537 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2538 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2539 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2540 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2541 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2542 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2543 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2544 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2545 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2546 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2547 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2548 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2549 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2550 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2551 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2552 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2553 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2554 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2555 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2556 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2557 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2558 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2559 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2560 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2561 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2562 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2563 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2564 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2565 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2566 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2567 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2568 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2569 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2570 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2571 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2572 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2573 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2574 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2575 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2576 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2577 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2578 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2579 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2580 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2581 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2582 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2583 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2584 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2585 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2586 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2587 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2588 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2589 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2590 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2591 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2592 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2593 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2594 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2595 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2596 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2597 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2598 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2599 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2600 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2601 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2602 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2603 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2604 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2605 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2606 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2607 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2608 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2609 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2610 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2611 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2612 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2613 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2614 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2615 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2616 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2617
2618 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2621 NUM_BANKS(ADDR_SURF_16_BANK));
2622 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2623 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2624 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2625 NUM_BANKS(ADDR_SURF_16_BANK));
2626 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2629 NUM_BANKS(ADDR_SURF_16_BANK));
2630 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2632 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2633 NUM_BANKS(ADDR_SURF_16_BANK));
2634 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2637 NUM_BANKS(ADDR_SURF_16_BANK));
2638 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2639 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2640 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2641 NUM_BANKS(ADDR_SURF_16_BANK));
2642 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2645 NUM_BANKS(ADDR_SURF_16_BANK));
2646 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2649 NUM_BANKS(ADDR_SURF_16_BANK));
2650 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2653 NUM_BANKS(ADDR_SURF_16_BANK));
2654 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2657 NUM_BANKS(ADDR_SURF_16_BANK));
2658 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2661 NUM_BANKS(ADDR_SURF_16_BANK));
2662 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2665 NUM_BANKS(ADDR_SURF_8_BANK));
2666 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2669 NUM_BANKS(ADDR_SURF_4_BANK));
2670 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2673 NUM_BANKS(ADDR_SURF_4_BANK));
2674
2675 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2676 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2677
2678 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2679 if (reg_offset != 7)
2680 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2681
2682 break;
2683 case CHIP_POLARIS11:
2684 case CHIP_POLARIS12:
2685 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2686 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2687 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2688 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2689 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2690 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2691 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2692 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2693 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2694 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2695 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2696 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2697 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2698 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2699 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2700 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2701 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2702 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2703 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2704 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2705 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2706 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2707 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2708 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2709 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2710 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2711 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2712 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2713 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2714 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2716 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2717 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2718 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2719 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2720 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2721 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2722 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2723 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2724 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2725 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2726 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2727 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2728 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2729 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2730 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2731 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2732 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2733 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2734 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2735 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2736 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2737 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2738 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2739 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2740 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2741 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2742 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2743 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2744 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2745 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2746 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2747 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2748 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2749 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2750 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2751 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2752 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2753 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2754 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2755 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2756 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2757 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2758 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2759 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2760 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2761 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2762 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2763 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2764 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2765 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2766 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2767 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2768 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2769 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2770 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2771 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2772 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2773 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2774 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2775 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2776 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2777 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2778 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2779 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2780 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2781 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2782 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2783 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2784 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2785 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2786 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2787 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2788 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2789 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2790 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2791 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2792 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2793 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2794 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2795 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2796 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2797 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2798 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2799 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2800 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2801 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2802 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2803 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2804 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2805 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2806 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2807
2808 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2811 NUM_BANKS(ADDR_SURF_16_BANK));
2812
2813 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2816 NUM_BANKS(ADDR_SURF_16_BANK));
2817
2818 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2819 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2820 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2821 NUM_BANKS(ADDR_SURF_16_BANK));
2822
2823 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2824 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2825 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2826 NUM_BANKS(ADDR_SURF_16_BANK));
2827
2828 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2829 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2830 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2831 NUM_BANKS(ADDR_SURF_16_BANK));
2832
2833 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2834 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2835 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2836 NUM_BANKS(ADDR_SURF_16_BANK));
2837
2838 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2839 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2840 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2841 NUM_BANKS(ADDR_SURF_16_BANK));
2842
2843 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2844 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2845 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2846 NUM_BANKS(ADDR_SURF_16_BANK));
2847
2848 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2851 NUM_BANKS(ADDR_SURF_16_BANK));
2852
2853 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2854 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2855 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2856 NUM_BANKS(ADDR_SURF_16_BANK));
2857
2858 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2859 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2860 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2861 NUM_BANKS(ADDR_SURF_16_BANK));
2862
2863 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2864 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2865 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2866 NUM_BANKS(ADDR_SURF_16_BANK));
2867
2868 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2869 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2870 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2871 NUM_BANKS(ADDR_SURF_8_BANK));
2872
2873 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2876 NUM_BANKS(ADDR_SURF_4_BANK));
2877
2878 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2879 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2880
2881 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2882 if (reg_offset != 7)
2883 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2884
2885 break;
2886 case CHIP_POLARIS10:
2887 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2888 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2889 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2890 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2891 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2892 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2893 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2894 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2895 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2896 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2898 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2899 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2900 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2902 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2903 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2904 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2905 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2906 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2907 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2908 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2909 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2910 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2911 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2912 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2913 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2914 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2915 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2916 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2918 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2919 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2920 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2921 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2922 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2923 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2924 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2925 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2926 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2927 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2928 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2929 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2930 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2931 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2932 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2933 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2934 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2935 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2936 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2937 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2938 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2939 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2940 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2941 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2942 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2943 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2944 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2945 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2946 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2947 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2948 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2949 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2950 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2951 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2952 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2953 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2954 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2955 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2956 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2957 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2958 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2959 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2960 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2961 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2962 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2963 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2964 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2965 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2966 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2967 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2968 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2969 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2970 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2971 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2972 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2973 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2974 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2975 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2976 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2977 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2978 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2979 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2980 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2981 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2982 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2983 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2984 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2985 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2986 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2987 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2988 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2989 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2990 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2991 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2992 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2993 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2994 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2995 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2996 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2997 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2998 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2999 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3000 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3001 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3002 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3003 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3004 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3005 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3006 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
3007 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3008 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3009
3010 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3011 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3012 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3013 NUM_BANKS(ADDR_SURF_16_BANK));
3014
3015 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3016 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3017 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3018 NUM_BANKS(ADDR_SURF_16_BANK));
3019
3020 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3023 NUM_BANKS(ADDR_SURF_16_BANK));
3024
3025 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3026 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3027 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3028 NUM_BANKS(ADDR_SURF_16_BANK));
3029
3030 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3031 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3032 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3033 NUM_BANKS(ADDR_SURF_16_BANK));
3034
3035 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3036 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3037 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3038 NUM_BANKS(ADDR_SURF_16_BANK));
3039
3040 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3041 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3042 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3043 NUM_BANKS(ADDR_SURF_16_BANK));
3044
3045 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3048 NUM_BANKS(ADDR_SURF_16_BANK));
3049
3050 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3051 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3052 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3053 NUM_BANKS(ADDR_SURF_16_BANK));
3054
3055 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3056 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3057 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3058 NUM_BANKS(ADDR_SURF_16_BANK));
3059
3060 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3061 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3062 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3063 NUM_BANKS(ADDR_SURF_16_BANK));
3064
3065 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3066 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3067 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3068 NUM_BANKS(ADDR_SURF_8_BANK));
3069
3070 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3073 NUM_BANKS(ADDR_SURF_4_BANK));
3074
3075 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3076 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3077 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3078 NUM_BANKS(ADDR_SURF_4_BANK));
3079
3080 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3081 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3082
3083 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3084 if (reg_offset != 7)
3085 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3086
3087 break;
3088 case CHIP_STONEY:
3089 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3090 PIPE_CONFIG(ADDR_SURF_P2) |
3091 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3092 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3093 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3094 PIPE_CONFIG(ADDR_SURF_P2) |
3095 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3096 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3097 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3098 PIPE_CONFIG(ADDR_SURF_P2) |
3099 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3100 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3101 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3102 PIPE_CONFIG(ADDR_SURF_P2) |
3103 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3104 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3105 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3106 PIPE_CONFIG(ADDR_SURF_P2) |
3107 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3108 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3109 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3110 PIPE_CONFIG(ADDR_SURF_P2) |
3111 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3112 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3113 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3114 PIPE_CONFIG(ADDR_SURF_P2) |
3115 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3116 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3117 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3118 PIPE_CONFIG(ADDR_SURF_P2));
3119 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3120 PIPE_CONFIG(ADDR_SURF_P2) |
3121 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3123 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3124 PIPE_CONFIG(ADDR_SURF_P2) |
3125 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3127 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3128 PIPE_CONFIG(ADDR_SURF_P2) |
3129 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3130 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3131 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3132 PIPE_CONFIG(ADDR_SURF_P2) |
3133 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3134 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3135 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3136 PIPE_CONFIG(ADDR_SURF_P2) |
3137 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3138 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3139 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3140 PIPE_CONFIG(ADDR_SURF_P2) |
3141 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3142 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3143 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3144 PIPE_CONFIG(ADDR_SURF_P2) |
3145 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3146 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3147 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3148 PIPE_CONFIG(ADDR_SURF_P2) |
3149 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3150 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3151 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3152 PIPE_CONFIG(ADDR_SURF_P2) |
3153 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3154 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3155 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3156 PIPE_CONFIG(ADDR_SURF_P2) |
3157 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3158 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3159 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3160 PIPE_CONFIG(ADDR_SURF_P2) |
3161 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3162 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3163 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3164 PIPE_CONFIG(ADDR_SURF_P2) |
3165 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3166 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3167 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3168 PIPE_CONFIG(ADDR_SURF_P2) |
3169 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3170 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3171 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3172 PIPE_CONFIG(ADDR_SURF_P2) |
3173 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3174 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3175 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3176 PIPE_CONFIG(ADDR_SURF_P2) |
3177 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3178 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3179 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3180 PIPE_CONFIG(ADDR_SURF_P2) |
3181 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3182 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3183 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3184 PIPE_CONFIG(ADDR_SURF_P2) |
3185 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3186 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3187 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3188 PIPE_CONFIG(ADDR_SURF_P2) |
3189 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3190 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3191
3192 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3195 NUM_BANKS(ADDR_SURF_8_BANK));
3196 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3197 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3198 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3199 NUM_BANKS(ADDR_SURF_8_BANK));
3200 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3201 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3202 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3203 NUM_BANKS(ADDR_SURF_8_BANK));
3204 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3207 NUM_BANKS(ADDR_SURF_8_BANK));
3208 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3211 NUM_BANKS(ADDR_SURF_8_BANK));
3212 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3215 NUM_BANKS(ADDR_SURF_8_BANK));
3216 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3217 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3218 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3219 NUM_BANKS(ADDR_SURF_8_BANK));
3220 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3223 NUM_BANKS(ADDR_SURF_16_BANK));
3224 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3225 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3226 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3227 NUM_BANKS(ADDR_SURF_16_BANK));
3228 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3231 NUM_BANKS(ADDR_SURF_16_BANK));
3232 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3233 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3234 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3235 NUM_BANKS(ADDR_SURF_16_BANK));
3236 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3239 NUM_BANKS(ADDR_SURF_16_BANK));
3240 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3241 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3242 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3243 NUM_BANKS(ADDR_SURF_16_BANK));
3244 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3247 NUM_BANKS(ADDR_SURF_8_BANK));
3248
3249 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3250 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3251 reg_offset != 23)
3252 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3253
3254 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3255 if (reg_offset != 7)
3256 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3257
3258 break;
3259 default:
3260 dev_warn(adev->dev,
3261 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3262 adev->asic_type);
3263 fallthrough;
3264
3265 case CHIP_CARRIZO:
3266 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3267 PIPE_CONFIG(ADDR_SURF_P2) |
3268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3269 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3270 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3271 PIPE_CONFIG(ADDR_SURF_P2) |
3272 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3273 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3274 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3275 PIPE_CONFIG(ADDR_SURF_P2) |
3276 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3277 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3278 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3279 PIPE_CONFIG(ADDR_SURF_P2) |
3280 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3281 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3282 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3283 PIPE_CONFIG(ADDR_SURF_P2) |
3284 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3285 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3286 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3287 PIPE_CONFIG(ADDR_SURF_P2) |
3288 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3289 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3290 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3291 PIPE_CONFIG(ADDR_SURF_P2) |
3292 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3293 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3294 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3295 PIPE_CONFIG(ADDR_SURF_P2));
3296 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3297 PIPE_CONFIG(ADDR_SURF_P2) |
3298 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3299 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3300 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3301 PIPE_CONFIG(ADDR_SURF_P2) |
3302 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3303 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3304 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3305 PIPE_CONFIG(ADDR_SURF_P2) |
3306 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3307 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3308 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3309 PIPE_CONFIG(ADDR_SURF_P2) |
3310 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3311 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3312 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3313 PIPE_CONFIG(ADDR_SURF_P2) |
3314 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3315 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3316 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3317 PIPE_CONFIG(ADDR_SURF_P2) |
3318 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3319 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3320 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3321 PIPE_CONFIG(ADDR_SURF_P2) |
3322 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3323 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3324 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3325 PIPE_CONFIG(ADDR_SURF_P2) |
3326 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3327 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3328 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3329 PIPE_CONFIG(ADDR_SURF_P2) |
3330 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3331 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3332 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3333 PIPE_CONFIG(ADDR_SURF_P2) |
3334 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3335 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3336 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3337 PIPE_CONFIG(ADDR_SURF_P2) |
3338 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3339 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3340 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3341 PIPE_CONFIG(ADDR_SURF_P2) |
3342 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3343 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3344 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3345 PIPE_CONFIG(ADDR_SURF_P2) |
3346 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3347 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3348 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3349 PIPE_CONFIG(ADDR_SURF_P2) |
3350 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3351 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3352 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3353 PIPE_CONFIG(ADDR_SURF_P2) |
3354 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3355 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3356 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3357 PIPE_CONFIG(ADDR_SURF_P2) |
3358 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3359 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3360 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3361 PIPE_CONFIG(ADDR_SURF_P2) |
3362 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3363 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3364 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3365 PIPE_CONFIG(ADDR_SURF_P2) |
3366 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3367 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3368
3369 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3370 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3371 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3372 NUM_BANKS(ADDR_SURF_8_BANK));
3373 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3374 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3375 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3376 NUM_BANKS(ADDR_SURF_8_BANK));
3377 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3378 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3379 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3380 NUM_BANKS(ADDR_SURF_8_BANK));
3381 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3382 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3383 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3384 NUM_BANKS(ADDR_SURF_8_BANK));
3385 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3386 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3387 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3388 NUM_BANKS(ADDR_SURF_8_BANK));
3389 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3390 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3391 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3392 NUM_BANKS(ADDR_SURF_8_BANK));
3393 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3394 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3395 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3396 NUM_BANKS(ADDR_SURF_8_BANK));
3397 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3398 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3399 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3400 NUM_BANKS(ADDR_SURF_16_BANK));
3401 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3402 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3403 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3404 NUM_BANKS(ADDR_SURF_16_BANK));
3405 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3406 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3407 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3408 NUM_BANKS(ADDR_SURF_16_BANK));
3409 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3412 NUM_BANKS(ADDR_SURF_16_BANK));
3413 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3414 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3415 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3416 NUM_BANKS(ADDR_SURF_16_BANK));
3417 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3418 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3419 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3420 NUM_BANKS(ADDR_SURF_16_BANK));
3421 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3424 NUM_BANKS(ADDR_SURF_8_BANK));
3425
3426 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3427 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3428 reg_offset != 23)
3429 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3430
3431 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3432 if (reg_offset != 7)
3433 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3434
3435 break;
3436 }
3437}
3438
3439static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3440 u32 se_num, u32 sh_num, u32 instance)
3441{
3442 u32 data;
3443
3444 if (instance == 0xffffffff)
3445 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3446 else
3447 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3448
3449 if (se_num == 0xffffffff)
3450 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3451 else
3452 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3453
3454 if (sh_num == 0xffffffff)
3455 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3456 else
3457 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3458
3459 WREG32(mmGRBM_GFX_INDEX, data);
3460}
3461
3462static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3463 u32 me, u32 pipe, u32 q, u32 vm)
3464{
3465 vi_srbm_select(adev, me, pipe, q, vm);
3466}
3467
3468static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3469{
3470 u32 data, mask;
3471
3472 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3473 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3474
3475 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3476
3477 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3478 adev->gfx.config.max_sh_per_se);
3479
3480 return (~data) & mask;
3481}
3482
3483static void
3484gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3485{
3486 switch (adev->asic_type) {
3487 case CHIP_FIJI:
3488 case CHIP_VEGAM:
3489 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3490 RB_XSEL2(1) | PKR_MAP(2) |
3491 PKR_XSEL(1) | PKR_YSEL(1) |
3492 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3493 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3494 SE_PAIR_YSEL(2);
3495 break;
3496 case CHIP_TONGA:
3497 case CHIP_POLARIS10:
3498 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3499 SE_XSEL(1) | SE_YSEL(1);
3500 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3501 SE_PAIR_YSEL(2);
3502 break;
3503 case CHIP_TOPAZ:
3504 case CHIP_CARRIZO:
3505 *rconf |= RB_MAP_PKR0(2);
3506 *rconf1 |= 0x0;
3507 break;
3508 case CHIP_POLARIS11:
3509 case CHIP_POLARIS12:
3510 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3511 SE_XSEL(1) | SE_YSEL(1);
3512 *rconf1 |= 0x0;
3513 break;
3514 case CHIP_STONEY:
3515 *rconf |= 0x0;
3516 *rconf1 |= 0x0;
3517 break;
3518 default:
3519 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3520 break;
3521 }
3522}
3523
3524static void
3525gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3526 u32 raster_config, u32 raster_config_1,
3527 unsigned rb_mask, unsigned num_rb)
3528{
3529 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3530 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3531 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3532 unsigned rb_per_se = num_rb / num_se;
3533 unsigned se_mask[4];
3534 unsigned se;
3535
3536 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3537 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3538 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3539 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3540
3541 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3542 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3543 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3544
3545 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3546 (!se_mask[2] && !se_mask[3]))) {
3547 raster_config_1 &= ~SE_PAIR_MAP_MASK;
3548
3549 if (!se_mask[0] && !se_mask[1]) {
3550 raster_config_1 |=
3551 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3552 } else {
3553 raster_config_1 |=
3554 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3555 }
3556 }
3557
3558 for (se = 0; se < num_se; se++) {
3559 unsigned raster_config_se = raster_config;
3560 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3561 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3562 int idx = (se / 2) * 2;
3563
3564 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3565 raster_config_se &= ~SE_MAP_MASK;
3566
3567 if (!se_mask[idx]) {
3568 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3569 } else {
3570 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3571 }
3572 }
3573
3574 pkr0_mask &= rb_mask;
3575 pkr1_mask &= rb_mask;
3576 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3577 raster_config_se &= ~PKR_MAP_MASK;
3578
3579 if (!pkr0_mask) {
3580 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3581 } else {
3582 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3583 }
3584 }
3585
3586 if (rb_per_se >= 2) {
3587 unsigned rb0_mask = 1 << (se * rb_per_se);
3588 unsigned rb1_mask = rb0_mask << 1;
3589
3590 rb0_mask &= rb_mask;
3591 rb1_mask &= rb_mask;
3592 if (!rb0_mask || !rb1_mask) {
3593 raster_config_se &= ~RB_MAP_PKR0_MASK;
3594
3595 if (!rb0_mask) {
3596 raster_config_se |=
3597 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3598 } else {
3599 raster_config_se |=
3600 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3601 }
3602 }
3603
3604 if (rb_per_se > 2) {
3605 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3606 rb1_mask = rb0_mask << 1;
3607 rb0_mask &= rb_mask;
3608 rb1_mask &= rb_mask;
3609 if (!rb0_mask || !rb1_mask) {
3610 raster_config_se &= ~RB_MAP_PKR1_MASK;
3611
3612 if (!rb0_mask) {
3613 raster_config_se |=
3614 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3615 } else {
3616 raster_config_se |=
3617 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3618 }
3619 }
3620 }
3621 }
3622
3623 /* GRBM_GFX_INDEX has a different offset on VI */
3624 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
3625 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3626 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3627 }
3628
3629 /* GRBM_GFX_INDEX has a different offset on VI */
3630 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3631}
3632
3633static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3634{
3635 int i, j;
3636 u32 data;
3637 u32 raster_config = 0, raster_config_1 = 0;
3638 u32 active_rbs = 0;
3639 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3640 adev->gfx.config.max_sh_per_se;
3641 unsigned num_rb_pipes;
3642
3643 mutex_lock(&adev->grbm_idx_mutex);
3644 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3646 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3647 data = gfx_v8_0_get_rb_active_bitmap(adev);
3648 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3649 rb_bitmap_width_per_sh);
3650 }
3651 }
3652 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3653
3654 adev->gfx.config.backend_enable_mask = active_rbs;
3655 adev->gfx.config.num_rbs = hweight32(active_rbs);
3656
3657 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3658 adev->gfx.config.max_shader_engines, 16);
3659
3660 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3661
3662 if (!adev->gfx.config.backend_enable_mask ||
3663 adev->gfx.config.num_rbs >= num_rb_pipes) {
3664 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3665 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3666 } else {
3667 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3668 adev->gfx.config.backend_enable_mask,
3669 num_rb_pipes);
3670 }
3671
3672 /* cache the values for userspace */
3673 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3674 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3675 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3676 adev->gfx.config.rb_config[i][j].rb_backend_disable =
3677 RREG32(mmCC_RB_BACKEND_DISABLE);
3678 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3679 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3680 adev->gfx.config.rb_config[i][j].raster_config =
3681 RREG32(mmPA_SC_RASTER_CONFIG);
3682 adev->gfx.config.rb_config[i][j].raster_config_1 =
3683 RREG32(mmPA_SC_RASTER_CONFIG_1);
3684 }
3685 }
3686 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3687 mutex_unlock(&adev->grbm_idx_mutex);
3688}
3689
3690#define DEFAULT_SH_MEM_BASES (0x6000)
3691/**
3692 * gfx_v8_0_init_compute_vmid - gart enable
3693 *
3694 * @adev: amdgpu_device pointer
3695 *
3696 * Initialize compute vmid sh_mem registers
3697 *
3698 */
3699static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3700{
3701 int i;
3702 uint32_t sh_mem_config;
3703 uint32_t sh_mem_bases;
3704
3705 /*
3706 * Configure apertures:
3707 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3708 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3709 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3710 */
3711 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3712
3713 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3714 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3715 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3716 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3717 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3718 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3719
3720 mutex_lock(&adev->srbm_mutex);
3721 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3722 vi_srbm_select(adev, 0, 0, 0, i);
3723 /* CP and shaders */
3724 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3725 WREG32(mmSH_MEM_APE1_BASE, 1);
3726 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3727 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3728 }
3729 vi_srbm_select(adev, 0, 0, 0, 0);
3730 mutex_unlock(&adev->srbm_mutex);
3731
3732 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
3733 acccess. These should be enabled by FW for target VMIDs. */
3734 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
3735 WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
3736 WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
3737 WREG32(amdgpu_gds_reg_offset[i].gws, 0);
3738 WREG32(amdgpu_gds_reg_offset[i].oa, 0);
3739 }
3740}
3741
3742static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
3743{
3744 int vmid;
3745
3746 /*
3747 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
3748 * access. Compute VMIDs should be enabled by FW for target VMIDs,
3749 * the driver can enable them for graphics. VMID0 should maintain
3750 * access so that HWS firmware can save/restore entries.
3751 */
3752 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
3753 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
3754 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
3755 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
3756 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
3757 }
3758}
3759
3760static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3761{
3762 switch (adev->asic_type) {
3763 default:
3764 adev->gfx.config.double_offchip_lds_buf = 1;
3765 break;
3766 case CHIP_CARRIZO:
3767 case CHIP_STONEY:
3768 adev->gfx.config.double_offchip_lds_buf = 0;
3769 break;
3770 }
3771}
3772
3773static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
3774{
3775 u32 tmp, sh_static_mem_cfg;
3776 int i;
3777
3778 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3779 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3780 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3781 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3782
3783 gfx_v8_0_tiling_mode_table_init(adev);
3784 gfx_v8_0_setup_rb(adev);
3785 gfx_v8_0_get_cu_info(adev);
3786 gfx_v8_0_config_init(adev);
3787
3788 /* XXX SH_MEM regs */
3789 /* where to put LDS, scratch, GPUVM in FSA64 space */
3790 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3791 SWIZZLE_ENABLE, 1);
3792 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3793 ELEMENT_SIZE, 1);
3794 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3795 INDEX_STRIDE, 3);
3796 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3797
3798 mutex_lock(&adev->srbm_mutex);
3799 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3800 vi_srbm_select(adev, 0, 0, 0, i);
3801 /* CP and shaders */
3802 if (i == 0) {
3803 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3804 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3805 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3806 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3807 WREG32(mmSH_MEM_CONFIG, tmp);
3808 WREG32(mmSH_MEM_BASES, 0);
3809 } else {
3810 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3811 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3812 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3813 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3814 WREG32(mmSH_MEM_CONFIG, tmp);
3815 tmp = adev->gmc.shared_aperture_start >> 48;
3816 WREG32(mmSH_MEM_BASES, tmp);
3817 }
3818
3819 WREG32(mmSH_MEM_APE1_BASE, 1);
3820 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3821 }
3822 vi_srbm_select(adev, 0, 0, 0, 0);
3823 mutex_unlock(&adev->srbm_mutex);
3824
3825 gfx_v8_0_init_compute_vmid(adev);
3826 gfx_v8_0_init_gds_vmid(adev);
3827
3828 mutex_lock(&adev->grbm_idx_mutex);
3829 /*
3830 * making sure that the following register writes will be broadcasted
3831 * to all the shaders
3832 */
3833 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3834
3835 WREG32(mmPA_SC_FIFO_SIZE,
3836 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3837 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3838 (adev->gfx.config.sc_prim_fifo_size_backend <<
3839 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3840 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3841 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3842 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3843 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3844
3845 tmp = RREG32(mmSPI_ARB_PRIORITY);
3846 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3847 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3848 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3849 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3850 WREG32(mmSPI_ARB_PRIORITY, tmp);
3851
3852 mutex_unlock(&adev->grbm_idx_mutex);
3853
3854}
3855
3856static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3857{
3858 u32 i, j, k;
3859 u32 mask;
3860
3861 mutex_lock(&adev->grbm_idx_mutex);
3862 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3863 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3864 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3865 for (k = 0; k < adev->usec_timeout; k++) {
3866 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3867 break;
3868 udelay(1);
3869 }
3870 if (k == adev->usec_timeout) {
3871 gfx_v8_0_select_se_sh(adev, 0xffffffff,
3872 0xffffffff, 0xffffffff);
3873 mutex_unlock(&adev->grbm_idx_mutex);
3874 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3875 i, j);
3876 return;
3877 }
3878 }
3879 }
3880 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3881 mutex_unlock(&adev->grbm_idx_mutex);
3882
3883 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3884 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3885 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3886 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3887 for (k = 0; k < adev->usec_timeout; k++) {
3888 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3889 break;
3890 udelay(1);
3891 }
3892}
3893
3894static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3895 bool enable)
3896{
3897 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3898
3899 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3900 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3901 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3902 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3903
3904 WREG32(mmCP_INT_CNTL_RING0, tmp);
3905}
3906
3907static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3908{
3909 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
3910 /* csib */
3911 WREG32(mmRLC_CSIB_ADDR_HI,
3912 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3913 WREG32(mmRLC_CSIB_ADDR_LO,
3914 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3915 WREG32(mmRLC_CSIB_LENGTH,
3916 adev->gfx.rlc.clear_state_size);
3917}
3918
3919static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3920 int ind_offset,
3921 int list_size,
3922 int *unique_indices,
3923 int *indices_count,
3924 int max_indices,
3925 int *ind_start_offsets,
3926 int *offset_count,
3927 int max_offset)
3928{
3929 int indices;
3930 bool new_entry = true;
3931
3932 for (; ind_offset < list_size; ind_offset++) {
3933
3934 if (new_entry) {
3935 new_entry = false;
3936 ind_start_offsets[*offset_count] = ind_offset;
3937 *offset_count = *offset_count + 1;
3938 BUG_ON(*offset_count >= max_offset);
3939 }
3940
3941 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3942 new_entry = true;
3943 continue;
3944 }
3945
3946 ind_offset += 2;
3947
3948 /* look for the matching indice */
3949 for (indices = 0;
3950 indices < *indices_count;
3951 indices++) {
3952 if (unique_indices[indices] ==
3953 register_list_format[ind_offset])
3954 break;
3955 }
3956
3957 if (indices >= *indices_count) {
3958 unique_indices[*indices_count] =
3959 register_list_format[ind_offset];
3960 indices = *indices_count;
3961 *indices_count = *indices_count + 1;
3962 BUG_ON(*indices_count >= max_indices);
3963 }
3964
3965 register_list_format[ind_offset] = indices;
3966 }
3967}
3968
3969static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3970{
3971 int i, temp, data;
3972 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3973 int indices_count = 0;
3974 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3975 int offset_count = 0;
3976
3977 int list_size;
3978 unsigned int *register_list_format =
3979 kmemdup(adev->gfx.rlc.register_list_format,
3980 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3981 if (!register_list_format)
3982 return -ENOMEM;
3983
3984 gfx_v8_0_parse_ind_reg_list(register_list_format,
3985 RLC_FormatDirectRegListLength,
3986 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3987 unique_indices,
3988 &indices_count,
3989 ARRAY_SIZE(unique_indices),
3990 indirect_start_offsets,
3991 &offset_count,
3992 ARRAY_SIZE(indirect_start_offsets));
3993
3994 /* save and restore list */
3995 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3996
3997 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3998 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
3999 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
4000
4001 /* indirect list */
4002 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
4003 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
4004 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
4005
4006 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
4007 list_size = list_size >> 1;
4008 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
4009 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
4010
4011 /* starting offsets starts */
4012 WREG32(mmRLC_GPM_SCRATCH_ADDR,
4013 adev->gfx.rlc.starting_offsets_start);
4014 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
4015 WREG32(mmRLC_GPM_SCRATCH_DATA,
4016 indirect_start_offsets[i]);
4017
4018 /* unique indices */
4019 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
4020 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
4021 for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
4022 if (unique_indices[i] != 0) {
4023 WREG32(temp + i, unique_indices[i] & 0x3FFFF);
4024 WREG32(data + i, unique_indices[i] >> 20);
4025 }
4026 }
4027 kfree(register_list_format);
4028
4029 return 0;
4030}
4031
4032static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
4033{
4034 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
4035}
4036
4037static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
4038{
4039 uint32_t data;
4040
4041 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
4042
4043 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
4044 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
4045 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
4046 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
4047 WREG32(mmRLC_PG_DELAY, data);
4048
4049 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4050 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4051
4052}
4053
4054static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
4055 bool enable)
4056{
4057 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4058}
4059
4060static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
4061 bool enable)
4062{
4063 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4064}
4065
4066static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
4067{
4068 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4069}
4070
4071static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4072{
4073 if ((adev->asic_type == CHIP_CARRIZO) ||
4074 (adev->asic_type == CHIP_STONEY)) {
4075 gfx_v8_0_init_csb(adev);
4076 gfx_v8_0_init_save_restore_list(adev);
4077 gfx_v8_0_enable_save_restore_machine(adev);
4078 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4079 gfx_v8_0_init_power_gating(adev);
4080 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4081 } else if ((adev->asic_type == CHIP_POLARIS11) ||
4082 (adev->asic_type == CHIP_POLARIS12) ||
4083 (adev->asic_type == CHIP_VEGAM)) {
4084 gfx_v8_0_init_csb(adev);
4085 gfx_v8_0_init_save_restore_list(adev);
4086 gfx_v8_0_enable_save_restore_machine(adev);
4087 gfx_v8_0_init_power_gating(adev);
4088 }
4089
4090}
4091
4092static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
4093{
4094 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4095
4096 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4097 gfx_v8_0_wait_for_rlc_serdes(adev);
4098}
4099
4100static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4101{
4102 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4103 udelay(50);
4104
4105 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4106 udelay(50);
4107}
4108
4109static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4110{
4111 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
4112
4113 /* carrizo do enable cp interrupt after cp inited */
4114 if (!(adev->flags & AMD_IS_APU))
4115 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4116
4117 udelay(50);
4118}
4119
4120static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4121{
4122 if (amdgpu_sriov_vf(adev)) {
4123 gfx_v8_0_init_csb(adev);
4124 return 0;
4125 }
4126
4127 adev->gfx.rlc.funcs->stop(adev);
4128 adev->gfx.rlc.funcs->reset(adev);
4129 gfx_v8_0_init_pg(adev);
4130 adev->gfx.rlc.funcs->start(adev);
4131
4132 return 0;
4133}
4134
4135static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4136{
4137 u32 tmp = RREG32(mmCP_ME_CNTL);
4138
4139 if (enable) {
4140 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4141 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4142 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4143 } else {
4144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4145 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4146 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4147 }
4148 WREG32(mmCP_ME_CNTL, tmp);
4149 udelay(50);
4150}
4151
4152static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4153{
4154 u32 count = 0;
4155 const struct cs_section_def *sect = NULL;
4156 const struct cs_extent_def *ext = NULL;
4157
4158 /* begin clear state */
4159 count += 2;
4160 /* context control state */
4161 count += 3;
4162
4163 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4164 for (ext = sect->section; ext->extent != NULL; ++ext) {
4165 if (sect->id == SECT_CONTEXT)
4166 count += 2 + ext->reg_count;
4167 else
4168 return 0;
4169 }
4170 }
4171 /* pa_sc_raster_config/pa_sc_raster_config1 */
4172 count += 4;
4173 /* end clear state */
4174 count += 2;
4175 /* clear state */
4176 count += 2;
4177
4178 return count;
4179}
4180
4181static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4182{
4183 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4184 const struct cs_section_def *sect = NULL;
4185 const struct cs_extent_def *ext = NULL;
4186 int r, i;
4187
4188 /* init the CP */
4189 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4190 WREG32(mmCP_ENDIAN_SWAP, 0);
4191 WREG32(mmCP_DEVICE_ID, 1);
4192
4193 gfx_v8_0_cp_gfx_enable(adev, true);
4194
4195 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
4196 if (r) {
4197 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4198 return r;
4199 }
4200
4201 /* clear state buffer */
4202 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4203 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4204
4205 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4206 amdgpu_ring_write(ring, 0x80000000);
4207 amdgpu_ring_write(ring, 0x80000000);
4208
4209 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4210 for (ext = sect->section; ext->extent != NULL; ++ext) {
4211 if (sect->id == SECT_CONTEXT) {
4212 amdgpu_ring_write(ring,
4213 PACKET3(PACKET3_SET_CONTEXT_REG,
4214 ext->reg_count));
4215 amdgpu_ring_write(ring,
4216 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4217 for (i = 0; i < ext->reg_count; i++)
4218 amdgpu_ring_write(ring, ext->extent[i]);
4219 }
4220 }
4221 }
4222
4223 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4224 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4225 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
4226 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
4227
4228 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4229 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4230
4231 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4232 amdgpu_ring_write(ring, 0);
4233
4234 /* init the CE partitions */
4235 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4236 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4237 amdgpu_ring_write(ring, 0x8000);
4238 amdgpu_ring_write(ring, 0x8000);
4239
4240 amdgpu_ring_commit(ring);
4241
4242 return 0;
4243}
4244static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
4245{
4246 u32 tmp;
4247 /* no gfx doorbells on iceland */
4248 if (adev->asic_type == CHIP_TOPAZ)
4249 return;
4250
4251 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4252
4253 if (ring->use_doorbell) {
4254 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4255 DOORBELL_OFFSET, ring->doorbell_index);
4256 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4257 DOORBELL_HIT, 0);
4258 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4259 DOORBELL_EN, 1);
4260 } else {
4261 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
4262 }
4263
4264 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4265
4266 if (adev->flags & AMD_IS_APU)
4267 return;
4268
4269 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4270 DOORBELL_RANGE_LOWER,
4271 adev->doorbell_index.gfx_ring0);
4272 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4273
4274 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4275 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4276}
4277
4278static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4279{
4280 struct amdgpu_ring *ring;
4281 u32 tmp;
4282 u32 rb_bufsz;
4283 u64 rb_addr, rptr_addr, wptr_gpu_addr;
4284
4285 /* Set the write pointer delay */
4286 WREG32(mmCP_RB_WPTR_DELAY, 0);
4287
4288 /* set the RB to use vmid 0 */
4289 WREG32(mmCP_RB_VMID, 0);
4290
4291 /* Set ring buffer size */
4292 ring = &adev->gfx.gfx_ring[0];
4293 rb_bufsz = order_base_2(ring->ring_size / 8);
4294 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4295 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4296 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4297 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4298#ifdef __BIG_ENDIAN
4299 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4300#endif
4301 WREG32(mmCP_RB0_CNTL, tmp);
4302
4303 /* Initialize the ring buffer's read and write pointers */
4304 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4305 ring->wptr = 0;
4306 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4307
4308 /* set the wb address wether it's enabled or not */
4309 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4310 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4311 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4312
4313 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4314 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4315 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4316 mdelay(1);
4317 WREG32(mmCP_RB0_CNTL, tmp);
4318
4319 rb_addr = ring->gpu_addr >> 8;
4320 WREG32(mmCP_RB0_BASE, rb_addr);
4321 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4322
4323 gfx_v8_0_set_cpg_door_bell(adev, ring);
4324 /* start the ring */
4325 amdgpu_ring_clear_ring(ring);
4326 gfx_v8_0_cp_gfx_start(adev);
4327 ring->sched.ready = true;
4328
4329 return 0;
4330}
4331
4332static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4333{
4334 if (enable) {
4335 WREG32(mmCP_MEC_CNTL, 0);
4336 } else {
4337 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4338 adev->gfx.kiq.ring.sched.ready = false;
4339 }
4340 udelay(50);
4341}
4342
4343/* KIQ functions */
4344static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
4345{
4346 uint32_t tmp;
4347 struct amdgpu_device *adev = ring->adev;
4348
4349 /* tell RLC which is KIQ queue */
4350 tmp = RREG32(mmRLC_CP_SCHEDULERS);
4351 tmp &= 0xffffff00;
4352 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
4353 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4354 tmp |= 0x80;
4355 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4356}
4357
4358static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
4359{
4360 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4361 uint64_t queue_mask = 0;
4362 int r, i;
4363
4364 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4365 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
4366 continue;
4367
4368 /* This situation may be hit in the future if a new HW
4369 * generation exposes more than 64 queues. If so, the
4370 * definition of queue_mask needs updating */
4371 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
4372 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
4373 break;
4374 }
4375
4376 queue_mask |= (1ull << i);
4377 }
4378
4379 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
4380 if (r) {
4381 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4382 return r;
4383 }
4384 /* set resources */
4385 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4386 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4387 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4388 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4389 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4390 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4391 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4392 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
4393 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4394 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4395 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
4396 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4397
4398 /* map queues */
4399 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
4400 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
4401 amdgpu_ring_write(kiq_ring,
4402 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
4403 amdgpu_ring_write(kiq_ring,
4404 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) |
4405 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
4406 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
4407 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */
4408 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
4409 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
4410 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
4411 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
4412 }
4413
4414 amdgpu_ring_commit(kiq_ring);
4415
4416 return 0;
4417}
4418
4419static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
4420{
4421 int i, r = 0;
4422
4423 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4424 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
4425 for (i = 0; i < adev->usec_timeout; i++) {
4426 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4427 break;
4428 udelay(1);
4429 }
4430 if (i == adev->usec_timeout)
4431 r = -ETIMEDOUT;
4432 }
4433 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
4434 WREG32(mmCP_HQD_PQ_RPTR, 0);
4435 WREG32(mmCP_HQD_PQ_WPTR, 0);
4436
4437 return r;
4438}
4439
4440static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd)
4441{
4442 struct amdgpu_device *adev = ring->adev;
4443
4444 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4445 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
4446 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
4447 mqd->cp_hqd_queue_priority =
4448 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
4449 }
4450 }
4451}
4452
4453static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4454{
4455 struct amdgpu_device *adev = ring->adev;
4456 struct vi_mqd *mqd = ring->mqd_ptr;
4457 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4458 uint32_t tmp;
4459
4460 mqd->header = 0xC0310800;
4461 mqd->compute_pipelinestat_enable = 0x00000001;
4462 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4463 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4464 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4465 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4466 mqd->compute_misc_reserved = 0x00000003;
4467 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4468 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4469 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4470 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4471 eop_base_addr = ring->eop_gpu_addr >> 8;
4472 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4473 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4474
4475 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4476 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4477 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4478 (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1));
4479
4480 mqd->cp_hqd_eop_control = tmp;
4481
4482 /* enable doorbell? */
4483 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
4484 CP_HQD_PQ_DOORBELL_CONTROL,
4485 DOORBELL_EN,
4486 ring->use_doorbell ? 1 : 0);
4487
4488 mqd->cp_hqd_pq_doorbell_control = tmp;
4489
4490 /* set the pointer to the MQD */
4491 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4492 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4493
4494 /* set MQD vmid to 0 */
4495 tmp = RREG32(mmCP_MQD_CONTROL);
4496 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4497 mqd->cp_mqd_control = tmp;
4498
4499 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4500 hqd_gpu_addr = ring->gpu_addr >> 8;
4501 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4502 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4503
4504 /* set up the HQD, this is similar to CP_RB0_CNTL */
4505 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4507 (order_base_2(ring->ring_size / 4) - 1));
4508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4509 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4510#ifdef __BIG_ENDIAN
4511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4512#endif
4513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4514 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4515 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4516 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4517 mqd->cp_hqd_pq_control = tmp;
4518
4519 /* set the wb address whether it's enabled or not */
4520 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4521 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4522 mqd->cp_hqd_pq_rptr_report_addr_hi =
4523 upper_32_bits(wb_gpu_addr) & 0xffff;
4524
4525 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4526 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4527 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4528 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4529
4530 tmp = 0;
4531 /* enable the doorbell if requested */
4532 if (ring->use_doorbell) {
4533 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4535 DOORBELL_OFFSET, ring->doorbell_index);
4536
4537 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4538 DOORBELL_EN, 1);
4539 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4540 DOORBELL_SOURCE, 0);
4541 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4542 DOORBELL_HIT, 0);
4543 }
4544
4545 mqd->cp_hqd_pq_doorbell_control = tmp;
4546
4547 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4548 ring->wptr = 0;
4549 mqd->cp_hqd_pq_wptr = ring->wptr;
4550 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4551
4552 /* set the vmid for the queue */
4553 mqd->cp_hqd_vmid = 0;
4554
4555 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4556 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4557 mqd->cp_hqd_persistent_state = tmp;
4558
4559 /* set MTYPE */
4560 tmp = RREG32(mmCP_HQD_IB_CONTROL);
4561 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4562 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
4563 mqd->cp_hqd_ib_control = tmp;
4564
4565 tmp = RREG32(mmCP_HQD_IQ_TIMER);
4566 tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
4567 mqd->cp_hqd_iq_timer = tmp;
4568
4569 tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
4570 tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4571 mqd->cp_hqd_ctx_save_control = tmp;
4572
4573 /* defaults */
4574 mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4575 mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4576 mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4577 mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4578 mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4579 mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4580 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4581 mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4582 mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4583 mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4584 mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4585 mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4586
4587 /* set static priority for a queue/ring */
4588 gfx_v8_0_mqd_set_priority(ring, mqd);
4589 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4590
4591 /* map_queues packet doesn't need activate the queue,
4592 * so only kiq need set this field.
4593 */
4594 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
4595 mqd->cp_hqd_active = 1;
4596
4597 return 0;
4598}
4599
4600static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4601 struct vi_mqd *mqd)
4602{
4603 uint32_t mqd_reg;
4604 uint32_t *mqd_data;
4605
4606 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4607 mqd_data = &mqd->cp_mqd_base_addr_lo;
4608
4609 /* disable wptr polling */
4610 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4611
4612 /* program all HQD registers */
4613 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
4614 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4615
4616 /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
4617 * This is safe since EOP RPTR==WPTR for any inactive HQD
4618 * on ASICs that do not support context-save.
4619 * EOP writes/reads can start anywhere in the ring.
4620 */
4621 if (adev->asic_type != CHIP_TONGA) {
4622 WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4623 WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4624 WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4625 }
4626
4627 for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
4628 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4629
4630 /* activate the HQD */
4631 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4632 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4633
4634 return 0;
4635}
4636
4637static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4638{
4639 struct amdgpu_device *adev = ring->adev;
4640 struct vi_mqd *mqd = ring->mqd_ptr;
4641 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
4642
4643 gfx_v8_0_kiq_setting(ring);
4644
4645 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4646 /* reset MQD to a clean status */
4647 if (adev->gfx.mec.mqd_backup[mqd_idx])
4648 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4649
4650 /* reset ring buffer */
4651 ring->wptr = 0;
4652 amdgpu_ring_clear_ring(ring);
4653 mutex_lock(&adev->srbm_mutex);
4654 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4655 gfx_v8_0_mqd_commit(adev, mqd);
4656 vi_srbm_select(adev, 0, 0, 0, 0);
4657 mutex_unlock(&adev->srbm_mutex);
4658 } else {
4659 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4660 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4661 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4662 mutex_lock(&adev->srbm_mutex);
4663 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4664 gfx_v8_0_mqd_init(ring);
4665 gfx_v8_0_mqd_commit(adev, mqd);
4666 vi_srbm_select(adev, 0, 0, 0, 0);
4667 mutex_unlock(&adev->srbm_mutex);
4668
4669 if (adev->gfx.mec.mqd_backup[mqd_idx])
4670 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4671 }
4672
4673 return 0;
4674}
4675
4676static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4677{
4678 struct amdgpu_device *adev = ring->adev;
4679 struct vi_mqd *mqd = ring->mqd_ptr;
4680 int mqd_idx = ring - &adev->gfx.compute_ring[0];
4681
4682 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4683 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4684 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4685 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4686 mutex_lock(&adev->srbm_mutex);
4687 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4688 gfx_v8_0_mqd_init(ring);
4689 vi_srbm_select(adev, 0, 0, 0, 0);
4690 mutex_unlock(&adev->srbm_mutex);
4691
4692 if (adev->gfx.mec.mqd_backup[mqd_idx])
4693 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4694 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4695 /* reset MQD to a clean status */
4696 if (adev->gfx.mec.mqd_backup[mqd_idx])
4697 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4698 /* reset ring buffer */
4699 ring->wptr = 0;
4700 amdgpu_ring_clear_ring(ring);
4701 } else {
4702 amdgpu_ring_clear_ring(ring);
4703 }
4704 return 0;
4705}
4706
4707static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
4708{
4709 if (adev->asic_type > CHIP_TONGA) {
4710 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
4711 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
4712 }
4713 /* enable doorbells */
4714 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4715}
4716
4717static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4718{
4719 struct amdgpu_ring *ring;
4720 int r;
4721
4722 ring = &adev->gfx.kiq.ring;
4723
4724 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4725 if (unlikely(r != 0))
4726 return r;
4727
4728 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4729 if (unlikely(r != 0))
4730 return r;
4731
4732 gfx_v8_0_kiq_init_queue(ring);
4733 amdgpu_bo_kunmap(ring->mqd_obj);
4734 ring->mqd_ptr = NULL;
4735 amdgpu_bo_unreserve(ring->mqd_obj);
4736 ring->sched.ready = true;
4737 return 0;
4738}
4739
4740static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
4741{
4742 struct amdgpu_ring *ring = NULL;
4743 int r = 0, i;
4744
4745 gfx_v8_0_cp_compute_enable(adev, true);
4746
4747 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4748 ring = &adev->gfx.compute_ring[i];
4749
4750 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4751 if (unlikely(r != 0))
4752 goto done;
4753 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4754 if (!r) {
4755 r = gfx_v8_0_kcq_init_queue(ring);
4756 amdgpu_bo_kunmap(ring->mqd_obj);
4757 ring->mqd_ptr = NULL;
4758 }
4759 amdgpu_bo_unreserve(ring->mqd_obj);
4760 if (r)
4761 goto done;
4762 }
4763
4764 gfx_v8_0_set_mec_doorbell_range(adev);
4765
4766 r = gfx_v8_0_kiq_kcq_enable(adev);
4767 if (r)
4768 goto done;
4769
4770done:
4771 return r;
4772}
4773
4774static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
4775{
4776 int r, i;
4777 struct amdgpu_ring *ring;
4778
4779 /* collect all the ring_tests here, gfx, kiq, compute */
4780 ring = &adev->gfx.gfx_ring[0];
4781 r = amdgpu_ring_test_helper(ring);
4782 if (r)
4783 return r;
4784
4785 ring = &adev->gfx.kiq.ring;
4786 r = amdgpu_ring_test_helper(ring);
4787 if (r)
4788 return r;
4789
4790 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4791 ring = &adev->gfx.compute_ring[i];
4792 amdgpu_ring_test_helper(ring);
4793 }
4794
4795 return 0;
4796}
4797
4798static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4799{
4800 int r;
4801
4802 if (!(adev->flags & AMD_IS_APU))
4803 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4804
4805 r = gfx_v8_0_kiq_resume(adev);
4806 if (r)
4807 return r;
4808
4809 r = gfx_v8_0_cp_gfx_resume(adev);
4810 if (r)
4811 return r;
4812
4813 r = gfx_v8_0_kcq_resume(adev);
4814 if (r)
4815 return r;
4816
4817 r = gfx_v8_0_cp_test_all_rings(adev);
4818 if (r)
4819 return r;
4820
4821 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4822
4823 return 0;
4824}
4825
4826static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4827{
4828 gfx_v8_0_cp_gfx_enable(adev, enable);
4829 gfx_v8_0_cp_compute_enable(adev, enable);
4830}
4831
4832static int gfx_v8_0_hw_init(void *handle)
4833{
4834 int r;
4835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4836
4837 gfx_v8_0_init_golden_registers(adev);
4838 gfx_v8_0_constants_init(adev);
4839
4840 r = adev->gfx.rlc.funcs->resume(adev);
4841 if (r)
4842 return r;
4843
4844 r = gfx_v8_0_cp_resume(adev);
4845
4846 return r;
4847}
4848
4849static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
4850{
4851 int r, i;
4852 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4853
4854 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
4855 if (r)
4856 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4857
4858 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4859 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4860
4861 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
4862 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
4863 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
4864 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
4865 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
4866 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
4867 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
4868 amdgpu_ring_write(kiq_ring, 0);
4869 amdgpu_ring_write(kiq_ring, 0);
4870 amdgpu_ring_write(kiq_ring, 0);
4871 }
4872 r = amdgpu_ring_test_helper(kiq_ring);
4873 if (r)
4874 DRM_ERROR("KCQ disable failed\n");
4875
4876 return r;
4877}
4878
4879static bool gfx_v8_0_is_idle(void *handle)
4880{
4881 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4882
4883 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
4884 || RREG32(mmGRBM_STATUS2) != 0x8)
4885 return false;
4886 else
4887 return true;
4888}
4889
4890static bool gfx_v8_0_rlc_is_idle(void *handle)
4891{
4892 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4893
4894 if (RREG32(mmGRBM_STATUS2) != 0x8)
4895 return false;
4896 else
4897 return true;
4898}
4899
4900static int gfx_v8_0_wait_for_rlc_idle(void *handle)
4901{
4902 unsigned int i;
4903 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4904
4905 for (i = 0; i < adev->usec_timeout; i++) {
4906 if (gfx_v8_0_rlc_is_idle(handle))
4907 return 0;
4908
4909 udelay(1);
4910 }
4911 return -ETIMEDOUT;
4912}
4913
4914static int gfx_v8_0_wait_for_idle(void *handle)
4915{
4916 unsigned int i;
4917 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4918
4919 for (i = 0; i < adev->usec_timeout; i++) {
4920 if (gfx_v8_0_is_idle(handle))
4921 return 0;
4922
4923 udelay(1);
4924 }
4925 return -ETIMEDOUT;
4926}
4927
4928static int gfx_v8_0_hw_fini(void *handle)
4929{
4930 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4931
4932 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4933 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4934
4935 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4936
4937 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);
4938
4939 /* disable KCQ to avoid CPC touch memory not valid anymore */
4940 gfx_v8_0_kcq_disable(adev);
4941
4942 if (amdgpu_sriov_vf(adev)) {
4943 pr_debug("For SRIOV client, shouldn't do anything.\n");
4944 return 0;
4945 }
4946 amdgpu_gfx_rlc_enter_safe_mode(adev);
4947 if (!gfx_v8_0_wait_for_idle(adev))
4948 gfx_v8_0_cp_enable(adev, false);
4949 else
4950 pr_err("cp is busy, skip halt cp\n");
4951 if (!gfx_v8_0_wait_for_rlc_idle(adev))
4952 adev->gfx.rlc.funcs->stop(adev);
4953 else
4954 pr_err("rlc is busy, skip halt rlc\n");
4955 amdgpu_gfx_rlc_exit_safe_mode(adev);
4956
4957 return 0;
4958}
4959
4960static int gfx_v8_0_suspend(void *handle)
4961{
4962 return gfx_v8_0_hw_fini(handle);
4963}
4964
4965static int gfx_v8_0_resume(void *handle)
4966{
4967 return gfx_v8_0_hw_init(handle);
4968}
4969
4970static bool gfx_v8_0_check_soft_reset(void *handle)
4971{
4972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4973 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4974 u32 tmp;
4975
4976 /* GRBM_STATUS */
4977 tmp = RREG32(mmGRBM_STATUS);
4978 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4979 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4980 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4981 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4982 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4983 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
4984 GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4985 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4986 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4987 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4988 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4989 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4990 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4991 }
4992
4993 /* GRBM_STATUS2 */
4994 tmp = RREG32(mmGRBM_STATUS2);
4995 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4996 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4997 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4998
4999 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
5000 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
5001 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
5002 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5003 SOFT_RESET_CPF, 1);
5004 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5005 SOFT_RESET_CPC, 1);
5006 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5007 SOFT_RESET_CPG, 1);
5008 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
5009 SOFT_RESET_GRBM, 1);
5010 }
5011
5012 /* SRBM_STATUS */
5013 tmp = RREG32(mmSRBM_STATUS);
5014 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
5015 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5016 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5017 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
5018 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5019 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
5020
5021 if (grbm_soft_reset || srbm_soft_reset) {
5022 adev->gfx.grbm_soft_reset = grbm_soft_reset;
5023 adev->gfx.srbm_soft_reset = srbm_soft_reset;
5024 return true;
5025 } else {
5026 adev->gfx.grbm_soft_reset = 0;
5027 adev->gfx.srbm_soft_reset = 0;
5028 return false;
5029 }
5030}
5031
5032static int gfx_v8_0_pre_soft_reset(void *handle)
5033{
5034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5035 u32 grbm_soft_reset = 0;
5036
5037 if ((!adev->gfx.grbm_soft_reset) &&
5038 (!adev->gfx.srbm_soft_reset))
5039 return 0;
5040
5041 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5042
5043 /* stop the rlc */
5044 adev->gfx.rlc.funcs->stop(adev);
5045
5046 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5047 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5048 /* Disable GFX parsing/prefetching */
5049 gfx_v8_0_cp_gfx_enable(adev, false);
5050
5051 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5052 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5053 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5054 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5055 int i;
5056
5057 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5058 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5059
5060 mutex_lock(&adev->srbm_mutex);
5061 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5062 gfx_v8_0_deactivate_hqd(adev, 2);
5063 vi_srbm_select(adev, 0, 0, 0, 0);
5064 mutex_unlock(&adev->srbm_mutex);
5065 }
5066 /* Disable MEC parsing/prefetching */
5067 gfx_v8_0_cp_compute_enable(adev, false);
5068 }
5069
5070 return 0;
5071}
5072
5073static int gfx_v8_0_soft_reset(void *handle)
5074{
5075 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5076 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5077 u32 tmp;
5078
5079 if ((!adev->gfx.grbm_soft_reset) &&
5080 (!adev->gfx.srbm_soft_reset))
5081 return 0;
5082
5083 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5084 srbm_soft_reset = adev->gfx.srbm_soft_reset;
5085
5086 if (grbm_soft_reset || srbm_soft_reset) {
5087 tmp = RREG32(mmGMCON_DEBUG);
5088 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5089 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5090 WREG32(mmGMCON_DEBUG, tmp);
5091 udelay(50);
5092 }
5093
5094 if (grbm_soft_reset) {
5095 tmp = RREG32(mmGRBM_SOFT_RESET);
5096 tmp |= grbm_soft_reset;
5097 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5098 WREG32(mmGRBM_SOFT_RESET, tmp);
5099 tmp = RREG32(mmGRBM_SOFT_RESET);
5100
5101 udelay(50);
5102
5103 tmp &= ~grbm_soft_reset;
5104 WREG32(mmGRBM_SOFT_RESET, tmp);
5105 tmp = RREG32(mmGRBM_SOFT_RESET);
5106 }
5107
5108 if (srbm_soft_reset) {
5109 tmp = RREG32(mmSRBM_SOFT_RESET);
5110 tmp |= srbm_soft_reset;
5111 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5112 WREG32(mmSRBM_SOFT_RESET, tmp);
5113 tmp = RREG32(mmSRBM_SOFT_RESET);
5114
5115 udelay(50);
5116
5117 tmp &= ~srbm_soft_reset;
5118 WREG32(mmSRBM_SOFT_RESET, tmp);
5119 tmp = RREG32(mmSRBM_SOFT_RESET);
5120 }
5121
5122 if (grbm_soft_reset || srbm_soft_reset) {
5123 tmp = RREG32(mmGMCON_DEBUG);
5124 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5125 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5126 WREG32(mmGMCON_DEBUG, tmp);
5127 }
5128
5129 /* Wait a little for things to settle down */
5130 udelay(50);
5131
5132 return 0;
5133}
5134
5135static int gfx_v8_0_post_soft_reset(void *handle)
5136{
5137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5138 u32 grbm_soft_reset = 0;
5139
5140 if ((!adev->gfx.grbm_soft_reset) &&
5141 (!adev->gfx.srbm_soft_reset))
5142 return 0;
5143
5144 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5145
5146 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5147 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5148 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5149 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5150 int i;
5151
5152 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5153 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5154
5155 mutex_lock(&adev->srbm_mutex);
5156 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5157 gfx_v8_0_deactivate_hqd(adev, 2);
5158 vi_srbm_select(adev, 0, 0, 0, 0);
5159 mutex_unlock(&adev->srbm_mutex);
5160 }
5161 gfx_v8_0_kiq_resume(adev);
5162 gfx_v8_0_kcq_resume(adev);
5163 }
5164
5165 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5166 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5167 gfx_v8_0_cp_gfx_resume(adev);
5168
5169 gfx_v8_0_cp_test_all_rings(adev);
5170
5171 adev->gfx.rlc.funcs->start(adev);
5172
5173 return 0;
5174}
5175
5176/**
5177 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5178 *
5179 * @adev: amdgpu_device pointer
5180 *
5181 * Fetches a GPU clock counter snapshot.
5182 * Returns the 64 bit clock counter snapshot.
5183 */
5184static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5185{
5186 uint64_t clock;
5187
5188 mutex_lock(&adev->gfx.gpu_clock_mutex);
5189 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5190 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5191 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5192 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5193 return clock;
5194}
5195
5196static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5197 uint32_t vmid,
5198 uint32_t gds_base, uint32_t gds_size,
5199 uint32_t gws_base, uint32_t gws_size,
5200 uint32_t oa_base, uint32_t oa_size)
5201{
5202 /* GDS Base */
5203 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5204 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5205 WRITE_DATA_DST_SEL(0)));
5206 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5207 amdgpu_ring_write(ring, 0);
5208 amdgpu_ring_write(ring, gds_base);
5209
5210 /* GDS Size */
5211 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5212 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5213 WRITE_DATA_DST_SEL(0)));
5214 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5215 amdgpu_ring_write(ring, 0);
5216 amdgpu_ring_write(ring, gds_size);
5217
5218 /* GWS */
5219 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5220 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5221 WRITE_DATA_DST_SEL(0)));
5222 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5223 amdgpu_ring_write(ring, 0);
5224 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5225
5226 /* OA */
5227 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5228 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5229 WRITE_DATA_DST_SEL(0)));
5230 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5231 amdgpu_ring_write(ring, 0);
5232 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5233}
5234
5235static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5236{
5237 WREG32(mmSQ_IND_INDEX,
5238 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5239 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5240 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5241 (SQ_IND_INDEX__FORCE_READ_MASK));
5242 return RREG32(mmSQ_IND_DATA);
5243}
5244
5245static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5246 uint32_t wave, uint32_t thread,
5247 uint32_t regno, uint32_t num, uint32_t *out)
5248{
5249 WREG32(mmSQ_IND_INDEX,
5250 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5251 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5252 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5253 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5254 (SQ_IND_INDEX__FORCE_READ_MASK) |
5255 (SQ_IND_INDEX__AUTO_INCR_MASK));
5256 while (num--)
5257 *(out++) = RREG32(mmSQ_IND_DATA);
5258}
5259
5260static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5261{
5262 /* type 0 wave data */
5263 dst[(*no_fields)++] = 0;
5264 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5265 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5266 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5267 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5268 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5269 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5270 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5271 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5272 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5273 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5274 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5275 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
5276 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5277 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5278 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5279 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5280 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5281 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
5282}
5283
5284static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
5285 uint32_t wave, uint32_t start,
5286 uint32_t size, uint32_t *dst)
5287{
5288 wave_read_regs(
5289 adev, simd, wave, 0,
5290 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5291}
5292
5293
5294static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5295 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5296 .select_se_sh = &gfx_v8_0_select_se_sh,
5297 .read_wave_data = &gfx_v8_0_read_wave_data,
5298 .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5299 .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
5300};
5301
5302static int gfx_v8_0_early_init(void *handle)
5303{
5304 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5305
5306 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5307 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
5308 AMDGPU_MAX_COMPUTE_RINGS);
5309 adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
5310 gfx_v8_0_set_ring_funcs(adev);
5311 gfx_v8_0_set_irq_funcs(adev);
5312 gfx_v8_0_set_gds_init(adev);
5313 gfx_v8_0_set_rlc_funcs(adev);
5314
5315 return 0;
5316}
5317
5318static int gfx_v8_0_late_init(void *handle)
5319{
5320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5321 int r;
5322
5323 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5324 if (r)
5325 return r;
5326
5327 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5328 if (r)
5329 return r;
5330
5331 /* requires IBs so do in late init after IB pool is initialized */
5332 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5333 if (r)
5334 return r;
5335
5336 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
5337 if (r) {
5338 DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r);
5339 return r;
5340 }
5341
5342 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);
5343 if (r) {
5344 DRM_ERROR(
5345 "amdgpu_irq_get() failed to get IRQ for SQ, r: %d.\n",
5346 r);
5347 return r;
5348 }
5349
5350 return 0;
5351}
5352
5353static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5354 bool enable)
5355{
5356 if ((adev->asic_type == CHIP_POLARIS11) ||
5357 (adev->asic_type == CHIP_POLARIS12) ||
5358 (adev->asic_type == CHIP_VEGAM))
5359 /* Send msg to SMU via Powerplay */
5360 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
5361
5362 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5363}
5364
5365static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5366 bool enable)
5367{
5368 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5369}
5370
5371static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5372 bool enable)
5373{
5374 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5375}
5376
5377static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5378 bool enable)
5379{
5380 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5381}
5382
5383static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5384 bool enable)
5385{
5386 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
5387
5388 /* Read any GFX register to wake up GFX. */
5389 if (!enable)
5390 RREG32(mmDB_RENDER_CONTROL);
5391}
5392
5393static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5394 bool enable)
5395{
5396 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5397 cz_enable_gfx_cg_power_gating(adev, true);
5398 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5399 cz_enable_gfx_pipeline_power_gating(adev, true);
5400 } else {
5401 cz_enable_gfx_cg_power_gating(adev, false);
5402 cz_enable_gfx_pipeline_power_gating(adev, false);
5403 }
5404}
5405
5406static int gfx_v8_0_set_powergating_state(void *handle,
5407 enum amd_powergating_state state)
5408{
5409 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5410 bool enable = (state == AMD_PG_STATE_GATE);
5411
5412 if (amdgpu_sriov_vf(adev))
5413 return 0;
5414
5415 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5416 AMD_PG_SUPPORT_RLC_SMU_HS |
5417 AMD_PG_SUPPORT_CP |
5418 AMD_PG_SUPPORT_GFX_DMG))
5419 amdgpu_gfx_rlc_enter_safe_mode(adev);
5420 switch (adev->asic_type) {
5421 case CHIP_CARRIZO:
5422 case CHIP_STONEY:
5423
5424 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5425 cz_enable_sck_slow_down_on_power_up(adev, true);
5426 cz_enable_sck_slow_down_on_power_down(adev, true);
5427 } else {
5428 cz_enable_sck_slow_down_on_power_up(adev, false);
5429 cz_enable_sck_slow_down_on_power_down(adev, false);
5430 }
5431 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5432 cz_enable_cp_power_gating(adev, true);
5433 else
5434 cz_enable_cp_power_gating(adev, false);
5435
5436 cz_update_gfx_cg_power_gating(adev, enable);
5437
5438 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5439 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5440 else
5441 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5442
5443 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5444 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5445 else
5446 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5447 break;
5448 case CHIP_POLARIS11:
5449 case CHIP_POLARIS12:
5450 case CHIP_VEGAM:
5451 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5452 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5453 else
5454 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5455
5456 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5457 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5458 else
5459 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5460
5461 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5462 polaris11_enable_gfx_quick_mg_power_gating(adev, true);
5463 else
5464 polaris11_enable_gfx_quick_mg_power_gating(adev, false);
5465 break;
5466 default:
5467 break;
5468 }
5469 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5470 AMD_PG_SUPPORT_RLC_SMU_HS |
5471 AMD_PG_SUPPORT_CP |
5472 AMD_PG_SUPPORT_GFX_DMG))
5473 amdgpu_gfx_rlc_exit_safe_mode(adev);
5474 return 0;
5475}
5476
5477static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags)
5478{
5479 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5480 int data;
5481
5482 if (amdgpu_sriov_vf(adev))
5483 *flags = 0;
5484
5485 /* AMD_CG_SUPPORT_GFX_MGCG */
5486 data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5487 if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
5488 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5489
5490 /* AMD_CG_SUPPORT_GFX_CGLG */
5491 data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5492 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5493 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5494
5495 /* AMD_CG_SUPPORT_GFX_CGLS */
5496 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5497 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5498
5499 /* AMD_CG_SUPPORT_GFX_CGTS */
5500 data = RREG32(mmCGTS_SM_CTRL_REG);
5501 if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
5502 *flags |= AMD_CG_SUPPORT_GFX_CGTS;
5503
5504 /* AMD_CG_SUPPORT_GFX_CGTS_LS */
5505 if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
5506 *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
5507
5508 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5509 data = RREG32(mmRLC_MEM_SLP_CNTL);
5510 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5511 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5512
5513 /* AMD_CG_SUPPORT_GFX_CP_LS */
5514 data = RREG32(mmCP_MEM_SLP_CNTL);
5515 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5516 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5517}
5518
5519static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
5520 uint32_t reg_addr, uint32_t cmd)
5521{
5522 uint32_t data;
5523
5524 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5525
5526 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5527 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5528
5529 data = RREG32(mmRLC_SERDES_WR_CTRL);
5530 if (adev->asic_type == CHIP_STONEY)
5531 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5532 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5533 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5534 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5535 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5536 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5537 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5538 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5539 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5540 else
5541 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5542 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5543 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5544 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5545 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5546 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5547 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5548 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5549 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5550 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5551 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5552 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
5553 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5554 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5555 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
5556
5557 WREG32(mmRLC_SERDES_WR_CTRL, data);
5558}
5559
5560#define MSG_ENTER_RLC_SAFE_MODE 1
5561#define MSG_EXIT_RLC_SAFE_MODE 0
5562#define RLC_GPR_REG2__REQ_MASK 0x00000001
5563#define RLC_GPR_REG2__REQ__SHIFT 0
5564#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5565#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5566
5567static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
5568{
5569 uint32_t rlc_setting;
5570
5571 rlc_setting = RREG32(mmRLC_CNTL);
5572 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
5573 return false;
5574
5575 return true;
5576}
5577
5578static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev)
5579{
5580 uint32_t data;
5581 unsigned i;
5582 data = RREG32(mmRLC_CNTL);
5583 data |= RLC_SAFE_MODE__CMD_MASK;
5584 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5585 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5586 WREG32(mmRLC_SAFE_MODE, data);
5587
5588 /* wait for RLC_SAFE_MODE */
5589 for (i = 0; i < adev->usec_timeout; i++) {
5590 if ((RREG32(mmRLC_GPM_STAT) &
5591 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5592 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5593 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5594 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5595 break;
5596 udelay(1);
5597 }
5598 for (i = 0; i < adev->usec_timeout; i++) {
5599 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5600 break;
5601 udelay(1);
5602 }
5603}
5604
5605static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev)
5606{
5607 uint32_t data;
5608 unsigned i;
5609
5610 data = RREG32(mmRLC_CNTL);
5611 data |= RLC_SAFE_MODE__CMD_MASK;
5612 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5613 WREG32(mmRLC_SAFE_MODE, data);
5614
5615 for (i = 0; i < adev->usec_timeout; i++) {
5616 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5617 break;
5618 udelay(1);
5619 }
5620}
5621
5622static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5623{
5624 u32 data;
5625
5626 if (amdgpu_sriov_is_pp_one_vf(adev))
5627 data = RREG32_NO_KIQ(mmRLC_SPM_VMID);
5628 else
5629 data = RREG32(mmRLC_SPM_VMID);
5630
5631 data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;
5632 data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;
5633
5634 if (amdgpu_sriov_is_pp_one_vf(adev))
5635 WREG32_NO_KIQ(mmRLC_SPM_VMID, data);
5636 else
5637 WREG32(mmRLC_SPM_VMID, data);
5638}
5639
5640static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5641 .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
5642 .set_safe_mode = gfx_v8_0_set_safe_mode,
5643 .unset_safe_mode = gfx_v8_0_unset_safe_mode,
5644 .init = gfx_v8_0_rlc_init,
5645 .get_csb_size = gfx_v8_0_get_csb_size,
5646 .get_csb_buffer = gfx_v8_0_get_csb_buffer,
5647 .get_cp_table_num = gfx_v8_0_cp_jump_table_num,
5648 .resume = gfx_v8_0_rlc_resume,
5649 .stop = gfx_v8_0_rlc_stop,
5650 .reset = gfx_v8_0_rlc_reset,
5651 .start = gfx_v8_0_rlc_start,
5652 .update_spm_vmid = gfx_v8_0_update_spm_vmid
5653};
5654
5655static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5656 bool enable)
5657{
5658 uint32_t temp, data;
5659
5660 amdgpu_gfx_rlc_enter_safe_mode(adev);
5661
5662 /* It is disabled by HW by default */
5663 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5664 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5665 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
5666 /* 1 - RLC memory Light sleep */
5667 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
5668
5669 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5670 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
5671 }
5672
5673 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5674 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5675 if (adev->flags & AMD_IS_APU)
5676 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5677 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5678 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5679 else
5680 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5681 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5682 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5683 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5684
5685 if (temp != data)
5686 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5687
5688 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5689 gfx_v8_0_wait_for_rlc_serdes(adev);
5690
5691 /* 5 - clear mgcg override */
5692 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5693
5694 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5695 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5696 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5697 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5698 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5699 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5700 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5701 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5702 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5703 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5704 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5705 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5706 if (temp != data)
5707 WREG32(mmCGTS_SM_CTRL_REG, data);
5708 }
5709 udelay(50);
5710
5711 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5712 gfx_v8_0_wait_for_rlc_serdes(adev);
5713 } else {
5714 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5715 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5716 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5717 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5718 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5719 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5720 if (temp != data)
5721 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5722
5723 /* 2 - disable MGLS in RLC */
5724 data = RREG32(mmRLC_MEM_SLP_CNTL);
5725 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5726 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5727 WREG32(mmRLC_MEM_SLP_CNTL, data);
5728 }
5729
5730 /* 3 - disable MGLS in CP */
5731 data = RREG32(mmCP_MEM_SLP_CNTL);
5732 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5733 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5734 WREG32(mmCP_MEM_SLP_CNTL, data);
5735 }
5736
5737 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5738 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5739 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5740 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5741 if (temp != data)
5742 WREG32(mmCGTS_SM_CTRL_REG, data);
5743
5744 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5745 gfx_v8_0_wait_for_rlc_serdes(adev);
5746
5747 /* 6 - set mgcg override */
5748 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5749
5750 udelay(50);
5751
5752 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5753 gfx_v8_0_wait_for_rlc_serdes(adev);
5754 }
5755
5756 amdgpu_gfx_rlc_exit_safe_mode(adev);
5757}
5758
5759static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5760 bool enable)
5761{
5762 uint32_t temp, temp1, data, data1;
5763
5764 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5765
5766 amdgpu_gfx_rlc_enter_safe_mode(adev);
5767
5768 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5769 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5770 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5771 if (temp1 != data1)
5772 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5773
5774 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5775 gfx_v8_0_wait_for_rlc_serdes(adev);
5776
5777 /* 2 - clear cgcg override */
5778 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5779
5780 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5781 gfx_v8_0_wait_for_rlc_serdes(adev);
5782
5783 /* 3 - write cmd to set CGLS */
5784 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5785
5786 /* 4 - enable cgcg */
5787 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5788
5789 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5790 /* enable cgls*/
5791 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5792
5793 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5794 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
5795
5796 if (temp1 != data1)
5797 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5798 } else {
5799 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5800 }
5801
5802 if (temp != data)
5803 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5804
5805 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5806 * Cmp_busy/GFX_Idle interrupts
5807 */
5808 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5809 } else {
5810 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5811 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5812
5813 /* TEST CGCG */
5814 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5815 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5816 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5817 if (temp1 != data1)
5818 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5819
5820 /* read gfx register to wake up cgcg */
5821 RREG32(mmCB_CGTT_SCLK_CTRL);
5822 RREG32(mmCB_CGTT_SCLK_CTRL);
5823 RREG32(mmCB_CGTT_SCLK_CTRL);
5824 RREG32(mmCB_CGTT_SCLK_CTRL);
5825
5826 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5827 gfx_v8_0_wait_for_rlc_serdes(adev);
5828
5829 /* write cmd to Set CGCG Overrride */
5830 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5831
5832 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5833 gfx_v8_0_wait_for_rlc_serdes(adev);
5834
5835 /* write cmd to Clear CGLS */
5836 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
5837
5838 /* disable cgcg, cgls should be disabled too. */
5839 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
5840 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
5841 if (temp != data)
5842 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5843 /* enable interrupts again for PG */
5844 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5845 }
5846
5847 gfx_v8_0_wait_for_rlc_serdes(adev);
5848
5849 amdgpu_gfx_rlc_exit_safe_mode(adev);
5850}
5851static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5852 bool enable)
5853{
5854 if (enable) {
5855 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5856 * === MGCG + MGLS + TS(CG/LS) ===
5857 */
5858 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5859 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5860 } else {
5861 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5862 * === CGCG + CGLS ===
5863 */
5864 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5865 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5866 }
5867 return 0;
5868}
5869
5870static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5871 enum amd_clockgating_state state)
5872{
5873 uint32_t msg_id, pp_state = 0;
5874 uint32_t pp_support_state = 0;
5875
5876 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5877 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5878 pp_support_state = PP_STATE_SUPPORT_LS;
5879 pp_state = PP_STATE_LS;
5880 }
5881 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5882 pp_support_state |= PP_STATE_SUPPORT_CG;
5883 pp_state |= PP_STATE_CG;
5884 }
5885 if (state == AMD_CG_STATE_UNGATE)
5886 pp_state = 0;
5887
5888 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5889 PP_BLOCK_GFX_CG,
5890 pp_support_state,
5891 pp_state);
5892 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5893 }
5894
5895 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5896 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5897 pp_support_state = PP_STATE_SUPPORT_LS;
5898 pp_state = PP_STATE_LS;
5899 }
5900
5901 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5902 pp_support_state |= PP_STATE_SUPPORT_CG;
5903 pp_state |= PP_STATE_CG;
5904 }
5905
5906 if (state == AMD_CG_STATE_UNGATE)
5907 pp_state = 0;
5908
5909 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5910 PP_BLOCK_GFX_MG,
5911 pp_support_state,
5912 pp_state);
5913 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5914 }
5915
5916 return 0;
5917}
5918
5919static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5920 enum amd_clockgating_state state)
5921{
5922
5923 uint32_t msg_id, pp_state = 0;
5924 uint32_t pp_support_state = 0;
5925
5926 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5927 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5928 pp_support_state = PP_STATE_SUPPORT_LS;
5929 pp_state = PP_STATE_LS;
5930 }
5931 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5932 pp_support_state |= PP_STATE_SUPPORT_CG;
5933 pp_state |= PP_STATE_CG;
5934 }
5935 if (state == AMD_CG_STATE_UNGATE)
5936 pp_state = 0;
5937
5938 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5939 PP_BLOCK_GFX_CG,
5940 pp_support_state,
5941 pp_state);
5942 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5943 }
5944
5945 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5946 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5947 pp_support_state = PP_STATE_SUPPORT_LS;
5948 pp_state = PP_STATE_LS;
5949 }
5950 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5951 pp_support_state |= PP_STATE_SUPPORT_CG;
5952 pp_state |= PP_STATE_CG;
5953 }
5954 if (state == AMD_CG_STATE_UNGATE)
5955 pp_state = 0;
5956
5957 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5958 PP_BLOCK_GFX_3D,
5959 pp_support_state,
5960 pp_state);
5961 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5962 }
5963
5964 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5965 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5966 pp_support_state = PP_STATE_SUPPORT_LS;
5967 pp_state = PP_STATE_LS;
5968 }
5969
5970 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5971 pp_support_state |= PP_STATE_SUPPORT_CG;
5972 pp_state |= PP_STATE_CG;
5973 }
5974
5975 if (state == AMD_CG_STATE_UNGATE)
5976 pp_state = 0;
5977
5978 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5979 PP_BLOCK_GFX_MG,
5980 pp_support_state,
5981 pp_state);
5982 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5983 }
5984
5985 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5986 pp_support_state = PP_STATE_SUPPORT_LS;
5987
5988 if (state == AMD_CG_STATE_UNGATE)
5989 pp_state = 0;
5990 else
5991 pp_state = PP_STATE_LS;
5992
5993 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5994 PP_BLOCK_GFX_RLC,
5995 pp_support_state,
5996 pp_state);
5997 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5998 }
5999
6000 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
6001 pp_support_state = PP_STATE_SUPPORT_LS;
6002
6003 if (state == AMD_CG_STATE_UNGATE)
6004 pp_state = 0;
6005 else
6006 pp_state = PP_STATE_LS;
6007 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
6008 PP_BLOCK_GFX_CP,
6009 pp_support_state,
6010 pp_state);
6011 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6012 }
6013
6014 return 0;
6015}
6016
6017static int gfx_v8_0_set_clockgating_state(void *handle,
6018 enum amd_clockgating_state state)
6019{
6020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6021
6022 if (amdgpu_sriov_vf(adev))
6023 return 0;
6024
6025 switch (adev->asic_type) {
6026 case CHIP_FIJI:
6027 case CHIP_CARRIZO:
6028 case CHIP_STONEY:
6029 gfx_v8_0_update_gfx_clock_gating(adev,
6030 state == AMD_CG_STATE_GATE);
6031 break;
6032 case CHIP_TONGA:
6033 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
6034 break;
6035 case CHIP_POLARIS10:
6036 case CHIP_POLARIS11:
6037 case CHIP_POLARIS12:
6038 case CHIP_VEGAM:
6039 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
6040 break;
6041 default:
6042 break;
6043 }
6044 return 0;
6045}
6046
6047static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
6048{
6049 return ring->adev->wb.wb[ring->rptr_offs];
6050}
6051
6052static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
6053{
6054 struct amdgpu_device *adev = ring->adev;
6055
6056 if (ring->use_doorbell)
6057 /* XXX check if swapping is necessary on BE */
6058 return ring->adev->wb.wb[ring->wptr_offs];
6059 else
6060 return RREG32(mmCP_RB0_WPTR);
6061}
6062
6063static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
6064{
6065 struct amdgpu_device *adev = ring->adev;
6066
6067 if (ring->use_doorbell) {
6068 /* XXX check if swapping is necessary on BE */
6069 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6070 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6071 } else {
6072 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6073 (void)RREG32(mmCP_RB0_WPTR);
6074 }
6075}
6076
6077static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6078{
6079 u32 ref_and_mask, reg_mem_engine;
6080
6081 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||
6082 (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {
6083 switch (ring->me) {
6084 case 1:
6085 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6086 break;
6087 case 2:
6088 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6089 break;
6090 default:
6091 return;
6092 }
6093 reg_mem_engine = 0;
6094 } else {
6095 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6096 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
6097 }
6098
6099 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6100 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
6101 WAIT_REG_MEM_FUNCTION(3) | /* == */
6102 reg_mem_engine));
6103 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
6104 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
6105 amdgpu_ring_write(ring, ref_and_mask);
6106 amdgpu_ring_write(ring, ref_and_mask);
6107 amdgpu_ring_write(ring, 0x20); /* poll interval */
6108}
6109
6110static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6111{
6112 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6113 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6114 EVENT_INDEX(4));
6115
6116 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6117 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6118 EVENT_INDEX(0));
6119}
6120
6121static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6122 struct amdgpu_job *job,
6123 struct amdgpu_ib *ib,
6124 uint32_t flags)
6125{
6126 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6127 u32 header, control = 0;
6128
6129 if (ib->flags & AMDGPU_IB_FLAG_CE)
6130 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
6131 else
6132 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6133
6134 control |= ib->length_dw | (vmid << 24);
6135
6136 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6137 control |= INDIRECT_BUFFER_PRE_ENB(1);
6138
6139 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
6140 gfx_v8_0_ring_emit_de_meta(ring);
6141 }
6142
6143 amdgpu_ring_write(ring, header);
6144 amdgpu_ring_write(ring,
6145#ifdef __BIG_ENDIAN
6146 (2 << 0) |
6147#endif
6148 (ib->gpu_addr & 0xFFFFFFFC));
6149 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6150 amdgpu_ring_write(ring, control);
6151}
6152
6153static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6154 struct amdgpu_job *job,
6155 struct amdgpu_ib *ib,
6156 uint32_t flags)
6157{
6158 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6159 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6160
6161 /* Currently, there is a high possibility to get wave ID mismatch
6162 * between ME and GDS, leading to a hw deadlock, because ME generates
6163 * different wave IDs than the GDS expects. This situation happens
6164 * randomly when at least 5 compute pipes use GDS ordered append.
6165 * The wave IDs generated by ME are also wrong after suspend/resume.
6166 * Those are probably bugs somewhere else in the kernel driver.
6167 *
6168 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
6169 * GDS to 0 for this ring (me/pipe).
6170 */
6171 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
6172 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
6173 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
6174 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
6175 }
6176
6177 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6178 amdgpu_ring_write(ring,
6179#ifdef __BIG_ENDIAN
6180 (2 << 0) |
6181#endif
6182 (ib->gpu_addr & 0xFFFFFFFC));
6183 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6184 amdgpu_ring_write(ring, control);
6185}
6186
6187static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
6188 u64 seq, unsigned flags)
6189{
6190 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6191 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6192
6193 /* Workaround for cache flush problems. First send a dummy EOP
6194 * event down the pipe with seq one below.
6195 */
6196 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6197 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6198 EOP_TC_ACTION_EN |
6199 EOP_TC_WB_ACTION_EN |
6200 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6201 EVENT_INDEX(5)));
6202 amdgpu_ring_write(ring, addr & 0xfffffffc);
6203 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6204 DATA_SEL(1) | INT_SEL(0));
6205 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
6206 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
6207
6208 /* Then send the real EOP event down the pipe:
6209 * EVENT_WRITE_EOP - flush caches, send int */
6210 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6211 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6212 EOP_TC_ACTION_EN |
6213 EOP_TC_WB_ACTION_EN |
6214 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6215 EVENT_INDEX(5)));
6216 amdgpu_ring_write(ring, addr & 0xfffffffc);
6217 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6218 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6219 amdgpu_ring_write(ring, lower_32_bits(seq));
6220 amdgpu_ring_write(ring, upper_32_bits(seq));
6221
6222}
6223
6224static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6225{
6226 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6227 uint32_t seq = ring->fence_drv.sync_seq;
6228 uint64_t addr = ring->fence_drv.gpu_addr;
6229
6230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6231 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
6232 WAIT_REG_MEM_FUNCTION(3) | /* equal */
6233 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
6234 amdgpu_ring_write(ring, addr & 0xfffffffc);
6235 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6236 amdgpu_ring_write(ring, seq);
6237 amdgpu_ring_write(ring, 0xffffffff);
6238 amdgpu_ring_write(ring, 4); /* poll interval */
6239}
6240
6241static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6242 unsigned vmid, uint64_t pd_addr)
6243{
6244 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6245
6246 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6247
6248 /* wait for the invalidate to complete */
6249 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6250 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6251 WAIT_REG_MEM_FUNCTION(0) | /* always */
6252 WAIT_REG_MEM_ENGINE(0))); /* me */
6253 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6254 amdgpu_ring_write(ring, 0);
6255 amdgpu_ring_write(ring, 0); /* ref */
6256 amdgpu_ring_write(ring, 0); /* mask */
6257 amdgpu_ring_write(ring, 0x20); /* poll interval */
6258
6259 /* compute doesn't have PFP */
6260 if (usepfp) {
6261 /* sync PFP to ME, otherwise we might get invalid PFP reads */
6262 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6263 amdgpu_ring_write(ring, 0x0);
6264 }
6265}
6266
6267static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6268{
6269 return ring->adev->wb.wb[ring->wptr_offs];
6270}
6271
6272static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6273{
6274 struct amdgpu_device *adev = ring->adev;
6275
6276 /* XXX check if swapping is necessary on BE */
6277 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6278 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6279}
6280
6281static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6282 u64 addr, u64 seq,
6283 unsigned flags)
6284{
6285 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6286 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6287
6288 /* RELEASE_MEM - flush caches, send int */
6289 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6290 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6291 EOP_TC_ACTION_EN |
6292 EOP_TC_WB_ACTION_EN |
6293 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6294 EVENT_INDEX(5)));
6295 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6296 amdgpu_ring_write(ring, addr & 0xfffffffc);
6297 amdgpu_ring_write(ring, upper_32_bits(addr));
6298 amdgpu_ring_write(ring, lower_32_bits(seq));
6299 amdgpu_ring_write(ring, upper_32_bits(seq));
6300}
6301
6302static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
6303 u64 seq, unsigned int flags)
6304{
6305 /* we only allocate 32bit for each seq wb address */
6306 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
6307
6308 /* write fence seq to the "addr" */
6309 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6310 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6311 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
6312 amdgpu_ring_write(ring, lower_32_bits(addr));
6313 amdgpu_ring_write(ring, upper_32_bits(addr));
6314 amdgpu_ring_write(ring, lower_32_bits(seq));
6315
6316 if (flags & AMDGPU_FENCE_FLAG_INT) {
6317 /* set register to trigger INT */
6318 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6319 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6320 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
6321 amdgpu_ring_write(ring, mmCPC_INT_STATUS);
6322 amdgpu_ring_write(ring, 0);
6323 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
6324 }
6325}
6326
6327static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6328{
6329 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6330 amdgpu_ring_write(ring, 0);
6331}
6332
6333static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6334{
6335 uint32_t dw2 = 0;
6336
6337 if (amdgpu_sriov_vf(ring->adev))
6338 gfx_v8_0_ring_emit_ce_meta(ring);
6339
6340 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6341 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6342 gfx_v8_0_ring_emit_vgt_flush(ring);
6343 /* set load_global_config & load_global_uconfig */
6344 dw2 |= 0x8001;
6345 /* set load_cs_sh_regs */
6346 dw2 |= 0x01000000;
6347 /* set load_per_context_state & load_gfx_sh_regs for GFX */
6348 dw2 |= 0x10002;
6349
6350 /* set load_ce_ram if preamble presented */
6351 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6352 dw2 |= 0x10000000;
6353 } else {
6354 /* still load_ce_ram if this is the first time preamble presented
6355 * although there is no context switch happens.
6356 */
6357 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6358 dw2 |= 0x10000000;
6359 }
6360
6361 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6362 amdgpu_ring_write(ring, dw2);
6363 amdgpu_ring_write(ring, 0);
6364}
6365
6366static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
6367{
6368 unsigned ret;
6369
6370 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
6371 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
6372 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
6373 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
6374 ret = ring->wptr & ring->buf_mask;
6375 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
6376 return ret;
6377}
6378
6379static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
6380{
6381 unsigned cur;
6382
6383 BUG_ON(offset > ring->buf_mask);
6384 BUG_ON(ring->ring[offset] != 0x55aa55aa);
6385
6386 cur = (ring->wptr & ring->buf_mask) - 1;
6387 if (likely(cur > offset))
6388 ring->ring[offset] = cur - offset;
6389 else
6390 ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
6391}
6392
6393static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
6394 uint32_t reg_val_offs)
6395{
6396 struct amdgpu_device *adev = ring->adev;
6397
6398 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6399 amdgpu_ring_write(ring, 0 | /* src: register*/
6400 (5 << 8) | /* dst: memory */
6401 (1 << 20)); /* write confirm */
6402 amdgpu_ring_write(ring, reg);
6403 amdgpu_ring_write(ring, 0);
6404 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6405 reg_val_offs * 4));
6406 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6407 reg_val_offs * 4));
6408}
6409
6410static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6411 uint32_t val)
6412{
6413 uint32_t cmd;
6414
6415 switch (ring->funcs->type) {
6416 case AMDGPU_RING_TYPE_GFX:
6417 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6418 break;
6419 case AMDGPU_RING_TYPE_KIQ:
6420 cmd = 1 << 16; /* no inc addr */
6421 break;
6422 default:
6423 cmd = WR_CONFIRM;
6424 break;
6425 }
6426
6427 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6428 amdgpu_ring_write(ring, cmd);
6429 amdgpu_ring_write(ring, reg);
6430 amdgpu_ring_write(ring, 0);
6431 amdgpu_ring_write(ring, val);
6432}
6433
6434static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
6435{
6436 struct amdgpu_device *adev = ring->adev;
6437 uint32_t value = 0;
6438
6439 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6440 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6441 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6442 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6443 WREG32(mmSQ_CMD, value);
6444}
6445
6446static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6447 enum amdgpu_interrupt_state state)
6448{
6449 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6450 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6451}
6452
6453static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6454 int me, int pipe,
6455 enum amdgpu_interrupt_state state)
6456{
6457 u32 mec_int_cntl, mec_int_cntl_reg;
6458
6459 /*
6460 * amdgpu controls only the first MEC. That's why this function only
6461 * handles the setting of interrupts for this specific MEC. All other
6462 * pipes' interrupts are set by amdkfd.
6463 */
6464
6465 if (me == 1) {
6466 switch (pipe) {
6467 case 0:
6468 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6469 break;
6470 case 1:
6471 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6472 break;
6473 case 2:
6474 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6475 break;
6476 case 3:
6477 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6478 break;
6479 default:
6480 DRM_DEBUG("invalid pipe %d\n", pipe);
6481 return;
6482 }
6483 } else {
6484 DRM_DEBUG("invalid me %d\n", me);
6485 return;
6486 }
6487
6488 switch (state) {
6489 case AMDGPU_IRQ_STATE_DISABLE:
6490 mec_int_cntl = RREG32(mec_int_cntl_reg);
6491 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6492 WREG32(mec_int_cntl_reg, mec_int_cntl);
6493 break;
6494 case AMDGPU_IRQ_STATE_ENABLE:
6495 mec_int_cntl = RREG32(mec_int_cntl_reg);
6496 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6497 WREG32(mec_int_cntl_reg, mec_int_cntl);
6498 break;
6499 default:
6500 break;
6501 }
6502}
6503
6504static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6505 struct amdgpu_irq_src *source,
6506 unsigned type,
6507 enum amdgpu_interrupt_state state)
6508{
6509 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6510 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6511
6512 return 0;
6513}
6514
6515static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6516 struct amdgpu_irq_src *source,
6517 unsigned type,
6518 enum amdgpu_interrupt_state state)
6519{
6520 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6521 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6522
6523 return 0;
6524}
6525
6526static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6527 struct amdgpu_irq_src *src,
6528 unsigned type,
6529 enum amdgpu_interrupt_state state)
6530{
6531 switch (type) {
6532 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
6533 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6534 break;
6535 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6536 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6537 break;
6538 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6539 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6540 break;
6541 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6542 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6543 break;
6544 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6545 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6546 break;
6547 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6548 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6549 break;
6550 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6551 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6552 break;
6553 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6554 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6555 break;
6556 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6557 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6558 break;
6559 default:
6560 break;
6561 }
6562 return 0;
6563}
6564
6565static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev,
6566 struct amdgpu_irq_src *source,
6567 unsigned int type,
6568 enum amdgpu_interrupt_state state)
6569{
6570 int enable_flag;
6571
6572 switch (state) {
6573 case AMDGPU_IRQ_STATE_DISABLE:
6574 enable_flag = 0;
6575 break;
6576
6577 case AMDGPU_IRQ_STATE_ENABLE:
6578 enable_flag = 1;
6579 break;
6580
6581 default:
6582 return -EINVAL;
6583 }
6584
6585 WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6586 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6587 WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6588 WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6589 WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6590 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6591 enable_flag);
6592 WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6593 enable_flag);
6594 WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6595 enable_flag);
6596 WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6597 enable_flag);
6598 WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6599 enable_flag);
6600 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6601 enable_flag);
6602 WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6603 enable_flag);
6604 WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6605 enable_flag);
6606
6607 return 0;
6608}
6609
6610static int gfx_v8_0_set_sq_int_state(struct amdgpu_device *adev,
6611 struct amdgpu_irq_src *source,
6612 unsigned int type,
6613 enum amdgpu_interrupt_state state)
6614{
6615 int enable_flag;
6616
6617 switch (state) {
6618 case AMDGPU_IRQ_STATE_DISABLE:
6619 enable_flag = 1;
6620 break;
6621
6622 case AMDGPU_IRQ_STATE_ENABLE:
6623 enable_flag = 0;
6624 break;
6625
6626 default:
6627 return -EINVAL;
6628 }
6629
6630 WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,
6631 enable_flag);
6632
6633 return 0;
6634}
6635
6636static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6637 struct amdgpu_irq_src *source,
6638 struct amdgpu_iv_entry *entry)
6639{
6640 int i;
6641 u8 me_id, pipe_id, queue_id;
6642 struct amdgpu_ring *ring;
6643
6644 DRM_DEBUG("IH: CP EOP\n");
6645 me_id = (entry->ring_id & 0x0c) >> 2;
6646 pipe_id = (entry->ring_id & 0x03) >> 0;
6647 queue_id = (entry->ring_id & 0x70) >> 4;
6648
6649 switch (me_id) {
6650 case 0:
6651 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6652 break;
6653 case 1:
6654 case 2:
6655 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6656 ring = &adev->gfx.compute_ring[i];
6657 /* Per-queue interrupt is supported for MEC starting from VI.
6658 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6659 */
6660 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6661 amdgpu_fence_process(ring);
6662 }
6663 break;
6664 }
6665 return 0;
6666}
6667
6668static void gfx_v8_0_fault(struct amdgpu_device *adev,
6669 struct amdgpu_iv_entry *entry)
6670{
6671 u8 me_id, pipe_id, queue_id;
6672 struct amdgpu_ring *ring;
6673 int i;
6674
6675 me_id = (entry->ring_id & 0x0c) >> 2;
6676 pipe_id = (entry->ring_id & 0x03) >> 0;
6677 queue_id = (entry->ring_id & 0x70) >> 4;
6678
6679 switch (me_id) {
6680 case 0:
6681 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
6682 break;
6683 case 1:
6684 case 2:
6685 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6686 ring = &adev->gfx.compute_ring[i];
6687 if (ring->me == me_id && ring->pipe == pipe_id &&
6688 ring->queue == queue_id)
6689 drm_sched_fault(&ring->sched);
6690 }
6691 break;
6692 }
6693}
6694
6695static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6696 struct amdgpu_irq_src *source,
6697 struct amdgpu_iv_entry *entry)
6698{
6699 DRM_ERROR("Illegal register access in command stream\n");
6700 gfx_v8_0_fault(adev, entry);
6701 return 0;
6702}
6703
6704static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6705 struct amdgpu_irq_src *source,
6706 struct amdgpu_iv_entry *entry)
6707{
6708 DRM_ERROR("Illegal instruction in command stream\n");
6709 gfx_v8_0_fault(adev, entry);
6710 return 0;
6711}
6712
6713static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev,
6714 struct amdgpu_irq_src *source,
6715 struct amdgpu_iv_entry *entry)
6716{
6717 DRM_ERROR("CP EDC/ECC error detected.");
6718 return 0;
6719}
6720
6721static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data,
6722 bool from_wq)
6723{
6724 u32 enc, se_id, sh_id, cu_id;
6725 char type[20];
6726 int sq_edc_source = -1;
6727
6728 enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
6729 se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
6730
6731 switch (enc) {
6732 case 0:
6733 DRM_INFO("SQ general purpose intr detected:"
6734 "se_id %d, immed_overflow %d, host_reg_overflow %d,"
6735 "host_cmd_overflow %d, cmd_timestamp %d,"
6736 "reg_timestamp %d, thread_trace_buff_full %d,"
6737 "wlt %d, thread_trace %d.\n",
6738 se_id,
6739 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
6740 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
6741 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
6742 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
6743 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
6744 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
6745 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
6746 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
6747 );
6748 break;
6749 case 1:
6750 case 2:
6751
6752 cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
6753 sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
6754
6755 /*
6756 * This function can be called either directly from ISR
6757 * or from BH in which case we can access SQ_EDC_INFO
6758 * instance
6759 */
6760 if (from_wq) {
6761 mutex_lock(&adev->grbm_idx_mutex);
6762 gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id);
6763
6764 sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
6765
6766 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6767 mutex_unlock(&adev->grbm_idx_mutex);
6768 }
6769
6770 if (enc == 1)
6771 sprintf(type, "instruction intr");
6772 else
6773 sprintf(type, "EDC/ECC error");
6774
6775 DRM_INFO(
6776 "SQ %s detected: "
6777 "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d "
6778 "trap %s, sq_ed_info.source %s.\n",
6779 type, se_id, sh_id, cu_id,
6780 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
6781 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
6782 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
6783 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
6784 (sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable"
6785 );
6786 break;
6787 default:
6788 DRM_ERROR("SQ invalid encoding type\n.");
6789 }
6790}
6791
6792static void gfx_v8_0_sq_irq_work_func(struct work_struct *work)
6793{
6794
6795 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work);
6796 struct sq_work *sq_work = container_of(work, struct sq_work, work);
6797
6798 gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data, true);
6799}
6800
6801static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
6802 struct amdgpu_irq_src *source,
6803 struct amdgpu_iv_entry *entry)
6804{
6805 unsigned ih_data = entry->src_data[0];
6806
6807 /*
6808 * Try to submit work so SQ_EDC_INFO can be accessed from
6809 * BH. If previous work submission hasn't finished yet
6810 * just print whatever info is possible directly from the ISR.
6811 */
6812 if (work_pending(&adev->gfx.sq_work.work)) {
6813 gfx_v8_0_parse_sq_irq(adev, ih_data, false);
6814 } else {
6815 adev->gfx.sq_work.ih_data = ih_data;
6816 schedule_work(&adev->gfx.sq_work.work);
6817 }
6818
6819 return 0;
6820}
6821
6822static void gfx_v8_0_emit_mem_sync(struct amdgpu_ring *ring)
6823{
6824 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
6825 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6826 PACKET3_TC_ACTION_ENA |
6827 PACKET3_SH_KCACHE_ACTION_ENA |
6828 PACKET3_SH_ICACHE_ACTION_ENA |
6829 PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6830 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6831 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6832 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6833}
6834
6835static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring)
6836{
6837 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
6838 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
6839 PACKET3_TC_ACTION_ENA |
6840 PACKET3_SH_KCACHE_ACTION_ENA |
6841 PACKET3_SH_ICACHE_ACTION_ENA |
6842 PACKET3_TC_WB_ACTION_ENA); /* CP_COHER_CNTL */
6843 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
6844 amdgpu_ring_write(ring, 0xff); /* CP_COHER_SIZE_HI */
6845 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6846 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
6847 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
6848}
6849
6850
6851/* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
6852#define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f
6853static void gfx_v8_0_emit_wave_limit_cs(struct amdgpu_ring *ring,
6854 uint32_t pipe, bool enable)
6855{
6856 uint32_t val;
6857 uint32_t wcl_cs_reg;
6858
6859 val = enable ? 0x1 : mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT;
6860
6861 switch (pipe) {
6862 case 0:
6863 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0;
6864 break;
6865 case 1:
6866 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1;
6867 break;
6868 case 2:
6869 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2;
6870 break;
6871 case 3:
6872 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3;
6873 break;
6874 default:
6875 DRM_DEBUG("invalid pipe %d\n", pipe);
6876 return;
6877 }
6878
6879 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
6880
6881}
6882
6883#define mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT 0x07ffffff
6884static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
6885{
6886 struct amdgpu_device *adev = ring->adev;
6887 uint32_t val;
6888 int i;
6889
6890 /* mmSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
6891 * number of gfx waves. Setting 5 bit will make sure gfx only gets
6892 * around 25% of gpu resources.
6893 */
6894 val = enable ? 0x1f : mmSPI_WCL_PIPE_PERCENT_GFX_DEFAULT;
6895 amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
6896
6897 /* Restrict waves for normal/low priority compute queues as well
6898 * to get best QoS for high priority compute jobs.
6899 *
6900 * amdgpu controls only 1st ME(0-3 CS pipes).
6901 */
6902 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
6903 if (i != ring->pipe)
6904 gfx_v8_0_emit_wave_limit_cs(ring, i, enable);
6905
6906 }
6907
6908}
6909
6910static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6911 .name = "gfx_v8_0",
6912 .early_init = gfx_v8_0_early_init,
6913 .late_init = gfx_v8_0_late_init,
6914 .sw_init = gfx_v8_0_sw_init,
6915 .sw_fini = gfx_v8_0_sw_fini,
6916 .hw_init = gfx_v8_0_hw_init,
6917 .hw_fini = gfx_v8_0_hw_fini,
6918 .suspend = gfx_v8_0_suspend,
6919 .resume = gfx_v8_0_resume,
6920 .is_idle = gfx_v8_0_is_idle,
6921 .wait_for_idle = gfx_v8_0_wait_for_idle,
6922 .check_soft_reset = gfx_v8_0_check_soft_reset,
6923 .pre_soft_reset = gfx_v8_0_pre_soft_reset,
6924 .soft_reset = gfx_v8_0_soft_reset,
6925 .post_soft_reset = gfx_v8_0_post_soft_reset,
6926 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6927 .set_powergating_state = gfx_v8_0_set_powergating_state,
6928 .get_clockgating_state = gfx_v8_0_get_clockgating_state,
6929};
6930
6931static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6932 .type = AMDGPU_RING_TYPE_GFX,
6933 .align_mask = 0xff,
6934 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6935 .support_64bit_ptrs = false,
6936 .get_rptr = gfx_v8_0_ring_get_rptr,
6937 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6938 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6939 .emit_frame_size = /* maximum 215dw if count 16 IBs in */
6940 5 + /* COND_EXEC */
6941 7 + /* PIPELINE_SYNC */
6942 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
6943 12 + /* FENCE for VM_FLUSH */
6944 20 + /* GDS switch */
6945 4 + /* double SWITCH_BUFFER,
6946 the first COND_EXEC jump to the place just
6947 prior to this double SWITCH_BUFFER */
6948 5 + /* COND_EXEC */
6949 7 + /* HDP_flush */
6950 4 + /* VGT_flush */
6951 14 + /* CE_META */
6952 31 + /* DE_META */
6953 3 + /* CNTX_CTRL */
6954 5 + /* HDP_INVL */
6955 12 + 12 + /* FENCE x2 */
6956 2 + /* SWITCH_BUFFER */
6957 5, /* SURFACE_SYNC */
6958 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6959 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6960 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
6961 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6962 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6963 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6964 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6965 .test_ring = gfx_v8_0_ring_test_ring,
6966 .test_ib = gfx_v8_0_ring_test_ib,
6967 .insert_nop = amdgpu_ring_insert_nop,
6968 .pad_ib = amdgpu_ring_generic_pad_ib,
6969 .emit_switch_buffer = gfx_v8_ring_emit_sb,
6970 .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
6971 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
6972 .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
6973 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6974 .soft_recovery = gfx_v8_0_ring_soft_recovery,
6975 .emit_mem_sync = gfx_v8_0_emit_mem_sync,
6976};
6977
6978static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6979 .type = AMDGPU_RING_TYPE_COMPUTE,
6980 .align_mask = 0xff,
6981 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6982 .support_64bit_ptrs = false,
6983 .get_rptr = gfx_v8_0_ring_get_rptr,
6984 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6985 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6986 .emit_frame_size =
6987 20 + /* gfx_v8_0_ring_emit_gds_switch */
6988 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6989 5 + /* hdp_invalidate */
6990 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6991 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6992 7 + 7 + 7 + /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6993 7 + /* gfx_v8_0_emit_mem_sync_compute */
6994 5 + /* gfx_v8_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
6995 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
6996 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6997 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6998 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
6999 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
7000 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
7001 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
7002 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
7003 .test_ring = gfx_v8_0_ring_test_ring,
7004 .test_ib = gfx_v8_0_ring_test_ib,
7005 .insert_nop = amdgpu_ring_insert_nop,
7006 .pad_ib = amdgpu_ring_generic_pad_ib,
7007 .emit_wreg = gfx_v8_0_ring_emit_wreg,
7008 .emit_mem_sync = gfx_v8_0_emit_mem_sync_compute,
7009 .emit_wave_limit = gfx_v8_0_emit_wave_limit,
7010};
7011
7012static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
7013 .type = AMDGPU_RING_TYPE_KIQ,
7014 .align_mask = 0xff,
7015 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7016 .support_64bit_ptrs = false,
7017 .get_rptr = gfx_v8_0_ring_get_rptr,
7018 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
7019 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
7020 .emit_frame_size =
7021 20 + /* gfx_v8_0_ring_emit_gds_switch */
7022 7 + /* gfx_v8_0_ring_emit_hdp_flush */
7023 5 + /* hdp_invalidate */
7024 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
7025 17 + /* gfx_v8_0_ring_emit_vm_flush */
7026 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
7027 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
7028 .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
7029 .test_ring = gfx_v8_0_ring_test_ring,
7030 .insert_nop = amdgpu_ring_insert_nop,
7031 .pad_ib = amdgpu_ring_generic_pad_ib,
7032 .emit_rreg = gfx_v8_0_ring_emit_rreg,
7033 .emit_wreg = gfx_v8_0_ring_emit_wreg,
7034};
7035
7036static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
7037{
7038 int i;
7039
7040 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq;
7041
7042 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7043 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
7044
7045 for (i = 0; i < adev->gfx.num_compute_rings; i++)
7046 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
7047}
7048
7049static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
7050 .set = gfx_v8_0_set_eop_interrupt_state,
7051 .process = gfx_v8_0_eop_irq,
7052};
7053
7054static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
7055 .set = gfx_v8_0_set_priv_reg_fault_state,
7056 .process = gfx_v8_0_priv_reg_irq,
7057};
7058
7059static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
7060 .set = gfx_v8_0_set_priv_inst_fault_state,
7061 .process = gfx_v8_0_priv_inst_irq,
7062};
7063
7064static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = {
7065 .set = gfx_v8_0_set_cp_ecc_int_state,
7066 .process = gfx_v8_0_cp_ecc_error_irq,
7067};
7068
7069static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = {
7070 .set = gfx_v8_0_set_sq_int_state,
7071 .process = gfx_v8_0_sq_irq,
7072};
7073
7074static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
7075{
7076 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7077 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
7078
7079 adev->gfx.priv_reg_irq.num_types = 1;
7080 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
7081
7082 adev->gfx.priv_inst_irq.num_types = 1;
7083 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
7084
7085 adev->gfx.cp_ecc_error_irq.num_types = 1;
7086 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;
7087
7088 adev->gfx.sq_irq.num_types = 1;
7089 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs;
7090}
7091
7092static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
7093{
7094 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
7095}
7096
7097static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
7098{
7099 /* init asci gds info */
7100 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
7101 adev->gds.gws_size = 64;
7102 adev->gds.oa_size = 16;
7103 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
7104}
7105
7106static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7107 u32 bitmap)
7108{
7109 u32 data;
7110
7111 if (!bitmap)
7112 return;
7113
7114 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7115 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7116
7117 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
7118}
7119
7120static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7121{
7122 u32 data, mask;
7123
7124 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
7125 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
7126
7127 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7128
7129 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
7130}
7131
7132static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
7133{
7134 int i, j, k, counter, active_cu_number = 0;
7135 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7136 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
7137 unsigned disable_masks[4 * 2];
7138 u32 ao_cu_num;
7139
7140 memset(cu_info, 0, sizeof(*cu_info));
7141
7142 if (adev->flags & AMD_IS_APU)
7143 ao_cu_num = 2;
7144 else
7145 ao_cu_num = adev->gfx.config.max_cu_per_sh;
7146
7147 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
7148
7149 mutex_lock(&adev->grbm_idx_mutex);
7150 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7151 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7152 mask = 1;
7153 ao_bitmap = 0;
7154 counter = 0;
7155 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
7156 if (i < 4 && j < 2)
7157 gfx_v8_0_set_user_cu_inactive_bitmap(
7158 adev, disable_masks[i * 2 + j]);
7159 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7160 cu_info->bitmap[i][j] = bitmap;
7161
7162 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7163 if (bitmap & mask) {
7164 if (counter < ao_cu_num)
7165 ao_bitmap |= mask;
7166 counter ++;
7167 }
7168 mask <<= 1;
7169 }
7170 active_cu_number += counter;
7171 if (i < 2 && j < 2)
7172 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7173 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
7174 }
7175 }
7176 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
7177 mutex_unlock(&adev->grbm_idx_mutex);
7178
7179 cu_info->number = active_cu_number;
7180 cu_info->ao_cu_mask = ao_cu_mask;
7181 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7182 cu_info->max_waves_per_simd = 10;
7183 cu_info->max_scratch_slots_per_cu = 32;
7184 cu_info->wave_front_size = 64;
7185 cu_info->lds_size = 64;
7186}
7187
7188const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
7189{
7190 .type = AMD_IP_BLOCK_TYPE_GFX,
7191 .major = 8,
7192 .minor = 0,
7193 .rev = 0,
7194 .funcs = &gfx_v8_0_ip_funcs,
7195};
7196
7197const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
7198{
7199 .type = AMD_IP_BLOCK_TYPE_GFX,
7200 .major = 8,
7201 .minor = 1,
7202 .rev = 0,
7203 .funcs = &gfx_v8_0_ip_funcs,
7204};
7205
7206static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
7207{
7208 uint64_t ce_payload_addr;
7209 int cnt_ce;
7210 union {
7211 struct vi_ce_ib_state regular;
7212 struct vi_ce_ib_state_chained_ib chained;
7213 } ce_payload = {};
7214
7215 if (ring->adev->virt.chained_ib_support) {
7216 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7217 offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
7218 cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
7219 } else {
7220 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7221 offsetof(struct vi_gfx_meta_data, ce_payload);
7222 cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
7223 }
7224
7225 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));
7226 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7227 WRITE_DATA_DST_SEL(8) |
7228 WR_CONFIRM) |
7229 WRITE_DATA_CACHE_POLICY(0));
7230 amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
7231 amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));
7232 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
7233}
7234
7235static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
7236{
7237 uint64_t de_payload_addr, gds_addr, csa_addr;
7238 int cnt_de;
7239 union {
7240 struct vi_de_ib_state regular;
7241 struct vi_de_ib_state_chained_ib chained;
7242 } de_payload = {};
7243
7244 csa_addr = amdgpu_csa_vaddr(ring->adev);
7245 gds_addr = csa_addr + 4096;
7246 if (ring->adev->virt.chained_ib_support) {
7247 de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
7248 de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
7249 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload);
7250 cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2;
7251 } else {
7252 de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
7253 de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);
7254 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload);
7255 cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2;
7256 }
7257
7258 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));
7259 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7260 WRITE_DATA_DST_SEL(8) |
7261 WR_CONFIRM) |
7262 WRITE_DATA_CACHE_POLICY(0));
7263 amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
7264 amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));
7265 amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2);
7266}