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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * DMA Engine test module
4 *
5 * Copyright (C) 2007 Atmel Corporation
6 * Copyright (C) 2013 Intel Corporation
7 */
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/err.h>
11#include <linux/delay.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmaengine.h>
14#include <linux/freezer.h>
15#include <linux/init.h>
16#include <linux/kthread.h>
17#include <linux/sched/task.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/random.h>
21#include <linux/slab.h>
22#include <linux/wait.h>
23
24static bool nobounce;
25module_param(nobounce, bool, 0644);
26MODULE_PARM_DESC(nobounce, "Prevent using swiotlb buffer (default: use swiotlb buffer)");
27
28static unsigned int test_buf_size = 16384;
29module_param(test_buf_size, uint, 0644);
30MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
31
32static char test_device[32];
33module_param_string(device, test_device, sizeof(test_device), 0644);
34MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
35
36static unsigned int threads_per_chan = 1;
37module_param(threads_per_chan, uint, 0644);
38MODULE_PARM_DESC(threads_per_chan,
39 "Number of threads to start per channel (default: 1)");
40
41static unsigned int max_channels;
42module_param(max_channels, uint, 0644);
43MODULE_PARM_DESC(max_channels,
44 "Maximum number of channels to use (default: all)");
45
46static unsigned int iterations;
47module_param(iterations, uint, 0644);
48MODULE_PARM_DESC(iterations,
49 "Iterations before stopping test (default: infinite)");
50
51static unsigned int dmatest;
52module_param(dmatest, uint, 0644);
53MODULE_PARM_DESC(dmatest,
54 "dmatest 0-memcpy 1-memset (default: 0)");
55
56static unsigned int xor_sources = 3;
57module_param(xor_sources, uint, 0644);
58MODULE_PARM_DESC(xor_sources,
59 "Number of xor source buffers (default: 3)");
60
61static unsigned int pq_sources = 3;
62module_param(pq_sources, uint, 0644);
63MODULE_PARM_DESC(pq_sources,
64 "Number of p+q source buffers (default: 3)");
65
66static int timeout = 3000;
67module_param(timeout, int, 0644);
68MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
69 "Pass -1 for infinite timeout");
70
71static bool noverify;
72module_param(noverify, bool, 0644);
73MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
74
75static bool norandom;
76module_param(norandom, bool, 0644);
77MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
78
79static bool verbose;
80module_param(verbose, bool, 0644);
81MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
82
83static int alignment = -1;
84module_param(alignment, int, 0644);
85MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
86
87static unsigned int transfer_size;
88module_param(transfer_size, uint, 0644);
89MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
90
91static bool polled;
92module_param(polled, bool, 0644);
93MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
94
95/**
96 * struct dmatest_params - test parameters.
97 * @nobounce: prevent using swiotlb buffer
98 * @buf_size: size of the memcpy test buffer
99 * @channel: bus ID of the channel to test
100 * @device: bus ID of the DMA Engine to test
101 * @threads_per_chan: number of threads to start per channel
102 * @max_channels: maximum number of channels to use
103 * @iterations: iterations before stopping test
104 * @xor_sources: number of xor source buffers
105 * @pq_sources: number of p+q source buffers
106 * @timeout: transfer timeout in msec, -1 for infinite timeout
107 * @noverify: disable data verification
108 * @norandom: disable random offset setup
109 * @alignment: custom data address alignment taken as 2^alignment
110 * @transfer_size: custom transfer size in bytes
111 * @polled: use polling for completion instead of interrupts
112 */
113struct dmatest_params {
114 bool nobounce;
115 unsigned int buf_size;
116 char channel[20];
117 char device[32];
118 unsigned int threads_per_chan;
119 unsigned int max_channels;
120 unsigned int iterations;
121 unsigned int xor_sources;
122 unsigned int pq_sources;
123 int timeout;
124 bool noverify;
125 bool norandom;
126 int alignment;
127 unsigned int transfer_size;
128 bool polled;
129};
130
131/**
132 * struct dmatest_info - test information.
133 * @params: test parameters
134 * @channels: channels under test
135 * @nr_channels: number of channels under test
136 * @lock: access protection to the fields of this structure
137 * @did_init: module has been initialized completely
138 * @last_error: test has faced configuration issues
139 */
140static struct dmatest_info {
141 /* Test parameters */
142 struct dmatest_params params;
143
144 /* Internal state */
145 struct list_head channels;
146 unsigned int nr_channels;
147 int last_error;
148 struct mutex lock;
149 bool did_init;
150} test_info = {
151 .channels = LIST_HEAD_INIT(test_info.channels),
152 .lock = __MUTEX_INITIALIZER(test_info.lock),
153};
154
155static int dmatest_run_set(const char *val, const struct kernel_param *kp);
156static int dmatest_run_get(char *val, const struct kernel_param *kp);
157static const struct kernel_param_ops run_ops = {
158 .set = dmatest_run_set,
159 .get = dmatest_run_get,
160};
161static bool dmatest_run;
162module_param_cb(run, &run_ops, &dmatest_run, 0644);
163MODULE_PARM_DESC(run, "Run the test (default: false)");
164
165static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
166static int dmatest_chan_get(char *val, const struct kernel_param *kp);
167static const struct kernel_param_ops multi_chan_ops = {
168 .set = dmatest_chan_set,
169 .get = dmatest_chan_get,
170};
171
172static char test_channel[20];
173static struct kparam_string newchan_kps = {
174 .string = test_channel,
175 .maxlen = 20,
176};
177module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644);
178MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
179
180static int dmatest_test_list_get(char *val, const struct kernel_param *kp);
181static const struct kernel_param_ops test_list_ops = {
182 .get = dmatest_test_list_get,
183};
184module_param_cb(test_list, &test_list_ops, NULL, 0444);
185MODULE_PARM_DESC(test_list, "Print current test list");
186
187/* Maximum amount of mismatched bytes in buffer to print */
188#define MAX_ERROR_COUNT 32
189
190/*
191 * Initialization patterns. All bytes in the source buffer has bit 7
192 * set, all bytes in the destination buffer has bit 7 cleared.
193 *
194 * Bit 6 is set for all bytes which are to be copied by the DMA
195 * engine. Bit 5 is set for all bytes which are to be overwritten by
196 * the DMA engine.
197 *
198 * The remaining bits are the inverse of a counter which increments by
199 * one for each byte address.
200 */
201#define PATTERN_SRC 0x80
202#define PATTERN_DST 0x00
203#define PATTERN_COPY 0x40
204#define PATTERN_OVERWRITE 0x20
205#define PATTERN_COUNT_MASK 0x1f
206#define PATTERN_MEMSET_IDX 0x01
207
208/* Fixed point arithmetic ops */
209#define FIXPT_SHIFT 8
210#define FIXPNT_MASK 0xFF
211#define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT)
212#define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT)
213#define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT)
214
215/* poor man's completion - we want to use wait_event_freezable() on it */
216struct dmatest_done {
217 bool done;
218 wait_queue_head_t *wait;
219};
220
221struct dmatest_data {
222 u8 **raw;
223 u8 **aligned;
224 gfp_t gfp_flags;
225 unsigned int cnt;
226 unsigned int off;
227};
228
229struct dmatest_thread {
230 struct list_head node;
231 struct dmatest_info *info;
232 struct task_struct *task;
233 struct dma_chan *chan;
234 struct dmatest_data src;
235 struct dmatest_data dst;
236 enum dma_transaction_type type;
237 wait_queue_head_t done_wait;
238 struct dmatest_done test_done;
239 bool done;
240 bool pending;
241};
242
243struct dmatest_chan {
244 struct list_head node;
245 struct dma_chan *chan;
246 struct list_head threads;
247};
248
249static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
250static bool wait;
251
252static bool is_threaded_test_run(struct dmatest_info *info)
253{
254 struct dmatest_chan *dtc;
255
256 list_for_each_entry(dtc, &info->channels, node) {
257 struct dmatest_thread *thread;
258
259 list_for_each_entry(thread, &dtc->threads, node) {
260 if (!thread->done && !thread->pending)
261 return true;
262 }
263 }
264
265 return false;
266}
267
268static bool is_threaded_test_pending(struct dmatest_info *info)
269{
270 struct dmatest_chan *dtc;
271
272 list_for_each_entry(dtc, &info->channels, node) {
273 struct dmatest_thread *thread;
274
275 list_for_each_entry(thread, &dtc->threads, node) {
276 if (thread->pending)
277 return true;
278 }
279 }
280
281 return false;
282}
283
284static int dmatest_wait_get(char *val, const struct kernel_param *kp)
285{
286 struct dmatest_info *info = &test_info;
287 struct dmatest_params *params = &info->params;
288
289 if (params->iterations)
290 wait_event(thread_wait, !is_threaded_test_run(info));
291 wait = true;
292 return param_get_bool(val, kp);
293}
294
295static const struct kernel_param_ops wait_ops = {
296 .get = dmatest_wait_get,
297 .set = param_set_bool,
298};
299module_param_cb(wait, &wait_ops, &wait, 0444);
300MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
301
302static bool dmatest_match_channel(struct dmatest_params *params,
303 struct dma_chan *chan)
304{
305 if (params->channel[0] == '\0')
306 return true;
307 return strcmp(dma_chan_name(chan), params->channel) == 0;
308}
309
310static bool dmatest_match_device(struct dmatest_params *params,
311 struct dma_device *device)
312{
313 if (params->device[0] == '\0')
314 return true;
315 return strcmp(dev_name(device->dev), params->device) == 0;
316}
317
318static unsigned long dmatest_random(void)
319{
320 unsigned long buf;
321
322 get_random_bytes(&buf, sizeof(buf));
323 return buf;
324}
325
326static inline u8 gen_inv_idx(u8 index, bool is_memset)
327{
328 u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
329
330 return ~val & PATTERN_COUNT_MASK;
331}
332
333static inline u8 gen_src_value(u8 index, bool is_memset)
334{
335 return PATTERN_SRC | gen_inv_idx(index, is_memset);
336}
337
338static inline u8 gen_dst_value(u8 index, bool is_memset)
339{
340 return PATTERN_DST | gen_inv_idx(index, is_memset);
341}
342
343static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
344 unsigned int buf_size, bool is_memset)
345{
346 unsigned int i;
347 u8 *buf;
348
349 for (; (buf = *bufs); bufs++) {
350 for (i = 0; i < start; i++)
351 buf[i] = gen_src_value(i, is_memset);
352 for ( ; i < start + len; i++)
353 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
354 for ( ; i < buf_size; i++)
355 buf[i] = gen_src_value(i, is_memset);
356 buf++;
357 }
358}
359
360static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
361 unsigned int buf_size, bool is_memset)
362{
363 unsigned int i;
364 u8 *buf;
365
366 for (; (buf = *bufs); bufs++) {
367 for (i = 0; i < start; i++)
368 buf[i] = gen_dst_value(i, is_memset);
369 for ( ; i < start + len; i++)
370 buf[i] = gen_dst_value(i, is_memset) |
371 PATTERN_OVERWRITE;
372 for ( ; i < buf_size; i++)
373 buf[i] = gen_dst_value(i, is_memset);
374 }
375}
376
377static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
378 unsigned int counter, bool is_srcbuf, bool is_memset)
379{
380 u8 diff = actual ^ pattern;
381 u8 expected = pattern | gen_inv_idx(counter, is_memset);
382 const char *thread_name = current->comm;
383
384 if (is_srcbuf)
385 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
386 thread_name, index, expected, actual);
387 else if ((pattern & PATTERN_COPY)
388 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
389 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
390 thread_name, index, expected, actual);
391 else if (diff & PATTERN_SRC)
392 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
393 thread_name, index, expected, actual);
394 else
395 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
396 thread_name, index, expected, actual);
397}
398
399static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
400 unsigned int end, unsigned int counter, u8 pattern,
401 bool is_srcbuf, bool is_memset)
402{
403 unsigned int i;
404 unsigned int error_count = 0;
405 u8 actual;
406 u8 expected;
407 u8 *buf;
408 unsigned int counter_orig = counter;
409
410 for (; (buf = *bufs); bufs++) {
411 counter = counter_orig;
412 for (i = start; i < end; i++) {
413 actual = buf[i];
414 expected = pattern | gen_inv_idx(counter, is_memset);
415 if (actual != expected) {
416 if (error_count < MAX_ERROR_COUNT)
417 dmatest_mismatch(actual, pattern, i,
418 counter, is_srcbuf,
419 is_memset);
420 error_count++;
421 }
422 counter++;
423 }
424 }
425
426 if (error_count > MAX_ERROR_COUNT)
427 pr_warn("%s: %u errors suppressed\n",
428 current->comm, error_count - MAX_ERROR_COUNT);
429
430 return error_count;
431}
432
433
434static void dmatest_callback(void *arg)
435{
436 struct dmatest_done *done = arg;
437 struct dmatest_thread *thread =
438 container_of(done, struct dmatest_thread, test_done);
439 if (!thread->done) {
440 done->done = true;
441 wake_up_all(done->wait);
442 } else {
443 /*
444 * If thread->done, it means that this callback occurred
445 * after the parent thread has cleaned up. This can
446 * happen in the case that driver doesn't implement
447 * the terminate_all() functionality and a dma operation
448 * did not occur within the timeout period
449 */
450 WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
451 }
452}
453
454static unsigned int min_odd(unsigned int x, unsigned int y)
455{
456 unsigned int val = min(x, y);
457
458 return val % 2 ? val : val - 1;
459}
460
461static void result(const char *err, unsigned int n, unsigned int src_off,
462 unsigned int dst_off, unsigned int len, unsigned long data)
463{
464 if (IS_ERR_VALUE(data)) {
465 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%ld)\n",
466 current->comm, n, err, src_off, dst_off, len, data);
467 } else {
468 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
469 current->comm, n, err, src_off, dst_off, len, data);
470 }
471}
472
473static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
474 unsigned int dst_off, unsigned int len,
475 unsigned long data)
476{
477 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
478 current->comm, n, err, src_off, dst_off, len, data);
479}
480
481#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
482 if (verbose) \
483 result(err, n, src_off, dst_off, len, data); \
484 else \
485 dbg_result(err, n, src_off, dst_off, len, data);\
486})
487
488static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
489{
490 unsigned long long per_sec = 1000000;
491
492 if (runtime <= 0)
493 return 0;
494
495 /* drop precision until runtime is 32-bits */
496 while (runtime > UINT_MAX) {
497 runtime >>= 1;
498 per_sec <<= 1;
499 }
500
501 per_sec *= val;
502 per_sec = INT_TO_FIXPT(per_sec);
503 do_div(per_sec, runtime);
504
505 return per_sec;
506}
507
508static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
509{
510 return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10));
511}
512
513static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt)
514{
515 unsigned int i;
516
517 for (i = 0; i < cnt; i++)
518 kfree(d->raw[i]);
519
520 kfree(d->aligned);
521 kfree(d->raw);
522}
523
524static void dmatest_free_test_data(struct dmatest_data *d)
525{
526 __dmatest_free_test_data(d, d->cnt);
527}
528
529static int dmatest_alloc_test_data(struct dmatest_data *d,
530 unsigned int buf_size, u8 align)
531{
532 unsigned int i = 0;
533
534 d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
535 if (!d->raw)
536 return -ENOMEM;
537
538 d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
539 if (!d->aligned)
540 goto err;
541
542 for (i = 0; i < d->cnt; i++) {
543 d->raw[i] = kmalloc(buf_size + align, d->gfp_flags);
544 if (!d->raw[i])
545 goto err;
546
547 /* align to alignment restriction */
548 if (align)
549 d->aligned[i] = PTR_ALIGN(d->raw[i], align);
550 else
551 d->aligned[i] = d->raw[i];
552 }
553
554 return 0;
555err:
556 __dmatest_free_test_data(d, i);
557 return -ENOMEM;
558}
559
560/*
561 * This function repeatedly tests DMA transfers of various lengths and
562 * offsets for a given operation type until it is told to exit by
563 * kthread_stop(). There may be multiple threads running this function
564 * in parallel for a single channel, and there may be multiple channels
565 * being tested in parallel.
566 *
567 * Before each test, the source and destination buffer is initialized
568 * with a known pattern. This pattern is different depending on
569 * whether it's in an area which is supposed to be copied or
570 * overwritten, and different in the source and destination buffers.
571 * So if the DMA engine doesn't copy exactly what we tell it to copy,
572 * we'll notice.
573 */
574static int dmatest_func(void *data)
575{
576 struct dmatest_thread *thread = data;
577 struct dmatest_done *done = &thread->test_done;
578 struct dmatest_info *info;
579 struct dmatest_params *params;
580 struct dma_chan *chan;
581 struct dma_device *dev;
582 struct device *dma_dev;
583 unsigned int error_count;
584 unsigned int failed_tests = 0;
585 unsigned int total_tests = 0;
586 dma_cookie_t cookie;
587 enum dma_status status;
588 enum dma_ctrl_flags flags;
589 u8 *pq_coefs = NULL;
590 int ret;
591 unsigned int buf_size;
592 struct dmatest_data *src;
593 struct dmatest_data *dst;
594 int i;
595 ktime_t ktime, start, diff;
596 ktime_t filltime = 0;
597 ktime_t comparetime = 0;
598 s64 runtime = 0;
599 unsigned long long total_len = 0;
600 unsigned long long iops = 0;
601 u8 align = 0;
602 bool is_memset = false;
603 dma_addr_t *srcs;
604 dma_addr_t *dma_pq;
605
606 set_freezable();
607
608 ret = -ENOMEM;
609
610 smp_rmb();
611 thread->pending = false;
612 info = thread->info;
613 params = &info->params;
614 chan = thread->chan;
615 dev = chan->device;
616 dma_dev = dmaengine_get_dma_device(chan);
617
618 src = &thread->src;
619 dst = &thread->dst;
620 if (thread->type == DMA_MEMCPY) {
621 align = params->alignment < 0 ? dev->copy_align :
622 params->alignment;
623 src->cnt = dst->cnt = 1;
624 } else if (thread->type == DMA_MEMSET) {
625 align = params->alignment < 0 ? dev->fill_align :
626 params->alignment;
627 src->cnt = dst->cnt = 1;
628 is_memset = true;
629 } else if (thread->type == DMA_XOR) {
630 /* force odd to ensure dst = src */
631 src->cnt = min_odd(params->xor_sources | 1, dev->max_xor);
632 dst->cnt = 1;
633 align = params->alignment < 0 ? dev->xor_align :
634 params->alignment;
635 } else if (thread->type == DMA_PQ) {
636 /* force odd to ensure dst = src */
637 src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
638 dst->cnt = 2;
639 align = params->alignment < 0 ? dev->pq_align :
640 params->alignment;
641
642 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
643 if (!pq_coefs)
644 goto err_thread_type;
645
646 for (i = 0; i < src->cnt; i++)
647 pq_coefs[i] = 1;
648 } else
649 goto err_thread_type;
650
651 /* Check if buffer count fits into map count variable (u8) */
652 if ((src->cnt + dst->cnt) >= 255) {
653 pr_err("too many buffers (%d of 255 supported)\n",
654 src->cnt + dst->cnt);
655 goto err_free_coefs;
656 }
657
658 buf_size = params->buf_size;
659 if (1 << align > buf_size) {
660 pr_err("%u-byte buffer too small for %d-byte alignment\n",
661 buf_size, 1 << align);
662 goto err_free_coefs;
663 }
664
665 src->gfp_flags = GFP_KERNEL;
666 dst->gfp_flags = GFP_KERNEL;
667 if (params->nobounce) {
668 src->gfp_flags = GFP_DMA;
669 dst->gfp_flags = GFP_DMA;
670 }
671
672 if (dmatest_alloc_test_data(src, buf_size, align) < 0)
673 goto err_free_coefs;
674
675 if (dmatest_alloc_test_data(dst, buf_size, align) < 0)
676 goto err_src;
677
678 set_user_nice(current, 10);
679
680 srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL);
681 if (!srcs)
682 goto err_dst;
683
684 dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL);
685 if (!dma_pq)
686 goto err_srcs_array;
687
688 /*
689 * src and dst buffers are freed by ourselves below
690 */
691 if (params->polled)
692 flags = DMA_CTRL_ACK;
693 else
694 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
695
696 ktime = ktime_get();
697 while (!(kthread_should_stop() ||
698 (params->iterations && total_tests >= params->iterations))) {
699 struct dma_async_tx_descriptor *tx = NULL;
700 struct dmaengine_unmap_data *um;
701 dma_addr_t *dsts;
702 unsigned int len;
703
704 total_tests++;
705
706 if (params->transfer_size) {
707 if (params->transfer_size >= buf_size) {
708 pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
709 params->transfer_size, buf_size);
710 break;
711 }
712 len = params->transfer_size;
713 } else if (params->norandom) {
714 len = buf_size;
715 } else {
716 len = dmatest_random() % buf_size + 1;
717 }
718
719 /* Do not alter transfer size explicitly defined by user */
720 if (!params->transfer_size) {
721 len = (len >> align) << align;
722 if (!len)
723 len = 1 << align;
724 }
725 total_len += len;
726
727 if (params->norandom) {
728 src->off = 0;
729 dst->off = 0;
730 } else {
731 src->off = dmatest_random() % (buf_size - len + 1);
732 dst->off = dmatest_random() % (buf_size - len + 1);
733
734 src->off = (src->off >> align) << align;
735 dst->off = (dst->off >> align) << align;
736 }
737
738 if (!params->noverify) {
739 start = ktime_get();
740 dmatest_init_srcs(src->aligned, src->off, len,
741 buf_size, is_memset);
742 dmatest_init_dsts(dst->aligned, dst->off, len,
743 buf_size, is_memset);
744
745 diff = ktime_sub(ktime_get(), start);
746 filltime = ktime_add(filltime, diff);
747 }
748
749 um = dmaengine_get_unmap_data(dma_dev, src->cnt + dst->cnt,
750 GFP_KERNEL);
751 if (!um) {
752 failed_tests++;
753 result("unmap data NULL", total_tests,
754 src->off, dst->off, len, ret);
755 continue;
756 }
757
758 um->len = buf_size;
759 for (i = 0; i < src->cnt; i++) {
760 void *buf = src->aligned[i];
761 struct page *pg = virt_to_page(buf);
762 unsigned long pg_off = offset_in_page(buf);
763
764 um->addr[i] = dma_map_page(dma_dev, pg, pg_off,
765 um->len, DMA_TO_DEVICE);
766 srcs[i] = um->addr[i] + src->off;
767 ret = dma_mapping_error(dma_dev, um->addr[i]);
768 if (ret) {
769 result("src mapping error", total_tests,
770 src->off, dst->off, len, ret);
771 goto error_unmap_continue;
772 }
773 um->to_cnt++;
774 }
775 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
776 dsts = &um->addr[src->cnt];
777 for (i = 0; i < dst->cnt; i++) {
778 void *buf = dst->aligned[i];
779 struct page *pg = virt_to_page(buf);
780 unsigned long pg_off = offset_in_page(buf);
781
782 dsts[i] = dma_map_page(dma_dev, pg, pg_off, um->len,
783 DMA_BIDIRECTIONAL);
784 ret = dma_mapping_error(dma_dev, dsts[i]);
785 if (ret) {
786 result("dst mapping error", total_tests,
787 src->off, dst->off, len, ret);
788 goto error_unmap_continue;
789 }
790 um->bidi_cnt++;
791 }
792
793 if (thread->type == DMA_MEMCPY)
794 tx = dev->device_prep_dma_memcpy(chan,
795 dsts[0] + dst->off,
796 srcs[0], len, flags);
797 else if (thread->type == DMA_MEMSET)
798 tx = dev->device_prep_dma_memset(chan,
799 dsts[0] + dst->off,
800 *(src->aligned[0] + src->off),
801 len, flags);
802 else if (thread->type == DMA_XOR)
803 tx = dev->device_prep_dma_xor(chan,
804 dsts[0] + dst->off,
805 srcs, src->cnt,
806 len, flags);
807 else if (thread->type == DMA_PQ) {
808 for (i = 0; i < dst->cnt; i++)
809 dma_pq[i] = dsts[i] + dst->off;
810 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
811 src->cnt, pq_coefs,
812 len, flags);
813 }
814
815 if (!tx) {
816 result("prep error", total_tests, src->off,
817 dst->off, len, ret);
818 msleep(100);
819 goto error_unmap_continue;
820 }
821
822 done->done = false;
823 if (!params->polled) {
824 tx->callback = dmatest_callback;
825 tx->callback_param = done;
826 }
827 cookie = tx->tx_submit(tx);
828
829 if (dma_submit_error(cookie)) {
830 result("submit error", total_tests, src->off,
831 dst->off, len, ret);
832 msleep(100);
833 goto error_unmap_continue;
834 }
835
836 if (params->polled) {
837 status = dma_sync_wait(chan, cookie);
838 dmaengine_terminate_sync(chan);
839 if (status == DMA_COMPLETE)
840 done->done = true;
841 } else {
842 dma_async_issue_pending(chan);
843
844 wait_event_freezable_timeout(thread->done_wait,
845 done->done,
846 msecs_to_jiffies(params->timeout));
847
848 status = dma_async_is_tx_complete(chan, cookie, NULL,
849 NULL);
850 }
851
852 if (!done->done) {
853 result("test timed out", total_tests, src->off, dst->off,
854 len, 0);
855 goto error_unmap_continue;
856 } else if (status != DMA_COMPLETE &&
857 !(dma_has_cap(DMA_COMPLETION_NO_ORDER,
858 dev->cap_mask) &&
859 status == DMA_OUT_OF_ORDER)) {
860 result(status == DMA_ERROR ?
861 "completion error status" :
862 "completion busy status", total_tests, src->off,
863 dst->off, len, ret);
864 goto error_unmap_continue;
865 }
866
867 dmaengine_unmap_put(um);
868
869 if (params->noverify) {
870 verbose_result("test passed", total_tests, src->off,
871 dst->off, len, 0);
872 continue;
873 }
874
875 start = ktime_get();
876 pr_debug("%s: verifying source buffer...\n", current->comm);
877 error_count = dmatest_verify(src->aligned, 0, src->off,
878 0, PATTERN_SRC, true, is_memset);
879 error_count += dmatest_verify(src->aligned, src->off,
880 src->off + len, src->off,
881 PATTERN_SRC | PATTERN_COPY, true, is_memset);
882 error_count += dmatest_verify(src->aligned, src->off + len,
883 buf_size, src->off + len,
884 PATTERN_SRC, true, is_memset);
885
886 pr_debug("%s: verifying dest buffer...\n", current->comm);
887 error_count += dmatest_verify(dst->aligned, 0, dst->off,
888 0, PATTERN_DST, false, is_memset);
889
890 error_count += dmatest_verify(dst->aligned, dst->off,
891 dst->off + len, src->off,
892 PATTERN_SRC | PATTERN_COPY, false, is_memset);
893
894 error_count += dmatest_verify(dst->aligned, dst->off + len,
895 buf_size, dst->off + len,
896 PATTERN_DST, false, is_memset);
897
898 diff = ktime_sub(ktime_get(), start);
899 comparetime = ktime_add(comparetime, diff);
900
901 if (error_count) {
902 result("data error", total_tests, src->off, dst->off,
903 len, error_count);
904 failed_tests++;
905 } else {
906 verbose_result("test passed", total_tests, src->off,
907 dst->off, len, 0);
908 }
909
910 continue;
911
912error_unmap_continue:
913 dmaengine_unmap_put(um);
914 failed_tests++;
915 }
916 ktime = ktime_sub(ktime_get(), ktime);
917 ktime = ktime_sub(ktime, comparetime);
918 ktime = ktime_sub(ktime, filltime);
919 runtime = ktime_to_us(ktime);
920
921 ret = 0;
922 kfree(dma_pq);
923err_srcs_array:
924 kfree(srcs);
925err_dst:
926 dmatest_free_test_data(dst);
927err_src:
928 dmatest_free_test_data(src);
929err_free_coefs:
930 kfree(pq_coefs);
931err_thread_type:
932 iops = dmatest_persec(runtime, total_tests);
933 pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n",
934 current->comm, total_tests, failed_tests,
935 FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops),
936 dmatest_KBs(runtime, total_len), ret);
937
938 /* terminate all transfers on specified channels */
939 if (ret || failed_tests)
940 dmaengine_terminate_sync(chan);
941
942 thread->done = true;
943 wake_up(&thread_wait);
944
945 return ret;
946}
947
948static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
949{
950 struct dmatest_thread *thread;
951 struct dmatest_thread *_thread;
952 int ret;
953
954 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
955 ret = kthread_stop(thread->task);
956 pr_debug("thread %s exited with status %d\n",
957 thread->task->comm, ret);
958 list_del(&thread->node);
959 put_task_struct(thread->task);
960 kfree(thread);
961 }
962
963 /* terminate all transfers on specified channels */
964 dmaengine_terminate_sync(dtc->chan);
965
966 kfree(dtc);
967}
968
969static int dmatest_add_threads(struct dmatest_info *info,
970 struct dmatest_chan *dtc, enum dma_transaction_type type)
971{
972 struct dmatest_params *params = &info->params;
973 struct dmatest_thread *thread;
974 struct dma_chan *chan = dtc->chan;
975 char *op;
976 unsigned int i;
977
978 if (type == DMA_MEMCPY)
979 op = "copy";
980 else if (type == DMA_MEMSET)
981 op = "set";
982 else if (type == DMA_XOR)
983 op = "xor";
984 else if (type == DMA_PQ)
985 op = "pq";
986 else
987 return -EINVAL;
988
989 for (i = 0; i < params->threads_per_chan; i++) {
990 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
991 if (!thread) {
992 pr_warn("No memory for %s-%s%u\n",
993 dma_chan_name(chan), op, i);
994 break;
995 }
996 thread->info = info;
997 thread->chan = dtc->chan;
998 thread->type = type;
999 thread->test_done.wait = &thread->done_wait;
1000 init_waitqueue_head(&thread->done_wait);
1001 smp_wmb();
1002 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
1003 dma_chan_name(chan), op, i);
1004 if (IS_ERR(thread->task)) {
1005 pr_warn("Failed to create thread %s-%s%u\n",
1006 dma_chan_name(chan), op, i);
1007 kfree(thread);
1008 break;
1009 }
1010
1011 /* srcbuf and dstbuf are allocated by the thread itself */
1012 get_task_struct(thread->task);
1013 list_add_tail(&thread->node, &dtc->threads);
1014 thread->pending = true;
1015 }
1016
1017 return i;
1018}
1019
1020static int dmatest_add_channel(struct dmatest_info *info,
1021 struct dma_chan *chan)
1022{
1023 struct dmatest_chan *dtc;
1024 struct dma_device *dma_dev = chan->device;
1025 unsigned int thread_count = 0;
1026 int cnt;
1027
1028 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
1029 if (!dtc) {
1030 pr_warn("No memory for %s\n", dma_chan_name(chan));
1031 return -ENOMEM;
1032 }
1033
1034 dtc->chan = chan;
1035 INIT_LIST_HEAD(&dtc->threads);
1036
1037 if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) &&
1038 info->params.polled) {
1039 info->params.polled = false;
1040 pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n");
1041 }
1042
1043 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1044 if (dmatest == 0) {
1045 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
1046 thread_count += cnt > 0 ? cnt : 0;
1047 }
1048 }
1049
1050 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1051 if (dmatest == 1) {
1052 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
1053 thread_count += cnt > 0 ? cnt : 0;
1054 }
1055 }
1056
1057 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1058 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
1059 thread_count += cnt > 0 ? cnt : 0;
1060 }
1061 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1062 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
1063 thread_count += cnt > 0 ? cnt : 0;
1064 }
1065
1066 pr_info("Added %u threads using %s\n",
1067 thread_count, dma_chan_name(chan));
1068
1069 list_add_tail(&dtc->node, &info->channels);
1070 info->nr_channels++;
1071
1072 return 0;
1073}
1074
1075static bool filter(struct dma_chan *chan, void *param)
1076{
1077 return dmatest_match_channel(param, chan) && dmatest_match_device(param, chan->device);
1078}
1079
1080static void request_channels(struct dmatest_info *info,
1081 enum dma_transaction_type type)
1082{
1083 dma_cap_mask_t mask;
1084
1085 dma_cap_zero(mask);
1086 dma_cap_set(type, mask);
1087 for (;;) {
1088 struct dmatest_params *params = &info->params;
1089 struct dma_chan *chan;
1090
1091 chan = dma_request_channel(mask, filter, params);
1092 if (chan) {
1093 if (dmatest_add_channel(info, chan)) {
1094 dma_release_channel(chan);
1095 break; /* add_channel failed, punt */
1096 }
1097 } else
1098 break; /* no more channels available */
1099 if (params->max_channels &&
1100 info->nr_channels >= params->max_channels)
1101 break; /* we have all we need */
1102 }
1103}
1104
1105static void add_threaded_test(struct dmatest_info *info)
1106{
1107 struct dmatest_params *params = &info->params;
1108
1109 /* Copy test parameters */
1110 params->nobounce = nobounce;
1111 params->buf_size = test_buf_size;
1112 strscpy(params->channel, strim(test_channel), sizeof(params->channel));
1113 strscpy(params->device, strim(test_device), sizeof(params->device));
1114 params->threads_per_chan = threads_per_chan;
1115 params->max_channels = max_channels;
1116 params->iterations = iterations;
1117 params->xor_sources = xor_sources;
1118 params->pq_sources = pq_sources;
1119 params->timeout = timeout;
1120 params->noverify = noverify;
1121 params->norandom = norandom;
1122 params->alignment = alignment;
1123 params->transfer_size = transfer_size;
1124 params->polled = polled;
1125
1126 request_channels(info, DMA_MEMCPY);
1127 request_channels(info, DMA_MEMSET);
1128 request_channels(info, DMA_XOR);
1129 request_channels(info, DMA_PQ);
1130}
1131
1132static void run_pending_tests(struct dmatest_info *info)
1133{
1134 struct dmatest_chan *dtc;
1135 unsigned int thread_count = 0;
1136
1137 list_for_each_entry(dtc, &info->channels, node) {
1138 struct dmatest_thread *thread;
1139
1140 thread_count = 0;
1141 list_for_each_entry(thread, &dtc->threads, node) {
1142 wake_up_process(thread->task);
1143 thread_count++;
1144 }
1145 pr_info("Started %u threads using %s\n",
1146 thread_count, dma_chan_name(dtc->chan));
1147 }
1148}
1149
1150static void stop_threaded_test(struct dmatest_info *info)
1151{
1152 struct dmatest_chan *dtc, *_dtc;
1153 struct dma_chan *chan;
1154
1155 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
1156 list_del(&dtc->node);
1157 chan = dtc->chan;
1158 dmatest_cleanup_channel(dtc);
1159 pr_debug("dropped channel %s\n", dma_chan_name(chan));
1160 dma_release_channel(chan);
1161 }
1162
1163 info->nr_channels = 0;
1164}
1165
1166static void start_threaded_tests(struct dmatest_info *info)
1167{
1168 /* we might be called early to set run=, defer running until all
1169 * parameters have been evaluated
1170 */
1171 if (!info->did_init)
1172 return;
1173
1174 run_pending_tests(info);
1175}
1176
1177static int dmatest_run_get(char *val, const struct kernel_param *kp)
1178{
1179 struct dmatest_info *info = &test_info;
1180
1181 mutex_lock(&info->lock);
1182 if (is_threaded_test_run(info)) {
1183 dmatest_run = true;
1184 } else {
1185 if (!is_threaded_test_pending(info))
1186 stop_threaded_test(info);
1187 dmatest_run = false;
1188 }
1189 mutex_unlock(&info->lock);
1190
1191 return param_get_bool(val, kp);
1192}
1193
1194static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1195{
1196 struct dmatest_info *info = &test_info;
1197 int ret;
1198
1199 mutex_lock(&info->lock);
1200 ret = param_set_bool(val, kp);
1201 if (ret) {
1202 mutex_unlock(&info->lock);
1203 return ret;
1204 } else if (dmatest_run) {
1205 if (!is_threaded_test_pending(info)) {
1206 /*
1207 * We have nothing to run. This can be due to:
1208 */
1209 ret = info->last_error;
1210 if (ret) {
1211 /* 1) Misconfiguration */
1212 pr_err("Channel misconfigured, can't continue\n");
1213 mutex_unlock(&info->lock);
1214 return ret;
1215 } else {
1216 /* 2) We rely on defaults */
1217 pr_info("No channels configured, continue with any\n");
1218 if (!is_threaded_test_run(info))
1219 stop_threaded_test(info);
1220 add_threaded_test(info);
1221 }
1222 }
1223 start_threaded_tests(info);
1224 } else {
1225 stop_threaded_test(info);
1226 }
1227
1228 mutex_unlock(&info->lock);
1229
1230 return ret;
1231}
1232
1233static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
1234{
1235 struct dmatest_info *info = &test_info;
1236 struct dmatest_chan *dtc;
1237 char chan_reset_val[20];
1238 int ret;
1239
1240 mutex_lock(&info->lock);
1241 ret = param_set_copystring(val, kp);
1242 if (ret) {
1243 mutex_unlock(&info->lock);
1244 return ret;
1245 }
1246 /*Clear any previously run threads */
1247 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info))
1248 stop_threaded_test(info);
1249 /* Reject channels that are already registered */
1250 if (is_threaded_test_pending(info)) {
1251 list_for_each_entry(dtc, &info->channels, node) {
1252 if (strcmp(dma_chan_name(dtc->chan),
1253 strim(test_channel)) == 0) {
1254 dtc = list_last_entry(&info->channels,
1255 struct dmatest_chan,
1256 node);
1257 strscpy(chan_reset_val,
1258 dma_chan_name(dtc->chan),
1259 sizeof(chan_reset_val));
1260 ret = -EBUSY;
1261 goto add_chan_err;
1262 }
1263 }
1264 }
1265
1266 add_threaded_test(info);
1267
1268 /* Check if channel was added successfully */
1269 if (!list_empty(&info->channels)) {
1270 /*
1271 * if new channel was not successfully added, revert the
1272 * "test_channel" string to the name of the last successfully
1273 * added channel. exception for when users issues empty string
1274 * to channel parameter.
1275 */
1276 dtc = list_last_entry(&info->channels, struct dmatest_chan, node);
1277 if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0)
1278 && (strcmp("", strim(test_channel)) != 0)) {
1279 ret = -EINVAL;
1280 strscpy(chan_reset_val, dma_chan_name(dtc->chan),
1281 sizeof(chan_reset_val));
1282 goto add_chan_err;
1283 }
1284
1285 } else {
1286 /* Clear test_channel if no channels were added successfully */
1287 strscpy(chan_reset_val, "", sizeof(chan_reset_val));
1288 ret = -EBUSY;
1289 goto add_chan_err;
1290 }
1291
1292 info->last_error = ret;
1293 mutex_unlock(&info->lock);
1294
1295 return ret;
1296
1297add_chan_err:
1298 param_set_copystring(chan_reset_val, kp);
1299 info->last_error = ret;
1300 mutex_unlock(&info->lock);
1301
1302 return ret;
1303}
1304
1305static int dmatest_chan_get(char *val, const struct kernel_param *kp)
1306{
1307 struct dmatest_info *info = &test_info;
1308
1309 mutex_lock(&info->lock);
1310 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) {
1311 stop_threaded_test(info);
1312 strscpy(test_channel, "", sizeof(test_channel));
1313 }
1314 mutex_unlock(&info->lock);
1315
1316 return param_get_string(val, kp);
1317}
1318
1319static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
1320{
1321 struct dmatest_info *info = &test_info;
1322 struct dmatest_chan *dtc;
1323 unsigned int thread_count = 0;
1324
1325 list_for_each_entry(dtc, &info->channels, node) {
1326 struct dmatest_thread *thread;
1327
1328 thread_count = 0;
1329 list_for_each_entry(thread, &dtc->threads, node) {
1330 thread_count++;
1331 }
1332 pr_info("%u threads using %s\n",
1333 thread_count, dma_chan_name(dtc->chan));
1334 }
1335
1336 return 0;
1337}
1338
1339static int __init dmatest_init(void)
1340{
1341 struct dmatest_info *info = &test_info;
1342 struct dmatest_params *params = &info->params;
1343
1344 if (dmatest_run) {
1345 mutex_lock(&info->lock);
1346 add_threaded_test(info);
1347 run_pending_tests(info);
1348 mutex_unlock(&info->lock);
1349 }
1350
1351 if (params->iterations && wait)
1352 wait_event(thread_wait, !is_threaded_test_run(info));
1353
1354 /* module parameters are stable, inittime tests are started,
1355 * let userspace take over 'run' control
1356 */
1357 info->did_init = true;
1358
1359 return 0;
1360}
1361/* when compiled-in wait for drivers to load first */
1362late_initcall(dmatest_init);
1363
1364static void __exit dmatest_exit(void)
1365{
1366 struct dmatest_info *info = &test_info;
1367
1368 mutex_lock(&info->lock);
1369 stop_threaded_test(info);
1370 mutex_unlock(&info->lock);
1371}
1372module_exit(dmatest_exit);
1373
1374MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1375MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * DMA Engine test module
4 *
5 * Copyright (C) 2007 Atmel Corporation
6 * Copyright (C) 2013 Intel Corporation
7 */
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/err.h>
11#include <linux/delay.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmaengine.h>
14#include <linux/freezer.h>
15#include <linux/init.h>
16#include <linux/kthread.h>
17#include <linux/sched/task.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/random.h>
21#include <linux/slab.h>
22#include <linux/wait.h>
23
24static unsigned int test_buf_size = 16384;
25module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
26MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
27
28static char test_device[32];
29module_param_string(device, test_device, sizeof(test_device),
30 S_IRUGO | S_IWUSR);
31MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
32
33static unsigned int threads_per_chan = 1;
34module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
35MODULE_PARM_DESC(threads_per_chan,
36 "Number of threads to start per channel (default: 1)");
37
38static unsigned int max_channels;
39module_param(max_channels, uint, S_IRUGO | S_IWUSR);
40MODULE_PARM_DESC(max_channels,
41 "Maximum number of channels to use (default: all)");
42
43static unsigned int iterations;
44module_param(iterations, uint, S_IRUGO | S_IWUSR);
45MODULE_PARM_DESC(iterations,
46 "Iterations before stopping test (default: infinite)");
47
48static unsigned int dmatest;
49module_param(dmatest, uint, S_IRUGO | S_IWUSR);
50MODULE_PARM_DESC(dmatest,
51 "dmatest 0-memcpy 1-memset (default: 0)");
52
53static unsigned int xor_sources = 3;
54module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
55MODULE_PARM_DESC(xor_sources,
56 "Number of xor source buffers (default: 3)");
57
58static unsigned int pq_sources = 3;
59module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
60MODULE_PARM_DESC(pq_sources,
61 "Number of p+q source buffers (default: 3)");
62
63static int timeout = 3000;
64module_param(timeout, int, S_IRUGO | S_IWUSR);
65MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
66 "Pass -1 for infinite timeout");
67
68static bool noverify;
69module_param(noverify, bool, S_IRUGO | S_IWUSR);
70MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
71
72static bool norandom;
73module_param(norandom, bool, 0644);
74MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
75
76static bool verbose;
77module_param(verbose, bool, S_IRUGO | S_IWUSR);
78MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
79
80static int alignment = -1;
81module_param(alignment, int, 0644);
82MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
83
84static unsigned int transfer_size;
85module_param(transfer_size, uint, 0644);
86MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
87
88static bool polled;
89module_param(polled, bool, S_IRUGO | S_IWUSR);
90MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
91
92/**
93 * struct dmatest_params - test parameters.
94 * @buf_size: size of the memcpy test buffer
95 * @channel: bus ID of the channel to test
96 * @device: bus ID of the DMA Engine to test
97 * @threads_per_chan: number of threads to start per channel
98 * @max_channels: maximum number of channels to use
99 * @iterations: iterations before stopping test
100 * @xor_sources: number of xor source buffers
101 * @pq_sources: number of p+q source buffers
102 * @timeout: transfer timeout in msec, -1 for infinite timeout
103 * @noverify: disable data verification
104 * @norandom: disable random offset setup
105 * @alignment: custom data address alignment taken as 2^alignment
106 * @transfer_size: custom transfer size in bytes
107 * @polled: use polling for completion instead of interrupts
108 */
109struct dmatest_params {
110 unsigned int buf_size;
111 char channel[20];
112 char device[32];
113 unsigned int threads_per_chan;
114 unsigned int max_channels;
115 unsigned int iterations;
116 unsigned int xor_sources;
117 unsigned int pq_sources;
118 int timeout;
119 bool noverify;
120 bool norandom;
121 int alignment;
122 unsigned int transfer_size;
123 bool polled;
124};
125
126/**
127 * struct dmatest_info - test information.
128 * @params: test parameters
129 * @channels: channels under test
130 * @nr_channels: number of channels under test
131 * @lock: access protection to the fields of this structure
132 * @did_init: module has been initialized completely
133 * @last_error: test has faced configuration issues
134 */
135static struct dmatest_info {
136 /* Test parameters */
137 struct dmatest_params params;
138
139 /* Internal state */
140 struct list_head channels;
141 unsigned int nr_channels;
142 int last_error;
143 struct mutex lock;
144 bool did_init;
145} test_info = {
146 .channels = LIST_HEAD_INIT(test_info.channels),
147 .lock = __MUTEX_INITIALIZER(test_info.lock),
148};
149
150static int dmatest_run_set(const char *val, const struct kernel_param *kp);
151static int dmatest_run_get(char *val, const struct kernel_param *kp);
152static const struct kernel_param_ops run_ops = {
153 .set = dmatest_run_set,
154 .get = dmatest_run_get,
155};
156static bool dmatest_run;
157module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
158MODULE_PARM_DESC(run, "Run the test (default: false)");
159
160static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
161static int dmatest_chan_get(char *val, const struct kernel_param *kp);
162static const struct kernel_param_ops multi_chan_ops = {
163 .set = dmatest_chan_set,
164 .get = dmatest_chan_get,
165};
166
167static char test_channel[20];
168static struct kparam_string newchan_kps = {
169 .string = test_channel,
170 .maxlen = 20,
171};
172module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644);
173MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
174
175static int dmatest_test_list_get(char *val, const struct kernel_param *kp);
176static const struct kernel_param_ops test_list_ops = {
177 .get = dmatest_test_list_get,
178};
179module_param_cb(test_list, &test_list_ops, NULL, 0444);
180MODULE_PARM_DESC(test_list, "Print current test list");
181
182/* Maximum amount of mismatched bytes in buffer to print */
183#define MAX_ERROR_COUNT 32
184
185/*
186 * Initialization patterns. All bytes in the source buffer has bit 7
187 * set, all bytes in the destination buffer has bit 7 cleared.
188 *
189 * Bit 6 is set for all bytes which are to be copied by the DMA
190 * engine. Bit 5 is set for all bytes which are to be overwritten by
191 * the DMA engine.
192 *
193 * The remaining bits are the inverse of a counter which increments by
194 * one for each byte address.
195 */
196#define PATTERN_SRC 0x80
197#define PATTERN_DST 0x00
198#define PATTERN_COPY 0x40
199#define PATTERN_OVERWRITE 0x20
200#define PATTERN_COUNT_MASK 0x1f
201#define PATTERN_MEMSET_IDX 0x01
202
203/* Fixed point arithmetic ops */
204#define FIXPT_SHIFT 8
205#define FIXPNT_MASK 0xFF
206#define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT)
207#define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT)
208#define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT)
209
210/* poor man's completion - we want to use wait_event_freezable() on it */
211struct dmatest_done {
212 bool done;
213 wait_queue_head_t *wait;
214};
215
216struct dmatest_data {
217 u8 **raw;
218 u8 **aligned;
219 unsigned int cnt;
220 unsigned int off;
221};
222
223struct dmatest_thread {
224 struct list_head node;
225 struct dmatest_info *info;
226 struct task_struct *task;
227 struct dma_chan *chan;
228 struct dmatest_data src;
229 struct dmatest_data dst;
230 enum dma_transaction_type type;
231 wait_queue_head_t done_wait;
232 struct dmatest_done test_done;
233 bool done;
234 bool pending;
235};
236
237struct dmatest_chan {
238 struct list_head node;
239 struct dma_chan *chan;
240 struct list_head threads;
241};
242
243static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
244static bool wait;
245
246static bool is_threaded_test_run(struct dmatest_info *info)
247{
248 struct dmatest_chan *dtc;
249
250 list_for_each_entry(dtc, &info->channels, node) {
251 struct dmatest_thread *thread;
252
253 list_for_each_entry(thread, &dtc->threads, node) {
254 if (!thread->done && !thread->pending)
255 return true;
256 }
257 }
258
259 return false;
260}
261
262static bool is_threaded_test_pending(struct dmatest_info *info)
263{
264 struct dmatest_chan *dtc;
265
266 list_for_each_entry(dtc, &info->channels, node) {
267 struct dmatest_thread *thread;
268
269 list_for_each_entry(thread, &dtc->threads, node) {
270 if (thread->pending)
271 return true;
272 }
273 }
274
275 return false;
276}
277
278static int dmatest_wait_get(char *val, const struct kernel_param *kp)
279{
280 struct dmatest_info *info = &test_info;
281 struct dmatest_params *params = &info->params;
282
283 if (params->iterations)
284 wait_event(thread_wait, !is_threaded_test_run(info));
285 wait = true;
286 return param_get_bool(val, kp);
287}
288
289static const struct kernel_param_ops wait_ops = {
290 .get = dmatest_wait_get,
291 .set = param_set_bool,
292};
293module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
294MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
295
296static bool dmatest_match_channel(struct dmatest_params *params,
297 struct dma_chan *chan)
298{
299 if (params->channel[0] == '\0')
300 return true;
301 return strcmp(dma_chan_name(chan), params->channel) == 0;
302}
303
304static bool dmatest_match_device(struct dmatest_params *params,
305 struct dma_device *device)
306{
307 if (params->device[0] == '\0')
308 return true;
309 return strcmp(dev_name(device->dev), params->device) == 0;
310}
311
312static unsigned long dmatest_random(void)
313{
314 unsigned long buf;
315
316 prandom_bytes(&buf, sizeof(buf));
317 return buf;
318}
319
320static inline u8 gen_inv_idx(u8 index, bool is_memset)
321{
322 u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
323
324 return ~val & PATTERN_COUNT_MASK;
325}
326
327static inline u8 gen_src_value(u8 index, bool is_memset)
328{
329 return PATTERN_SRC | gen_inv_idx(index, is_memset);
330}
331
332static inline u8 gen_dst_value(u8 index, bool is_memset)
333{
334 return PATTERN_DST | gen_inv_idx(index, is_memset);
335}
336
337static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
338 unsigned int buf_size, bool is_memset)
339{
340 unsigned int i;
341 u8 *buf;
342
343 for (; (buf = *bufs); bufs++) {
344 for (i = 0; i < start; i++)
345 buf[i] = gen_src_value(i, is_memset);
346 for ( ; i < start + len; i++)
347 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
348 for ( ; i < buf_size; i++)
349 buf[i] = gen_src_value(i, is_memset);
350 buf++;
351 }
352}
353
354static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
355 unsigned int buf_size, bool is_memset)
356{
357 unsigned int i;
358 u8 *buf;
359
360 for (; (buf = *bufs); bufs++) {
361 for (i = 0; i < start; i++)
362 buf[i] = gen_dst_value(i, is_memset);
363 for ( ; i < start + len; i++)
364 buf[i] = gen_dst_value(i, is_memset) |
365 PATTERN_OVERWRITE;
366 for ( ; i < buf_size; i++)
367 buf[i] = gen_dst_value(i, is_memset);
368 }
369}
370
371static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
372 unsigned int counter, bool is_srcbuf, bool is_memset)
373{
374 u8 diff = actual ^ pattern;
375 u8 expected = pattern | gen_inv_idx(counter, is_memset);
376 const char *thread_name = current->comm;
377
378 if (is_srcbuf)
379 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
380 thread_name, index, expected, actual);
381 else if ((pattern & PATTERN_COPY)
382 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
383 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
384 thread_name, index, expected, actual);
385 else if (diff & PATTERN_SRC)
386 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
387 thread_name, index, expected, actual);
388 else
389 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
390 thread_name, index, expected, actual);
391}
392
393static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
394 unsigned int end, unsigned int counter, u8 pattern,
395 bool is_srcbuf, bool is_memset)
396{
397 unsigned int i;
398 unsigned int error_count = 0;
399 u8 actual;
400 u8 expected;
401 u8 *buf;
402 unsigned int counter_orig = counter;
403
404 for (; (buf = *bufs); bufs++) {
405 counter = counter_orig;
406 for (i = start; i < end; i++) {
407 actual = buf[i];
408 expected = pattern | gen_inv_idx(counter, is_memset);
409 if (actual != expected) {
410 if (error_count < MAX_ERROR_COUNT)
411 dmatest_mismatch(actual, pattern, i,
412 counter, is_srcbuf,
413 is_memset);
414 error_count++;
415 }
416 counter++;
417 }
418 }
419
420 if (error_count > MAX_ERROR_COUNT)
421 pr_warn("%s: %u errors suppressed\n",
422 current->comm, error_count - MAX_ERROR_COUNT);
423
424 return error_count;
425}
426
427
428static void dmatest_callback(void *arg)
429{
430 struct dmatest_done *done = arg;
431 struct dmatest_thread *thread =
432 container_of(done, struct dmatest_thread, test_done);
433 if (!thread->done) {
434 done->done = true;
435 wake_up_all(done->wait);
436 } else {
437 /*
438 * If thread->done, it means that this callback occurred
439 * after the parent thread has cleaned up. This can
440 * happen in the case that driver doesn't implement
441 * the terminate_all() functionality and a dma operation
442 * did not occur within the timeout period
443 */
444 WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
445 }
446}
447
448static unsigned int min_odd(unsigned int x, unsigned int y)
449{
450 unsigned int val = min(x, y);
451
452 return val % 2 ? val : val - 1;
453}
454
455static void result(const char *err, unsigned int n, unsigned int src_off,
456 unsigned int dst_off, unsigned int len, unsigned long data)
457{
458 if (IS_ERR_VALUE(data)) {
459 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%ld)\n",
460 current->comm, n, err, src_off, dst_off, len, data);
461 } else {
462 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
463 current->comm, n, err, src_off, dst_off, len, data);
464 }
465}
466
467static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
468 unsigned int dst_off, unsigned int len,
469 unsigned long data)
470{
471 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
472 current->comm, n, err, src_off, dst_off, len, data);
473}
474
475#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
476 if (verbose) \
477 result(err, n, src_off, dst_off, len, data); \
478 else \
479 dbg_result(err, n, src_off, dst_off, len, data);\
480})
481
482static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
483{
484 unsigned long long per_sec = 1000000;
485
486 if (runtime <= 0)
487 return 0;
488
489 /* drop precision until runtime is 32-bits */
490 while (runtime > UINT_MAX) {
491 runtime >>= 1;
492 per_sec <<= 1;
493 }
494
495 per_sec *= val;
496 per_sec = INT_TO_FIXPT(per_sec);
497 do_div(per_sec, runtime);
498
499 return per_sec;
500}
501
502static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
503{
504 return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10));
505}
506
507static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt)
508{
509 unsigned int i;
510
511 for (i = 0; i < cnt; i++)
512 kfree(d->raw[i]);
513
514 kfree(d->aligned);
515 kfree(d->raw);
516}
517
518static void dmatest_free_test_data(struct dmatest_data *d)
519{
520 __dmatest_free_test_data(d, d->cnt);
521}
522
523static int dmatest_alloc_test_data(struct dmatest_data *d,
524 unsigned int buf_size, u8 align)
525{
526 unsigned int i = 0;
527
528 d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
529 if (!d->raw)
530 return -ENOMEM;
531
532 d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
533 if (!d->aligned)
534 goto err;
535
536 for (i = 0; i < d->cnt; i++) {
537 d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL);
538 if (!d->raw[i])
539 goto err;
540
541 /* align to alignment restriction */
542 if (align)
543 d->aligned[i] = PTR_ALIGN(d->raw[i], align);
544 else
545 d->aligned[i] = d->raw[i];
546 }
547
548 return 0;
549err:
550 __dmatest_free_test_data(d, i);
551 return -ENOMEM;
552}
553
554/*
555 * This function repeatedly tests DMA transfers of various lengths and
556 * offsets for a given operation type until it is told to exit by
557 * kthread_stop(). There may be multiple threads running this function
558 * in parallel for a single channel, and there may be multiple channels
559 * being tested in parallel.
560 *
561 * Before each test, the source and destination buffer is initialized
562 * with a known pattern. This pattern is different depending on
563 * whether it's in an area which is supposed to be copied or
564 * overwritten, and different in the source and destination buffers.
565 * So if the DMA engine doesn't copy exactly what we tell it to copy,
566 * we'll notice.
567 */
568static int dmatest_func(void *data)
569{
570 struct dmatest_thread *thread = data;
571 struct dmatest_done *done = &thread->test_done;
572 struct dmatest_info *info;
573 struct dmatest_params *params;
574 struct dma_chan *chan;
575 struct dma_device *dev;
576 struct device *dma_dev;
577 unsigned int error_count;
578 unsigned int failed_tests = 0;
579 unsigned int total_tests = 0;
580 dma_cookie_t cookie;
581 enum dma_status status;
582 enum dma_ctrl_flags flags;
583 u8 *pq_coefs = NULL;
584 int ret;
585 unsigned int buf_size;
586 struct dmatest_data *src;
587 struct dmatest_data *dst;
588 int i;
589 ktime_t ktime, start, diff;
590 ktime_t filltime = 0;
591 ktime_t comparetime = 0;
592 s64 runtime = 0;
593 unsigned long long total_len = 0;
594 unsigned long long iops = 0;
595 u8 align = 0;
596 bool is_memset = false;
597 dma_addr_t *srcs;
598 dma_addr_t *dma_pq;
599
600 set_freezable();
601
602 ret = -ENOMEM;
603
604 smp_rmb();
605 thread->pending = false;
606 info = thread->info;
607 params = &info->params;
608 chan = thread->chan;
609 dev = chan->device;
610 dma_dev = dmaengine_get_dma_device(chan);
611
612 src = &thread->src;
613 dst = &thread->dst;
614 if (thread->type == DMA_MEMCPY) {
615 align = params->alignment < 0 ? dev->copy_align :
616 params->alignment;
617 src->cnt = dst->cnt = 1;
618 } else if (thread->type == DMA_MEMSET) {
619 align = params->alignment < 0 ? dev->fill_align :
620 params->alignment;
621 src->cnt = dst->cnt = 1;
622 is_memset = true;
623 } else if (thread->type == DMA_XOR) {
624 /* force odd to ensure dst = src */
625 src->cnt = min_odd(params->xor_sources | 1, dev->max_xor);
626 dst->cnt = 1;
627 align = params->alignment < 0 ? dev->xor_align :
628 params->alignment;
629 } else if (thread->type == DMA_PQ) {
630 /* force odd to ensure dst = src */
631 src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
632 dst->cnt = 2;
633 align = params->alignment < 0 ? dev->pq_align :
634 params->alignment;
635
636 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
637 if (!pq_coefs)
638 goto err_thread_type;
639
640 for (i = 0; i < src->cnt; i++)
641 pq_coefs[i] = 1;
642 } else
643 goto err_thread_type;
644
645 /* Check if buffer count fits into map count variable (u8) */
646 if ((src->cnt + dst->cnt) >= 255) {
647 pr_err("too many buffers (%d of 255 supported)\n",
648 src->cnt + dst->cnt);
649 goto err_free_coefs;
650 }
651
652 buf_size = params->buf_size;
653 if (1 << align > buf_size) {
654 pr_err("%u-byte buffer too small for %d-byte alignment\n",
655 buf_size, 1 << align);
656 goto err_free_coefs;
657 }
658
659 if (dmatest_alloc_test_data(src, buf_size, align) < 0)
660 goto err_free_coefs;
661
662 if (dmatest_alloc_test_data(dst, buf_size, align) < 0)
663 goto err_src;
664
665 set_user_nice(current, 10);
666
667 srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL);
668 if (!srcs)
669 goto err_dst;
670
671 dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL);
672 if (!dma_pq)
673 goto err_srcs_array;
674
675 /*
676 * src and dst buffers are freed by ourselves below
677 */
678 if (params->polled)
679 flags = DMA_CTRL_ACK;
680 else
681 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
682
683 ktime = ktime_get();
684 while (!(kthread_should_stop() ||
685 (params->iterations && total_tests >= params->iterations))) {
686 struct dma_async_tx_descriptor *tx = NULL;
687 struct dmaengine_unmap_data *um;
688 dma_addr_t *dsts;
689 unsigned int len;
690
691 total_tests++;
692
693 if (params->transfer_size) {
694 if (params->transfer_size >= buf_size) {
695 pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
696 params->transfer_size, buf_size);
697 break;
698 }
699 len = params->transfer_size;
700 } else if (params->norandom) {
701 len = buf_size;
702 } else {
703 len = dmatest_random() % buf_size + 1;
704 }
705
706 /* Do not alter transfer size explicitly defined by user */
707 if (!params->transfer_size) {
708 len = (len >> align) << align;
709 if (!len)
710 len = 1 << align;
711 }
712 total_len += len;
713
714 if (params->norandom) {
715 src->off = 0;
716 dst->off = 0;
717 } else {
718 src->off = dmatest_random() % (buf_size - len + 1);
719 dst->off = dmatest_random() % (buf_size - len + 1);
720
721 src->off = (src->off >> align) << align;
722 dst->off = (dst->off >> align) << align;
723 }
724
725 if (!params->noverify) {
726 start = ktime_get();
727 dmatest_init_srcs(src->aligned, src->off, len,
728 buf_size, is_memset);
729 dmatest_init_dsts(dst->aligned, dst->off, len,
730 buf_size, is_memset);
731
732 diff = ktime_sub(ktime_get(), start);
733 filltime = ktime_add(filltime, diff);
734 }
735
736 um = dmaengine_get_unmap_data(dma_dev, src->cnt + dst->cnt,
737 GFP_KERNEL);
738 if (!um) {
739 failed_tests++;
740 result("unmap data NULL", total_tests,
741 src->off, dst->off, len, ret);
742 continue;
743 }
744
745 um->len = buf_size;
746 for (i = 0; i < src->cnt; i++) {
747 void *buf = src->aligned[i];
748 struct page *pg = virt_to_page(buf);
749 unsigned long pg_off = offset_in_page(buf);
750
751 um->addr[i] = dma_map_page(dma_dev, pg, pg_off,
752 um->len, DMA_TO_DEVICE);
753 srcs[i] = um->addr[i] + src->off;
754 ret = dma_mapping_error(dma_dev, um->addr[i]);
755 if (ret) {
756 result("src mapping error", total_tests,
757 src->off, dst->off, len, ret);
758 goto error_unmap_continue;
759 }
760 um->to_cnt++;
761 }
762 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
763 dsts = &um->addr[src->cnt];
764 for (i = 0; i < dst->cnt; i++) {
765 void *buf = dst->aligned[i];
766 struct page *pg = virt_to_page(buf);
767 unsigned long pg_off = offset_in_page(buf);
768
769 dsts[i] = dma_map_page(dma_dev, pg, pg_off, um->len,
770 DMA_BIDIRECTIONAL);
771 ret = dma_mapping_error(dma_dev, dsts[i]);
772 if (ret) {
773 result("dst mapping error", total_tests,
774 src->off, dst->off, len, ret);
775 goto error_unmap_continue;
776 }
777 um->bidi_cnt++;
778 }
779
780 if (thread->type == DMA_MEMCPY)
781 tx = dev->device_prep_dma_memcpy(chan,
782 dsts[0] + dst->off,
783 srcs[0], len, flags);
784 else if (thread->type == DMA_MEMSET)
785 tx = dev->device_prep_dma_memset(chan,
786 dsts[0] + dst->off,
787 *(src->aligned[0] + src->off),
788 len, flags);
789 else if (thread->type == DMA_XOR)
790 tx = dev->device_prep_dma_xor(chan,
791 dsts[0] + dst->off,
792 srcs, src->cnt,
793 len, flags);
794 else if (thread->type == DMA_PQ) {
795 for (i = 0; i < dst->cnt; i++)
796 dma_pq[i] = dsts[i] + dst->off;
797 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
798 src->cnt, pq_coefs,
799 len, flags);
800 }
801
802 if (!tx) {
803 result("prep error", total_tests, src->off,
804 dst->off, len, ret);
805 msleep(100);
806 goto error_unmap_continue;
807 }
808
809 done->done = false;
810 if (!params->polled) {
811 tx->callback = dmatest_callback;
812 tx->callback_param = done;
813 }
814 cookie = tx->tx_submit(tx);
815
816 if (dma_submit_error(cookie)) {
817 result("submit error", total_tests, src->off,
818 dst->off, len, ret);
819 msleep(100);
820 goto error_unmap_continue;
821 }
822
823 if (params->polled) {
824 status = dma_sync_wait(chan, cookie);
825 dmaengine_terminate_sync(chan);
826 if (status == DMA_COMPLETE)
827 done->done = true;
828 } else {
829 dma_async_issue_pending(chan);
830
831 wait_event_freezable_timeout(thread->done_wait,
832 done->done,
833 msecs_to_jiffies(params->timeout));
834
835 status = dma_async_is_tx_complete(chan, cookie, NULL,
836 NULL);
837 }
838
839 if (!done->done) {
840 result("test timed out", total_tests, src->off, dst->off,
841 len, 0);
842 goto error_unmap_continue;
843 } else if (status != DMA_COMPLETE &&
844 !(dma_has_cap(DMA_COMPLETION_NO_ORDER,
845 dev->cap_mask) &&
846 status == DMA_OUT_OF_ORDER)) {
847 result(status == DMA_ERROR ?
848 "completion error status" :
849 "completion busy status", total_tests, src->off,
850 dst->off, len, ret);
851 goto error_unmap_continue;
852 }
853
854 dmaengine_unmap_put(um);
855
856 if (params->noverify) {
857 verbose_result("test passed", total_tests, src->off,
858 dst->off, len, 0);
859 continue;
860 }
861
862 start = ktime_get();
863 pr_debug("%s: verifying source buffer...\n", current->comm);
864 error_count = dmatest_verify(src->aligned, 0, src->off,
865 0, PATTERN_SRC, true, is_memset);
866 error_count += dmatest_verify(src->aligned, src->off,
867 src->off + len, src->off,
868 PATTERN_SRC | PATTERN_COPY, true, is_memset);
869 error_count += dmatest_verify(src->aligned, src->off + len,
870 buf_size, src->off + len,
871 PATTERN_SRC, true, is_memset);
872
873 pr_debug("%s: verifying dest buffer...\n", current->comm);
874 error_count += dmatest_verify(dst->aligned, 0, dst->off,
875 0, PATTERN_DST, false, is_memset);
876
877 error_count += dmatest_verify(dst->aligned, dst->off,
878 dst->off + len, src->off,
879 PATTERN_SRC | PATTERN_COPY, false, is_memset);
880
881 error_count += dmatest_verify(dst->aligned, dst->off + len,
882 buf_size, dst->off + len,
883 PATTERN_DST, false, is_memset);
884
885 diff = ktime_sub(ktime_get(), start);
886 comparetime = ktime_add(comparetime, diff);
887
888 if (error_count) {
889 result("data error", total_tests, src->off, dst->off,
890 len, error_count);
891 failed_tests++;
892 } else {
893 verbose_result("test passed", total_tests, src->off,
894 dst->off, len, 0);
895 }
896
897 continue;
898
899error_unmap_continue:
900 dmaengine_unmap_put(um);
901 failed_tests++;
902 }
903 ktime = ktime_sub(ktime_get(), ktime);
904 ktime = ktime_sub(ktime, comparetime);
905 ktime = ktime_sub(ktime, filltime);
906 runtime = ktime_to_us(ktime);
907
908 ret = 0;
909 kfree(dma_pq);
910err_srcs_array:
911 kfree(srcs);
912err_dst:
913 dmatest_free_test_data(dst);
914err_src:
915 dmatest_free_test_data(src);
916err_free_coefs:
917 kfree(pq_coefs);
918err_thread_type:
919 iops = dmatest_persec(runtime, total_tests);
920 pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n",
921 current->comm, total_tests, failed_tests,
922 FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops),
923 dmatest_KBs(runtime, total_len), ret);
924
925 /* terminate all transfers on specified channels */
926 if (ret || failed_tests)
927 dmaengine_terminate_sync(chan);
928
929 thread->done = true;
930 wake_up(&thread_wait);
931
932 return ret;
933}
934
935static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
936{
937 struct dmatest_thread *thread;
938 struct dmatest_thread *_thread;
939 int ret;
940
941 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
942 ret = kthread_stop(thread->task);
943 pr_debug("thread %s exited with status %d\n",
944 thread->task->comm, ret);
945 list_del(&thread->node);
946 put_task_struct(thread->task);
947 kfree(thread);
948 }
949
950 /* terminate all transfers on specified channels */
951 dmaengine_terminate_sync(dtc->chan);
952
953 kfree(dtc);
954}
955
956static int dmatest_add_threads(struct dmatest_info *info,
957 struct dmatest_chan *dtc, enum dma_transaction_type type)
958{
959 struct dmatest_params *params = &info->params;
960 struct dmatest_thread *thread;
961 struct dma_chan *chan = dtc->chan;
962 char *op;
963 unsigned int i;
964
965 if (type == DMA_MEMCPY)
966 op = "copy";
967 else if (type == DMA_MEMSET)
968 op = "set";
969 else if (type == DMA_XOR)
970 op = "xor";
971 else if (type == DMA_PQ)
972 op = "pq";
973 else
974 return -EINVAL;
975
976 for (i = 0; i < params->threads_per_chan; i++) {
977 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
978 if (!thread) {
979 pr_warn("No memory for %s-%s%u\n",
980 dma_chan_name(chan), op, i);
981 break;
982 }
983 thread->info = info;
984 thread->chan = dtc->chan;
985 thread->type = type;
986 thread->test_done.wait = &thread->done_wait;
987 init_waitqueue_head(&thread->done_wait);
988 smp_wmb();
989 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
990 dma_chan_name(chan), op, i);
991 if (IS_ERR(thread->task)) {
992 pr_warn("Failed to create thread %s-%s%u\n",
993 dma_chan_name(chan), op, i);
994 kfree(thread);
995 break;
996 }
997
998 /* srcbuf and dstbuf are allocated by the thread itself */
999 get_task_struct(thread->task);
1000 list_add_tail(&thread->node, &dtc->threads);
1001 thread->pending = true;
1002 }
1003
1004 return i;
1005}
1006
1007static int dmatest_add_channel(struct dmatest_info *info,
1008 struct dma_chan *chan)
1009{
1010 struct dmatest_chan *dtc;
1011 struct dma_device *dma_dev = chan->device;
1012 unsigned int thread_count = 0;
1013 int cnt;
1014
1015 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
1016 if (!dtc) {
1017 pr_warn("No memory for %s\n", dma_chan_name(chan));
1018 return -ENOMEM;
1019 }
1020
1021 dtc->chan = chan;
1022 INIT_LIST_HEAD(&dtc->threads);
1023
1024 if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) &&
1025 info->params.polled) {
1026 info->params.polled = false;
1027 pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n");
1028 }
1029
1030 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1031 if (dmatest == 0) {
1032 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
1033 thread_count += cnt > 0 ? cnt : 0;
1034 }
1035 }
1036
1037 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1038 if (dmatest == 1) {
1039 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
1040 thread_count += cnt > 0 ? cnt : 0;
1041 }
1042 }
1043
1044 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1045 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
1046 thread_count += cnt > 0 ? cnt : 0;
1047 }
1048 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1049 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
1050 thread_count += cnt > 0 ? cnt : 0;
1051 }
1052
1053 pr_info("Added %u threads using %s\n",
1054 thread_count, dma_chan_name(chan));
1055
1056 list_add_tail(&dtc->node, &info->channels);
1057 info->nr_channels++;
1058
1059 return 0;
1060}
1061
1062static bool filter(struct dma_chan *chan, void *param)
1063{
1064 return dmatest_match_channel(param, chan) && dmatest_match_device(param, chan->device);
1065}
1066
1067static void request_channels(struct dmatest_info *info,
1068 enum dma_transaction_type type)
1069{
1070 dma_cap_mask_t mask;
1071
1072 dma_cap_zero(mask);
1073 dma_cap_set(type, mask);
1074 for (;;) {
1075 struct dmatest_params *params = &info->params;
1076 struct dma_chan *chan;
1077
1078 chan = dma_request_channel(mask, filter, params);
1079 if (chan) {
1080 if (dmatest_add_channel(info, chan)) {
1081 dma_release_channel(chan);
1082 break; /* add_channel failed, punt */
1083 }
1084 } else
1085 break; /* no more channels available */
1086 if (params->max_channels &&
1087 info->nr_channels >= params->max_channels)
1088 break; /* we have all we need */
1089 }
1090}
1091
1092static void add_threaded_test(struct dmatest_info *info)
1093{
1094 struct dmatest_params *params = &info->params;
1095
1096 /* Copy test parameters */
1097 params->buf_size = test_buf_size;
1098 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
1099 strlcpy(params->device, strim(test_device), sizeof(params->device));
1100 params->threads_per_chan = threads_per_chan;
1101 params->max_channels = max_channels;
1102 params->iterations = iterations;
1103 params->xor_sources = xor_sources;
1104 params->pq_sources = pq_sources;
1105 params->timeout = timeout;
1106 params->noverify = noverify;
1107 params->norandom = norandom;
1108 params->alignment = alignment;
1109 params->transfer_size = transfer_size;
1110 params->polled = polled;
1111
1112 request_channels(info, DMA_MEMCPY);
1113 request_channels(info, DMA_MEMSET);
1114 request_channels(info, DMA_XOR);
1115 request_channels(info, DMA_PQ);
1116}
1117
1118static void run_pending_tests(struct dmatest_info *info)
1119{
1120 struct dmatest_chan *dtc;
1121 unsigned int thread_count = 0;
1122
1123 list_for_each_entry(dtc, &info->channels, node) {
1124 struct dmatest_thread *thread;
1125
1126 thread_count = 0;
1127 list_for_each_entry(thread, &dtc->threads, node) {
1128 wake_up_process(thread->task);
1129 thread_count++;
1130 }
1131 pr_info("Started %u threads using %s\n",
1132 thread_count, dma_chan_name(dtc->chan));
1133 }
1134}
1135
1136static void stop_threaded_test(struct dmatest_info *info)
1137{
1138 struct dmatest_chan *dtc, *_dtc;
1139 struct dma_chan *chan;
1140
1141 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
1142 list_del(&dtc->node);
1143 chan = dtc->chan;
1144 dmatest_cleanup_channel(dtc);
1145 pr_debug("dropped channel %s\n", dma_chan_name(chan));
1146 dma_release_channel(chan);
1147 }
1148
1149 info->nr_channels = 0;
1150}
1151
1152static void start_threaded_tests(struct dmatest_info *info)
1153{
1154 /* we might be called early to set run=, defer running until all
1155 * parameters have been evaluated
1156 */
1157 if (!info->did_init)
1158 return;
1159
1160 run_pending_tests(info);
1161}
1162
1163static int dmatest_run_get(char *val, const struct kernel_param *kp)
1164{
1165 struct dmatest_info *info = &test_info;
1166
1167 mutex_lock(&info->lock);
1168 if (is_threaded_test_run(info)) {
1169 dmatest_run = true;
1170 } else {
1171 if (!is_threaded_test_pending(info))
1172 stop_threaded_test(info);
1173 dmatest_run = false;
1174 }
1175 mutex_unlock(&info->lock);
1176
1177 return param_get_bool(val, kp);
1178}
1179
1180static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1181{
1182 struct dmatest_info *info = &test_info;
1183 int ret;
1184
1185 mutex_lock(&info->lock);
1186 ret = param_set_bool(val, kp);
1187 if (ret) {
1188 mutex_unlock(&info->lock);
1189 return ret;
1190 } else if (dmatest_run) {
1191 if (!is_threaded_test_pending(info)) {
1192 /*
1193 * We have nothing to run. This can be due to:
1194 */
1195 ret = info->last_error;
1196 if (ret) {
1197 /* 1) Misconfiguration */
1198 pr_err("Channel misconfigured, can't continue\n");
1199 mutex_unlock(&info->lock);
1200 return ret;
1201 } else {
1202 /* 2) We rely on defaults */
1203 pr_info("No channels configured, continue with any\n");
1204 if (!is_threaded_test_run(info))
1205 stop_threaded_test(info);
1206 add_threaded_test(info);
1207 }
1208 }
1209 start_threaded_tests(info);
1210 } else {
1211 stop_threaded_test(info);
1212 }
1213
1214 mutex_unlock(&info->lock);
1215
1216 return ret;
1217}
1218
1219static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
1220{
1221 struct dmatest_info *info = &test_info;
1222 struct dmatest_chan *dtc;
1223 char chan_reset_val[20];
1224 int ret;
1225
1226 mutex_lock(&info->lock);
1227 ret = param_set_copystring(val, kp);
1228 if (ret) {
1229 mutex_unlock(&info->lock);
1230 return ret;
1231 }
1232 /*Clear any previously run threads */
1233 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info))
1234 stop_threaded_test(info);
1235 /* Reject channels that are already registered */
1236 if (is_threaded_test_pending(info)) {
1237 list_for_each_entry(dtc, &info->channels, node) {
1238 if (strcmp(dma_chan_name(dtc->chan),
1239 strim(test_channel)) == 0) {
1240 dtc = list_last_entry(&info->channels,
1241 struct dmatest_chan,
1242 node);
1243 strlcpy(chan_reset_val,
1244 dma_chan_name(dtc->chan),
1245 sizeof(chan_reset_val));
1246 ret = -EBUSY;
1247 goto add_chan_err;
1248 }
1249 }
1250 }
1251
1252 add_threaded_test(info);
1253
1254 /* Check if channel was added successfully */
1255 if (!list_empty(&info->channels)) {
1256 /*
1257 * if new channel was not successfully added, revert the
1258 * "test_channel" string to the name of the last successfully
1259 * added channel. exception for when users issues empty string
1260 * to channel parameter.
1261 */
1262 dtc = list_last_entry(&info->channels, struct dmatest_chan, node);
1263 if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0)
1264 && (strcmp("", strim(test_channel)) != 0)) {
1265 ret = -EINVAL;
1266 strlcpy(chan_reset_val, dma_chan_name(dtc->chan),
1267 sizeof(chan_reset_val));
1268 goto add_chan_err;
1269 }
1270
1271 } else {
1272 /* Clear test_channel if no channels were added successfully */
1273 strlcpy(chan_reset_val, "", sizeof(chan_reset_val));
1274 ret = -EBUSY;
1275 goto add_chan_err;
1276 }
1277
1278 info->last_error = ret;
1279 mutex_unlock(&info->lock);
1280
1281 return ret;
1282
1283add_chan_err:
1284 param_set_copystring(chan_reset_val, kp);
1285 info->last_error = ret;
1286 mutex_unlock(&info->lock);
1287
1288 return ret;
1289}
1290
1291static int dmatest_chan_get(char *val, const struct kernel_param *kp)
1292{
1293 struct dmatest_info *info = &test_info;
1294
1295 mutex_lock(&info->lock);
1296 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) {
1297 stop_threaded_test(info);
1298 strlcpy(test_channel, "", sizeof(test_channel));
1299 }
1300 mutex_unlock(&info->lock);
1301
1302 return param_get_string(val, kp);
1303}
1304
1305static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
1306{
1307 struct dmatest_info *info = &test_info;
1308 struct dmatest_chan *dtc;
1309 unsigned int thread_count = 0;
1310
1311 list_for_each_entry(dtc, &info->channels, node) {
1312 struct dmatest_thread *thread;
1313
1314 thread_count = 0;
1315 list_for_each_entry(thread, &dtc->threads, node) {
1316 thread_count++;
1317 }
1318 pr_info("%u threads using %s\n",
1319 thread_count, dma_chan_name(dtc->chan));
1320 }
1321
1322 return 0;
1323}
1324
1325static int __init dmatest_init(void)
1326{
1327 struct dmatest_info *info = &test_info;
1328 struct dmatest_params *params = &info->params;
1329
1330 if (dmatest_run) {
1331 mutex_lock(&info->lock);
1332 add_threaded_test(info);
1333 run_pending_tests(info);
1334 mutex_unlock(&info->lock);
1335 }
1336
1337 if (params->iterations && wait)
1338 wait_event(thread_wait, !is_threaded_test_run(info));
1339
1340 /* module parameters are stable, inittime tests are started,
1341 * let userspace take over 'run' control
1342 */
1343 info->did_init = true;
1344
1345 return 0;
1346}
1347/* when compiled-in wait for drivers to load first */
1348late_initcall(dmatest_init);
1349
1350static void __exit dmatest_exit(void)
1351{
1352 struct dmatest_info *info = &test_info;
1353
1354 mutex_lock(&info->lock);
1355 stop_threaded_test(info);
1356 mutex_unlock(&info->lock);
1357}
1358module_exit(dmatest_exit);
1359
1360MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1361MODULE_LICENSE("GPL v2");