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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Parts of this file are based on Ralink's 2.6.21 BSP
5 *
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
9 */
10
11#ifndef _MT7620_REGS_H_
12#define _MT7620_REGS_H_
13
14#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
15#define MT7620_SYSC_BASE IOMEM(0x10000000)
16
17#define SYSC_REG_CHIP_NAME0 0x00
18#define SYSC_REG_CHIP_NAME1 0x04
19#define SYSC_REG_EFUSE_CFG 0x08
20#define SYSC_REG_CHIP_REV 0x0c
21#define SYSC_REG_SYSTEM_CONFIG0 0x10
22#define SYSC_REG_SYSTEM_CONFIG1 0x14
23
24#define MT7620_CHIP_NAME0 0x3637544d
25#define MT7620_CHIP_NAME1 0x20203032
26#define MT7628_CHIP_NAME1 0x20203832
27
28#define CHIP_REV_PKG_MASK 0x1
29#define CHIP_REV_PKG_SHIFT 16
30#define CHIP_REV_VER_MASK 0xf
31#define CHIP_REV_VER_SHIFT 8
32#define CHIP_REV_ECO_MASK 0xf
33
34#define SYSCFG0_DRAM_TYPE_MASK 0x3
35#define SYSCFG0_DRAM_TYPE_SHIFT 4
36#define SYSCFG0_DRAM_TYPE_SDRAM 0
37#define SYSCFG0_DRAM_TYPE_DDR1 1
38#define SYSCFG0_DRAM_TYPE_DDR2 2
39#define SYSCFG0_DRAM_TYPE_UNKNOWN 3
40
41#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
42#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
43
44#define MT7620_DRAM_BASE 0x0
45#define MT7620_SDRAM_SIZE_MIN 2
46#define MT7620_SDRAM_SIZE_MAX 64
47#define MT7620_DDR1_SIZE_MIN 32
48#define MT7620_DDR1_SIZE_MAX 128
49#define MT7620_DDR2_SIZE_MIN 32
50#define MT7620_DDR2_SIZE_MAX 256
51
52extern enum ralink_soc_type ralink_soc;
53
54static inline int is_mt76x8(void)
55{
56 return ralink_soc == MT762X_SOC_MT7628AN ||
57 ralink_soc == MT762X_SOC_MT7688;
58}
59
60static inline int mt7620_get_eco(void)
61{
62 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
63}
64
65#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Parts of this file are based on Ralink's 2.6.21 BSP
5 *
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
9 */
10
11#ifndef _MT7620_REGS_H_
12#define _MT7620_REGS_H_
13
14#define MT7620_SYSC_BASE 0x10000000
15
16#define SYSC_REG_CHIP_NAME0 0x00
17#define SYSC_REG_CHIP_NAME1 0x04
18#define SYSC_REG_EFUSE_CFG 0x08
19#define SYSC_REG_CHIP_REV 0x0c
20#define SYSC_REG_SYSTEM_CONFIG0 0x10
21#define SYSC_REG_SYSTEM_CONFIG1 0x14
22#define SYSC_REG_CLKCFG0 0x2c
23#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
24#define SYSC_REG_CPLL_CONFIG0 0x54
25#define SYSC_REG_CPLL_CONFIG1 0x58
26
27#define MT7620_CHIP_NAME0 0x3637544d
28#define MT7620_CHIP_NAME1 0x20203032
29#define MT7628_CHIP_NAME1 0x20203832
30
31#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
32
33#define CHIP_REV_PKG_MASK 0x1
34#define CHIP_REV_PKG_SHIFT 16
35#define CHIP_REV_VER_MASK 0xf
36#define CHIP_REV_VER_SHIFT 8
37#define CHIP_REV_ECO_MASK 0xf
38
39#define CLKCFG0_PERI_CLK_SEL BIT(4)
40
41#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
42#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
43#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
44#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
45#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
46#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
47#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
48#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
49#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
50#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
51#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
52#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
53#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
54#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
55#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
56
57#define CPLL_CFG0_SW_CFG BIT(31)
58#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
59#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
60#define CPLL_CFG0_LC_CURFCK BIT(15)
61#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
62#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
63#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
64
65#define CPLL_CFG1_CPU_AUX1 BIT(25)
66#define CPLL_CFG1_CPU_AUX0 BIT(24)
67
68#define SYSCFG0_DRAM_TYPE_MASK 0x3
69#define SYSCFG0_DRAM_TYPE_SHIFT 4
70#define SYSCFG0_DRAM_TYPE_SDRAM 0
71#define SYSCFG0_DRAM_TYPE_DDR1 1
72#define SYSCFG0_DRAM_TYPE_DDR2 2
73#define SYSCFG0_DRAM_TYPE_UNKNOWN 3
74
75#define SYSCFG0_DRAM_TYPE_DDR2_MT7628 0
76#define SYSCFG0_DRAM_TYPE_DDR1_MT7628 1
77
78#define MT7620_DRAM_BASE 0x0
79#define MT7620_SDRAM_SIZE_MIN 2
80#define MT7620_SDRAM_SIZE_MAX 64
81#define MT7620_DDR1_SIZE_MIN 32
82#define MT7620_DDR1_SIZE_MAX 128
83#define MT7620_DDR2_SIZE_MIN 32
84#define MT7620_DDR2_SIZE_MAX 256
85
86extern enum ralink_soc_type ralink_soc;
87
88static inline int is_mt76x8(void)
89{
90 return ralink_soc == MT762X_SOC_MT7628AN ||
91 ralink_soc == MT762X_SOC_MT7688;
92}
93
94static inline int mt7620_get_eco(void)
95{
96 return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
97}
98
99#endif