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1/* SPDX-License-Identifier: GPL-2.0 */
2/****************************************************************************/
3
4/*
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
6 *
7 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
8 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
9 */
10
11/****************************************************************************/
12#ifndef m5206sim_h
13#define m5206sim_h
14/****************************************************************************/
15
16#define CPU_NAME "COLDFIRE(m5206)"
17#define CPU_INSTR_PER_JIFFY 3
18#define MCF_BUSCLK MCF_CLK
19
20#include <asm/m52xxacr.h>
21
22/*
23 * Define the 5206 SIM register set addresses.
24 */
25#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
26#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
27#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
28#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
29#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
30#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
31#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
32#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
33#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
34#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
35#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
36#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
37#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
38#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
39#ifdef CONFIG_M5206e
40#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
41#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
42#endif
43
44#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
45#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
46
47#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
48#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
49
50#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
51#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
52
53#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
54#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
55#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
56#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
57#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
58#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
59#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
60#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
61
62#define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63#define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64#define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65#define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66#define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67#define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
68#define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
69#define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
70#define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
71#define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
72#define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
73#define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
74#define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
75#define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
76#define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
77#define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
78#define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
79#define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
80#define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
81#define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
82#define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
83#define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
84#define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
85#define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
86#define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
87
88#ifdef CONFIG_M5206e
89#define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
90#else
91#define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
92#endif
93
94#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
95#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
96
97#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
98#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
99
100#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
101#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
102
103#if defined(CONFIG_NETtel)
104#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
105#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
106#else
107#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
108#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
109#endif
110
111/*
112 * Define system peripheral IRQ usage.
113 */
114#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
115#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
116#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
117#define MCF_IRQ_UART0 73 /* UART0 */
118#define MCF_IRQ_UART1 74 /* UART1 */
119
120/*
121 * Generic GPIO
122 */
123#define MCFGPIO_PIN_MAX 8
124#define MCFGPIO_IRQ_VECBASE -1
125#define MCFGPIO_IRQ_MAX -1
126
127/*
128 * Some symbol defines for the Parallel Port Pin Assignment Register
129 */
130#ifdef CONFIG_M5206e
131#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
132 /* Clear to select T0 input */
133#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
134 /* Clear to select T0 output */
135#endif
136
137/*
138 * Some symbol defines for the Interrupt Control Register
139 */
140#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
141#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
142#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
143#define MCFSIM_I2CICR MCFSIM_ICR11 /* I2C ICR */
144#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
145#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
146#ifdef CONFIG_M5206e
147#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
148#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
149#endif
150
151/*
152 * I2C Controller
153*/
154#define MCFI2C_BASE0 (MCF_MBAR + 0x1e0)
155#define MCFI2C_SIZE0 0x40
156
157/****************************************************************************/
158#endif /* m5206sim_h */
1/* SPDX-License-Identifier: GPL-2.0 */
2/****************************************************************************/
3
4/*
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
6 *
7 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
8 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
9 */
10
11/****************************************************************************/
12#ifndef m5206sim_h
13#define m5206sim_h
14/****************************************************************************/
15
16#define CPU_NAME "COLDFIRE(m5206)"
17#define CPU_INSTR_PER_JIFFY 3
18#define MCF_BUSCLK MCF_CLK
19
20#include <asm/m52xxacr.h>
21
22/*
23 * Define the 5206 SIM register set addresses.
24 */
25#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
26#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
27#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
28#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
29#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
30#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
31#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
32#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
33#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
34#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
35#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
36#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
37#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
38#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
39#ifdef CONFIG_M5206e
40#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
41#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
42#endif
43
44#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
45#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
46
47#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
48#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
49
50#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
51#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
52
53#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
54#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
55#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
56#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
57#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
58#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
59#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
60#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
61
62#define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63#define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64#define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65#define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66#define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67#define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
68#define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
69#define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
70#define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
71#define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
72#define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
73#define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
74#define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
75#define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
76#define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
77#define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
78#define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
79#define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
80#define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
81#define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
82#define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
83#define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
84#define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
85#define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
86#define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
87
88#ifdef CONFIG_M5206e
89#define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
90#else
91#define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
92#endif
93
94#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
95#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
96
97#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
98#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
99
100#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
101#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
102
103#if defined(CONFIG_NETtel)
104#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
105#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
106#else
107#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
108#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
109#endif
110
111/*
112 * Define system peripheral IRQ usage.
113 */
114#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
115#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
116#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
117#define MCF_IRQ_UART0 73 /* UART0 */
118#define MCF_IRQ_UART1 74 /* UART1 */
119
120/*
121 * Generic GPIO
122 */
123#define MCFGPIO_PIN_MAX 8
124#define MCFGPIO_IRQ_VECBASE -1
125#define MCFGPIO_IRQ_MAX -1
126
127/*
128 * Some symbol defines for the Parallel Port Pin Assignment Register
129 */
130#ifdef CONFIG_M5206e
131#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
132 /* Clear to select T0 input */
133#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
134 /* Clear to select T0 output */
135#endif
136
137/*
138 * Some symbol defines for the Interrupt Control Register
139 */
140#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
141#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
142#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
143#define MCFSIM_I2CICR MCFSIM_ICR11 /* I2C ICR */
144#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
145#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
146#ifdef CONFIG_M5206e
147#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
148#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
149#endif
150
151/*
152 * I2C Controller
153*/
154#define MCFI2C_BASE0 (MCF_MBAR + 0x1e0)
155#define MCFI2C_SIZE0 0x40
156
157/****************************************************************************/
158#endif /* m5206sim_h */