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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * SiFive UART driver
4 * Copyright (C) 2018 Paul Walmsley <paul@pwsan.com>
5 * Copyright (C) 2018-2019 SiFive
6 *
7 * Based partially on:
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
13 *
14 * See the following sources for further documentation:
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
17 * - The tree/master/src/main/scala/devices/uart directory of
18 * https://github.com/sifive/sifive-blocks/
19 *
20 * The SiFive UART design is not 8250-compatible. The following common
21 * features are not supported:
22 * - Word lengths other than 8 bits
23 * - Break handling
24 * - Parity
25 * - Flow control
26 * - Modem signals (DSR, RI, etc.)
27 * On the other hand, the design is free from the baggage of the 8250
28 * programming model.
29 */
30
31#include <linux/clk.h>
32#include <linux/console.h>
33#include <linux/delay.h>
34#include <linux/init.h>
35#include <linux/io.h>
36#include <linux/irq.h>
37#include <linux/module.h>
38#include <linux/of.h>
39#include <linux/of_irq.h>
40#include <linux/platform_device.h>
41#include <linux/serial_core.h>
42#include <linux/serial_reg.h>
43#include <linux/slab.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46
47/*
48 * Register offsets
49 */
50
51/* TXDATA */
52#define SIFIVE_SERIAL_TXDATA_OFFS 0x0
53#define SIFIVE_SERIAL_TXDATA_FULL_SHIFT 31
54#define SIFIVE_SERIAL_TXDATA_FULL_MASK (1 << SIFIVE_SERIAL_TXDATA_FULL_SHIFT)
55#define SIFIVE_SERIAL_TXDATA_DATA_SHIFT 0
56#define SIFIVE_SERIAL_TXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_TXDATA_DATA_SHIFT)
57
58/* RXDATA */
59#define SIFIVE_SERIAL_RXDATA_OFFS 0x4
60#define SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT 31
61#define SIFIVE_SERIAL_RXDATA_EMPTY_MASK (1 << SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT)
62#define SIFIVE_SERIAL_RXDATA_DATA_SHIFT 0
63#define SIFIVE_SERIAL_RXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_RXDATA_DATA_SHIFT)
64
65/* TXCTRL */
66#define SIFIVE_SERIAL_TXCTRL_OFFS 0x8
67#define SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT 16
68#define SIFIVE_SERIAL_TXCTRL_TXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
69#define SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT 1
70#define SIFIVE_SERIAL_TXCTRL_NSTOP_MASK (1 << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT)
71#define SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT 0
72#define SIFIVE_SERIAL_TXCTRL_TXEN_MASK (1 << SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT)
73
74/* RXCTRL */
75#define SIFIVE_SERIAL_RXCTRL_OFFS 0xC
76#define SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT 16
77#define SIFIVE_SERIAL_RXCTRL_RXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
78#define SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT 0
79#define SIFIVE_SERIAL_RXCTRL_RXEN_MASK (1 << SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT)
80
81/* IE */
82#define SIFIVE_SERIAL_IE_OFFS 0x10
83#define SIFIVE_SERIAL_IE_RXWM_SHIFT 1
84#define SIFIVE_SERIAL_IE_RXWM_MASK (1 << SIFIVE_SERIAL_IE_RXWM_SHIFT)
85#define SIFIVE_SERIAL_IE_TXWM_SHIFT 0
86#define SIFIVE_SERIAL_IE_TXWM_MASK (1 << SIFIVE_SERIAL_IE_TXWM_SHIFT)
87
88/* IP */
89#define SIFIVE_SERIAL_IP_OFFS 0x14
90#define SIFIVE_SERIAL_IP_RXWM_SHIFT 1
91#define SIFIVE_SERIAL_IP_RXWM_MASK (1 << SIFIVE_SERIAL_IP_RXWM_SHIFT)
92#define SIFIVE_SERIAL_IP_TXWM_SHIFT 0
93#define SIFIVE_SERIAL_IP_TXWM_MASK (1 << SIFIVE_SERIAL_IP_TXWM_SHIFT)
94
95/* DIV */
96#define SIFIVE_SERIAL_DIV_OFFS 0x18
97#define SIFIVE_SERIAL_DIV_DIV_SHIFT 0
98#define SIFIVE_SERIAL_DIV_DIV_MASK (0xffff << SIFIVE_SERIAL_IP_DIV_SHIFT)
99
100/*
101 * Config macros
102 */
103
104/*
105 * SIFIVE_SERIAL_MAX_PORTS: maximum number of UARTs on a device that can
106 * host a serial console
107 */
108#define SIFIVE_SERIAL_MAX_PORTS 8
109
110/*
111 * SIFIVE_DEFAULT_BAUD_RATE: default baud rate that the driver should
112 * configure itself to use
113 */
114#define SIFIVE_DEFAULT_BAUD_RATE 115200
115
116/* SIFIVE_SERIAL_NAME: our driver's name that we pass to the operating system */
117#define SIFIVE_SERIAL_NAME "sifive-serial"
118
119/* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
120#define SIFIVE_TTY_PREFIX "ttySIF"
121
122/* SIFIVE_TX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
123#define SIFIVE_TX_FIFO_DEPTH 8
124
125/* SIFIVE_RX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
126#define SIFIVE_RX_FIFO_DEPTH 8
127
128#if (SIFIVE_TX_FIFO_DEPTH != SIFIVE_RX_FIFO_DEPTH)
129#error Driver does not support configurations with different TX, RX FIFO sizes
130#endif
131
132/*
133 *
134 */
135
136/**
137 * struct sifive_serial_port - driver-specific data extension to struct uart_port
138 * @port: struct uart_port embedded in this struct
139 * @dev: struct device *
140 * @ier: shadowed copy of the interrupt enable register
141 * @baud_rate: UART serial line rate (e.g., 115200 baud)
142 * @clk: reference to this device's clock
143 * @clk_notifier: clock rate change notifier for upstream clock changes
144 *
145 * Configuration data specific to this SiFive UART.
146 */
147struct sifive_serial_port {
148 struct uart_port port;
149 struct device *dev;
150 unsigned char ier;
151 unsigned long baud_rate;
152 struct clk *clk;
153 struct notifier_block clk_notifier;
154};
155
156/*
157 * Structure container-of macros
158 */
159
160#define port_to_sifive_serial_port(p) (container_of((p), \
161 struct sifive_serial_port, \
162 port))
163
164#define notifier_to_sifive_serial_port(nb) (container_of((nb), \
165 struct sifive_serial_port, \
166 clk_notifier))
167
168/*
169 * Forward declarations
170 */
171static void sifive_serial_stop_tx(struct uart_port *port);
172
173/*
174 * Internal functions
175 */
176
177/**
178 * __ssp_early_writel() - write to a SiFive serial port register (early)
179 * @port: pointer to a struct uart_port record
180 * @offs: register address offset from the IP block base address
181 * @v: value to write to the register
182 *
183 * Given a pointer @port to a struct uart_port record, write the value
184 * @v to the IP block register address offset @offs. This function is
185 * intended for early console use.
186 *
187 * Context: Intended to be used only by the earlyconsole code.
188 */
189static void __ssp_early_writel(u32 v, u16 offs, struct uart_port *port)
190{
191 writel_relaxed(v, port->membase + offs);
192}
193
194/**
195 * __ssp_early_readl() - read from a SiFive serial port register (early)
196 * @port: pointer to a struct uart_port record
197 * @offs: register address offset from the IP block base address
198 *
199 * Given a pointer @port to a struct uart_port record, read the
200 * contents of the IP block register located at offset @offs from the
201 * IP block base and return it. This function is intended for early
202 * console use.
203 *
204 * Context: Intended to be called only by the earlyconsole code or by
205 * __ssp_readl() or __ssp_writel() (in this driver)
206 *
207 * Returns: the register value read from the UART.
208 */
209static u32 __ssp_early_readl(struct uart_port *port, u16 offs)
210{
211 return readl_relaxed(port->membase + offs);
212}
213
214/**
215 * __ssp_writel() - write to a SiFive serial port register
216 * @v: value to write to the register
217 * @offs: register address offset from the IP block base address
218 * @ssp: pointer to a struct sifive_serial_port record
219 *
220 * Write the value @v to the IP block register located at offset @offs from the
221 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
222 *
223 * Context: Any context.
224 */
225static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp)
226{
227 __ssp_early_writel(v, offs, &ssp->port);
228}
229
230/**
231 * __ssp_readl() - read from a SiFive serial port register
232 * @ssp: pointer to a struct sifive_serial_port record
233 * @offs: register address offset from the IP block base address
234 *
235 * Read the contents of the IP block register located at offset @offs from the
236 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
237 *
238 * Context: Any context.
239 *
240 * Returns: the value of the UART register
241 */
242static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs)
243{
244 return __ssp_early_readl(&ssp->port, offs);
245}
246
247/**
248 * sifive_serial_is_txfifo_full() - is the TXFIFO full?
249 * @ssp: pointer to a struct sifive_serial_port
250 *
251 * Read the transmit FIFO "full" bit, returning a non-zero value if the
252 * TX FIFO is full, or zero if space remains. Intended to be used to prevent
253 * writes to the TX FIFO when it's full.
254 *
255 * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
256 * is full, or 0 if space remains.
257 */
258static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp)
259{
260 return __ssp_readl(ssp, SIFIVE_SERIAL_TXDATA_OFFS) &
261 SIFIVE_SERIAL_TXDATA_FULL_MASK;
262}
263
264/**
265 * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
266 * @ssp: pointer to a struct sifive_serial_port
267 * @ch: character to transmit
268 *
269 * Enqueue a byte @ch onto the transmit FIFO, given a pointer @ssp to the
270 * struct sifive_serial_port * to transmit on. Caller should first check to
271 * ensure that the TXFIFO has space; see sifive_serial_is_txfifo_full().
272 *
273 * Context: Any context.
274 */
275static void __ssp_transmit_char(struct sifive_serial_port *ssp, int ch)
276{
277 __ssp_writel(ch, SIFIVE_SERIAL_TXDATA_OFFS, ssp);
278}
279
280/**
281 * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
282 * @ssp: pointer to a struct sifive_serial_port
283 *
284 * Transfer up to a TX FIFO size's worth of characters from the Linux serial
285 * transmit buffer to the SiFive UART TX FIFO.
286 *
287 * Context: Any context. Expects @ssp->port.lock to be held by caller.
288 */
289static void __ssp_transmit_chars(struct sifive_serial_port *ssp)
290{
291 u8 ch;
292
293 uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH,
294 true,
295 __ssp_transmit_char(ssp, ch),
296 ({}));
297}
298
299/**
300 * __ssp_enable_txwm() - enable transmit watermark interrupts
301 * @ssp: pointer to a struct sifive_serial_port
302 *
303 * Enable interrupt generation when the transmit FIFO watermark is reached
304 * on the SiFive UART referred to by @ssp.
305 */
306static void __ssp_enable_txwm(struct sifive_serial_port *ssp)
307{
308 if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)
309 return;
310
311 ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;
312 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
313}
314
315/**
316 * __ssp_enable_rxwm() - enable receive watermark interrupts
317 * @ssp: pointer to a struct sifive_serial_port
318 *
319 * Enable interrupt generation when the receive FIFO watermark is reached
320 * on the SiFive UART referred to by @ssp.
321 */
322static void __ssp_enable_rxwm(struct sifive_serial_port *ssp)
323{
324 if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)
325 return;
326
327 ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;
328 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
329}
330
331/**
332 * __ssp_disable_txwm() - disable transmit watermark interrupts
333 * @ssp: pointer to a struct sifive_serial_port
334 *
335 * Disable interrupt generation when the transmit FIFO watermark is reached
336 * on the UART referred to by @ssp.
337 */
338static void __ssp_disable_txwm(struct sifive_serial_port *ssp)
339{
340 if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))
341 return;
342
343 ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;
344 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
345}
346
347/**
348 * __ssp_disable_rxwm() - disable receive watermark interrupts
349 * @ssp: pointer to a struct sifive_serial_port
350 *
351 * Disable interrupt generation when the receive FIFO watermark is reached
352 * on the UART referred to by @ssp.
353 */
354static void __ssp_disable_rxwm(struct sifive_serial_port *ssp)
355{
356 if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))
357 return;
358
359 ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;
360 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
361}
362
363/**
364 * __ssp_receive_char() - receive a byte from the UART
365 * @ssp: pointer to a struct sifive_serial_port
366 * @is_empty: char pointer to return whether the RX FIFO is empty
367 *
368 * Try to read a byte from the SiFive UART RX FIFO, referenced by
369 * @ssp, and to return it. Also returns the RX FIFO empty bit in
370 * the char pointed to by @ch. The caller must pass the byte back to the
371 * Linux serial layer if needed.
372 *
373 * Returns: the byte read from the UART RX FIFO.
374 */
375static char __ssp_receive_char(struct sifive_serial_port *ssp, char *is_empty)
376{
377 u32 v;
378 u8 ch;
379
380 v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS);
381
382 if (!is_empty)
383 WARN_ON(1);
384 else
385 *is_empty = (v & SIFIVE_SERIAL_RXDATA_EMPTY_MASK) >>
386 SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT;
387
388 ch = (v & SIFIVE_SERIAL_RXDATA_DATA_MASK) >>
389 SIFIVE_SERIAL_RXDATA_DATA_SHIFT;
390
391 return ch;
392}
393
394/**
395 * __ssp_receive_chars() - receive multiple bytes from the UART
396 * @ssp: pointer to a struct sifive_serial_port
397 *
398 * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
399 * to by @ssp and pass them up to the Linux serial layer.
400 *
401 * Context: Expects ssp->port.lock to be held by caller.
402 */
403static void __ssp_receive_chars(struct sifive_serial_port *ssp)
404{
405 char is_empty;
406 int c;
407 u8 ch;
408
409 for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {
410 ch = __ssp_receive_char(ssp, &is_empty);
411 if (is_empty)
412 break;
413
414 ssp->port.icount.rx++;
415 uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);
416 }
417
418 tty_flip_buffer_push(&ssp->port.state->port);
419}
420
421/**
422 * __ssp_update_div() - calculate the divisor setting by the line rate
423 * @ssp: pointer to a struct sifive_serial_port
424 *
425 * Calculate the appropriate value of the clock divisor for the UART
426 * and target line rate referred to by @ssp and write it into the
427 * hardware.
428 */
429static void __ssp_update_div(struct sifive_serial_port *ssp)
430{
431 u16 div;
432
433 div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1;
434
435 __ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
436}
437
438/**
439 * __ssp_update_baud_rate() - set the UART "baud rate"
440 * @ssp: pointer to a struct sifive_serial_port
441 * @rate: new target bit rate
442 *
443 * Calculate the UART divisor value for the target bit rate @rate for the
444 * SiFive UART described by @ssp and program it into the UART. There may
445 * be some error between the target bit rate and the actual bit rate implemented
446 * by the UART due to clock ratio granularity.
447 */
448static void __ssp_update_baud_rate(struct sifive_serial_port *ssp,
449 unsigned int rate)
450{
451 if (ssp->baud_rate == rate)
452 return;
453
454 ssp->baud_rate = rate;
455 __ssp_update_div(ssp);
456}
457
458/**
459 * __ssp_set_stop_bits() - set the number of stop bits
460 * @ssp: pointer to a struct sifive_serial_port
461 * @nstop: 1 or 2 (stop bits)
462 *
463 * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
464 */
465static void __ssp_set_stop_bits(struct sifive_serial_port *ssp, char nstop)
466{
467 u32 v;
468
469 if (nstop < 1 || nstop > 2) {
470 WARN_ON(1);
471 return;
472 }
473
474 v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS);
475 v &= ~SIFIVE_SERIAL_TXCTRL_NSTOP_MASK;
476 v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;
477 __ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
478}
479
480/**
481 * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
482 * @ssp: pointer to a struct sifive_serial_port
483 *
484 * Delay while the UART TX FIFO referred to by @ssp is marked as full.
485 *
486 * Context: Any context.
487 */
488static void __maybe_unused __ssp_wait_for_xmitr(struct sifive_serial_port *ssp)
489{
490 while (sifive_serial_is_txfifo_full(ssp))
491 udelay(1); /* XXX Could probably be more intelligent here */
492}
493
494/*
495 * Linux serial API functions
496 */
497
498static void sifive_serial_stop_tx(struct uart_port *port)
499{
500 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
501
502 __ssp_disable_txwm(ssp);
503}
504
505static void sifive_serial_stop_rx(struct uart_port *port)
506{
507 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
508
509 __ssp_disable_rxwm(ssp);
510}
511
512static void sifive_serial_start_tx(struct uart_port *port)
513{
514 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
515
516 __ssp_enable_txwm(ssp);
517}
518
519static irqreturn_t sifive_serial_irq(int irq, void *dev_id)
520{
521 struct sifive_serial_port *ssp = dev_id;
522 u32 ip;
523
524 uart_port_lock(&ssp->port);
525
526 ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS);
527 if (!ip) {
528 uart_port_unlock(&ssp->port);
529 return IRQ_NONE;
530 }
531
532 if (ip & SIFIVE_SERIAL_IP_RXWM_MASK)
533 __ssp_receive_chars(ssp);
534 if (ip & SIFIVE_SERIAL_IP_TXWM_MASK)
535 __ssp_transmit_chars(ssp);
536
537 uart_port_unlock(&ssp->port);
538
539 return IRQ_HANDLED;
540}
541
542static unsigned int sifive_serial_tx_empty(struct uart_port *port)
543{
544 return TIOCSER_TEMT;
545}
546
547static unsigned int sifive_serial_get_mctrl(struct uart_port *port)
548{
549 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
550}
551
552static void sifive_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
553{
554 /* IP block does not support these signals */
555}
556
557static void sifive_serial_break_ctl(struct uart_port *port, int break_state)
558{
559 /* IP block does not support sending a break */
560}
561
562static int sifive_serial_startup(struct uart_port *port)
563{
564 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
565
566 __ssp_enable_rxwm(ssp);
567
568 return 0;
569}
570
571static void sifive_serial_shutdown(struct uart_port *port)
572{
573 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
574
575 __ssp_disable_rxwm(ssp);
576 __ssp_disable_txwm(ssp);
577}
578
579/**
580 * sifive_serial_clk_notifier() - clock post-rate-change notifier
581 * @nb: pointer to the struct notifier_block, from the notifier code
582 * @event: event mask from the notifier code
583 * @data: pointer to the struct clk_notifier_data from the notifier code
584 *
585 * On the V0 SoC, the UART IP block is derived from the CPU clock source
586 * after a synchronous divide-by-two divider, so any CPU clock rate change
587 * requires the UART baud rate to be updated. This presumably corrupts any
588 * serial word currently being transmitted or received. In order to avoid
589 * corrupting the output data stream, we drain the transmit queue before
590 * allowing the clock's rate to be changed.
591 */
592static int sifive_serial_clk_notifier(struct notifier_block *nb,
593 unsigned long event, void *data)
594{
595 struct clk_notifier_data *cnd = data;
596 struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb);
597
598 if (event == PRE_RATE_CHANGE) {
599 /*
600 * The TX watermark is always set to 1 by this driver, which
601 * means that the TX busy bit will lower when there are 0 bytes
602 * left in the TX queue -- in other words, when the TX FIFO is
603 * empty.
604 */
605 __ssp_wait_for_xmitr(ssp);
606 /*
607 * On the cycle the TX FIFO goes empty there is still a full
608 * UART frame left to be transmitted in the shift register.
609 * The UART provides no way for software to directly determine
610 * when that last frame has been transmitted, so we just sleep
611 * here instead. As we're not tracking the number of stop bits
612 * they're just worst cased here. The rest of the serial
613 * framing parameters aren't configurable by software.
614 */
615 udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
616 }
617
618 if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) {
619 ssp->port.uartclk = cnd->new_rate;
620 __ssp_update_div(ssp);
621 }
622
623 return NOTIFY_OK;
624}
625
626static void sifive_serial_set_termios(struct uart_port *port,
627 struct ktermios *termios,
628 const struct ktermios *old)
629{
630 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
631 unsigned long flags;
632 u32 v, old_v;
633 int rate;
634 char nstop;
635
636 if ((termios->c_cflag & CSIZE) != CS8) {
637 dev_err_once(ssp->port.dev, "only 8-bit words supported\n");
638 termios->c_cflag &= ~CSIZE;
639 termios->c_cflag |= CS8;
640 }
641 if (termios->c_iflag & (INPCK | PARMRK))
642 dev_err_once(ssp->port.dev, "parity checking not supported\n");
643 if (termios->c_iflag & BRKINT)
644 dev_err_once(ssp->port.dev, "BREAK detection not supported\n");
645 termios->c_iflag &= ~(INPCK|PARMRK|BRKINT);
646
647 /* Set number of stop bits */
648 nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;
649 __ssp_set_stop_bits(ssp, nstop);
650
651 /* Set line rate */
652 rate = uart_get_baud_rate(port, termios, old, 0,
653 ssp->port.uartclk / 16);
654 __ssp_update_baud_rate(ssp, rate);
655
656 uart_port_lock_irqsave(&ssp->port, &flags);
657
658 /* Update the per-port timeout */
659 uart_update_timeout(port, termios->c_cflag, rate);
660
661 ssp->port.read_status_mask = 0;
662
663 /* Ignore all characters if CREAD is not set */
664 v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS);
665 old_v = v;
666 if ((termios->c_cflag & CREAD) == 0)
667 v &= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
668 else
669 v |= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
670 if (v != old_v)
671 __ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
672
673 uart_port_unlock_irqrestore(&ssp->port, flags);
674}
675
676static void sifive_serial_release_port(struct uart_port *port)
677{
678}
679
680static int sifive_serial_request_port(struct uart_port *port)
681{
682 return 0;
683}
684
685static void sifive_serial_config_port(struct uart_port *port, int flags)
686{
687 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
688
689 ssp->port.type = PORT_SIFIVE_V0;
690}
691
692static int sifive_serial_verify_port(struct uart_port *port,
693 struct serial_struct *ser)
694{
695 return -EINVAL;
696}
697
698static const char *sifive_serial_type(struct uart_port *port)
699{
700 return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;
701}
702
703#ifdef CONFIG_CONSOLE_POLL
704static int sifive_serial_poll_get_char(struct uart_port *port)
705{
706 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
707 char is_empty, ch;
708
709 ch = __ssp_receive_char(ssp, &is_empty);
710 if (is_empty)
711 return NO_POLL_CHAR;
712
713 return ch;
714}
715
716static void sifive_serial_poll_put_char(struct uart_port *port,
717 unsigned char c)
718{
719 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
720
721 __ssp_wait_for_xmitr(ssp);
722 __ssp_transmit_char(ssp, c);
723}
724#endif /* CONFIG_CONSOLE_POLL */
725
726/*
727 * Early console support
728 */
729
730#ifdef CONFIG_SERIAL_EARLYCON
731static void early_sifive_serial_putc(struct uart_port *port, unsigned char c)
732{
733 while (__ssp_early_readl(port, SIFIVE_SERIAL_TXDATA_OFFS) &
734 SIFIVE_SERIAL_TXDATA_FULL_MASK)
735 cpu_relax();
736
737 __ssp_early_writel(c, SIFIVE_SERIAL_TXDATA_OFFS, port);
738}
739
740static void early_sifive_serial_write(struct console *con, const char *s,
741 unsigned int n)
742{
743 struct earlycon_device *dev = con->data;
744 struct uart_port *port = &dev->port;
745
746 uart_console_write(port, s, n, early_sifive_serial_putc);
747}
748
749static int __init early_sifive_serial_setup(struct earlycon_device *dev,
750 const char *options)
751{
752 struct uart_port *port = &dev->port;
753
754 if (!port->membase)
755 return -ENODEV;
756
757 dev->con->write = early_sifive_serial_write;
758
759 return 0;
760}
761
762OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
763OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
764 early_sifive_serial_setup);
765#endif /* CONFIG_SERIAL_EARLYCON */
766
767/*
768 * Linux console interface
769 */
770
771#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
772
773static struct sifive_serial_port *sifive_serial_console_ports[SIFIVE_SERIAL_MAX_PORTS];
774
775static void sifive_serial_console_putchar(struct uart_port *port, unsigned char ch)
776{
777 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
778
779 __ssp_wait_for_xmitr(ssp);
780 __ssp_transmit_char(ssp, ch);
781}
782
783static void sifive_serial_console_write(struct console *co, const char *s,
784 unsigned int count)
785{
786 struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];
787 unsigned long flags;
788 unsigned int ier;
789 int locked = 1;
790
791 if (!ssp)
792 return;
793
794 local_irq_save(flags);
795 if (ssp->port.sysrq)
796 locked = 0;
797 else if (oops_in_progress)
798 locked = uart_port_trylock(&ssp->port);
799 else
800 uart_port_lock(&ssp->port);
801
802 ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS);
803 __ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp);
804
805 uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);
806
807 __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
808
809 if (locked)
810 uart_port_unlock(&ssp->port);
811 local_irq_restore(flags);
812}
813
814static int sifive_serial_console_setup(struct console *co, char *options)
815{
816 struct sifive_serial_port *ssp;
817 int baud = SIFIVE_DEFAULT_BAUD_RATE;
818 int bits = 8;
819 int parity = 'n';
820 int flow = 'n';
821
822 if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)
823 return -ENODEV;
824
825 ssp = sifive_serial_console_ports[co->index];
826 if (!ssp)
827 return -ENODEV;
828
829 if (options)
830 uart_parse_options(options, &baud, &parity, &bits, &flow);
831
832 return uart_set_options(&ssp->port, co, baud, parity, bits, flow);
833}
834
835static struct uart_driver sifive_serial_uart_driver;
836
837static struct console sifive_serial_console = {
838 .name = SIFIVE_TTY_PREFIX,
839 .write = sifive_serial_console_write,
840 .device = uart_console_device,
841 .setup = sifive_serial_console_setup,
842 .flags = CON_PRINTBUFFER,
843 .index = -1,
844 .data = &sifive_serial_uart_driver,
845};
846
847static int __init sifive_console_init(void)
848{
849 register_console(&sifive_serial_console);
850 return 0;
851}
852
853console_initcall(sifive_console_init);
854
855static void __ssp_add_console_port(struct sifive_serial_port *ssp)
856{
857 sifive_serial_console_ports[ssp->port.line] = ssp;
858}
859
860static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
861{
862 sifive_serial_console_ports[ssp->port.line] = NULL;
863}
864
865#define SIFIVE_SERIAL_CONSOLE (&sifive_serial_console)
866
867#else
868
869#define SIFIVE_SERIAL_CONSOLE NULL
870
871static void __ssp_add_console_port(struct sifive_serial_port *ssp)
872{}
873static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
874{}
875
876#endif
877
878static const struct uart_ops sifive_serial_uops = {
879 .tx_empty = sifive_serial_tx_empty,
880 .set_mctrl = sifive_serial_set_mctrl,
881 .get_mctrl = sifive_serial_get_mctrl,
882 .stop_tx = sifive_serial_stop_tx,
883 .start_tx = sifive_serial_start_tx,
884 .stop_rx = sifive_serial_stop_rx,
885 .break_ctl = sifive_serial_break_ctl,
886 .startup = sifive_serial_startup,
887 .shutdown = sifive_serial_shutdown,
888 .set_termios = sifive_serial_set_termios,
889 .type = sifive_serial_type,
890 .release_port = sifive_serial_release_port,
891 .request_port = sifive_serial_request_port,
892 .config_port = sifive_serial_config_port,
893 .verify_port = sifive_serial_verify_port,
894#ifdef CONFIG_CONSOLE_POLL
895 .poll_get_char = sifive_serial_poll_get_char,
896 .poll_put_char = sifive_serial_poll_put_char,
897#endif
898};
899
900static struct uart_driver sifive_serial_uart_driver = {
901 .owner = THIS_MODULE,
902 .driver_name = SIFIVE_SERIAL_NAME,
903 .dev_name = SIFIVE_TTY_PREFIX,
904 .nr = SIFIVE_SERIAL_MAX_PORTS,
905 .cons = SIFIVE_SERIAL_CONSOLE,
906};
907
908static int sifive_serial_probe(struct platform_device *pdev)
909{
910 struct sifive_serial_port *ssp;
911 struct resource *mem;
912 struct clk *clk;
913 void __iomem *base;
914 int irq, id, r;
915
916 irq = platform_get_irq(pdev, 0);
917 if (irq < 0)
918 return -EPROBE_DEFER;
919
920 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
921 if (IS_ERR(base))
922 return PTR_ERR(base);
923
924 clk = devm_clk_get_enabled(&pdev->dev, NULL);
925 if (IS_ERR(clk)) {
926 dev_err(&pdev->dev, "unable to find controller clock\n");
927 return PTR_ERR(clk);
928 }
929
930 id = of_alias_get_id(pdev->dev.of_node, "serial");
931 if (id < 0) {
932 dev_err(&pdev->dev, "missing aliases entry\n");
933 return id;
934 }
935
936#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
937 if (id > SIFIVE_SERIAL_MAX_PORTS) {
938 dev_err(&pdev->dev, "too many UARTs (%d)\n", id);
939 return -EINVAL;
940 }
941#endif
942
943 ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
944 if (!ssp)
945 return -ENOMEM;
946
947 ssp->port.dev = &pdev->dev;
948 ssp->port.type = PORT_SIFIVE_V0;
949 ssp->port.iotype = UPIO_MEM;
950 ssp->port.irq = irq;
951 ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;
952 ssp->port.ops = &sifive_serial_uops;
953 ssp->port.line = id;
954 ssp->port.mapbase = mem->start;
955 ssp->port.membase = base;
956 ssp->dev = &pdev->dev;
957 ssp->clk = clk;
958 ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;
959
960 r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);
961 if (r) {
962 dev_err(&pdev->dev, "could not register clock notifier: %d\n",
963 r);
964 goto probe_out1;
965 }
966
967 /* Set up clock divider */
968 ssp->port.uartclk = clk_get_rate(ssp->clk);
969 ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
970 __ssp_update_div(ssp);
971
972 platform_set_drvdata(pdev, ssp);
973
974 /* Enable transmits and set the watermark level to 1 */
975 __ssp_writel((1 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) |
976 SIFIVE_SERIAL_TXCTRL_TXEN_MASK,
977 SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
978
979 /* Enable receives and set the watermark level to 0 */
980 __ssp_writel((0 << SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT) |
981 SIFIVE_SERIAL_RXCTRL_RXEN_MASK,
982 SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
983
984 r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,
985 dev_name(&pdev->dev), ssp);
986 if (r) {
987 dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);
988 goto probe_out2;
989 }
990
991 __ssp_add_console_port(ssp);
992
993 r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);
994 if (r != 0) {
995 dev_err(&pdev->dev, "could not add uart: %d\n", r);
996 goto probe_out3;
997 }
998
999 return 0;
1000
1001probe_out3:
1002 __ssp_remove_console_port(ssp);
1003 free_irq(ssp->port.irq, ssp);
1004probe_out2:
1005 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1006probe_out1:
1007 return r;
1008}
1009
1010static void sifive_serial_remove(struct platform_device *dev)
1011{
1012 struct sifive_serial_port *ssp = platform_get_drvdata(dev);
1013
1014 __ssp_remove_console_port(ssp);
1015 uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);
1016 free_irq(ssp->port.irq, ssp);
1017 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1018}
1019
1020static int sifive_serial_suspend(struct device *dev)
1021{
1022 struct sifive_serial_port *ssp = dev_get_drvdata(dev);
1023
1024 return uart_suspend_port(&sifive_serial_uart_driver, &ssp->port);
1025}
1026
1027static int sifive_serial_resume(struct device *dev)
1028{
1029 struct sifive_serial_port *ssp = dev_get_drvdata(dev);
1030
1031 return uart_resume_port(&sifive_serial_uart_driver, &ssp->port);
1032}
1033
1034static DEFINE_SIMPLE_DEV_PM_OPS(sifive_uart_pm_ops, sifive_serial_suspend,
1035 sifive_serial_resume);
1036
1037static const struct of_device_id sifive_serial_of_match[] = {
1038 { .compatible = "sifive,fu540-c000-uart0" },
1039 { .compatible = "sifive,uart0" },
1040 {},
1041};
1042MODULE_DEVICE_TABLE(of, sifive_serial_of_match);
1043
1044static struct platform_driver sifive_serial_platform_driver = {
1045 .probe = sifive_serial_probe,
1046 .remove_new = sifive_serial_remove,
1047 .driver = {
1048 .name = SIFIVE_SERIAL_NAME,
1049 .pm = pm_sleep_ptr(&sifive_uart_pm_ops),
1050 .of_match_table = sifive_serial_of_match,
1051 },
1052};
1053
1054static int __init sifive_serial_init(void)
1055{
1056 int r;
1057
1058 r = uart_register_driver(&sifive_serial_uart_driver);
1059 if (r)
1060 goto init_out1;
1061
1062 r = platform_driver_register(&sifive_serial_platform_driver);
1063 if (r)
1064 goto init_out2;
1065
1066 return 0;
1067
1068init_out2:
1069 uart_unregister_driver(&sifive_serial_uart_driver);
1070init_out1:
1071 return r;
1072}
1073
1074static void __exit sifive_serial_exit(void)
1075{
1076 platform_driver_unregister(&sifive_serial_platform_driver);
1077 uart_unregister_driver(&sifive_serial_uart_driver);
1078}
1079
1080module_init(sifive_serial_init);
1081module_exit(sifive_serial_exit);
1082
1083MODULE_DESCRIPTION("SiFive UART serial driver");
1084MODULE_LICENSE("GPL");
1085MODULE_AUTHOR("Paul Walmsley <paul@pwsan.com>");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * SiFive UART driver
4 * Copyright (C) 2018 Paul Walmsley <paul@pwsan.com>
5 * Copyright (C) 2018-2019 SiFive
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Based partially on:
18 * - drivers/tty/serial/pxa.c
19 * - drivers/tty/serial/amba-pl011.c
20 * - drivers/tty/serial/uartlite.c
21 * - drivers/tty/serial/omap-serial.c
22 * - drivers/pwm/pwm-sifive.c
23 *
24 * See the following sources for further documentation:
25 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
26 * SiFive FE310-G000 v2p3
27 * - The tree/master/src/main/scala/devices/uart directory of
28 * https://github.com/sifive/sifive-blocks/
29 *
30 * The SiFive UART design is not 8250-compatible. The following common
31 * features are not supported:
32 * - Word lengths other than 8 bits
33 * - Break handling
34 * - Parity
35 * - Flow control
36 * - Modem signals (DSR, RI, etc.)
37 * On the other hand, the design is free from the baggage of the 8250
38 * programming model.
39 */
40
41#include <linux/clk.h>
42#include <linux/console.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/io.h>
46#include <linux/irq.h>
47#include <linux/module.h>
48#include <linux/of.h>
49#include <linux/of_irq.h>
50#include <linux/platform_device.h>
51#include <linux/serial_core.h>
52#include <linux/serial_reg.h>
53#include <linux/slab.h>
54#include <linux/tty.h>
55#include <linux/tty_flip.h>
56
57/*
58 * Register offsets
59 */
60
61/* TXDATA */
62#define SIFIVE_SERIAL_TXDATA_OFFS 0x0
63#define SIFIVE_SERIAL_TXDATA_FULL_SHIFT 31
64#define SIFIVE_SERIAL_TXDATA_FULL_MASK (1 << SIFIVE_SERIAL_TXDATA_FULL_SHIFT)
65#define SIFIVE_SERIAL_TXDATA_DATA_SHIFT 0
66#define SIFIVE_SERIAL_TXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_TXDATA_DATA_SHIFT)
67
68/* RXDATA */
69#define SIFIVE_SERIAL_RXDATA_OFFS 0x4
70#define SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT 31
71#define SIFIVE_SERIAL_RXDATA_EMPTY_MASK (1 << SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT)
72#define SIFIVE_SERIAL_RXDATA_DATA_SHIFT 0
73#define SIFIVE_SERIAL_RXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_RXDATA_DATA_SHIFT)
74
75/* TXCTRL */
76#define SIFIVE_SERIAL_TXCTRL_OFFS 0x8
77#define SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT 16
78#define SIFIVE_SERIAL_TXCTRL_TXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
79#define SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT 1
80#define SIFIVE_SERIAL_TXCTRL_NSTOP_MASK (1 << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT)
81#define SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT 0
82#define SIFIVE_SERIAL_TXCTRL_TXEN_MASK (1 << SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT)
83
84/* RXCTRL */
85#define SIFIVE_SERIAL_RXCTRL_OFFS 0xC
86#define SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT 16
87#define SIFIVE_SERIAL_RXCTRL_RXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT)
88#define SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT 0
89#define SIFIVE_SERIAL_RXCTRL_RXEN_MASK (1 << SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT)
90
91/* IE */
92#define SIFIVE_SERIAL_IE_OFFS 0x10
93#define SIFIVE_SERIAL_IE_RXWM_SHIFT 1
94#define SIFIVE_SERIAL_IE_RXWM_MASK (1 << SIFIVE_SERIAL_IE_RXWM_SHIFT)
95#define SIFIVE_SERIAL_IE_TXWM_SHIFT 0
96#define SIFIVE_SERIAL_IE_TXWM_MASK (1 << SIFIVE_SERIAL_IE_TXWM_SHIFT)
97
98/* IP */
99#define SIFIVE_SERIAL_IP_OFFS 0x14
100#define SIFIVE_SERIAL_IP_RXWM_SHIFT 1
101#define SIFIVE_SERIAL_IP_RXWM_MASK (1 << SIFIVE_SERIAL_IP_RXWM_SHIFT)
102#define SIFIVE_SERIAL_IP_TXWM_SHIFT 0
103#define SIFIVE_SERIAL_IP_TXWM_MASK (1 << SIFIVE_SERIAL_IP_TXWM_SHIFT)
104
105/* DIV */
106#define SIFIVE_SERIAL_DIV_OFFS 0x18
107#define SIFIVE_SERIAL_DIV_DIV_SHIFT 0
108#define SIFIVE_SERIAL_DIV_DIV_MASK (0xffff << SIFIVE_SERIAL_IP_DIV_SHIFT)
109
110/*
111 * Config macros
112 */
113
114/*
115 * SIFIVE_SERIAL_MAX_PORTS: maximum number of UARTs on a device that can
116 * host a serial console
117 */
118#define SIFIVE_SERIAL_MAX_PORTS 8
119
120/*
121 * SIFIVE_DEFAULT_BAUD_RATE: default baud rate that the driver should
122 * configure itself to use
123 */
124#define SIFIVE_DEFAULT_BAUD_RATE 115200
125
126/* SIFIVE_SERIAL_NAME: our driver's name that we pass to the operating system */
127#define SIFIVE_SERIAL_NAME "sifive-serial"
128
129/* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
130#define SIFIVE_TTY_PREFIX "ttySIF"
131
132/* SIFIVE_TX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
133#define SIFIVE_TX_FIFO_DEPTH 8
134
135/* SIFIVE_RX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */
136#define SIFIVE_RX_FIFO_DEPTH 8
137
138#if (SIFIVE_TX_FIFO_DEPTH != SIFIVE_RX_FIFO_DEPTH)
139#error Driver does not support configurations with different TX, RX FIFO sizes
140#endif
141
142/*
143 *
144 */
145
146/**
147 * struct sifive_serial_port - driver-specific data extension to struct uart_port
148 * @port: struct uart_port embedded in this struct
149 * @dev: struct device *
150 * @ier: shadowed copy of the interrupt enable register
151 * @clkin_rate: input clock to the UART IP block.
152 * @baud_rate: UART serial line rate (e.g., 115200 baud)
153 * @clk: reference to this device's clock
154 * @clk_notifier: clock rate change notifier for upstream clock changes
155 *
156 * Configuration data specific to this SiFive UART.
157 */
158struct sifive_serial_port {
159 struct uart_port port;
160 struct device *dev;
161 unsigned char ier;
162 unsigned long clkin_rate;
163 unsigned long baud_rate;
164 struct clk *clk;
165 struct notifier_block clk_notifier;
166};
167
168/*
169 * Structure container-of macros
170 */
171
172#define port_to_sifive_serial_port(p) (container_of((p), \
173 struct sifive_serial_port, \
174 port))
175
176#define notifier_to_sifive_serial_port(nb) (container_of((nb), \
177 struct sifive_serial_port, \
178 clk_notifier))
179
180/*
181 * Forward declarations
182 */
183static void sifive_serial_stop_tx(struct uart_port *port);
184
185/*
186 * Internal functions
187 */
188
189/**
190 * __ssp_early_writel() - write to a SiFive serial port register (early)
191 * @port: pointer to a struct uart_port record
192 * @offs: register address offset from the IP block base address
193 * @v: value to write to the register
194 *
195 * Given a pointer @port to a struct uart_port record, write the value
196 * @v to the IP block register address offset @offs. This function is
197 * intended for early console use.
198 *
199 * Context: Intended to be used only by the earlyconsole code.
200 */
201static void __ssp_early_writel(u32 v, u16 offs, struct uart_port *port)
202{
203 writel_relaxed(v, port->membase + offs);
204}
205
206/**
207 * __ssp_early_readl() - read from a SiFive serial port register (early)
208 * @port: pointer to a struct uart_port record
209 * @offs: register address offset from the IP block base address
210 *
211 * Given a pointer @port to a struct uart_port record, read the
212 * contents of the IP block register located at offset @offs from the
213 * IP block base and return it. This function is intended for early
214 * console use.
215 *
216 * Context: Intended to be called only by the earlyconsole code or by
217 * __ssp_readl() or __ssp_writel() (in this driver)
218 *
219 * Returns: the register value read from the UART.
220 */
221static u32 __ssp_early_readl(struct uart_port *port, u16 offs)
222{
223 return readl_relaxed(port->membase + offs);
224}
225
226/**
227 * __ssp_writel() - write to a SiFive serial port register
228 * @v: value to write to the register
229 * @offs: register address offset from the IP block base address
230 * @ssp: pointer to a struct sifive_serial_port record
231 *
232 * Write the value @v to the IP block register located at offset @offs from the
233 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
234 *
235 * Context: Any context.
236 */
237static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp)
238{
239 __ssp_early_writel(v, offs, &ssp->port);
240}
241
242/**
243 * __ssp_readl() - read from a SiFive serial port register
244 * @ssp: pointer to a struct sifive_serial_port record
245 * @offs: register address offset from the IP block base address
246 *
247 * Read the contents of the IP block register located at offset @offs from the
248 * IP block base, given a pointer @ssp to a struct sifive_serial_port record.
249 *
250 * Context: Any context.
251 *
252 * Returns: the value of the UART register
253 */
254static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs)
255{
256 return __ssp_early_readl(&ssp->port, offs);
257}
258
259/**
260 * sifive_serial_is_txfifo_full() - is the TXFIFO full?
261 * @ssp: pointer to a struct sifive_serial_port
262 *
263 * Read the transmit FIFO "full" bit, returning a non-zero value if the
264 * TX FIFO is full, or zero if space remains. Intended to be used to prevent
265 * writes to the TX FIFO when it's full.
266 *
267 * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
268 * is full, or 0 if space remains.
269 */
270static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp)
271{
272 return __ssp_readl(ssp, SIFIVE_SERIAL_TXDATA_OFFS) &
273 SIFIVE_SERIAL_TXDATA_FULL_MASK;
274}
275
276/**
277 * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
278 * @ssp: pointer to a struct sifive_serial_port
279 * @ch: character to transmit
280 *
281 * Enqueue a byte @ch onto the transmit FIFO, given a pointer @ssp to the
282 * struct sifive_serial_port * to transmit on. Caller should first check to
283 * ensure that the TXFIFO has space; see sifive_serial_is_txfifo_full().
284 *
285 * Context: Any context.
286 */
287static void __ssp_transmit_char(struct sifive_serial_port *ssp, int ch)
288{
289 __ssp_writel(ch, SIFIVE_SERIAL_TXDATA_OFFS, ssp);
290}
291
292/**
293 * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
294 * @ssp: pointer to a struct sifive_serial_port
295 *
296 * Transfer up to a TX FIFO size's worth of characters from the Linux serial
297 * transmit buffer to the SiFive UART TX FIFO.
298 *
299 * Context: Any context. Expects @ssp->port.lock to be held by caller.
300 */
301static void __ssp_transmit_chars(struct sifive_serial_port *ssp)
302{
303 struct circ_buf *xmit = &ssp->port.state->xmit;
304 int count;
305
306 if (ssp->port.x_char) {
307 __ssp_transmit_char(ssp, ssp->port.x_char);
308 ssp->port.icount.tx++;
309 ssp->port.x_char = 0;
310 return;
311 }
312 if (uart_circ_empty(xmit) || uart_tx_stopped(&ssp->port)) {
313 sifive_serial_stop_tx(&ssp->port);
314 return;
315 }
316 count = SIFIVE_TX_FIFO_DEPTH;
317 do {
318 __ssp_transmit_char(ssp, xmit->buf[xmit->tail]);
319 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
320 ssp->port.icount.tx++;
321 if (uart_circ_empty(xmit))
322 break;
323 } while (--count > 0);
324
325 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
326 uart_write_wakeup(&ssp->port);
327
328 if (uart_circ_empty(xmit))
329 sifive_serial_stop_tx(&ssp->port);
330}
331
332/**
333 * __ssp_enable_txwm() - enable transmit watermark interrupts
334 * @ssp: pointer to a struct sifive_serial_port
335 *
336 * Enable interrupt generation when the transmit FIFO watermark is reached
337 * on the SiFive UART referred to by @ssp.
338 */
339static void __ssp_enable_txwm(struct sifive_serial_port *ssp)
340{
341 if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)
342 return;
343
344 ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;
345 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
346}
347
348/**
349 * __ssp_enable_rxwm() - enable receive watermark interrupts
350 * @ssp: pointer to a struct sifive_serial_port
351 *
352 * Enable interrupt generation when the receive FIFO watermark is reached
353 * on the SiFive UART referred to by @ssp.
354 */
355static void __ssp_enable_rxwm(struct sifive_serial_port *ssp)
356{
357 if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)
358 return;
359
360 ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;
361 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
362}
363
364/**
365 * __ssp_disable_txwm() - disable transmit watermark interrupts
366 * @ssp: pointer to a struct sifive_serial_port
367 *
368 * Disable interrupt generation when the transmit FIFO watermark is reached
369 * on the UART referred to by @ssp.
370 */
371static void __ssp_disable_txwm(struct sifive_serial_port *ssp)
372{
373 if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))
374 return;
375
376 ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;
377 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
378}
379
380/**
381 * __ssp_disable_rxwm() - disable receive watermark interrupts
382 * @ssp: pointer to a struct sifive_serial_port
383 *
384 * Disable interrupt generation when the receive FIFO watermark is reached
385 * on the UART referred to by @ssp.
386 */
387static void __ssp_disable_rxwm(struct sifive_serial_port *ssp)
388{
389 if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))
390 return;
391
392 ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;
393 __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);
394}
395
396/**
397 * __ssp_receive_char() - receive a byte from the UART
398 * @ssp: pointer to a struct sifive_serial_port
399 * @is_empty: char pointer to return whether the RX FIFO is empty
400 *
401 * Try to read a byte from the SiFive UART RX FIFO, referenced by
402 * @ssp, and to return it. Also returns the RX FIFO empty bit in
403 * the char pointed to by @ch. The caller must pass the byte back to the
404 * Linux serial layer if needed.
405 *
406 * Returns: the byte read from the UART RX FIFO.
407 */
408static char __ssp_receive_char(struct sifive_serial_port *ssp, char *is_empty)
409{
410 u32 v;
411 u8 ch;
412
413 v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS);
414
415 if (!is_empty)
416 WARN_ON(1);
417 else
418 *is_empty = (v & SIFIVE_SERIAL_RXDATA_EMPTY_MASK) >>
419 SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT;
420
421 ch = (v & SIFIVE_SERIAL_RXDATA_DATA_MASK) >>
422 SIFIVE_SERIAL_RXDATA_DATA_SHIFT;
423
424 return ch;
425}
426
427/**
428 * __ssp_receive_chars() - receive multiple bytes from the UART
429 * @ssp: pointer to a struct sifive_serial_port
430 *
431 * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
432 * to by @ssp and pass them up to the Linux serial layer.
433 *
434 * Context: Expects ssp->port.lock to be held by caller.
435 */
436static void __ssp_receive_chars(struct sifive_serial_port *ssp)
437{
438 unsigned char ch;
439 char is_empty;
440 int c;
441
442 for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {
443 ch = __ssp_receive_char(ssp, &is_empty);
444 if (is_empty)
445 break;
446
447 ssp->port.icount.rx++;
448 uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);
449 }
450
451 tty_flip_buffer_push(&ssp->port.state->port);
452}
453
454/**
455 * __ssp_update_div() - calculate the divisor setting by the line rate
456 * @ssp: pointer to a struct sifive_serial_port
457 *
458 * Calculate the appropriate value of the clock divisor for the UART
459 * and target line rate referred to by @ssp and write it into the
460 * hardware.
461 */
462static void __ssp_update_div(struct sifive_serial_port *ssp)
463{
464 u16 div;
465
466 div = DIV_ROUND_UP(ssp->clkin_rate, ssp->baud_rate) - 1;
467
468 __ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp);
469}
470
471/**
472 * __ssp_update_baud_rate() - set the UART "baud rate"
473 * @ssp: pointer to a struct sifive_serial_port
474 * @rate: new target bit rate
475 *
476 * Calculate the UART divisor value for the target bit rate @rate for the
477 * SiFive UART described by @ssp and program it into the UART. There may
478 * be some error between the target bit rate and the actual bit rate implemented
479 * by the UART due to clock ratio granularity.
480 */
481static void __ssp_update_baud_rate(struct sifive_serial_port *ssp,
482 unsigned int rate)
483{
484 if (ssp->baud_rate == rate)
485 return;
486
487 ssp->baud_rate = rate;
488 __ssp_update_div(ssp);
489}
490
491/**
492 * __ssp_set_stop_bits() - set the number of stop bits
493 * @ssp: pointer to a struct sifive_serial_port
494 * @nstop: 1 or 2 (stop bits)
495 *
496 * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
497 */
498static void __ssp_set_stop_bits(struct sifive_serial_port *ssp, char nstop)
499{
500 u32 v;
501
502 if (nstop < 1 || nstop > 2) {
503 WARN_ON(1);
504 return;
505 }
506
507 v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS);
508 v &= ~SIFIVE_SERIAL_TXCTRL_NSTOP_MASK;
509 v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;
510 __ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
511}
512
513/**
514 * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
515 * @ssp: pointer to a struct sifive_serial_port
516 *
517 * Delay while the UART TX FIFO referred to by @ssp is marked as full.
518 *
519 * Context: Any context.
520 */
521static void __maybe_unused __ssp_wait_for_xmitr(struct sifive_serial_port *ssp)
522{
523 while (sifive_serial_is_txfifo_full(ssp))
524 udelay(1); /* XXX Could probably be more intelligent here */
525}
526
527/*
528 * Linux serial API functions
529 */
530
531static void sifive_serial_stop_tx(struct uart_port *port)
532{
533 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
534
535 __ssp_disable_txwm(ssp);
536}
537
538static void sifive_serial_stop_rx(struct uart_port *port)
539{
540 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
541
542 __ssp_disable_rxwm(ssp);
543}
544
545static void sifive_serial_start_tx(struct uart_port *port)
546{
547 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
548
549 __ssp_enable_txwm(ssp);
550}
551
552static irqreturn_t sifive_serial_irq(int irq, void *dev_id)
553{
554 struct sifive_serial_port *ssp = dev_id;
555 u32 ip;
556
557 spin_lock(&ssp->port.lock);
558
559 ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS);
560 if (!ip) {
561 spin_unlock(&ssp->port.lock);
562 return IRQ_NONE;
563 }
564
565 if (ip & SIFIVE_SERIAL_IP_RXWM_MASK)
566 __ssp_receive_chars(ssp);
567 if (ip & SIFIVE_SERIAL_IP_TXWM_MASK)
568 __ssp_transmit_chars(ssp);
569
570 spin_unlock(&ssp->port.lock);
571
572 return IRQ_HANDLED;
573}
574
575static unsigned int sifive_serial_tx_empty(struct uart_port *port)
576{
577 return TIOCSER_TEMT;
578}
579
580static unsigned int sifive_serial_get_mctrl(struct uart_port *port)
581{
582 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
583}
584
585static void sifive_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
586{
587 /* IP block does not support these signals */
588}
589
590static void sifive_serial_break_ctl(struct uart_port *port, int break_state)
591{
592 /* IP block does not support sending a break */
593}
594
595static int sifive_serial_startup(struct uart_port *port)
596{
597 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
598
599 __ssp_enable_rxwm(ssp);
600
601 return 0;
602}
603
604static void sifive_serial_shutdown(struct uart_port *port)
605{
606 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
607
608 __ssp_disable_rxwm(ssp);
609 __ssp_disable_txwm(ssp);
610}
611
612/**
613 * sifive_serial_clk_notifier() - clock post-rate-change notifier
614 * @nb: pointer to the struct notifier_block, from the notifier code
615 * @event: event mask from the notifier code
616 * @data: pointer to the struct clk_notifier_data from the notifier code
617 *
618 * On the V0 SoC, the UART IP block is derived from the CPU clock source
619 * after a synchronous divide-by-two divider, so any CPU clock rate change
620 * requires the UART baud rate to be updated. This presumably corrupts any
621 * serial word currently being transmitted or received. In order to avoid
622 * corrupting the output data stream, we drain the transmit queue before
623 * allowing the clock's rate to be changed.
624 */
625static int sifive_serial_clk_notifier(struct notifier_block *nb,
626 unsigned long event, void *data)
627{
628 struct clk_notifier_data *cnd = data;
629 struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb);
630
631 if (event == PRE_RATE_CHANGE) {
632 /*
633 * The TX watermark is always set to 1 by this driver, which
634 * means that the TX busy bit will lower when there are 0 bytes
635 * left in the TX queue -- in other words, when the TX FIFO is
636 * empty.
637 */
638 __ssp_wait_for_xmitr(ssp);
639 /*
640 * On the cycle the TX FIFO goes empty there is still a full
641 * UART frame left to be transmitted in the shift register.
642 * The UART provides no way for software to directly determine
643 * when that last frame has been transmitted, so we just sleep
644 * here instead. As we're not tracking the number of stop bits
645 * they're just worst cased here. The rest of the serial
646 * framing parameters aren't configurable by software.
647 */
648 udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));
649 }
650
651 if (event == POST_RATE_CHANGE && ssp->clkin_rate != cnd->new_rate) {
652 ssp->clkin_rate = cnd->new_rate;
653 __ssp_update_div(ssp);
654 }
655
656 return NOTIFY_OK;
657}
658
659static void sifive_serial_set_termios(struct uart_port *port,
660 struct ktermios *termios,
661 struct ktermios *old)
662{
663 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
664 unsigned long flags;
665 u32 v, old_v;
666 int rate;
667 char nstop;
668
669 if ((termios->c_cflag & CSIZE) != CS8)
670 dev_err_once(ssp->port.dev, "only 8-bit words supported\n");
671 if (termios->c_iflag & (INPCK | PARMRK))
672 dev_err_once(ssp->port.dev, "parity checking not supported\n");
673 if (termios->c_iflag & BRKINT)
674 dev_err_once(ssp->port.dev, "BREAK detection not supported\n");
675
676 /* Set number of stop bits */
677 nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;
678 __ssp_set_stop_bits(ssp, nstop);
679
680 /* Set line rate */
681 rate = uart_get_baud_rate(port, termios, old, 0, ssp->clkin_rate / 16);
682 __ssp_update_baud_rate(ssp, rate);
683
684 spin_lock_irqsave(&ssp->port.lock, flags);
685
686 /* Update the per-port timeout */
687 uart_update_timeout(port, termios->c_cflag, rate);
688
689 ssp->port.read_status_mask = 0;
690
691 /* Ignore all characters if CREAD is not set */
692 v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS);
693 old_v = v;
694 if ((termios->c_cflag & CREAD) == 0)
695 v &= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
696 else
697 v |= SIFIVE_SERIAL_RXCTRL_RXEN_MASK;
698 if (v != old_v)
699 __ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
700
701 spin_unlock_irqrestore(&ssp->port.lock, flags);
702}
703
704static void sifive_serial_release_port(struct uart_port *port)
705{
706}
707
708static int sifive_serial_request_port(struct uart_port *port)
709{
710 return 0;
711}
712
713static void sifive_serial_config_port(struct uart_port *port, int flags)
714{
715 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
716
717 ssp->port.type = PORT_SIFIVE_V0;
718}
719
720static int sifive_serial_verify_port(struct uart_port *port,
721 struct serial_struct *ser)
722{
723 return -EINVAL;
724}
725
726static const char *sifive_serial_type(struct uart_port *port)
727{
728 return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;
729}
730
731#ifdef CONFIG_CONSOLE_POLL
732static int sifive_serial_poll_get_char(struct uart_port *port)
733{
734 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
735 char is_empty, ch;
736
737 ch = __ssp_receive_char(ssp, &is_empty);
738 if (is_empty)
739 return NO_POLL_CHAR;
740
741 return ch;
742}
743
744static void sifive_serial_poll_put_char(struct uart_port *port,
745 unsigned char c)
746{
747 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
748
749 __ssp_wait_for_xmitr(ssp);
750 __ssp_transmit_char(ssp, c);
751}
752#endif /* CONFIG_CONSOLE_POLL */
753
754/*
755 * Early console support
756 */
757
758#ifdef CONFIG_SERIAL_EARLYCON
759static void early_sifive_serial_putc(struct uart_port *port, int c)
760{
761 while (__ssp_early_readl(port, SIFIVE_SERIAL_TXDATA_OFFS) &
762 SIFIVE_SERIAL_TXDATA_FULL_MASK)
763 cpu_relax();
764
765 __ssp_early_writel(c, SIFIVE_SERIAL_TXDATA_OFFS, port);
766}
767
768static void early_sifive_serial_write(struct console *con, const char *s,
769 unsigned int n)
770{
771 struct earlycon_device *dev = con->data;
772 struct uart_port *port = &dev->port;
773
774 uart_console_write(port, s, n, early_sifive_serial_putc);
775}
776
777static int __init early_sifive_serial_setup(struct earlycon_device *dev,
778 const char *options)
779{
780 struct uart_port *port = &dev->port;
781
782 if (!port->membase)
783 return -ENODEV;
784
785 dev->con->write = early_sifive_serial_write;
786
787 return 0;
788}
789
790OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
791OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
792 early_sifive_serial_setup);
793#endif /* CONFIG_SERIAL_EARLYCON */
794
795/*
796 * Linux console interface
797 */
798
799#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
800
801static struct sifive_serial_port *sifive_serial_console_ports[SIFIVE_SERIAL_MAX_PORTS];
802
803static void sifive_serial_console_putchar(struct uart_port *port, int ch)
804{
805 struct sifive_serial_port *ssp = port_to_sifive_serial_port(port);
806
807 __ssp_wait_for_xmitr(ssp);
808 __ssp_transmit_char(ssp, ch);
809}
810
811static void sifive_serial_console_write(struct console *co, const char *s,
812 unsigned int count)
813{
814 struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];
815 unsigned long flags;
816 unsigned int ier;
817 int locked = 1;
818
819 if (!ssp)
820 return;
821
822 local_irq_save(flags);
823 if (ssp->port.sysrq)
824 locked = 0;
825 else if (oops_in_progress)
826 locked = spin_trylock(&ssp->port.lock);
827 else
828 spin_lock(&ssp->port.lock);
829
830 ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS);
831 __ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp);
832
833 uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);
834
835 __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
836
837 if (locked)
838 spin_unlock(&ssp->port.lock);
839 local_irq_restore(flags);
840}
841
842static int __init sifive_serial_console_setup(struct console *co, char *options)
843{
844 struct sifive_serial_port *ssp;
845 int baud = SIFIVE_DEFAULT_BAUD_RATE;
846 int bits = 8;
847 int parity = 'n';
848 int flow = 'n';
849
850 if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)
851 return -ENODEV;
852
853 ssp = sifive_serial_console_ports[co->index];
854 if (!ssp)
855 return -ENODEV;
856
857 if (options)
858 uart_parse_options(options, &baud, &parity, &bits, &flow);
859
860 return uart_set_options(&ssp->port, co, baud, parity, bits, flow);
861}
862
863static struct uart_driver sifive_serial_uart_driver;
864
865static struct console sifive_serial_console = {
866 .name = SIFIVE_TTY_PREFIX,
867 .write = sifive_serial_console_write,
868 .device = uart_console_device,
869 .setup = sifive_serial_console_setup,
870 .flags = CON_PRINTBUFFER,
871 .index = -1,
872 .data = &sifive_serial_uart_driver,
873};
874
875static int __init sifive_console_init(void)
876{
877 register_console(&sifive_serial_console);
878 return 0;
879}
880
881console_initcall(sifive_console_init);
882
883static void __ssp_add_console_port(struct sifive_serial_port *ssp)
884{
885 sifive_serial_console_ports[ssp->port.line] = ssp;
886}
887
888static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
889{
890 sifive_serial_console_ports[ssp->port.line] = 0;
891}
892
893#define SIFIVE_SERIAL_CONSOLE (&sifive_serial_console)
894
895#else
896
897#define SIFIVE_SERIAL_CONSOLE NULL
898
899static void __ssp_add_console_port(struct sifive_serial_port *ssp)
900{}
901static void __ssp_remove_console_port(struct sifive_serial_port *ssp)
902{}
903
904#endif
905
906static const struct uart_ops sifive_serial_uops = {
907 .tx_empty = sifive_serial_tx_empty,
908 .set_mctrl = sifive_serial_set_mctrl,
909 .get_mctrl = sifive_serial_get_mctrl,
910 .stop_tx = sifive_serial_stop_tx,
911 .start_tx = sifive_serial_start_tx,
912 .stop_rx = sifive_serial_stop_rx,
913 .break_ctl = sifive_serial_break_ctl,
914 .startup = sifive_serial_startup,
915 .shutdown = sifive_serial_shutdown,
916 .set_termios = sifive_serial_set_termios,
917 .type = sifive_serial_type,
918 .release_port = sifive_serial_release_port,
919 .request_port = sifive_serial_request_port,
920 .config_port = sifive_serial_config_port,
921 .verify_port = sifive_serial_verify_port,
922#ifdef CONFIG_CONSOLE_POLL
923 .poll_get_char = sifive_serial_poll_get_char,
924 .poll_put_char = sifive_serial_poll_put_char,
925#endif
926};
927
928static struct uart_driver sifive_serial_uart_driver = {
929 .owner = THIS_MODULE,
930 .driver_name = SIFIVE_SERIAL_NAME,
931 .dev_name = SIFIVE_TTY_PREFIX,
932 .nr = SIFIVE_SERIAL_MAX_PORTS,
933 .cons = SIFIVE_SERIAL_CONSOLE,
934};
935
936static int sifive_serial_probe(struct platform_device *pdev)
937{
938 struct sifive_serial_port *ssp;
939 struct resource *mem;
940 struct clk *clk;
941 void __iomem *base;
942 int irq, id, r;
943
944 irq = platform_get_irq(pdev, 0);
945 if (irq < 0)
946 return -EPROBE_DEFER;
947
948 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
949 base = devm_ioremap_resource(&pdev->dev, mem);
950 if (IS_ERR(base)) {
951 dev_err(&pdev->dev, "could not acquire device memory\n");
952 return PTR_ERR(base);
953 }
954
955 clk = devm_clk_get(&pdev->dev, NULL);
956 if (IS_ERR(clk)) {
957 dev_err(&pdev->dev, "unable to find controller clock\n");
958 return PTR_ERR(clk);
959 }
960
961 id = of_alias_get_id(pdev->dev.of_node, "serial");
962 if (id < 0) {
963 dev_err(&pdev->dev, "missing aliases entry\n");
964 return id;
965 }
966
967#ifdef CONFIG_SERIAL_SIFIVE_CONSOLE
968 if (id > SIFIVE_SERIAL_MAX_PORTS) {
969 dev_err(&pdev->dev, "too many UARTs (%d)\n", id);
970 return -EINVAL;
971 }
972#endif
973
974 ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);
975 if (!ssp)
976 return -ENOMEM;
977
978 ssp->port.dev = &pdev->dev;
979 ssp->port.type = PORT_SIFIVE_V0;
980 ssp->port.iotype = UPIO_MEM;
981 ssp->port.irq = irq;
982 ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;
983 ssp->port.ops = &sifive_serial_uops;
984 ssp->port.line = id;
985 ssp->port.mapbase = mem->start;
986 ssp->port.membase = base;
987 ssp->dev = &pdev->dev;
988 ssp->clk = clk;
989 ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;
990
991 r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);
992 if (r) {
993 dev_err(&pdev->dev, "could not register clock notifier: %d\n",
994 r);
995 goto probe_out1;
996 }
997
998 /* Set up clock divider */
999 ssp->clkin_rate = clk_get_rate(ssp->clk);
1000 ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
1001 ssp->port.uartclk = ssp->baud_rate * 16;
1002 __ssp_update_div(ssp);
1003
1004 platform_set_drvdata(pdev, ssp);
1005
1006 /* Enable transmits and set the watermark level to 1 */
1007 __ssp_writel((1 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) |
1008 SIFIVE_SERIAL_TXCTRL_TXEN_MASK,
1009 SIFIVE_SERIAL_TXCTRL_OFFS, ssp);
1010
1011 /* Enable receives and set the watermark level to 0 */
1012 __ssp_writel((0 << SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT) |
1013 SIFIVE_SERIAL_RXCTRL_RXEN_MASK,
1014 SIFIVE_SERIAL_RXCTRL_OFFS, ssp);
1015
1016 r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,
1017 dev_name(&pdev->dev), ssp);
1018 if (r) {
1019 dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);
1020 goto probe_out2;
1021 }
1022
1023 __ssp_add_console_port(ssp);
1024
1025 r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);
1026 if (r != 0) {
1027 dev_err(&pdev->dev, "could not add uart: %d\n", r);
1028 goto probe_out3;
1029 }
1030
1031 return 0;
1032
1033probe_out3:
1034 __ssp_remove_console_port(ssp);
1035 free_irq(ssp->port.irq, ssp);
1036probe_out2:
1037 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1038probe_out1:
1039 return r;
1040}
1041
1042static int sifive_serial_remove(struct platform_device *dev)
1043{
1044 struct sifive_serial_port *ssp = platform_get_drvdata(dev);
1045
1046 __ssp_remove_console_port(ssp);
1047 uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);
1048 free_irq(ssp->port.irq, ssp);
1049 clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);
1050
1051 return 0;
1052}
1053
1054static const struct of_device_id sifive_serial_of_match[] = {
1055 { .compatible = "sifive,fu540-c000-uart0" },
1056 { .compatible = "sifive,uart0" },
1057 {},
1058};
1059MODULE_DEVICE_TABLE(of, sifive_serial_of_match);
1060
1061static struct platform_driver sifive_serial_platform_driver = {
1062 .probe = sifive_serial_probe,
1063 .remove = sifive_serial_remove,
1064 .driver = {
1065 .name = SIFIVE_SERIAL_NAME,
1066 .of_match_table = of_match_ptr(sifive_serial_of_match),
1067 },
1068};
1069
1070static int __init sifive_serial_init(void)
1071{
1072 int r;
1073
1074 r = uart_register_driver(&sifive_serial_uart_driver);
1075 if (r)
1076 goto init_out1;
1077
1078 r = platform_driver_register(&sifive_serial_platform_driver);
1079 if (r)
1080 goto init_out2;
1081
1082 return 0;
1083
1084init_out2:
1085 uart_unregister_driver(&sifive_serial_uart_driver);
1086init_out1:
1087 return r;
1088}
1089
1090static void __exit sifive_serial_exit(void)
1091{
1092 platform_driver_unregister(&sifive_serial_platform_driver);
1093 uart_unregister_driver(&sifive_serial_uart_driver);
1094}
1095
1096module_init(sifive_serial_init);
1097module_exit(sifive_serial_exit);
1098
1099MODULE_DESCRIPTION("SiFive UART serial driver");
1100MODULE_LICENSE("GPL");
1101MODULE_AUTHOR("Paul Walmsley <paul@pwsan.com>");