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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * NinjaSCSI-32Bi Cardbus, NinjaSCSI-32UDE PCI/CardBus SCSI driver
4 * Copyright (C) 2001, 2002, 2003
5 * YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>
6 * GOTO Masanori <gotom@debian.or.jp>, <gotom@debian.org>
7 *
8 * Revision History:
9 * 1.0: Initial Release.
10 * 1.1: Add /proc SDTR status.
11 * Remove obsolete error handler nsp32_reset.
12 * Some clean up.
13 * 1.2: PowerPC (big endian) support.
14 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/string.h>
20#include <linux/timer.h>
21#include <linux/ioport.h>
22#include <linux/major.h>
23#include <linux/blkdev.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/ctype.h>
28#include <linux/dma-mapping.h>
29
30#include <asm/dma.h>
31#include <asm/io.h>
32
33#include <scsi/scsi.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_device.h>
36#include <scsi/scsi_host.h>
37#include <scsi/scsi_ioctl.h>
38
39#include "nsp32.h"
40
41
42/***********************************************************************
43 * Module parameters
44 */
45static int trans_mode = 0; /* default: BIOS */
46module_param (trans_mode, int, 0);
47MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
48#define ASYNC_MODE 1
49#define ULTRA20M_MODE 2
50
51static bool auto_param = 0; /* default: ON */
52module_param (auto_param, bool, 0);
53MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
54
55static bool disc_priv = 1; /* default: OFF */
56module_param (disc_priv, bool, 0);
57MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
58
59MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>");
60MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module");
61MODULE_LICENSE("GPL");
62
63static const char *nsp32_release_version = "1.2";
64
65
66/****************************************************************************
67 * Supported hardware
68 */
69static struct pci_device_id nsp32_pci_table[] = {
70 {
71 .vendor = PCI_VENDOR_ID_IODATA,
72 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II,
73 .subvendor = PCI_ANY_ID,
74 .subdevice = PCI_ANY_ID,
75 .driver_data = MODEL_IODATA,
76 },
77 {
78 .vendor = PCI_VENDOR_ID_WORKBIT,
79 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME,
80 .subvendor = PCI_ANY_ID,
81 .subdevice = PCI_ANY_ID,
82 .driver_data = MODEL_KME,
83 },
84 {
85 .vendor = PCI_VENDOR_ID_WORKBIT,
86 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT,
87 .subvendor = PCI_ANY_ID,
88 .subdevice = PCI_ANY_ID,
89 .driver_data = MODEL_WORKBIT,
90 },
91 {
92 .vendor = PCI_VENDOR_ID_WORKBIT,
93 .device = PCI_DEVICE_ID_WORKBIT_STANDARD,
94 .subvendor = PCI_ANY_ID,
95 .subdevice = PCI_ANY_ID,
96 .driver_data = MODEL_PCI_WORKBIT,
97 },
98 {
99 .vendor = PCI_VENDOR_ID_WORKBIT,
100 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC,
101 .subvendor = PCI_ANY_ID,
102 .subdevice = PCI_ANY_ID,
103 .driver_data = MODEL_LOGITEC,
104 },
105 {
106 .vendor = PCI_VENDOR_ID_WORKBIT,
107 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC,
108 .subvendor = PCI_ANY_ID,
109 .subdevice = PCI_ANY_ID,
110 .driver_data = MODEL_PCI_LOGITEC,
111 },
112 {
113 .vendor = PCI_VENDOR_ID_WORKBIT,
114 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO,
115 .subvendor = PCI_ANY_ID,
116 .subdevice = PCI_ANY_ID,
117 .driver_data = MODEL_PCI_MELCO,
118 },
119 {
120 .vendor = PCI_VENDOR_ID_WORKBIT,
121 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II,
122 .subvendor = PCI_ANY_ID,
123 .subdevice = PCI_ANY_ID,
124 .driver_data = MODEL_PCI_MELCO,
125 },
126 {0,0,},
127};
128MODULE_DEVICE_TABLE(pci, nsp32_pci_table);
129
130static nsp32_hw_data nsp32_data_base; /* probe <-> detect glue */
131
132
133/*
134 * Period/AckWidth speed conversion table
135 *
136 * Note: This period/ackwidth speed table must be in descending order.
137 */
138static nsp32_sync_table nsp32_sync_table_40M[] = {
139 /* {PNo, AW, SP, EP, SREQ smpl} Speed(MB/s) Period AckWidth */
140 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */
141 {0x2, 0, 0x0d, 0x18, SMPL_40M}, /* 13.3 : 75ns, 25ns */
142 {0x3, 1, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
143 {0x4, 1, 0x1a, 0x1f, SMPL_20M}, /* 8.0 : 125ns, 50ns */
144 {0x5, 2, 0x20, 0x25, SMPL_20M}, /* 6.7 : 150ns, 75ns */
145 {0x6, 2, 0x26, 0x31, SMPL_20M}, /* 5.7 : 175ns, 75ns */
146 {0x7, 3, 0x32, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
147 {0x8, 3, 0x33, 0x38, SMPL_10M}, /* 4.4 : 225ns, 100ns */
148 {0x9, 3, 0x39, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
149};
150
151static nsp32_sync_table nsp32_sync_table_20M[] = {
152 {0x1, 0, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
153 {0x2, 0, 0x1a, 0x25, SMPL_20M}, /* 6.7 : 150ns, 50ns */
154 {0x3, 1, 0x26, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
155 {0x4, 1, 0x33, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
156 {0x5, 2, 0x3f, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 150ns */
157 {0x6, 2, 0x4c, 0x57, SMPL_10M}, /* 2.8 : 350ns, 150ns */
158 {0x7, 3, 0x58, 0x64, SMPL_10M}, /* 2.5 : 400ns, 200ns */
159 {0x8, 3, 0x65, 0x70, SMPL_10M}, /* 2.2 : 450ns, 200ns */
160 {0x9, 3, 0x71, 0x7d, SMPL_10M}, /* 2.0 : 500ns, 200ns */
161};
162
163static nsp32_sync_table nsp32_sync_table_pci[] = {
164 {0x1, 0, 0x0c, 0x0f, SMPL_40M}, /* 16.6 : 60ns, 30ns */
165 {0x2, 0, 0x10, 0x16, SMPL_40M}, /* 11.1 : 90ns, 30ns */
166 {0x3, 1, 0x17, 0x1e, SMPL_20M}, /* 8.3 : 120ns, 60ns */
167 {0x4, 1, 0x1f, 0x25, SMPL_20M}, /* 6.7 : 150ns, 60ns */
168 {0x5, 2, 0x26, 0x2d, SMPL_20M}, /* 5.6 : 180ns, 90ns */
169 {0x6, 2, 0x2e, 0x34, SMPL_10M}, /* 4.8 : 210ns, 90ns */
170 {0x7, 3, 0x35, 0x3c, SMPL_10M}, /* 4.2 : 240ns, 120ns */
171 {0x8, 3, 0x3d, 0x43, SMPL_10M}, /* 3.7 : 270ns, 120ns */
172 {0x9, 3, 0x44, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 120ns */
173};
174
175/*
176 * function declaration
177 */
178/* module entry point */
179static int nsp32_probe (struct pci_dev *, const struct pci_device_id *);
180static void nsp32_remove(struct pci_dev *);
181static int __init init_nsp32 (void);
182static void __exit exit_nsp32 (void);
183
184/* struct struct scsi_host_template */
185static int nsp32_show_info (struct seq_file *, struct Scsi_Host *);
186
187static int nsp32_detect (struct pci_dev *pdev);
188static int nsp32_queuecommand(struct Scsi_Host *, struct scsi_cmnd *);
189static const char *nsp32_info (struct Scsi_Host *);
190static int nsp32_release (struct Scsi_Host *);
191
192/* SCSI error handler */
193static int nsp32_eh_abort (struct scsi_cmnd *);
194static int nsp32_eh_host_reset(struct scsi_cmnd *);
195
196/* generate SCSI message */
197static void nsp32_build_identify(struct scsi_cmnd *);
198static void nsp32_build_nop (struct scsi_cmnd *);
199static void nsp32_build_reject (struct scsi_cmnd *);
200static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char,
201 unsigned char);
202
203/* SCSI message handler */
204static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short);
205static void nsp32_msgout_occur (struct scsi_cmnd *);
206static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long,
207 unsigned short);
208
209static int nsp32_setup_sg_table (struct scsi_cmnd *);
210static int nsp32_selection_autopara(struct scsi_cmnd *);
211static int nsp32_selection_autoscsi(struct scsi_cmnd *);
212static void nsp32_scsi_done (struct scsi_cmnd *);
213static int nsp32_arbitration (struct scsi_cmnd *, unsigned int);
214static int nsp32_reselection (struct scsi_cmnd *, unsigned char);
215static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int);
216static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short);
217
218/* SCSI SDTR */
219static void nsp32_analyze_sdtr (struct scsi_cmnd *);
220static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *,
221 unsigned char);
222static void nsp32_set_async (nsp32_hw_data *, nsp32_target *);
223static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *,
224 unsigned char *, unsigned char *);
225static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *,
226 int, unsigned char);
227
228/* SCSI bus status handler */
229static void nsp32_wait_req (nsp32_hw_data *, int);
230static void nsp32_wait_sack (nsp32_hw_data *, int);
231static void nsp32_sack_assert (nsp32_hw_data *);
232static void nsp32_sack_negate (nsp32_hw_data *);
233static void nsp32_do_bus_reset(nsp32_hw_data *);
234
235/* hardware interrupt handler */
236static irqreturn_t do_nsp32_isr(int, void *);
237
238/* initialize hardware */
239static int nsp32hw_init(nsp32_hw_data *);
240
241/* EEPROM handler */
242static int nsp32_getprom_param (nsp32_hw_data *);
243static int nsp32_getprom_at24 (nsp32_hw_data *);
244static int nsp32_getprom_c16 (nsp32_hw_data *);
245static void nsp32_prom_start (nsp32_hw_data *);
246static void nsp32_prom_stop (nsp32_hw_data *);
247static int nsp32_prom_read (nsp32_hw_data *, int);
248static int nsp32_prom_read_bit (nsp32_hw_data *);
249static void nsp32_prom_write_bit(nsp32_hw_data *, int);
250static void nsp32_prom_set (nsp32_hw_data *, int, int);
251static int nsp32_prom_get (nsp32_hw_data *, int);
252
253/* debug/warning/info message */
254static void nsp32_message (const char *, int, char *, char *, ...);
255#ifdef NSP32_DEBUG
256static void nsp32_dmessage(const char *, int, int, char *, ...);
257#endif
258
259/*
260 * max_sectors is currently limited up to 128.
261 */
262static const struct scsi_host_template nsp32_template = {
263 .proc_name = "nsp32",
264 .name = "Workbit NinjaSCSI-32Bi/UDE",
265 .show_info = nsp32_show_info,
266 .info = nsp32_info,
267 .queuecommand = nsp32_queuecommand,
268 .can_queue = 1,
269 .sg_tablesize = NSP32_SG_SIZE,
270 .max_sectors = 128,
271 .this_id = NSP32_HOST_SCSIID,
272 .dma_boundary = PAGE_SIZE - 1,
273 .eh_abort_handler = nsp32_eh_abort,
274 .eh_host_reset_handler = nsp32_eh_host_reset,
275/* .highmem_io = 1, */
276 .cmd_size = sizeof(struct nsp32_cmd_priv),
277};
278
279#include "nsp32_io.h"
280
281/***********************************************************************
282 * debug, error print
283 */
284#ifndef NSP32_DEBUG
285# define NSP32_DEBUG_MASK 0x000000
286# define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args)
287# define nsp32_dbg(mask, args...) /* */
288#else
289# define NSP32_DEBUG_MASK 0xffffff
290# define nsp32_msg(type, args...) \
291 nsp32_message (__func__, __LINE__, (type), args)
292# define nsp32_dbg(mask, args...) \
293 nsp32_dmessage(__func__, __LINE__, (mask), args)
294#endif
295
296#define NSP32_DEBUG_QUEUECOMMAND BIT(0)
297#define NSP32_DEBUG_REGISTER BIT(1)
298#define NSP32_DEBUG_AUTOSCSI BIT(2)
299#define NSP32_DEBUG_INTR BIT(3)
300#define NSP32_DEBUG_SGLIST BIT(4)
301#define NSP32_DEBUG_BUSFREE BIT(5)
302#define NSP32_DEBUG_CDB_CONTENTS BIT(6)
303#define NSP32_DEBUG_RESELECTION BIT(7)
304#define NSP32_DEBUG_MSGINOCCUR BIT(8)
305#define NSP32_DEBUG_EEPROM BIT(9)
306#define NSP32_DEBUG_MSGOUTOCCUR BIT(10)
307#define NSP32_DEBUG_BUSRESET BIT(11)
308#define NSP32_DEBUG_RESTART BIT(12)
309#define NSP32_DEBUG_SYNC BIT(13)
310#define NSP32_DEBUG_WAIT BIT(14)
311#define NSP32_DEBUG_TARGETFLAG BIT(15)
312#define NSP32_DEBUG_PROC BIT(16)
313#define NSP32_DEBUG_INIT BIT(17)
314#define NSP32_SPECIAL_PRINT_REGISTER BIT(20)
315
316#define NSP32_DEBUG_BUF_LEN 100
317
318__printf(4, 5)
319static void nsp32_message(const char *func, int line, char *type, char *fmt, ...)
320{
321 va_list args;
322 char buf[NSP32_DEBUG_BUF_LEN];
323
324 va_start(args, fmt);
325 vsnprintf(buf, sizeof(buf), fmt, args);
326 va_end(args);
327
328#ifndef NSP32_DEBUG
329 printk("%snsp32: %s\n", type, buf);
330#else
331 printk("%snsp32: %s (%d): %s\n", type, func, line, buf);
332#endif
333}
334
335#ifdef NSP32_DEBUG
336static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...)
337{
338 va_list args;
339 char buf[NSP32_DEBUG_BUF_LEN];
340
341 va_start(args, fmt);
342 vsnprintf(buf, sizeof(buf), fmt, args);
343 va_end(args);
344
345 if (mask & NSP32_DEBUG_MASK) {
346 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf);
347 }
348}
349#endif
350
351#ifdef NSP32_DEBUG
352# include "nsp32_debug.c"
353#else
354# define show_command(arg) /* */
355# define show_busphase(arg) /* */
356# define show_autophase(arg) /* */
357#endif
358
359/*
360 * IDENTIFY Message
361 */
362static void nsp32_build_identify(struct scsi_cmnd *SCpnt)
363{
364 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
365 int pos = data->msgout_len;
366 int mode = FALSE;
367
368 /* XXX: Auto DiscPriv detection is progressing... */
369 if (disc_priv == 0) {
370 /* mode = TRUE; */
371 }
372
373 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++;
374
375 data->msgout_len = pos;
376}
377
378/*
379 * SDTR Message Routine
380 */
381static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt,
382 unsigned char period,
383 unsigned char offset)
384{
385 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
386 int pos = data->msgout_len;
387
388 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++;
389 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++;
390 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++;
391 data->msgoutbuf[pos] = period; pos++;
392 data->msgoutbuf[pos] = offset; pos++;
393
394 data->msgout_len = pos;
395}
396
397/*
398 * No Operation Message
399 */
400static void nsp32_build_nop(struct scsi_cmnd *SCpnt)
401{
402 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
403 int pos = data->msgout_len;
404
405 if (pos != 0) {
406 nsp32_msg(KERN_WARNING,
407 "Some messages are already contained!");
408 return;
409 }
410
411 data->msgoutbuf[pos] = NOP; pos++;
412 data->msgout_len = pos;
413}
414
415/*
416 * Reject Message
417 */
418static void nsp32_build_reject(struct scsi_cmnd *SCpnt)
419{
420 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
421 int pos = data->msgout_len;
422
423 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++;
424 data->msgout_len = pos;
425}
426
427/*
428 * timer
429 */
430#if 0
431static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time)
432{
433 unsigned int base = SCpnt->host->io_port;
434
435 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
436
437 if (time & (~TIMER_CNT_MASK)) {
438 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
439 }
440
441 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK);
442}
443#endif
444
445
446/*
447 * set SCSI command and other parameter to asic, and start selection phase
448 */
449static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt)
450{
451 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
452 unsigned int base = SCpnt->device->host->io_port;
453 unsigned int host_id = SCpnt->device->host->this_id;
454 unsigned char target = scmd_id(SCpnt);
455 nsp32_autoparam *param = data->autoparam;
456 unsigned char phase;
457 int i, ret;
458 unsigned int msgout;
459 u16_le s;
460
461 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
462
463 /*
464 * check bus free
465 */
466 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
467 if (phase != BUSMON_BUS_FREE) {
468 nsp32_msg(KERN_WARNING, "bus busy");
469 show_busphase(phase & BUSMON_PHASE_MASK);
470 SCpnt->result = DID_BUS_BUSY << 16;
471 return FALSE;
472 }
473
474 /*
475 * message out
476 *
477 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
478 * over 3 messages needs another routine.
479 */
480 if (data->msgout_len == 0) {
481 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
482 SCpnt->result = DID_ERROR << 16;
483 return FALSE;
484 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
485 msgout = 0;
486 for (i = 0; i < data->msgout_len; i++) {
487 /*
488 * the sending order of the message is:
489 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
490 * MCNT 2: MSG#1 -> MSG#2
491 * MCNT 1: MSG#2
492 */
493 msgout >>= 8;
494 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
495 }
496 msgout |= MV_VALID; /* MV valid */
497 msgout |= (unsigned int)data->msgout_len; /* len */
498 } else {
499 /* data->msgout_len > 3 */
500 msgout = 0;
501 }
502
503 // nsp_dbg(NSP32_DEBUG_AUTOSCSI, "sel time out=0x%x\n",
504 // nsp32_read2(base, SEL_TIME_OUT));
505 // nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
506
507 /*
508 * setup asic parameter
509 */
510 memset(param, 0, sizeof(nsp32_autoparam));
511
512 /* cdb */
513 for (i = 0; i < SCpnt->cmd_len; i++) {
514 param->cdb[4 * i] = SCpnt->cmnd[i];
515 }
516
517 /* outgoing messages */
518 param->msgout = cpu_to_le32(msgout);
519
520 /* syncreg, ackwidth, target id, SREQ sampling rate */
521 param->syncreg = data->cur_target->syncreg;
522 param->ackwidth = data->cur_target->ackwidth;
523 param->target_id = BIT(host_id) | BIT(target);
524 param->sample_reg = data->cur_target->sample_reg;
525
526 // nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "sample rate=0x%x\n", data->cur_target->sample_reg);
527
528 /* command control */
529 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER |
530 AUTOSCSI_START |
531 AUTO_MSGIN_00_OR_04 |
532 AUTO_MSGIN_02 |
533 AUTO_ATN );
534
535
536 /* transfer control */
537 s = 0;
538 switch (data->trans_method) {
539 case NSP32_TRANSFER_BUSMASTER:
540 s |= BM_START;
541 break;
542 case NSP32_TRANSFER_MMIO:
543 s |= CB_MMIO_MODE;
544 break;
545 case NSP32_TRANSFER_PIO:
546 s |= CB_IO_MODE;
547 break;
548 default:
549 nsp32_msg(KERN_ERR, "unknown trans_method");
550 break;
551 }
552 /*
553 * OR-ed BLIEND_MODE, FIFO intr is decreased, instead of PCI bus waits.
554 * For bus master transfer, it's taken off.
555 */
556 s |= (TRANSFER_GO | ALL_COUNTER_CLR);
557 param->transfer_control = cpu_to_le16(s);
558
559 /* sg table addr */
560 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr);
561
562 /*
563 * transfer parameter to ASIC
564 */
565 nsp32_write4(base, SGT_ADR, data->auto_paddr);
566 nsp32_write2(base, COMMAND_CONTROL,
567 CLEAR_CDB_FIFO_POINTER | AUTO_PARAMETER );
568
569 /*
570 * Check arbitration
571 */
572 ret = nsp32_arbitration(SCpnt, base);
573
574 return ret;
575}
576
577
578/*
579 * Selection with AUTO SCSI (without AUTO PARAMETER)
580 */
581static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt)
582{
583 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
584 unsigned int base = SCpnt->device->host->io_port;
585 unsigned int host_id = SCpnt->device->host->this_id;
586 unsigned char target = scmd_id(SCpnt);
587 unsigned char phase;
588 int status;
589 unsigned short command = 0;
590 unsigned int msgout = 0;
591 int i;
592
593 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
594
595 /*
596 * IRQ disable
597 */
598 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
599
600 /*
601 * check bus line
602 */
603 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
604 if ((phase & BUSMON_BSY) || (phase & BUSMON_SEL)) {
605 nsp32_msg(KERN_WARNING, "bus busy");
606 SCpnt->result = DID_BUS_BUSY << 16;
607 status = 1;
608 goto out;
609 }
610
611 /*
612 * clear execph
613 */
614 nsp32_read2(base, SCSI_EXECUTE_PHASE);
615
616 /*
617 * clear FIFO counter to set CDBs
618 */
619 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER);
620
621 /*
622 * set CDB0 - CDB15
623 */
624 for (i = 0; i < SCpnt->cmd_len; i++) {
625 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]);
626 }
627 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]);
628
629 /*
630 * set SCSIOUT LATCH(initiator)/TARGET(target) (OR-ed) ID
631 */
632 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID,
633 BIT(host_id) | BIT(target));
634
635 /*
636 * set SCSI MSGOUT REG
637 *
638 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
639 * over 3 messages needs another routine.
640 */
641 if (data->msgout_len == 0) {
642 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
643 SCpnt->result = DID_ERROR << 16;
644 status = 1;
645 goto out;
646 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
647 msgout = 0;
648 for (i = 0; i < data->msgout_len; i++) {
649 /*
650 * the sending order of the message is:
651 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
652 * MCNT 2: MSG#1 -> MSG#2
653 * MCNT 1: MSG#2
654 */
655 msgout >>= 8;
656 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
657 }
658 msgout |= MV_VALID; /* MV valid */
659 msgout |= (unsigned int)data->msgout_len; /* len */
660 nsp32_write4(base, SCSI_MSG_OUT, msgout);
661 } else {
662 /* data->msgout_len > 3 */
663 nsp32_write4(base, SCSI_MSG_OUT, 0);
664 }
665
666 /*
667 * set selection timeout(= 250ms)
668 */
669 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
670
671 /*
672 * set SREQ hazard killer sampling rate
673 *
674 * TODO: sample_rate (BASE+0F) is 0 when internal clock = 40MHz.
675 * check other internal clock!
676 */
677 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
678
679 /*
680 * clear Arbit
681 */
682 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
683
684 /*
685 * set SYNCREG
686 * Don't set BM_START_ADR before setting this register.
687 */
688 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
689
690 /*
691 * set ACKWIDTH
692 */
693 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
694
695 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
696 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x",
697 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH),
698 nsp32_read4(base, SGT_ADR),
699 nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID));
700 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x",
701 data->msgout_len, msgout);
702
703 /*
704 * set SGT ADDR (physical address)
705 */
706 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
707
708 /*
709 * set TRANSFER CONTROL REG
710 */
711 command = 0;
712 command |= (TRANSFER_GO | ALL_COUNTER_CLR);
713 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
714 if (scsi_bufflen(SCpnt) > 0) {
715 command |= BM_START;
716 }
717 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
718 command |= CB_MMIO_MODE;
719 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
720 command |= CB_IO_MODE;
721 }
722 nsp32_write2(base, TRANSFER_CONTROL, command);
723
724 /*
725 * start AUTO SCSI, kick off arbitration
726 */
727 command = (CLEAR_CDB_FIFO_POINTER |
728 AUTOSCSI_START |
729 AUTO_MSGIN_00_OR_04 |
730 AUTO_MSGIN_02 |
731 AUTO_ATN);
732 nsp32_write2(base, COMMAND_CONTROL, command);
733
734 /*
735 * Check arbitration
736 */
737 status = nsp32_arbitration(SCpnt, base);
738
739 out:
740 /*
741 * IRQ enable
742 */
743 nsp32_write2(base, IRQ_CONTROL, 0);
744
745 return status;
746}
747
748
749/*
750 * Arbitration Status Check
751 *
752 * Note: Arbitration counter is waited during ARBIT_GO is not lifting.
753 * Using udelay(1) consumes CPU time and system time, but
754 * arbitration delay time is defined minimal 2.4us in SCSI
755 * specification, thus udelay works as coarse grained wait timer.
756 */
757static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base)
758{
759 unsigned char arbit;
760 int status = TRUE;
761 int time = 0;
762
763 do {
764 arbit = nsp32_read1(base, ARBIT_STATUS);
765 time++;
766 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 &&
767 (time <= ARBIT_TIMEOUT_TIME));
768
769 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
770 "arbit: 0x%x, delay time: %d", arbit, time);
771
772 if (arbit & ARBIT_WIN) {
773 /* Arbitration succeeded */
774 SCpnt->result = DID_OK << 16;
775 nsp32_index_write1(base, EXT_PORT, LED_ON); /* PCI LED on */
776 } else if (arbit & ARBIT_FAIL) {
777 /* Arbitration failed */
778 SCpnt->result = DID_BUS_BUSY << 16;
779 status = FALSE;
780 } else {
781 /*
782 * unknown error or ARBIT_GO timeout,
783 * something lock up! guess no connection.
784 */
785 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout");
786 SCpnt->result = DID_NO_CONNECT << 16;
787 status = FALSE;
788 }
789
790 /*
791 * clear Arbit
792 */
793 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
794
795 return status;
796}
797
798
799/*
800 * reselection
801 *
802 * Note: This reselection routine is called from msgin_occur,
803 * reselection target id&lun must be already set.
804 * SCSI-2 says IDENTIFY implies RESTORE_POINTER operation.
805 */
806static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun)
807{
808 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
809 unsigned int host_id = SCpnt->device->host->this_id;
810 unsigned int base = SCpnt->device->host->io_port;
811 unsigned char tmpid, newid;
812
813 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter");
814
815 /*
816 * calculate reselected SCSI ID
817 */
818 tmpid = nsp32_read1(base, RESELECT_ID);
819 tmpid &= (~BIT(host_id));
820 newid = 0;
821 while (tmpid) {
822 if (tmpid & 1) {
823 break;
824 }
825 tmpid >>= 1;
826 newid++;
827 }
828
829 /*
830 * If reselected New ID:LUN is not existed
831 * or current nexus is not existed, unexpected
832 * reselection is occurred. Send reject message.
833 */
834 if (newid >= ARRAY_SIZE(data->lunt) ||
835 newlun >= ARRAY_SIZE(data->lunt[0])) {
836 nsp32_msg(KERN_WARNING, "unknown id/lun");
837 return FALSE;
838 } else if(data->lunt[newid][newlun].SCpnt == NULL) {
839 nsp32_msg(KERN_WARNING, "no SCSI command is processing");
840 return FALSE;
841 }
842
843 data->cur_id = newid;
844 data->cur_lun = newlun;
845 data->cur_target = &(data->target[newid]);
846 data->cur_lunt = &(data->lunt[newid][newlun]);
847
848 /* reset SACK/SavedACK counter (or ALL clear?) */
849 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
850
851 return TRUE;
852}
853
854
855/*
856 * nsp32_setup_sg_table - build scatter gather list for transfer data
857 * with bus master.
858 *
859 * Note: NinjaSCSI-32Bi/UDE bus master can not transfer over 64KB at a time.
860 */
861static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt)
862{
863 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
864 struct scatterlist *sg;
865 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
866 int num, i;
867 u32_le l;
868
869 if (sgt == NULL) {
870 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null");
871 return FALSE;
872 }
873
874 num = scsi_dma_map(SCpnt);
875 if (!num)
876 return TRUE;
877 else if (num < 0)
878 return FALSE;
879 else {
880 scsi_for_each_sg(SCpnt, sg, num, i) {
881 /*
882 * Build nsp32_sglist, substitute sg dma addresses.
883 */
884 sgt[i].addr = cpu_to_le32(sg_dma_address(sg));
885 sgt[i].len = cpu_to_le32(sg_dma_len(sg));
886
887 if (le32_to_cpu(sgt[i].len) > 0x10000) {
888 nsp32_msg(KERN_ERR,
889 "can't transfer over 64KB at a time, "
890 "size=0x%x", le32_to_cpu(sgt[i].len));
891 return FALSE;
892 }
893 nsp32_dbg(NSP32_DEBUG_SGLIST,
894 "num 0x%x : addr 0x%lx len 0x%lx",
895 i,
896 le32_to_cpu(sgt[i].addr),
897 le32_to_cpu(sgt[i].len ));
898 }
899
900 /* set end mark */
901 l = le32_to_cpu(sgt[num-1].len);
902 sgt[num-1].len = cpu_to_le32(l | SGTEND);
903 }
904
905 return TRUE;
906}
907
908static int nsp32_queuecommand_lck(struct scsi_cmnd *SCpnt)
909{
910 void (*done)(struct scsi_cmnd *) = scsi_done;
911 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
912 nsp32_target *target;
913 nsp32_lunt *cur_lunt;
914 int ret;
915
916 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
917 "enter. target: 0x%x LUN: 0x%llx cmnd: 0x%x cmndlen: 0x%x "
918 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x",
919 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0],
920 SCpnt->cmd_len, scsi_sg_count(SCpnt), scsi_sglist(SCpnt),
921 scsi_bufflen(SCpnt));
922
923 if (data->CurrentSC != NULL) {
924 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request");
925 data->CurrentSC = NULL;
926 SCpnt->result = DID_NO_CONNECT << 16;
927 done(SCpnt);
928 return 0;
929 }
930
931 /* check target ID is not same as this initiator ID */
932 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) {
933 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "target==host???");
934 SCpnt->result = DID_BAD_TARGET << 16;
935 done(SCpnt);
936 return 0;
937 }
938
939 /* check target LUN is allowable value */
940 if (SCpnt->device->lun >= MAX_LUN) {
941 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun");
942 SCpnt->result = DID_BAD_TARGET << 16;
943 done(SCpnt);
944 return 0;
945 }
946
947 show_command(SCpnt);
948
949 data->CurrentSC = SCpnt;
950 nsp32_priv(SCpnt)->status = SAM_STAT_CHECK_CONDITION;
951 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt));
952
953 /* initialize data */
954 data->msgout_len = 0;
955 data->msgin_len = 0;
956 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]);
957 cur_lunt->SCpnt = SCpnt;
958 cur_lunt->save_datp = 0;
959 cur_lunt->msgin03 = FALSE;
960 data->cur_lunt = cur_lunt;
961 data->cur_id = SCpnt->device->id;
962 data->cur_lun = SCpnt->device->lun;
963
964 ret = nsp32_setup_sg_table(SCpnt);
965 if (ret == FALSE) {
966 nsp32_msg(KERN_ERR, "SGT fail");
967 SCpnt->result = DID_ERROR << 16;
968 nsp32_scsi_done(SCpnt);
969 return 0;
970 }
971
972 /* Build IDENTIFY */
973 nsp32_build_identify(SCpnt);
974
975 /*
976 * If target is the first time to transfer after the reset
977 * (target don't have SDTR_DONE and SDTR_INITIATOR), sync
978 * message SDTR is needed to do synchronous transfer.
979 */
980 target = &data->target[scmd_id(SCpnt)];
981 data->cur_target = target;
982
983 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) {
984 unsigned char period, offset;
985
986 if (trans_mode != ASYNC_MODE) {
987 nsp32_set_max_sync(data, target, &period, &offset);
988 nsp32_build_sdtr(SCpnt, period, offset);
989 target->sync_flag |= SDTR_INITIATOR;
990 } else {
991 nsp32_set_async(data, target);
992 target->sync_flag |= SDTR_DONE;
993 }
994
995 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
996 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n",
997 target->limit_entry, period, offset);
998 } else if (target->sync_flag & SDTR_INITIATOR) {
999 /*
1000 * It was negotiating SDTR with target, sending from the
1001 * initiator, but there are no chance to remove this flag.
1002 * Set async because we don't get proper negotiation.
1003 */
1004 nsp32_set_async(data, target);
1005 target->sync_flag &= ~SDTR_INITIATOR;
1006 target->sync_flag |= SDTR_DONE;
1007
1008 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1009 "SDTR_INITIATOR: fall back to async");
1010 } else if (target->sync_flag & SDTR_TARGET) {
1011 /*
1012 * It was negotiating SDTR with target, sending from target,
1013 * but there are no chance to remove this flag. Set async
1014 * because we don't get proper negotiation.
1015 */
1016 nsp32_set_async(data, target);
1017 target->sync_flag &= ~SDTR_TARGET;
1018 target->sync_flag |= SDTR_DONE;
1019
1020 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1021 "Unknown SDTR from target is reached, fall back to async.");
1022 }
1023
1024 nsp32_dbg(NSP32_DEBUG_TARGETFLAG,
1025 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x",
1026 SCpnt->device->id, target->sync_flag, target->syncreg,
1027 target->ackwidth);
1028
1029 /* Selection */
1030 if (auto_param == 0) {
1031 ret = nsp32_selection_autopara(SCpnt);
1032 } else {
1033 ret = nsp32_selection_autoscsi(SCpnt);
1034 }
1035
1036 if (ret != TRUE) {
1037 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail");
1038 nsp32_scsi_done(SCpnt);
1039 }
1040
1041 return 0;
1042}
1043
1044static DEF_SCSI_QCMD(nsp32_queuecommand)
1045
1046/* initialize asic */
1047static int nsp32hw_init(nsp32_hw_data *data)
1048{
1049 unsigned int base = data->BaseAddress;
1050 unsigned short irq_stat;
1051 unsigned long lc_reg;
1052 unsigned char power;
1053
1054 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE);
1055 if ((lc_reg & 0xff00) == 0) {
1056 lc_reg |= (0x20 << 8);
1057 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff);
1058 }
1059
1060 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1061 nsp32_write2(base, TRANSFER_CONTROL, 0);
1062 nsp32_write4(base, BM_CNT, 0);
1063 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1064
1065 do {
1066 irq_stat = nsp32_read2(base, IRQ_STATUS);
1067 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat);
1068 } while (irq_stat & IRQSTATUS_ANY_IRQ);
1069
1070 /*
1071 * Fill FIFO_FULL_SHLD, FIFO_EMPTY_SHLD. Below parameter is
1072 * designated by specification.
1073 */
1074 if ((data->trans_method & NSP32_TRANSFER_PIO) ||
1075 (data->trans_method & NSP32_TRANSFER_MMIO)) {
1076 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40);
1077 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40);
1078 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1079 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10);
1080 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60);
1081 } else {
1082 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode");
1083 }
1084
1085 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x",
1086 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT),
1087 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT));
1088
1089 nsp32_index_write1(base, CLOCK_DIV, data->clock);
1090 nsp32_index_write1(base, BM_CYCLE,
1091 MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD);
1092 nsp32_write1(base, PARITY_CONTROL, 0); /* parity check is disable */
1093
1094 /*
1095 * initialize MISC_WRRD register
1096 *
1097 * Note: Designated parameters is obeyed as following:
1098 * MISC_SCSI_DIRECTION_DETECTOR_SELECT: It must be set.
1099 * MISC_MASTER_TERMINATION_SELECT: It must be set.
1100 * MISC_BMREQ_NEGATE_TIMING_SEL: It should be set.
1101 * MISC_AUTOSEL_TIMING_SEL: It should be set.
1102 * MISC_BMSTOP_CHANGE2_NONDATA_PHASE: It should be set.
1103 * MISC_DELAYED_BMSTART: It's selected for safety.
1104 *
1105 * Note: If MISC_BMSTOP_CHANGE2_NONDATA_PHASE is set, then
1106 * we have to set TRANSFERCONTROL_BM_START as 0 and set
1107 * appropriate value before restarting bus master transfer.
1108 */
1109 nsp32_index_write2(base, MISC_WR,
1110 (SCSI_DIRECTION_DETECTOR_SELECT |
1111 DELAYED_BMSTART |
1112 MASTER_TERMINATION_SELECT |
1113 BMREQ_NEGATE_TIMING_SEL |
1114 AUTOSEL_TIMING_SEL |
1115 BMSTOP_CHANGE2_NONDATA_PHASE));
1116
1117 nsp32_index_write1(base, TERM_PWR_CONTROL, 0);
1118 power = nsp32_index_read1(base, TERM_PWR_CONTROL);
1119 if (!(power & SENSE)) {
1120 nsp32_msg(KERN_INFO, "term power on");
1121 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR);
1122 }
1123
1124 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1125 nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */
1126
1127 nsp32_write1(base, SYNC_REG, 0);
1128 nsp32_write1(base, ACK_WIDTH, 0);
1129 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
1130
1131 /*
1132 * enable to select designated IRQ (except for
1133 * IRQSELECT_SERR, IRQSELECT_PERR, IRQSELECT_BMCNTERR)
1134 */
1135 nsp32_index_write2(base, IRQ_SELECT,
1136 IRQSELECT_TIMER_IRQ |
1137 IRQSELECT_SCSIRESET_IRQ |
1138 IRQSELECT_FIFO_SHLD_IRQ |
1139 IRQSELECT_RESELECT_IRQ |
1140 IRQSELECT_PHASE_CHANGE_IRQ |
1141 IRQSELECT_AUTO_SCSI_SEQ_IRQ |
1142 // IRQSELECT_BMCNTERR_IRQ |
1143 IRQSELECT_TARGET_ABORT_IRQ |
1144 IRQSELECT_MASTER_ABORT_IRQ );
1145 nsp32_write2(base, IRQ_CONTROL, 0);
1146
1147 /* PCI LED off */
1148 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF);
1149 nsp32_index_write1(base, EXT_PORT, LED_OFF);
1150
1151 return TRUE;
1152}
1153
1154
1155/* interrupt routine */
1156static irqreturn_t do_nsp32_isr(int irq, void *dev_id)
1157{
1158 nsp32_hw_data *data = dev_id;
1159 unsigned int base = data->BaseAddress;
1160 struct scsi_cmnd *SCpnt = data->CurrentSC;
1161 unsigned short auto_stat, irq_stat, trans_stat;
1162 unsigned char busmon, busphase;
1163 unsigned long flags;
1164 int ret;
1165 int handled = 0;
1166 struct Scsi_Host *host = data->Host;
1167
1168 spin_lock_irqsave(host->host_lock, flags);
1169
1170 /*
1171 * IRQ check, then enable IRQ mask
1172 */
1173 irq_stat = nsp32_read2(base, IRQ_STATUS);
1174 nsp32_dbg(NSP32_DEBUG_INTR,
1175 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat);
1176 /* is this interrupt comes from Ninja asic? */
1177 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) {
1178 nsp32_dbg(NSP32_DEBUG_INTR,
1179 "shared interrupt: irq other 0x%x", irq_stat);
1180 goto out2;
1181 }
1182 handled = 1;
1183 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1184
1185 busmon = nsp32_read1(base, SCSI_BUS_MONITOR);
1186 busphase = busmon & BUSMON_PHASE_MASK;
1187
1188 trans_stat = nsp32_read2(base, TRANSFER_STATUS);
1189 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) {
1190 nsp32_msg(KERN_INFO, "card disconnect");
1191 if (data->CurrentSC != NULL) {
1192 nsp32_msg(KERN_INFO, "clean up current SCSI command");
1193 SCpnt->result = DID_BAD_TARGET << 16;
1194 nsp32_scsi_done(SCpnt);
1195 }
1196 goto out;
1197 }
1198
1199 /* Timer IRQ */
1200 if (irq_stat & IRQSTATUS_TIMER_IRQ) {
1201 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1202 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1203 goto out;
1204 }
1205
1206 /* SCSI reset */
1207 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) {
1208 nsp32_msg(KERN_INFO, "detected someone do bus reset");
1209 nsp32_do_bus_reset(data);
1210 if (SCpnt != NULL) {
1211 SCpnt->result = DID_RESET << 16;
1212 nsp32_scsi_done(SCpnt);
1213 }
1214 goto out;
1215 }
1216
1217 if (SCpnt == NULL) {
1218 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened");
1219 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x",
1220 irq_stat, trans_stat);
1221 goto out;
1222 }
1223
1224 /*
1225 * AutoSCSI Interrupt.
1226 * Note: This interrupt is occurred when AutoSCSI is finished. Then
1227 * check SCSIEXECUTEPHASE, and do appropriate action. Each phases are
1228 * recorded when AutoSCSI sequencer has been processed.
1229 */
1230 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) {
1231 /* getting SCSI executed phase */
1232 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE);
1233 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1234
1235 /* Selection Timeout, go busfree phase. */
1236 if (auto_stat & SELECTION_TIMEOUT) {
1237 nsp32_dbg(NSP32_DEBUG_INTR,
1238 "selection timeout occurred");
1239
1240 SCpnt->result = DID_TIME_OUT << 16;
1241 nsp32_scsi_done(SCpnt);
1242 goto out;
1243 }
1244
1245 if (auto_stat & MSGOUT_PHASE) {
1246 /*
1247 * MsgOut phase was processed.
1248 * If MSG_IN_OCCUER is not set, then MsgOut phase is
1249 * completed. Thus, msgout_len must reset. Otherwise,
1250 * nothing to do here. If MSG_OUT_OCCUER is occurred,
1251 * then we will encounter the condition and check.
1252 */
1253 if (!(auto_stat & MSG_IN_OCCUER) &&
1254 (data->msgout_len <= 3)) {
1255 /*
1256 * !MSG_IN_OCCUER && msgout_len <=3
1257 * ---> AutoSCSI with MSGOUTreg is processed.
1258 */
1259 data->msgout_len = 0;
1260 }
1261
1262 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1263 }
1264
1265 if ((auto_stat & DATA_IN_PHASE) &&
1266 (scsi_get_resid(SCpnt) > 0) &&
1267 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) {
1268 printk( "auto+fifo\n");
1269 //nsp32_pio_read(SCpnt);
1270 }
1271
1272 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) {
1273 /* DATA_IN_PHASE/DATA_OUT_PHASE was processed. */
1274 nsp32_dbg(NSP32_DEBUG_INTR,
1275 "Data in/out phase processed");
1276
1277 /* read BMCNT, SGT pointer addr */
1278 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1279 nsp32_read4(base, BM_CNT));
1280 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1281 nsp32_read4(base, SGT_ADR));
1282 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1283 nsp32_read4(base, SACK_CNT));
1284 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1285 nsp32_read4(base, SAVED_SACK_CNT));
1286
1287 scsi_set_resid(SCpnt, 0); /* all data transferred! */
1288 }
1289
1290 /*
1291 * MsgIn Occur
1292 */
1293 if (auto_stat & MSG_IN_OCCUER) {
1294 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat);
1295 }
1296
1297 /*
1298 * MsgOut Occur
1299 */
1300 if (auto_stat & MSG_OUT_OCCUER) {
1301 nsp32_msgout_occur(SCpnt);
1302 }
1303
1304 /*
1305 * Bus Free Occur
1306 */
1307 if (auto_stat & BUS_FREE_OCCUER) {
1308 ret = nsp32_busfree_occur(SCpnt, auto_stat);
1309 if (ret == TRUE) {
1310 goto out;
1311 }
1312 }
1313
1314 if (auto_stat & STATUS_PHASE) {
1315 /*
1316 * Read CSB and substitute CSB for SCpnt->result
1317 * to save status phase stutas byte.
1318 * scsi error handler checks host_byte (DID_*:
1319 * low level driver to indicate status), then checks
1320 * status_byte (SCSI status byte).
1321 */
1322 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN);
1323 }
1324
1325 if (auto_stat & ILLEGAL_PHASE) {
1326 /* Illegal phase is detected. SACK is not back. */
1327 nsp32_msg(KERN_WARNING,
1328 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!");
1329
1330 /* TODO: currently we don't have any action... bus reset? */
1331
1332 /*
1333 * To send back SACK, assert, wait, and negate.
1334 */
1335 nsp32_sack_assert(data);
1336 nsp32_wait_req(data, NEGATE);
1337 nsp32_sack_negate(data);
1338
1339 }
1340
1341 if (auto_stat & COMMAND_PHASE) {
1342 /* nothing to do */
1343 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1344 }
1345
1346 if (auto_stat & AUTOSCSI_BUSY) {
1347 /* AutoSCSI is running */
1348 }
1349
1350 show_autophase(auto_stat);
1351 }
1352
1353 /* FIFO_SHLD_IRQ */
1354 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) {
1355 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1356
1357 switch(busphase) {
1358 case BUSPHASE_DATA_OUT:
1359 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1360
1361 //nsp32_pio_write(SCpnt);
1362
1363 break;
1364
1365 case BUSPHASE_DATA_IN:
1366 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1367
1368 //nsp32_pio_read(SCpnt);
1369
1370 break;
1371
1372 case BUSPHASE_STATUS:
1373 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1374
1375 nsp32_priv(SCpnt)->status = nsp32_read1(base, SCSI_CSB_IN);
1376
1377 break;
1378 default:
1379 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1380 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x",
1381 irq_stat, trans_stat);
1382 show_busphase(busphase);
1383 break;
1384 }
1385
1386 goto out;
1387 }
1388
1389 /* Phase Change IRQ */
1390 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) {
1391 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1392
1393 switch(busphase) {
1394 case BUSPHASE_MESSAGE_IN:
1395 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1396 nsp32_msgin_occur(SCpnt, irq_stat, 0);
1397 break;
1398 default:
1399 nsp32_msg(KERN_WARNING, "phase chg/other phase?");
1400 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n",
1401 irq_stat, trans_stat);
1402 show_busphase(busphase);
1403 break;
1404 }
1405 goto out;
1406 }
1407
1408 /* PCI_IRQ */
1409 if (irq_stat & IRQSTATUS_PCI_IRQ) {
1410 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1411 /* Do nothing */
1412 }
1413
1414 /* BMCNTERR_IRQ */
1415 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) {
1416 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! ");
1417 /*
1418 * TODO: To be implemented improving bus master
1419 * transfer reliability when BMCNTERR is occurred in
1420 * AutoSCSI phase described in specification.
1421 */
1422 }
1423
1424#if 0
1425 nsp32_dbg(NSP32_DEBUG_INTR,
1426 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1427 show_busphase(busphase);
1428#endif
1429
1430 out:
1431 /* disable IRQ mask */
1432 nsp32_write2(base, IRQ_CONTROL, 0);
1433
1434 out2:
1435 spin_unlock_irqrestore(host->host_lock, flags);
1436
1437 nsp32_dbg(NSP32_DEBUG_INTR, "exit");
1438
1439 return IRQ_RETVAL(handled);
1440}
1441
1442
1443static int nsp32_show_info(struct seq_file *m, struct Scsi_Host *host)
1444{
1445 unsigned long flags;
1446 nsp32_hw_data *data;
1447 int hostno;
1448 unsigned int base;
1449 unsigned char mode_reg;
1450 int id, speed;
1451 long model;
1452
1453 hostno = host->host_no;
1454 data = (nsp32_hw_data *)host->hostdata;
1455 base = host->io_port;
1456
1457 seq_puts(m, "NinjaSCSI-32 status\n\n");
1458 seq_printf(m, "Driver version: %s, $Revision: 1.33 $\n",
1459 nsp32_release_version);
1460 seq_printf(m, "SCSI host No.: %d\n", hostno);
1461 seq_printf(m, "IRQ: %d\n", host->irq);
1462 seq_printf(m, "IO: 0x%lx-0x%lx\n",
1463 host->io_port, host->io_port + host->n_io_port - 1);
1464 seq_printf(m, "MMIO(virtual address): 0x%lx-0x%lx\n",
1465 host->base, host->base + data->MmioLength - 1);
1466 seq_printf(m, "sg_tablesize: %d\n",
1467 host->sg_tablesize);
1468 seq_printf(m, "Chip revision: 0x%x\n",
1469 (nsp32_read2(base, INDEX_REG) >> 8) & 0xff);
1470
1471 mode_reg = nsp32_index_read1(base, CHIP_MODE);
1472 model = data->pci_devid->driver_data;
1473
1474#ifdef CONFIG_PM
1475 seq_printf(m, "Power Management: %s\n",
1476 (mode_reg & OPTF) ? "yes" : "no");
1477#endif
1478 seq_printf(m, "OEM: %ld, %s\n",
1479 (mode_reg & (OEM0|OEM1)), nsp32_model[model]);
1480
1481 spin_lock_irqsave(&(data->Lock), flags);
1482 seq_printf(m, "CurrentSC: 0x%p\n\n", data->CurrentSC);
1483 spin_unlock_irqrestore(&(data->Lock), flags);
1484
1485
1486 seq_puts(m, "SDTR status\n");
1487 for (id = 0; id < ARRAY_SIZE(data->target); id++) {
1488
1489 seq_printf(m, "id %d: ", id);
1490
1491 if (id == host->this_id) {
1492 seq_puts(m, "----- NinjaSCSI-32 host adapter\n");
1493 continue;
1494 }
1495
1496 if (data->target[id].sync_flag == SDTR_DONE) {
1497 if (data->target[id].period == 0 &&
1498 data->target[id].offset == ASYNC_OFFSET ) {
1499 seq_puts(m, "async");
1500 } else {
1501 seq_puts(m, " sync");
1502 }
1503 } else {
1504 seq_puts(m, " none");
1505 }
1506
1507 if (data->target[id].period != 0) {
1508
1509 speed = 1000000 / (data->target[id].period * 4);
1510
1511 seq_printf(m, " transfer %d.%dMB/s, offset %d",
1512 speed / 1000,
1513 speed % 1000,
1514 data->target[id].offset
1515 );
1516 }
1517 seq_putc(m, '\n');
1518 }
1519 return 0;
1520}
1521
1522
1523
1524/*
1525 * Reset parameters and call scsi_done for data->cur_lunt.
1526 * Be careful setting SCpnt->result = DID_* before calling this function.
1527 */
1528static void nsp32_scsi_done(struct scsi_cmnd *SCpnt)
1529{
1530 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1531 unsigned int base = SCpnt->device->host->io_port;
1532
1533 scsi_dma_unmap(SCpnt);
1534
1535 /*
1536 * clear TRANSFERCONTROL_BM_START
1537 */
1538 nsp32_write2(base, TRANSFER_CONTROL, 0);
1539 nsp32_write4(base, BM_CNT, 0);
1540
1541 /*
1542 * call scsi_done
1543 */
1544 scsi_done(SCpnt);
1545
1546 /*
1547 * reset parameters
1548 */
1549 data->cur_lunt->SCpnt = NULL;
1550 data->cur_lunt = NULL;
1551 data->cur_target = NULL;
1552 data->CurrentSC = NULL;
1553}
1554
1555
1556/*
1557 * Bus Free Occur
1558 *
1559 * Current Phase is BUSFREE. AutoSCSI is automatically execute BUSFREE phase
1560 * with ACK reply when below condition is matched:
1561 * MsgIn 00: Command Complete.
1562 * MsgIn 02: Save Data Pointer.
1563 * MsgIn 04: Disconnect.
1564 * In other case, unexpected BUSFREE is detected.
1565 */
1566static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph)
1567{
1568 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1569 unsigned int base = SCpnt->device->host->io_port;
1570
1571 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph);
1572 show_autophase(execph);
1573
1574 nsp32_write4(base, BM_CNT, 0);
1575 nsp32_write2(base, TRANSFER_CONTROL, 0);
1576
1577 /*
1578 * MsgIn 02: Save Data Pointer
1579 *
1580 * VALID:
1581 * Save Data Pointer is received. Adjust pointer.
1582 *
1583 * NO-VALID:
1584 * SCSI-3 says if Save Data Pointer is not received, then we restart
1585 * processing and we can't adjust any SCSI data pointer in next data
1586 * phase.
1587 */
1588 if (execph & MSGIN_02_VALID) {
1589 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid");
1590
1591 /*
1592 * Check sack_cnt/saved_sack_cnt, then adjust sg table if
1593 * needed.
1594 */
1595 if (!(execph & MSGIN_00_VALID) &&
1596 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) {
1597 unsigned int sacklen, s_sacklen;
1598
1599 /*
1600 * Read SACK count and SAVEDSACK count, then compare.
1601 */
1602 sacklen = nsp32_read4(base, SACK_CNT );
1603 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
1604
1605 /*
1606 * If SAVEDSACKCNT == 0, it means SavedDataPointer is
1607 * come after data transferring.
1608 */
1609 if (s_sacklen > 0) {
1610 /*
1611 * Comparing between sack and savedsack to
1612 * check the condition of AutoMsgIn03.
1613 *
1614 * If they are same, set msgin03 == TRUE,
1615 * COMMANDCONTROL_AUTO_MSGIN_03 is enabled at
1616 * reselection. On the other hand, if they
1617 * aren't same, set msgin03 == FALSE, and
1618 * COMMANDCONTROL_AUTO_MSGIN_03 is disabled at
1619 * reselection.
1620 */
1621 if (sacklen != s_sacklen) {
1622 data->cur_lunt->msgin03 = FALSE;
1623 } else {
1624 data->cur_lunt->msgin03 = TRUE;
1625 }
1626
1627 nsp32_adjust_busfree(SCpnt, s_sacklen);
1628 }
1629 }
1630
1631 /* This value has not substitude with valid value yet... */
1632 //data->cur_lunt->save_datp = data->cur_datp;
1633 } else {
1634 /*
1635 * no processing.
1636 */
1637 }
1638
1639 if (execph & MSGIN_03_VALID) {
1640 /* MsgIn03 was valid to be processed. No need processing. */
1641 }
1642
1643 /*
1644 * target SDTR check
1645 */
1646 if (data->cur_target->sync_flag & SDTR_INITIATOR) {
1647 /*
1648 * SDTR negotiation pulled by the initiator has not
1649 * finished yet. Fall back to ASYNC mode.
1650 */
1651 nsp32_set_async(data, data->cur_target);
1652 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
1653 data->cur_target->sync_flag |= SDTR_DONE;
1654 } else if (data->cur_target->sync_flag & SDTR_TARGET) {
1655 /*
1656 * SDTR negotiation pulled by the target has been
1657 * negotiating.
1658 */
1659 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) {
1660 /*
1661 * If valid message is received, then
1662 * negotiation is succeeded.
1663 */
1664 } else {
1665 /*
1666 * On the contrary, if unexpected bus free is
1667 * occurred, then negotiation is failed. Fall
1668 * back to ASYNC mode.
1669 */
1670 nsp32_set_async(data, data->cur_target);
1671 }
1672 data->cur_target->sync_flag &= ~SDTR_TARGET;
1673 data->cur_target->sync_flag |= SDTR_DONE;
1674 }
1675
1676 /*
1677 * It is always ensured by SCSI standard that initiator
1678 * switches into Bus Free Phase after
1679 * receiving message 00 (Command Complete), 04 (Disconnect).
1680 * It's the reason that processing here is valid.
1681 */
1682 if (execph & MSGIN_00_VALID) {
1683 /* MsgIn 00: Command Complete */
1684 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete");
1685
1686 nsp32_priv(SCpnt)->status = nsp32_read1(base, SCSI_CSB_IN);
1687 nsp32_dbg(NSP32_DEBUG_BUSFREE,
1688 "normal end stat=0x%x resid=0x%x\n",
1689 nsp32_priv(SCpnt)->status, scsi_get_resid(SCpnt));
1690 SCpnt->result = (DID_OK << 16) |
1691 (nsp32_priv(SCpnt)->status << 0);
1692 nsp32_scsi_done(SCpnt);
1693 /* All operation is done */
1694 return TRUE;
1695 } else if (execph & MSGIN_04_VALID) {
1696 /* MsgIn 04: Disconnect */
1697 nsp32_priv(SCpnt)->status = nsp32_read1(base, SCSI_CSB_IN);
1698
1699 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect");
1700 return TRUE;
1701 } else {
1702 /* Unexpected bus free */
1703 nsp32_msg(KERN_WARNING, "unexpected bus free occurred");
1704
1705 SCpnt->result = DID_ERROR << 16;
1706 nsp32_scsi_done(SCpnt);
1707 return TRUE;
1708 }
1709 return FALSE;
1710}
1711
1712
1713/*
1714 * nsp32_adjust_busfree - adjusting SG table
1715 *
1716 * Note: This driver adjust the SG table using SCSI ACK
1717 * counter instead of BMCNT counter!
1718 */
1719static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen)
1720{
1721 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1722 int old_entry = data->cur_entry;
1723 int new_entry;
1724 int sg_num = data->cur_lunt->sg_num;
1725 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
1726 unsigned int restlen, sentlen;
1727 u32_le len, addr;
1728
1729 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt));
1730
1731 /* adjust saved SACK count with 4 byte start address boundary */
1732 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3;
1733
1734 /*
1735 * calculate new_entry from sack count and each sgt[].len
1736 * calculate the byte which is intent to send
1737 */
1738 sentlen = 0;
1739 for (new_entry = old_entry; new_entry < sg_num; new_entry++) {
1740 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND);
1741 if (sentlen > s_sacklen) {
1742 break;
1743 }
1744 }
1745
1746 /* all sgt is processed */
1747 if (new_entry == sg_num) {
1748 goto last;
1749 }
1750
1751 if (sentlen == s_sacklen) {
1752 /* XXX: confirm it's ok or not */
1753 /* In this case, it's ok because we are at
1754 * the head element of the sg. restlen is correctly
1755 * calculated.
1756 */
1757 }
1758
1759 /* calculate the rest length for transferring */
1760 restlen = sentlen - s_sacklen;
1761
1762 /* update adjusting current SG table entry */
1763 len = le32_to_cpu(sgt[new_entry].len);
1764 addr = le32_to_cpu(sgt[new_entry].addr);
1765 addr += (len - restlen);
1766 sgt[new_entry].addr = cpu_to_le32(addr);
1767 sgt[new_entry].len = cpu_to_le32(restlen);
1768
1769 /* set cur_entry with new_entry */
1770 data->cur_entry = new_entry;
1771
1772 return;
1773
1774 last:
1775 if (scsi_get_resid(SCpnt) < sentlen) {
1776 nsp32_msg(KERN_ERR, "resid underflow");
1777 }
1778
1779 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen);
1780 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt));
1781
1782 /* update hostdata and lun */
1783
1784 return;
1785}
1786
1787
1788/*
1789 * It's called MsgOut phase occur.
1790 * NinjaSCSI-32Bi/UDE automatically processes up to 3 messages in
1791 * message out phase. It, however, has more than 3 messages,
1792 * HBA creates the interrupt and we have to process by hand.
1793 */
1794static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt)
1795{
1796 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1797 unsigned int base = SCpnt->device->host->io_port;
1798 int i;
1799
1800 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1801 "enter: msgout_len: 0x%x", data->msgout_len);
1802
1803 /*
1804 * If MsgOut phase is occurred without having any
1805 * message, then No_Operation is sent (SCSI-2).
1806 */
1807 if (data->msgout_len == 0) {
1808 nsp32_build_nop(SCpnt);
1809 }
1810
1811 /*
1812 * send messages
1813 */
1814 for (i = 0; i < data->msgout_len; i++) {
1815 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1816 "%d : 0x%x", i, data->msgoutbuf[i]);
1817
1818 /*
1819 * Check REQ is asserted.
1820 */
1821 nsp32_wait_req(data, ASSERT);
1822
1823 if (i == (data->msgout_len - 1)) {
1824 /*
1825 * If the last message, set the AutoSCSI restart
1826 * before send back the ack message. AutoSCSI
1827 * restart automatically negate ATN signal.
1828 */
1829 //command = (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
1830 //nsp32_restart_autoscsi(SCpnt, command);
1831 nsp32_write2(base, COMMAND_CONTROL,
1832 (CLEAR_CDB_FIFO_POINTER |
1833 AUTO_COMMAND_PHASE |
1834 AUTOSCSI_RESTART |
1835 AUTO_MSGIN_00_OR_04 |
1836 AUTO_MSGIN_02 ));
1837 }
1838 /*
1839 * Write data with SACK, then wait sack is
1840 * automatically negated.
1841 */
1842 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]);
1843 nsp32_wait_sack(data, NEGATE);
1844
1845 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n",
1846 nsp32_read1(base, SCSI_BUS_MONITOR));
1847 }
1848
1849 data->msgout_len = 0;
1850
1851 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit");
1852}
1853
1854/*
1855 * Restart AutoSCSI
1856 *
1857 * Note: Restarting AutoSCSI needs set:
1858 * SYNC_REG, ACK_WIDTH, SGT_ADR, TRANSFER_CONTROL
1859 */
1860static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command)
1861{
1862 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1863 unsigned int base = data->BaseAddress;
1864 unsigned short transfer = 0;
1865
1866 nsp32_dbg(NSP32_DEBUG_RESTART, "enter");
1867
1868 if (data->cur_target == NULL || data->cur_lunt == NULL) {
1869 nsp32_msg(KERN_ERR, "Target or Lun is invalid");
1870 }
1871
1872 /*
1873 * set SYNC_REG
1874 * Don't set BM_START_ADR before setting this register.
1875 */
1876 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
1877
1878 /*
1879 * set ACKWIDTH
1880 */
1881 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
1882
1883 /*
1884 * set SREQ hazard killer sampling rate
1885 */
1886 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
1887
1888 /*
1889 * set SGT ADDR (physical address)
1890 */
1891 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
1892
1893 /*
1894 * set TRANSFER CONTROL REG
1895 */
1896 transfer = 0;
1897 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR);
1898 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1899 if (scsi_bufflen(SCpnt) > 0) {
1900 transfer |= BM_START;
1901 }
1902 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
1903 transfer |= CB_MMIO_MODE;
1904 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
1905 transfer |= CB_IO_MODE;
1906 }
1907 nsp32_write2(base, TRANSFER_CONTROL, transfer);
1908
1909 /*
1910 * restart AutoSCSI
1911 *
1912 * TODO: COMMANDCONTROL_AUTO_COMMAND_PHASE is needed ?
1913 */
1914 command |= (CLEAR_CDB_FIFO_POINTER |
1915 AUTO_COMMAND_PHASE |
1916 AUTOSCSI_RESTART );
1917 nsp32_write2(base, COMMAND_CONTROL, command);
1918
1919 nsp32_dbg(NSP32_DEBUG_RESTART, "exit");
1920}
1921
1922
1923/*
1924 * cannot run automatically message in occur
1925 */
1926static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt,
1927 unsigned long irq_status,
1928 unsigned short execph)
1929{
1930 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1931 unsigned int base = SCpnt->device->host->io_port;
1932 unsigned char msg;
1933 unsigned char msgtype;
1934 unsigned char newlun;
1935 unsigned short command = 0;
1936 int msgclear = TRUE;
1937 long new_sgtp;
1938 int ret;
1939
1940 /*
1941 * read first message
1942 * Use SCSIDATA_W_ACK instead of SCSIDATAIN, because the procedure
1943 * of Message-In have to be processed before sending back SCSI ACK.
1944 */
1945 msg = nsp32_read1(base, SCSI_DATA_IN);
1946 data->msginbuf[(unsigned char)data->msgin_len] = msg;
1947 msgtype = data->msginbuf[0];
1948 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR,
1949 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x",
1950 data->msgin_len, msg, msgtype);
1951
1952 /*
1953 * TODO: We need checking whether bus phase is message in?
1954 */
1955
1956 /*
1957 * assert SCSI ACK
1958 */
1959 nsp32_sack_assert(data);
1960
1961 /*
1962 * processing IDENTIFY
1963 */
1964 if (msgtype & 0x80) {
1965 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) {
1966 /* Invalid (non reselect) phase */
1967 goto reject;
1968 }
1969
1970 newlun = msgtype & 0x1f; /* TODO: SPI-3 compliant? */
1971 ret = nsp32_reselection(SCpnt, newlun);
1972 if (ret == TRUE) {
1973 goto restart;
1974 } else {
1975 goto reject;
1976 }
1977 }
1978
1979 /*
1980 * processing messages except for IDENTIFY
1981 *
1982 * TODO: Messages are all SCSI-2 terminology. SCSI-3 compliance is TODO.
1983 */
1984 switch (msgtype) {
1985 /*
1986 * 1-byte message
1987 */
1988 case COMMAND_COMPLETE:
1989 case DISCONNECT:
1990 /*
1991 * These messages should not be occurred.
1992 * They should be processed on AutoSCSI sequencer.
1993 */
1994 nsp32_msg(KERN_WARNING,
1995 "unexpected message of AutoSCSI MsgIn: 0x%x", msg);
1996 break;
1997
1998 case RESTORE_POINTERS:
1999 /*
2000 * AutoMsgIn03 is disabled, and HBA gets this message.
2001 */
2002
2003 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) {
2004 unsigned int s_sacklen;
2005
2006 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
2007 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) {
2008 nsp32_adjust_busfree(SCpnt, s_sacklen);
2009 } else {
2010 /* No need to rewrite SGT */
2011 }
2012 }
2013 data->cur_lunt->msgin03 = FALSE;
2014
2015 /* Update with the new value */
2016
2017 /* reset SACK/SavedACK counter (or ALL clear?) */
2018 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2019
2020 /*
2021 * set new sg pointer
2022 */
2023 new_sgtp = data->cur_lunt->sglun_paddr +
2024 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
2025 nsp32_write4(base, SGT_ADR, new_sgtp);
2026
2027 break;
2028
2029 case SAVE_POINTERS:
2030 /*
2031 * These messages should not be occurred.
2032 * They should be processed on AutoSCSI sequencer.
2033 */
2034 nsp32_msg (KERN_WARNING,
2035 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS");
2036
2037 break;
2038
2039 case MESSAGE_REJECT:
2040 /* If previous message_out is sending SDTR, and get
2041 message_reject from target, SDTR negotiation is failed */
2042 if (data->cur_target->sync_flag &
2043 (SDTR_INITIATOR | SDTR_TARGET)) {
2044 /*
2045 * Current target is negotiating SDTR, but it's
2046 * failed. Fall back to async transfer mode, and set
2047 * SDTR_DONE.
2048 */
2049 nsp32_set_async(data, data->cur_target);
2050 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
2051 data->cur_target->sync_flag |= SDTR_DONE;
2052
2053 }
2054 break;
2055
2056 case LINKED_CMD_COMPLETE:
2057 case LINKED_FLG_CMD_COMPLETE:
2058 /* queue tag is not supported currently */
2059 nsp32_msg (KERN_WARNING,
2060 "unsupported message: 0x%x", msgtype);
2061 break;
2062
2063 case INITIATE_RECOVERY:
2064 /* staring ECA (Extended Contingent Allegiance) state. */
2065 /* This message is declined in SPI2 or later. */
2066
2067 goto reject;
2068
2069 /*
2070 * 2-byte message
2071 */
2072 case SIMPLE_QUEUE_TAG:
2073 case 0x23:
2074 /*
2075 * 0x23: Ignore_Wide_Residue is not declared in scsi.h.
2076 * No support is needed.
2077 */
2078 if (data->msgin_len >= 1) {
2079 goto reject;
2080 }
2081
2082 /* current position is 1-byte of 2 byte */
2083 msgclear = FALSE;
2084
2085 break;
2086
2087 /*
2088 * extended message
2089 */
2090 case EXTENDED_MESSAGE:
2091 if (data->msgin_len < 1) {
2092 /*
2093 * Current position does not reach 2-byte
2094 * (2-byte is extended message length).
2095 */
2096 msgclear = FALSE;
2097 break;
2098 }
2099
2100 if ((data->msginbuf[1] + 1) > data->msgin_len) {
2101 /*
2102 * Current extended message has msginbuf[1] + 2
2103 * (msgin_len starts counting from 0, so buf[1] + 1).
2104 * If current message position is not finished,
2105 * continue receiving message.
2106 */
2107 msgclear = FALSE;
2108 break;
2109 }
2110
2111 /*
2112 * Reach here means regular length of each type of
2113 * extended messages.
2114 */
2115 switch (data->msginbuf[2]) {
2116 case EXTENDED_MODIFY_DATA_POINTER:
2117 /* TODO */
2118 goto reject; /* not implemented yet */
2119 break;
2120
2121 case EXTENDED_SDTR:
2122 /*
2123 * Exchange this message between initiator and target.
2124 */
2125 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) {
2126 /*
2127 * received inappropriate message.
2128 */
2129 goto reject;
2130 break;
2131 }
2132
2133 nsp32_analyze_sdtr(SCpnt);
2134
2135 break;
2136
2137 case EXTENDED_EXTENDED_IDENTIFY:
2138 /* SCSI-I only, not supported. */
2139 goto reject; /* not implemented yet */
2140
2141 break;
2142
2143 case EXTENDED_WDTR:
2144 goto reject; /* not implemented yet */
2145
2146 break;
2147
2148 default:
2149 goto reject;
2150 }
2151 break;
2152
2153 default:
2154 goto reject;
2155 }
2156
2157 restart:
2158 if (msgclear == TRUE) {
2159 data->msgin_len = 0;
2160
2161 /*
2162 * If restarting AutoSCSI, but there are some message to out
2163 * (msgout_len > 0), set AutoATN, and set SCSIMSGOUT as 0
2164 * (MV_VALID = 0). When commandcontrol is written with
2165 * AutoSCSI restart, at the same time MsgOutOccur should be
2166 * happened (however, such situation is really possible...?).
2167 */
2168 if (data->msgout_len > 0) {
2169 nsp32_write4(base, SCSI_MSG_OUT, 0);
2170 command |= AUTO_ATN;
2171 }
2172
2173 /*
2174 * restart AutoSCSI
2175 * If it's failed, COMMANDCONTROL_AUTO_COMMAND_PHASE is needed.
2176 */
2177 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
2178
2179 /*
2180 * If current msgin03 is TRUE, then flag on.
2181 */
2182 if (data->cur_lunt->msgin03 == TRUE) {
2183 command |= AUTO_MSGIN_03;
2184 }
2185 data->cur_lunt->msgin03 = FALSE;
2186 } else {
2187 data->msgin_len++;
2188 }
2189
2190 /*
2191 * restart AutoSCSI
2192 */
2193 nsp32_restart_autoscsi(SCpnt, command);
2194
2195 /*
2196 * wait SCSI REQ negate for REQ-ACK handshake
2197 */
2198 nsp32_wait_req(data, NEGATE);
2199
2200 /*
2201 * negate SCSI ACK
2202 */
2203 nsp32_sack_negate(data);
2204
2205 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2206
2207 return;
2208
2209 reject:
2210 nsp32_msg(KERN_WARNING,
2211 "invalid or unsupported MessageIn, rejected. "
2212 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x",
2213 msg, data->msgin_len, msgtype);
2214 nsp32_build_reject(SCpnt);
2215 data->msgin_len = 0;
2216
2217 goto restart;
2218}
2219
2220/*
2221 *
2222 */
2223static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt)
2224{
2225 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2226 nsp32_target *target = data->cur_target;
2227 unsigned char get_period = data->msginbuf[3];
2228 unsigned char get_offset = data->msginbuf[4];
2229 int entry;
2230
2231 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter");
2232
2233 /*
2234 * If this inititor sent the SDTR message, then target responds SDTR,
2235 * initiator SYNCREG, ACKWIDTH from SDTR parameter.
2236 * Messages are not appropriate, then send back reject message.
2237 * If initiator did not send the SDTR, but target sends SDTR,
2238 * initiator calculator the appropriate parameter and send back SDTR.
2239 */
2240 if (target->sync_flag & SDTR_INITIATOR) {
2241 /*
2242 * Initiator sent SDTR, the target responds and
2243 * send back negotiation SDTR.
2244 */
2245 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR");
2246
2247 target->sync_flag &= ~SDTR_INITIATOR;
2248 target->sync_flag |= SDTR_DONE;
2249
2250 /*
2251 * offset:
2252 */
2253 if (get_offset > SYNC_OFFSET) {
2254 /*
2255 * Negotiation is failed, the target send back
2256 * unexpected offset value.
2257 */
2258 goto reject;
2259 }
2260
2261 if (get_offset == ASYNC_OFFSET) {
2262 /*
2263 * Negotiation is succeeded, the target want
2264 * to fall back into asynchronous transfer mode.
2265 */
2266 goto async;
2267 }
2268
2269 /*
2270 * period:
2271 * Check whether sync period is too short. If too short,
2272 * fall back to async mode. If it's ok, then investigate
2273 * the received sync period. If sync period is acceptable
2274 * between sync table start_period and end_period, then
2275 * set this I_T nexus as sent offset and period.
2276 * If it's not acceptable, send back reject and fall back
2277 * to async mode.
2278 */
2279 if (get_period < data->synct[0].period_num) {
2280 /*
2281 * Negotiation is failed, the target send back
2282 * unexpected period value.
2283 */
2284 goto reject;
2285 }
2286
2287 entry = nsp32_search_period_entry(data, target, get_period);
2288
2289 if (entry < 0) {
2290 /*
2291 * Target want to use long period which is not
2292 * acceptable NinjaSCSI-32Bi/UDE.
2293 */
2294 goto reject;
2295 }
2296
2297 /*
2298 * Set new sync table and offset in this I_T nexus.
2299 */
2300 nsp32_set_sync_entry(data, target, entry, get_offset);
2301 } else {
2302 /* Target send SDTR to initiator. */
2303 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR");
2304
2305 target->sync_flag |= SDTR_INITIATOR;
2306
2307 /* offset: */
2308 if (get_offset > SYNC_OFFSET) {
2309 /* send back as SYNC_OFFSET */
2310 get_offset = SYNC_OFFSET;
2311 }
2312
2313 /* period: */
2314 if (get_period < data->synct[0].period_num) {
2315 get_period = data->synct[0].period_num;
2316 }
2317
2318 entry = nsp32_search_period_entry(data, target, get_period);
2319
2320 if (get_offset == ASYNC_OFFSET || entry < 0) {
2321 nsp32_set_async(data, target);
2322 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET);
2323 } else {
2324 nsp32_set_sync_entry(data, target, entry, get_offset);
2325 nsp32_build_sdtr(SCpnt, get_period, get_offset);
2326 }
2327 }
2328
2329 target->period = get_period;
2330 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2331 return;
2332
2333 reject:
2334 /*
2335 * If the current message is unacceptable, send back to the target
2336 * with reject message.
2337 */
2338 nsp32_build_reject(SCpnt);
2339
2340 async:
2341 nsp32_set_async(data, target); /* set as ASYNC transfer mode */
2342
2343 target->period = 0;
2344 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async");
2345 return;
2346}
2347
2348
2349/*
2350 * Search config entry number matched in sync_table from given
2351 * target and speed period value. If failed to search, return negative value.
2352 */
2353static int nsp32_search_period_entry(nsp32_hw_data *data,
2354 nsp32_target *target,
2355 unsigned char period)
2356{
2357 int i;
2358
2359 if (target->limit_entry >= data->syncnum) {
2360 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!");
2361 target->limit_entry = 0;
2362 }
2363
2364 for (i = target->limit_entry; i < data->syncnum; i++) {
2365 if (period >= data->synct[i].start_period &&
2366 period <= data->synct[i].end_period) {
2367 break;
2368 }
2369 }
2370
2371 /*
2372 * Check given period value is over the sync_table value.
2373 * If so, return max value.
2374 */
2375 if (i == data->syncnum) {
2376 i = -1;
2377 }
2378
2379 return i;
2380}
2381
2382
2383/*
2384 * target <-> initiator use ASYNC transfer
2385 */
2386static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target)
2387{
2388 unsigned char period = data->synct[target->limit_entry].period_num;
2389
2390 target->offset = ASYNC_OFFSET;
2391 target->period = 0;
2392 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET);
2393 target->ackwidth = 0;
2394 target->sample_reg = 0;
2395
2396 nsp32_dbg(NSP32_DEBUG_SYNC, "set async");
2397}
2398
2399
2400/*
2401 * target <-> initiator use maximum SYNC transfer
2402 */
2403static void nsp32_set_max_sync(nsp32_hw_data *data,
2404 nsp32_target *target,
2405 unsigned char *period,
2406 unsigned char *offset)
2407{
2408 unsigned char period_num, ackwidth;
2409
2410 period_num = data->synct[target->limit_entry].period_num;
2411 *period = data->synct[target->limit_entry].start_period;
2412 ackwidth = data->synct[target->limit_entry].ackwidth;
2413 *offset = SYNC_OFFSET;
2414
2415 target->syncreg = TO_SYNCREG(period_num, *offset);
2416 target->ackwidth = ackwidth;
2417 target->offset = *offset;
2418 target->sample_reg = 0; /* disable SREQ sampling */
2419}
2420
2421
2422/*
2423 * target <-> initiator use entry number speed
2424 */
2425static void nsp32_set_sync_entry(nsp32_hw_data *data,
2426 nsp32_target *target,
2427 int entry,
2428 unsigned char offset)
2429{
2430 unsigned char period, ackwidth, sample_rate;
2431
2432 period = data->synct[entry].period_num;
2433 ackwidth = data->synct[entry].ackwidth;
2434 sample_rate = data->synct[entry].sample_rate;
2435
2436 target->syncreg = TO_SYNCREG(period, offset);
2437 target->ackwidth = ackwidth;
2438 target->offset = offset;
2439 target->sample_reg = sample_rate | SAMPLING_ENABLE;
2440
2441 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync");
2442}
2443
2444
2445/*
2446 * It waits until SCSI REQ becomes assertion or negation state.
2447 *
2448 * Note: If nsp32_msgin_occur is called, we asserts SCSI ACK. Then
2449 * connected target responds SCSI REQ negation. We have to wait
2450 * SCSI REQ becomes negation in order to negate SCSI ACK signal for
2451 * REQ-ACK handshake.
2452 */
2453static void nsp32_wait_req(nsp32_hw_data *data, int state)
2454{
2455 unsigned int base = data->BaseAddress;
2456 int wait_time = 0;
2457 unsigned char bus, req_bit;
2458
2459 if (!((state == ASSERT) || (state == NEGATE))) {
2460 nsp32_msg(KERN_ERR, "unknown state designation");
2461 }
2462 /* REQ is BIT(5) */
2463 req_bit = (state == ASSERT ? BUSMON_REQ : 0);
2464
2465 do {
2466 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2467 if ((bus & BUSMON_REQ) == req_bit) {
2468 nsp32_dbg(NSP32_DEBUG_WAIT,
2469 "wait_time: %d", wait_time);
2470 return;
2471 }
2472 udelay(1);
2473 wait_time++;
2474 } while (wait_time < REQSACK_TIMEOUT_TIME);
2475
2476 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit);
2477}
2478
2479/*
2480 * It waits until SCSI SACK becomes assertion or negation state.
2481 */
2482static void nsp32_wait_sack(nsp32_hw_data *data, int state)
2483{
2484 unsigned int base = data->BaseAddress;
2485 int wait_time = 0;
2486 unsigned char bus, ack_bit;
2487
2488 if (!((state == ASSERT) || (state == NEGATE))) {
2489 nsp32_msg(KERN_ERR, "unknown state designation");
2490 }
2491 /* ACK is BIT(4) */
2492 ack_bit = (state == ASSERT ? BUSMON_ACK : 0);
2493
2494 do {
2495 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2496 if ((bus & BUSMON_ACK) == ack_bit) {
2497 nsp32_dbg(NSP32_DEBUG_WAIT,
2498 "wait_time: %d", wait_time);
2499 return;
2500 }
2501 udelay(1);
2502 wait_time++;
2503 } while (wait_time < REQSACK_TIMEOUT_TIME);
2504
2505 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit);
2506}
2507
2508/*
2509 * assert SCSI ACK
2510 *
2511 * Note: SCSI ACK assertion needs with ACKENB=1, AUTODIRECTION=1.
2512 */
2513static void nsp32_sack_assert(nsp32_hw_data *data)
2514{
2515 unsigned int base = data->BaseAddress;
2516 unsigned char busctrl;
2517
2518 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2519 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB);
2520 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2521}
2522
2523/*
2524 * negate SCSI ACK
2525 */
2526static void nsp32_sack_negate(nsp32_hw_data *data)
2527{
2528 unsigned int base = data->BaseAddress;
2529 unsigned char busctrl;
2530
2531 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2532 busctrl &= ~BUSCTL_ACK;
2533 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2534}
2535
2536
2537
2538/*
2539 * Note: n_io_port is defined as 0x7f because I/O register port is
2540 * assigned as:
2541 * 0x800-0x8ff: memory mapped I/O port
2542 * 0x900-0xbff: (map same 0x800-0x8ff I/O port image repeatedly)
2543 * 0xc00-0xfff: CardBus status registers
2544 */
2545static int nsp32_detect(struct pci_dev *pdev)
2546{
2547 struct Scsi_Host *host; /* registered host structure */
2548 struct resource *res;
2549 nsp32_hw_data *data;
2550 int ret;
2551 int i, j;
2552
2553 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
2554
2555 /*
2556 * register this HBA as SCSI device
2557 */
2558 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data));
2559 if (host == NULL) {
2560 nsp32_msg (KERN_ERR, "failed to scsi register");
2561 goto err;
2562 }
2563
2564 /*
2565 * set nsp32_hw_data
2566 */
2567 data = (nsp32_hw_data *)host->hostdata;
2568
2569 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data));
2570
2571 host->irq = data->IrqNumber;
2572 host->io_port = data->BaseAddress;
2573 host->unique_id = data->BaseAddress;
2574 host->n_io_port = data->NumAddress;
2575 host->base = (unsigned long)data->MmioAddress;
2576
2577 data->Host = host;
2578 spin_lock_init(&(data->Lock));
2579
2580 data->cur_lunt = NULL;
2581 data->cur_target = NULL;
2582
2583 /*
2584 * Bus master transfer mode is supported currently.
2585 */
2586 data->trans_method = NSP32_TRANSFER_BUSMASTER;
2587
2588 /*
2589 * Set clock div, CLOCK_4 (HBA has own external clock, and
2590 * dividing * 100ns/4).
2591 * Currently CLOCK_4 has only tested, not for CLOCK_2/PCICLK yet.
2592 */
2593 data->clock = CLOCK_4;
2594
2595 /*
2596 * Select appropriate nsp32_sync_table and set I_CLOCKDIV.
2597 */
2598 switch (data->clock) {
2599 case CLOCK_4:
2600 /* If data->clock is CLOCK_4, then select 40M sync table. */
2601 data->synct = nsp32_sync_table_40M;
2602 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2603 break;
2604 case CLOCK_2:
2605 /* If data->clock is CLOCK_2, then select 20M sync table. */
2606 data->synct = nsp32_sync_table_20M;
2607 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M);
2608 break;
2609 case PCICLK:
2610 /* If data->clock is PCICLK, then select pci sync table. */
2611 data->synct = nsp32_sync_table_pci;
2612 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci);
2613 break;
2614 default:
2615 nsp32_msg(KERN_WARNING,
2616 "Invalid clock div is selected, set CLOCK_4.");
2617 /* Use default value CLOCK_4 */
2618 data->clock = CLOCK_4;
2619 data->synct = nsp32_sync_table_40M;
2620 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2621 }
2622
2623 /*
2624 * setup nsp32_lunt
2625 */
2626
2627 /*
2628 * setup DMA
2629 */
2630 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
2631 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask");
2632 goto scsi_unregister;
2633 }
2634
2635 /*
2636 * allocate autoparam DMA resource.
2637 */
2638 data->autoparam = dma_alloc_coherent(&pdev->dev,
2639 sizeof(nsp32_autoparam), &(data->auto_paddr),
2640 GFP_KERNEL);
2641 if (data->autoparam == NULL) {
2642 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2643 goto scsi_unregister;
2644 }
2645
2646 /*
2647 * allocate scatter-gather DMA resource.
2648 */
2649 data->sg_list = dma_alloc_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE,
2650 &data->sg_paddr, GFP_KERNEL);
2651 if (data->sg_list == NULL) {
2652 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2653 goto free_autoparam;
2654 }
2655
2656 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) {
2657 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) {
2658 int offset = i * ARRAY_SIZE(data->lunt[0]) + j;
2659 nsp32_lunt tmp = {
2660 .SCpnt = NULL,
2661 .save_datp = 0,
2662 .msgin03 = FALSE,
2663 .sg_num = 0,
2664 .cur_entry = 0,
2665 .sglun = &(data->sg_list[offset]),
2666 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)),
2667 };
2668
2669 data->lunt[i][j] = tmp;
2670 }
2671 }
2672
2673 /*
2674 * setup target
2675 */
2676 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2677 nsp32_target *target = &(data->target[i]);
2678
2679 target->limit_entry = 0;
2680 target->sync_flag = 0;
2681 nsp32_set_async(data, target);
2682 }
2683
2684 /*
2685 * EEPROM check
2686 */
2687 ret = nsp32_getprom_param(data);
2688 if (ret == FALSE) {
2689 data->resettime = 3; /* default 3 */
2690 }
2691
2692 /*
2693 * setup HBA
2694 */
2695 nsp32hw_init(data);
2696
2697 snprintf(data->info_str, sizeof(data->info_str),
2698 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x",
2699 host->irq, host->io_port, host->n_io_port);
2700
2701 /*
2702 * SCSI bus reset
2703 *
2704 * Note: It's important to reset SCSI bus in initialization phase.
2705 * NinjaSCSI-32Bi/UDE HBA EEPROM seems to exchange SDTR when
2706 * system is coming up, so SCSI devices connected to HBA is set as
2707 * un-asynchronous mode. It brings the merit that this HBA is
2708 * ready to start synchronous transfer without any preparation,
2709 * but we are difficult to control transfer speed. In addition,
2710 * it prevents device transfer speed from effecting EEPROM start-up
2711 * SDTR. NinjaSCSI-32Bi/UDE has the feature if EEPROM is set as
2712 * Auto Mode, then FAST-10M is selected when SCSI devices are
2713 * connected same or more than 4 devices. It should be avoided
2714 * depending on this specification. Thus, resetting the SCSI bus
2715 * restores all connected SCSI devices to asynchronous mode, then
2716 * this driver set SDTR safely later, and we can control all SCSI
2717 * device transfer mode.
2718 */
2719 nsp32_do_bus_reset(data);
2720
2721 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data);
2722 if (ret < 0) {
2723 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 "
2724 "SCSI PCI controller. Interrupt: %d", host->irq);
2725 goto free_sg_list;
2726 }
2727
2728 /*
2729 * PCI IO register
2730 */
2731 res = request_region(host->io_port, host->n_io_port, "nsp32");
2732 if (res == NULL) {
2733 nsp32_msg(KERN_ERR,
2734 "I/O region 0x%x+0x%x is already used",
2735 data->BaseAddress, data->NumAddress);
2736 goto free_irq;
2737 }
2738
2739 ret = scsi_add_host(host, &pdev->dev);
2740 if (ret) {
2741 nsp32_msg(KERN_ERR, "failed to add scsi host");
2742 goto free_region;
2743 }
2744 scsi_scan_host(host);
2745 pci_set_drvdata(pdev, host);
2746 return 0;
2747
2748 free_region:
2749 release_region(host->io_port, host->n_io_port);
2750
2751 free_irq:
2752 free_irq(host->irq, data);
2753
2754 free_sg_list:
2755 dma_free_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE,
2756 data->sg_list, data->sg_paddr);
2757
2758 free_autoparam:
2759 dma_free_coherent(&pdev->dev, sizeof(nsp32_autoparam),
2760 data->autoparam, data->auto_paddr);
2761
2762 scsi_unregister:
2763 scsi_host_put(host);
2764
2765 err:
2766 return 1;
2767}
2768
2769static int nsp32_release(struct Scsi_Host *host)
2770{
2771 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2772
2773 if (data->autoparam) {
2774 dma_free_coherent(&data->Pci->dev, sizeof(nsp32_autoparam),
2775 data->autoparam, data->auto_paddr);
2776 }
2777
2778 if (data->sg_list) {
2779 dma_free_coherent(&data->Pci->dev, NSP32_SG_TABLE_SIZE,
2780 data->sg_list, data->sg_paddr);
2781 }
2782
2783 if (host->irq) {
2784 free_irq(host->irq, data);
2785 }
2786
2787 if (host->io_port && host->n_io_port) {
2788 release_region(host->io_port, host->n_io_port);
2789 }
2790
2791 if (data->MmioAddress) {
2792 iounmap(data->MmioAddress);
2793 }
2794
2795 return 0;
2796}
2797
2798static const char *nsp32_info(struct Scsi_Host *shpnt)
2799{
2800 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata;
2801
2802 return data->info_str;
2803}
2804
2805
2806/****************************************************************************
2807 * error handler
2808 */
2809static int nsp32_eh_abort(struct scsi_cmnd *SCpnt)
2810{
2811 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2812 unsigned int base = SCpnt->device->host->io_port;
2813
2814 nsp32_msg(KERN_WARNING, "abort");
2815
2816 if (data->cur_lunt->SCpnt == NULL) {
2817 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed");
2818 return FAILED;
2819 }
2820
2821 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) {
2822 /* reset SDTR negotiation */
2823 data->cur_target->sync_flag = 0;
2824 nsp32_set_async(data, data->cur_target);
2825 }
2826
2827 nsp32_write2(base, TRANSFER_CONTROL, 0);
2828 nsp32_write2(base, BM_CNT, 0);
2829
2830 SCpnt->result = DID_ABORT << 16;
2831 nsp32_scsi_done(SCpnt);
2832
2833 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success");
2834 return SUCCESS;
2835}
2836
2837static void nsp32_do_bus_reset(nsp32_hw_data *data)
2838{
2839 unsigned int base = data->BaseAddress;
2840 int i;
2841 unsigned short __maybe_unused intrdat;
2842
2843 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in");
2844
2845 /*
2846 * stop all transfer
2847 * clear TRANSFERCONTROL_BM_START
2848 * clear counter
2849 */
2850 nsp32_write2(base, TRANSFER_CONTROL, 0);
2851 nsp32_write4(base, BM_CNT, 0);
2852 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2853
2854 /*
2855 * fall back to asynchronous transfer mode
2856 * initialize SDTR negotiation flag
2857 */
2858 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2859 nsp32_target *target = &data->target[i];
2860
2861 target->sync_flag = 0;
2862 nsp32_set_async(data, target);
2863 }
2864
2865 /*
2866 * reset SCSI bus
2867 */
2868 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST);
2869 mdelay(RESET_HOLD_TIME / 1000);
2870 nsp32_write1(base, SCSI_BUS_CONTROL, 0);
2871 for(i = 0; i < 5; i++) {
2872 intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */
2873 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat);
2874 }
2875
2876 data->CurrentSC = NULL;
2877}
2878
2879static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt)
2880{
2881 struct Scsi_Host *host = SCpnt->device->host;
2882 unsigned int base = SCpnt->device->host->io_port;
2883 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2884
2885 nsp32_msg(KERN_INFO, "Host Reset");
2886 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2887
2888 spin_lock_irq(SCpnt->device->host->host_lock);
2889
2890 nsp32hw_init(data);
2891 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2892 nsp32_do_bus_reset(data);
2893 nsp32_write2(base, IRQ_CONTROL, 0);
2894
2895 spin_unlock_irq(SCpnt->device->host->host_lock);
2896 return SUCCESS; /* Host reset is succeeded at any time. */
2897}
2898
2899
2900/**************************************************************************
2901 * EEPROM handler
2902 */
2903
2904/*
2905 * getting EEPROM parameter
2906 */
2907static int nsp32_getprom_param(nsp32_hw_data *data)
2908{
2909 int vendor = data->pci_devid->vendor;
2910 int device = data->pci_devid->device;
2911 int ret, i;
2912 int __maybe_unused val;
2913
2914 /*
2915 * EEPROM checking.
2916 */
2917 ret = nsp32_prom_read(data, 0x7e);
2918 if (ret != 0x55) {
2919 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret);
2920 return FALSE;
2921 }
2922 ret = nsp32_prom_read(data, 0x7f);
2923 if (ret != 0xaa) {
2924 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret);
2925 return FALSE;
2926 }
2927
2928 /*
2929 * check EEPROM type
2930 */
2931 if (vendor == PCI_VENDOR_ID_WORKBIT &&
2932 device == PCI_DEVICE_ID_WORKBIT_STANDARD) {
2933 ret = nsp32_getprom_c16(data);
2934 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2935 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) {
2936 ret = nsp32_getprom_at24(data);
2937 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2938 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) {
2939 ret = nsp32_getprom_at24(data);
2940 } else {
2941 nsp32_msg(KERN_WARNING, "Unknown EEPROM");
2942 ret = FALSE;
2943 }
2944
2945 /* for debug : SPROM data full checking */
2946 for (i = 0; i <= 0x1f; i++) {
2947 val = nsp32_prom_read(data, i);
2948 nsp32_dbg(NSP32_DEBUG_EEPROM,
2949 "rom address 0x%x : 0x%x", i, val);
2950 }
2951
2952 return ret;
2953}
2954
2955
2956/*
2957 * AT24C01A (Logitec: LHA-600S), AT24C02 (Melco Buffalo: IFC-USLP) data map:
2958 *
2959 * ROMADDR
2960 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
2961 * Value 0x0: ASYNC, 0x0c: Ultra-20M, 0x19: Fast-10M
2962 * 0x07 : HBA Synchronous Transfer Period
2963 * Value 0: AutoSync, 1: Manual Setting
2964 * 0x08 - 0x0f : Not Used? (0x0)
2965 * 0x10 : Bus Termination
2966 * Value 0: Auto[ON], 1: ON, 2: OFF
2967 * 0x11 : Not Used? (0)
2968 * 0x12 : Bus Reset Delay Time (0x03)
2969 * 0x13 : Bootable CD Support
2970 * Value 0: Disable, 1: Enable
2971 * 0x14 : Device Scan
2972 * Bit 7 6 5 4 3 2 1 0
2973 * | <----------------->
2974 * | SCSI ID: Value 0: Skip, 1: YES
2975 * |-> Value 0: ALL scan, Value 1: Manual
2976 * 0x15 - 0x1b : Not Used? (0)
2977 * 0x1c : Constant? (0x01) (clock div?)
2978 * 0x1d - 0x7c : Not Used (0xff)
2979 * 0x7d : Not Used? (0xff)
2980 * 0x7e : Constant (0x55), Validity signature
2981 * 0x7f : Constant (0xaa), Validity signature
2982 */
2983static int nsp32_getprom_at24(nsp32_hw_data *data)
2984{
2985 int ret, i;
2986 int auto_sync;
2987 nsp32_target *target;
2988 int entry;
2989
2990 /*
2991 * Reset time which is designated by EEPROM.
2992 *
2993 * TODO: Not used yet.
2994 */
2995 data->resettime = nsp32_prom_read(data, 0x12);
2996
2997 /*
2998 * HBA Synchronous Transfer Period
2999 *
3000 * Note: auto_sync = 0: auto, 1: manual. Ninja SCSI HBA spec says
3001 * that if auto_sync is 0 (auto), and connected SCSI devices are
3002 * same or lower than 3, then transfer speed is set as ULTRA-20M.
3003 * On the contrary if connected SCSI devices are same or higher
3004 * than 4, then transfer speed is set as FAST-10M.
3005 *
3006 * I break this rule. The number of connected SCSI devices are
3007 * only ignored. If auto_sync is 0 (auto), then transfer speed is
3008 * forced as ULTRA-20M.
3009 */
3010 ret = nsp32_prom_read(data, 0x07);
3011 switch (ret) {
3012 case 0:
3013 auto_sync = TRUE;
3014 break;
3015 case 1:
3016 auto_sync = FALSE;
3017 break;
3018 default:
3019 nsp32_msg(KERN_WARNING,
3020 "Unsupported Auto Sync mode. Fall back to manual mode.");
3021 auto_sync = TRUE;
3022 }
3023
3024 if (trans_mode == ULTRA20M_MODE) {
3025 auto_sync = TRUE;
3026 }
3027
3028 /*
3029 * each device Synchronous Transfer Period
3030 */
3031 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3032 target = &data->target[i];
3033 if (auto_sync == TRUE) {
3034 target->limit_entry = 0; /* set as ULTRA20M */
3035 } else {
3036 ret = nsp32_prom_read(data, i);
3037 entry = nsp32_search_period_entry(data, target, ret);
3038 if (entry < 0) {
3039 /* search failed... set maximum speed */
3040 entry = 0;
3041 }
3042 target->limit_entry = entry;
3043 }
3044 }
3045
3046 return TRUE;
3047}
3048
3049
3050/*
3051 * C16 110 (I-O Data: SC-NBD) data map:
3052 *
3053 * ROMADDR
3054 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
3055 * Value 0x0: 20MB/S, 0x1: 10MB/S, 0x2: 5MB/S, 0x3: ASYNC
3056 * 0x07 : 0 (HBA Synchronous Transfer Period: Auto Sync)
3057 * 0x08 - 0x0f : Not Used? (0x0)
3058 * 0x10 : Transfer Mode
3059 * Value 0: PIO, 1: Busmater
3060 * 0x11 : Bus Reset Delay Time (0x00-0x20)
3061 * 0x12 : Bus Termination
3062 * Value 0: Disable, 1: Enable
3063 * 0x13 - 0x19 : Disconnection
3064 * Value 0: Disable, 1: Enable
3065 * 0x1a - 0x7c : Not Used? (0)
3066 * 0x7d : Not Used? (0xf8)
3067 * 0x7e : Constant (0x55), Validity signature
3068 * 0x7f : Constant (0xaa), Validity signature
3069 */
3070static int nsp32_getprom_c16(nsp32_hw_data *data)
3071{
3072 int ret, i;
3073 nsp32_target *target;
3074 int entry, val;
3075
3076 /*
3077 * Reset time which is designated by EEPROM.
3078 *
3079 * TODO: Not used yet.
3080 */
3081 data->resettime = nsp32_prom_read(data, 0x11);
3082
3083 /*
3084 * each device Synchronous Transfer Period
3085 */
3086 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3087 target = &data->target[i];
3088 ret = nsp32_prom_read(data, i);
3089 switch (ret) {
3090 case 0: /* 20MB/s */
3091 val = 0x0c;
3092 break;
3093 case 1: /* 10MB/s */
3094 val = 0x19;
3095 break;
3096 case 2: /* 5MB/s */
3097 val = 0x32;
3098 break;
3099 case 3: /* ASYNC */
3100 val = 0x00;
3101 break;
3102 default: /* default 20MB/s */
3103 val = 0x0c;
3104 break;
3105 }
3106 entry = nsp32_search_period_entry(data, target, val);
3107 if (entry < 0 || trans_mode == ULTRA20M_MODE) {
3108 /* search failed... set maximum speed */
3109 entry = 0;
3110 }
3111 target->limit_entry = entry;
3112 }
3113
3114 return TRUE;
3115}
3116
3117
3118/*
3119 * Atmel AT24C01A (drived in 5V) serial EEPROM routines
3120 */
3121static int nsp32_prom_read(nsp32_hw_data *data, int romaddr)
3122{
3123 int i, val;
3124
3125 /* start condition */
3126 nsp32_prom_start(data);
3127
3128 /* device address */
3129 nsp32_prom_write_bit(data, 1); /* 1 */
3130 nsp32_prom_write_bit(data, 0); /* 0 */
3131 nsp32_prom_write_bit(data, 1); /* 1 */
3132 nsp32_prom_write_bit(data, 0); /* 0 */
3133 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3134 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3135 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3136
3137 /* R/W: W for dummy write */
3138 nsp32_prom_write_bit(data, 0);
3139
3140 /* ack */
3141 nsp32_prom_write_bit(data, 0);
3142
3143 /* word address */
3144 for (i = 7; i >= 0; i--) {
3145 nsp32_prom_write_bit(data, ((romaddr >> i) & 1));
3146 }
3147
3148 /* ack */
3149 nsp32_prom_write_bit(data, 0);
3150
3151 /* start condition */
3152 nsp32_prom_start(data);
3153
3154 /* device address */
3155 nsp32_prom_write_bit(data, 1); /* 1 */
3156 nsp32_prom_write_bit(data, 0); /* 0 */
3157 nsp32_prom_write_bit(data, 1); /* 1 */
3158 nsp32_prom_write_bit(data, 0); /* 0 */
3159 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3160 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3161 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3162
3163 /* R/W: R */
3164 nsp32_prom_write_bit(data, 1);
3165
3166 /* ack */
3167 nsp32_prom_write_bit(data, 0);
3168
3169 /* data... */
3170 val = 0;
3171 for (i = 7; i >= 0; i--) {
3172 val += (nsp32_prom_read_bit(data) << i);
3173 }
3174
3175 /* no ack */
3176 nsp32_prom_write_bit(data, 1);
3177
3178 /* stop condition */
3179 nsp32_prom_stop(data);
3180
3181 return val;
3182}
3183
3184static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val)
3185{
3186 int base = data->BaseAddress;
3187 int tmp;
3188
3189 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL);
3190
3191 if (val == 0) {
3192 tmp &= ~bit;
3193 } else {
3194 tmp |= bit;
3195 }
3196
3197 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp);
3198
3199 udelay(10);
3200}
3201
3202static int nsp32_prom_get(nsp32_hw_data *data, int bit)
3203{
3204 int base = data->BaseAddress;
3205 int tmp, ret;
3206
3207 if (bit != SDA) {
3208 nsp32_msg(KERN_ERR, "return value is not appropriate");
3209 return 0;
3210 }
3211
3212
3213 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit;
3214
3215 if (tmp == 0) {
3216 ret = 0;
3217 } else {
3218 ret = 1;
3219 }
3220
3221 udelay(10);
3222
3223 return ret;
3224}
3225
3226static void nsp32_prom_start (nsp32_hw_data *data)
3227{
3228 /* start condition */
3229 nsp32_prom_set(data, SCL, 1);
3230 nsp32_prom_set(data, SDA, 1);
3231 nsp32_prom_set(data, ENA, 1); /* output mode */
3232 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting
3233 * SDA 1->0 is start condition */
3234 nsp32_prom_set(data, SCL, 0);
3235}
3236
3237static void nsp32_prom_stop (nsp32_hw_data *data)
3238{
3239 /* stop condition */
3240 nsp32_prom_set(data, SCL, 1);
3241 nsp32_prom_set(data, SDA, 0);
3242 nsp32_prom_set(data, ENA, 1); /* output mode */
3243 nsp32_prom_set(data, SDA, 1);
3244 nsp32_prom_set(data, SCL, 0);
3245}
3246
3247static void nsp32_prom_write_bit(nsp32_hw_data *data, int val)
3248{
3249 /* write */
3250 nsp32_prom_set(data, SDA, val);
3251 nsp32_prom_set(data, SCL, 1 );
3252 nsp32_prom_set(data, SCL, 0 );
3253}
3254
3255static int nsp32_prom_read_bit(nsp32_hw_data *data)
3256{
3257 int val;
3258
3259 /* read */
3260 nsp32_prom_set(data, ENA, 0); /* input mode */
3261 nsp32_prom_set(data, SCL, 1);
3262
3263 val = nsp32_prom_get(data, SDA);
3264
3265 nsp32_prom_set(data, SCL, 0);
3266 nsp32_prom_set(data, ENA, 1); /* output mode */
3267
3268 return val;
3269}
3270
3271
3272/**************************************************************************
3273 * Power Management
3274 */
3275#ifdef CONFIG_PM
3276
3277/* Device suspended */
3278static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state)
3279{
3280 struct Scsi_Host *host = pci_get_drvdata(pdev);
3281
3282 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state.event=%x, slot=%s, host=0x%p",
3283 pdev, state.event, pci_name(pdev), host);
3284
3285 pci_save_state (pdev);
3286 pci_disable_device (pdev);
3287 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3288
3289 return 0;
3290}
3291
3292/* Device woken up */
3293static int nsp32_resume(struct pci_dev *pdev)
3294{
3295 struct Scsi_Host *host = pci_get_drvdata(pdev);
3296 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
3297 unsigned short reg;
3298
3299 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p",
3300 pdev, pci_name(pdev), host);
3301
3302 pci_set_power_state(pdev, PCI_D0);
3303 pci_enable_wake (pdev, PCI_D0, 0);
3304 pci_restore_state (pdev);
3305
3306 reg = nsp32_read2(data->BaseAddress, INDEX_REG);
3307
3308 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg);
3309
3310 if (reg == 0xffff) {
3311 nsp32_msg(KERN_INFO, "missing device. abort resume.");
3312 return 0;
3313 }
3314
3315 nsp32hw_init (data);
3316 nsp32_do_bus_reset(data);
3317
3318 nsp32_msg(KERN_INFO, "resume success");
3319
3320 return 0;
3321}
3322
3323#endif
3324
3325/************************************************************************
3326 * PCI/Cardbus probe/remove routine
3327 */
3328static int nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3329{
3330 int ret;
3331 nsp32_hw_data *data = &nsp32_data_base;
3332
3333 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3334
3335 ret = pci_enable_device(pdev);
3336 if (ret) {
3337 nsp32_msg(KERN_ERR, "failed to enable pci device");
3338 return ret;
3339 }
3340
3341 data->Pci = pdev;
3342 data->pci_devid = id;
3343 data->IrqNumber = pdev->irq;
3344 data->BaseAddress = pci_resource_start(pdev, 0);
3345 data->NumAddress = pci_resource_len (pdev, 0);
3346 data->MmioAddress = pci_ioremap_bar(pdev, 1);
3347 data->MmioLength = pci_resource_len (pdev, 1);
3348
3349 pci_set_master(pdev);
3350
3351 ret = nsp32_detect(pdev);
3352
3353 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s",
3354 pdev->irq,
3355 data->MmioAddress, data->MmioLength,
3356 pci_name(pdev),
3357 nsp32_model[id->driver_data]);
3358
3359 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret);
3360
3361 return ret;
3362}
3363
3364static void nsp32_remove(struct pci_dev *pdev)
3365{
3366 struct Scsi_Host *host = pci_get_drvdata(pdev);
3367
3368 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3369
3370 scsi_remove_host(host);
3371
3372 nsp32_release(host);
3373
3374 scsi_host_put(host);
3375}
3376
3377static struct pci_driver nsp32_driver = {
3378 .name = "nsp32",
3379 .id_table = nsp32_pci_table,
3380 .probe = nsp32_probe,
3381 .remove = nsp32_remove,
3382#ifdef CONFIG_PM
3383 .suspend = nsp32_suspend,
3384 .resume = nsp32_resume,
3385#endif
3386};
3387
3388/*********************************************************************
3389 * Moule entry point
3390 */
3391static int __init init_nsp32(void) {
3392 nsp32_msg(KERN_INFO, "loading...");
3393 return pci_register_driver(&nsp32_driver);
3394}
3395
3396static void __exit exit_nsp32(void) {
3397 nsp32_msg(KERN_INFO, "unloading...");
3398 pci_unregister_driver(&nsp32_driver);
3399}
3400
3401module_init(init_nsp32);
3402module_exit(exit_nsp32);
3403
3404/* end */
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * NinjaSCSI-32Bi Cardbus, NinjaSCSI-32UDE PCI/CardBus SCSI driver
4 * Copyright (C) 2001, 2002, 2003
5 * YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>
6 * GOTO Masanori <gotom@debian.or.jp>, <gotom@debian.org>
7 *
8 * Revision History:
9 * 1.0: Initial Release.
10 * 1.1: Add /proc SDTR status.
11 * Remove obsolete error handler nsp32_reset.
12 * Some clean up.
13 * 1.2: PowerPC (big endian) support.
14 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/string.h>
20#include <linux/timer.h>
21#include <linux/ioport.h>
22#include <linux/major.h>
23#include <linux/blkdev.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/ctype.h>
28#include <linux/dma-mapping.h>
29
30#include <asm/dma.h>
31#include <asm/io.h>
32
33#include <scsi/scsi.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_device.h>
36#include <scsi/scsi_host.h>
37#include <scsi/scsi_ioctl.h>
38
39#include "nsp32.h"
40
41
42/***********************************************************************
43 * Module parameters
44 */
45static int trans_mode = 0; /* default: BIOS */
46module_param (trans_mode, int, 0);
47MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
48#define ASYNC_MODE 1
49#define ULTRA20M_MODE 2
50
51static bool auto_param = 0; /* default: ON */
52module_param (auto_param, bool, 0);
53MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
54
55static bool disc_priv = 1; /* default: OFF */
56module_param (disc_priv, bool, 0);
57MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
58
59MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>");
60MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module");
61MODULE_LICENSE("GPL");
62
63static const char *nsp32_release_version = "1.2";
64
65
66/****************************************************************************
67 * Supported hardware
68 */
69static struct pci_device_id nsp32_pci_table[] = {
70 {
71 .vendor = PCI_VENDOR_ID_IODATA,
72 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II,
73 .subvendor = PCI_ANY_ID,
74 .subdevice = PCI_ANY_ID,
75 .driver_data = MODEL_IODATA,
76 },
77 {
78 .vendor = PCI_VENDOR_ID_WORKBIT,
79 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME,
80 .subvendor = PCI_ANY_ID,
81 .subdevice = PCI_ANY_ID,
82 .driver_data = MODEL_KME,
83 },
84 {
85 .vendor = PCI_VENDOR_ID_WORKBIT,
86 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT,
87 .subvendor = PCI_ANY_ID,
88 .subdevice = PCI_ANY_ID,
89 .driver_data = MODEL_WORKBIT,
90 },
91 {
92 .vendor = PCI_VENDOR_ID_WORKBIT,
93 .device = PCI_DEVICE_ID_WORKBIT_STANDARD,
94 .subvendor = PCI_ANY_ID,
95 .subdevice = PCI_ANY_ID,
96 .driver_data = MODEL_PCI_WORKBIT,
97 },
98 {
99 .vendor = PCI_VENDOR_ID_WORKBIT,
100 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC,
101 .subvendor = PCI_ANY_ID,
102 .subdevice = PCI_ANY_ID,
103 .driver_data = MODEL_LOGITEC,
104 },
105 {
106 .vendor = PCI_VENDOR_ID_WORKBIT,
107 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC,
108 .subvendor = PCI_ANY_ID,
109 .subdevice = PCI_ANY_ID,
110 .driver_data = MODEL_PCI_LOGITEC,
111 },
112 {
113 .vendor = PCI_VENDOR_ID_WORKBIT,
114 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO,
115 .subvendor = PCI_ANY_ID,
116 .subdevice = PCI_ANY_ID,
117 .driver_data = MODEL_PCI_MELCO,
118 },
119 {
120 .vendor = PCI_VENDOR_ID_WORKBIT,
121 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II,
122 .subvendor = PCI_ANY_ID,
123 .subdevice = PCI_ANY_ID,
124 .driver_data = MODEL_PCI_MELCO,
125 },
126 {0,0,},
127};
128MODULE_DEVICE_TABLE(pci, nsp32_pci_table);
129
130static nsp32_hw_data nsp32_data_base; /* probe <-> detect glue */
131
132
133/*
134 * Period/AckWidth speed conversion table
135 *
136 * Note: This period/ackwidth speed table must be in descending order.
137 */
138static nsp32_sync_table nsp32_sync_table_40M[] = {
139 /* {PNo, AW, SP, EP, SREQ smpl} Speed(MB/s) Period AckWidth */
140 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */
141 {0x2, 0, 0x0d, 0x18, SMPL_40M}, /* 13.3 : 75ns, 25ns */
142 {0x3, 1, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
143 {0x4, 1, 0x1a, 0x1f, SMPL_20M}, /* 8.0 : 125ns, 50ns */
144 {0x5, 2, 0x20, 0x25, SMPL_20M}, /* 6.7 : 150ns, 75ns */
145 {0x6, 2, 0x26, 0x31, SMPL_20M}, /* 5.7 : 175ns, 75ns */
146 {0x7, 3, 0x32, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
147 {0x8, 3, 0x33, 0x38, SMPL_10M}, /* 4.4 : 225ns, 100ns */
148 {0x9, 3, 0x39, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
149};
150
151static nsp32_sync_table nsp32_sync_table_20M[] = {
152 {0x1, 0, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
153 {0x2, 0, 0x1a, 0x25, SMPL_20M}, /* 6.7 : 150ns, 50ns */
154 {0x3, 1, 0x26, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
155 {0x4, 1, 0x33, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
156 {0x5, 2, 0x3f, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 150ns */
157 {0x6, 2, 0x4c, 0x57, SMPL_10M}, /* 2.8 : 350ns, 150ns */
158 {0x7, 3, 0x58, 0x64, SMPL_10M}, /* 2.5 : 400ns, 200ns */
159 {0x8, 3, 0x65, 0x70, SMPL_10M}, /* 2.2 : 450ns, 200ns */
160 {0x9, 3, 0x71, 0x7d, SMPL_10M}, /* 2.0 : 500ns, 200ns */
161};
162
163static nsp32_sync_table nsp32_sync_table_pci[] = {
164 {0x1, 0, 0x0c, 0x0f, SMPL_40M}, /* 16.6 : 60ns, 30ns */
165 {0x2, 0, 0x10, 0x16, SMPL_40M}, /* 11.1 : 90ns, 30ns */
166 {0x3, 1, 0x17, 0x1e, SMPL_20M}, /* 8.3 : 120ns, 60ns */
167 {0x4, 1, 0x1f, 0x25, SMPL_20M}, /* 6.7 : 150ns, 60ns */
168 {0x5, 2, 0x26, 0x2d, SMPL_20M}, /* 5.6 : 180ns, 90ns */
169 {0x6, 2, 0x2e, 0x34, SMPL_10M}, /* 4.8 : 210ns, 90ns */
170 {0x7, 3, 0x35, 0x3c, SMPL_10M}, /* 4.2 : 240ns, 120ns */
171 {0x8, 3, 0x3d, 0x43, SMPL_10M}, /* 3.7 : 270ns, 120ns */
172 {0x9, 3, 0x44, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 120ns */
173};
174
175/*
176 * function declaration
177 */
178/* module entry point */
179static int nsp32_probe (struct pci_dev *, const struct pci_device_id *);
180static void nsp32_remove(struct pci_dev *);
181static int __init init_nsp32 (void);
182static void __exit exit_nsp32 (void);
183
184/* struct struct scsi_host_template */
185static int nsp32_show_info (struct seq_file *, struct Scsi_Host *);
186
187static int nsp32_detect (struct pci_dev *pdev);
188static int nsp32_queuecommand(struct Scsi_Host *, struct scsi_cmnd *);
189static const char *nsp32_info (struct Scsi_Host *);
190static int nsp32_release (struct Scsi_Host *);
191
192/* SCSI error handler */
193static int nsp32_eh_abort (struct scsi_cmnd *);
194static int nsp32_eh_host_reset(struct scsi_cmnd *);
195
196/* generate SCSI message */
197static void nsp32_build_identify(struct scsi_cmnd *);
198static void nsp32_build_nop (struct scsi_cmnd *);
199static void nsp32_build_reject (struct scsi_cmnd *);
200static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char,
201 unsigned char);
202
203/* SCSI message handler */
204static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short);
205static void nsp32_msgout_occur (struct scsi_cmnd *);
206static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long,
207 unsigned short);
208
209static int nsp32_setup_sg_table (struct scsi_cmnd *);
210static int nsp32_selection_autopara(struct scsi_cmnd *);
211static int nsp32_selection_autoscsi(struct scsi_cmnd *);
212static void nsp32_scsi_done (struct scsi_cmnd *);
213static int nsp32_arbitration (struct scsi_cmnd *, unsigned int);
214static int nsp32_reselection (struct scsi_cmnd *, unsigned char);
215static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int);
216static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short);
217
218/* SCSI SDTR */
219static void nsp32_analyze_sdtr (struct scsi_cmnd *);
220static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *,
221 unsigned char);
222static void nsp32_set_async (nsp32_hw_data *, nsp32_target *);
223static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *,
224 unsigned char *, unsigned char *);
225static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *,
226 int, unsigned char);
227
228/* SCSI bus status handler */
229static void nsp32_wait_req (nsp32_hw_data *, int);
230static void nsp32_wait_sack (nsp32_hw_data *, int);
231static void nsp32_sack_assert (nsp32_hw_data *);
232static void nsp32_sack_negate (nsp32_hw_data *);
233static void nsp32_do_bus_reset(nsp32_hw_data *);
234
235/* hardware interrupt handler */
236static irqreturn_t do_nsp32_isr(int, void *);
237
238/* initialize hardware */
239static int nsp32hw_init(nsp32_hw_data *);
240
241/* EEPROM handler */
242static int nsp32_getprom_param (nsp32_hw_data *);
243static int nsp32_getprom_at24 (nsp32_hw_data *);
244static int nsp32_getprom_c16 (nsp32_hw_data *);
245static void nsp32_prom_start (nsp32_hw_data *);
246static void nsp32_prom_stop (nsp32_hw_data *);
247static int nsp32_prom_read (nsp32_hw_data *, int);
248static int nsp32_prom_read_bit (nsp32_hw_data *);
249static void nsp32_prom_write_bit(nsp32_hw_data *, int);
250static void nsp32_prom_set (nsp32_hw_data *, int, int);
251static int nsp32_prom_get (nsp32_hw_data *, int);
252
253/* debug/warning/info message */
254static void nsp32_message (const char *, int, char *, char *, ...);
255#ifdef NSP32_DEBUG
256static void nsp32_dmessage(const char *, int, int, char *, ...);
257#endif
258
259/*
260 * max_sectors is currently limited up to 128.
261 */
262static struct scsi_host_template nsp32_template = {
263 .proc_name = "nsp32",
264 .name = "Workbit NinjaSCSI-32Bi/UDE",
265 .show_info = nsp32_show_info,
266 .info = nsp32_info,
267 .queuecommand = nsp32_queuecommand,
268 .can_queue = 1,
269 .sg_tablesize = NSP32_SG_SIZE,
270 .max_sectors = 128,
271 .this_id = NSP32_HOST_SCSIID,
272 .dma_boundary = PAGE_SIZE - 1,
273 .eh_abort_handler = nsp32_eh_abort,
274 .eh_host_reset_handler = nsp32_eh_host_reset,
275/* .highmem_io = 1, */
276};
277
278#include "nsp32_io.h"
279
280/***********************************************************************
281 * debug, error print
282 */
283#ifndef NSP32_DEBUG
284# define NSP32_DEBUG_MASK 0x000000
285# define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args)
286# define nsp32_dbg(mask, args...) /* */
287#else
288# define NSP32_DEBUG_MASK 0xffffff
289# define nsp32_msg(type, args...) \
290 nsp32_message (__func__, __LINE__, (type), args)
291# define nsp32_dbg(mask, args...) \
292 nsp32_dmessage(__func__, __LINE__, (mask), args)
293#endif
294
295#define NSP32_DEBUG_QUEUECOMMAND BIT(0)
296#define NSP32_DEBUG_REGISTER BIT(1)
297#define NSP32_DEBUG_AUTOSCSI BIT(2)
298#define NSP32_DEBUG_INTR BIT(3)
299#define NSP32_DEBUG_SGLIST BIT(4)
300#define NSP32_DEBUG_BUSFREE BIT(5)
301#define NSP32_DEBUG_CDB_CONTENTS BIT(6)
302#define NSP32_DEBUG_RESELECTION BIT(7)
303#define NSP32_DEBUG_MSGINOCCUR BIT(8)
304#define NSP32_DEBUG_EEPROM BIT(9)
305#define NSP32_DEBUG_MSGOUTOCCUR BIT(10)
306#define NSP32_DEBUG_BUSRESET BIT(11)
307#define NSP32_DEBUG_RESTART BIT(12)
308#define NSP32_DEBUG_SYNC BIT(13)
309#define NSP32_DEBUG_WAIT BIT(14)
310#define NSP32_DEBUG_TARGETFLAG BIT(15)
311#define NSP32_DEBUG_PROC BIT(16)
312#define NSP32_DEBUG_INIT BIT(17)
313#define NSP32_SPECIAL_PRINT_REGISTER BIT(20)
314
315#define NSP32_DEBUG_BUF_LEN 100
316
317__printf(4, 5)
318static void nsp32_message(const char *func, int line, char *type, char *fmt, ...)
319{
320 va_list args;
321 char buf[NSP32_DEBUG_BUF_LEN];
322
323 va_start(args, fmt);
324 vsnprintf(buf, sizeof(buf), fmt, args);
325 va_end(args);
326
327#ifndef NSP32_DEBUG
328 printk("%snsp32: %s\n", type, buf);
329#else
330 printk("%snsp32: %s (%d): %s\n", type, func, line, buf);
331#endif
332}
333
334#ifdef NSP32_DEBUG
335static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...)
336{
337 va_list args;
338 char buf[NSP32_DEBUG_BUF_LEN];
339
340 va_start(args, fmt);
341 vsnprintf(buf, sizeof(buf), fmt, args);
342 va_end(args);
343
344 if (mask & NSP32_DEBUG_MASK) {
345 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf);
346 }
347}
348#endif
349
350#ifdef NSP32_DEBUG
351# include "nsp32_debug.c"
352#else
353# define show_command(arg) /* */
354# define show_busphase(arg) /* */
355# define show_autophase(arg) /* */
356#endif
357
358/*
359 * IDENTIFY Message
360 */
361static void nsp32_build_identify(struct scsi_cmnd *SCpnt)
362{
363 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
364 int pos = data->msgout_len;
365 int mode = FALSE;
366
367 /* XXX: Auto DiscPriv detection is progressing... */
368 if (disc_priv == 0) {
369 /* mode = TRUE; */
370 }
371
372 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++;
373
374 data->msgout_len = pos;
375}
376
377/*
378 * SDTR Message Routine
379 */
380static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt,
381 unsigned char period,
382 unsigned char offset)
383{
384 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
385 int pos = data->msgout_len;
386
387 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++;
388 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++;
389 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++;
390 data->msgoutbuf[pos] = period; pos++;
391 data->msgoutbuf[pos] = offset; pos++;
392
393 data->msgout_len = pos;
394}
395
396/*
397 * No Operation Message
398 */
399static void nsp32_build_nop(struct scsi_cmnd *SCpnt)
400{
401 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
402 int pos = data->msgout_len;
403
404 if (pos != 0) {
405 nsp32_msg(KERN_WARNING,
406 "Some messages are already contained!");
407 return;
408 }
409
410 data->msgoutbuf[pos] = NOP; pos++;
411 data->msgout_len = pos;
412}
413
414/*
415 * Reject Message
416 */
417static void nsp32_build_reject(struct scsi_cmnd *SCpnt)
418{
419 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
420 int pos = data->msgout_len;
421
422 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++;
423 data->msgout_len = pos;
424}
425
426/*
427 * timer
428 */
429#if 0
430static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time)
431{
432 unsigned int base = SCpnt->host->io_port;
433
434 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
435
436 if (time & (~TIMER_CNT_MASK)) {
437 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
438 }
439
440 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK);
441}
442#endif
443
444
445/*
446 * set SCSI command and other parameter to asic, and start selection phase
447 */
448static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt)
449{
450 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
451 unsigned int base = SCpnt->device->host->io_port;
452 unsigned int host_id = SCpnt->device->host->this_id;
453 unsigned char target = scmd_id(SCpnt);
454 nsp32_autoparam *param = data->autoparam;
455 unsigned char phase;
456 int i, ret;
457 unsigned int msgout;
458 u16_le s;
459
460 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
461
462 /*
463 * check bus free
464 */
465 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
466 if (phase != BUSMON_BUS_FREE) {
467 nsp32_msg(KERN_WARNING, "bus busy");
468 show_busphase(phase & BUSMON_PHASE_MASK);
469 SCpnt->result = DID_BUS_BUSY << 16;
470 return FALSE;
471 }
472
473 /*
474 * message out
475 *
476 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
477 * over 3 messages needs another routine.
478 */
479 if (data->msgout_len == 0) {
480 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
481 SCpnt->result = DID_ERROR << 16;
482 return FALSE;
483 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
484 msgout = 0;
485 for (i = 0; i < data->msgout_len; i++) {
486 /*
487 * the sending order of the message is:
488 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
489 * MCNT 2: MSG#1 -> MSG#2
490 * MCNT 1: MSG#2
491 */
492 msgout >>= 8;
493 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
494 }
495 msgout |= MV_VALID; /* MV valid */
496 msgout |= (unsigned int)data->msgout_len; /* len */
497 } else {
498 /* data->msgout_len > 3 */
499 msgout = 0;
500 }
501
502 // nsp_dbg(NSP32_DEBUG_AUTOSCSI, "sel time out=0x%x\n",
503 // nsp32_read2(base, SEL_TIME_OUT));
504 // nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
505
506 /*
507 * setup asic parameter
508 */
509 memset(param, 0, sizeof(nsp32_autoparam));
510
511 /* cdb */
512 for (i = 0; i < SCpnt->cmd_len; i++) {
513 param->cdb[4 * i] = SCpnt->cmnd[i];
514 }
515
516 /* outgoing messages */
517 param->msgout = cpu_to_le32(msgout);
518
519 /* syncreg, ackwidth, target id, SREQ sampling rate */
520 param->syncreg = data->cur_target->syncreg;
521 param->ackwidth = data->cur_target->ackwidth;
522 param->target_id = BIT(host_id) | BIT(target);
523 param->sample_reg = data->cur_target->sample_reg;
524
525 // nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "sample rate=0x%x\n", data->cur_target->sample_reg);
526
527 /* command control */
528 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER |
529 AUTOSCSI_START |
530 AUTO_MSGIN_00_OR_04 |
531 AUTO_MSGIN_02 |
532 AUTO_ATN );
533
534
535 /* transfer control */
536 s = 0;
537 switch (data->trans_method) {
538 case NSP32_TRANSFER_BUSMASTER:
539 s |= BM_START;
540 break;
541 case NSP32_TRANSFER_MMIO:
542 s |= CB_MMIO_MODE;
543 break;
544 case NSP32_TRANSFER_PIO:
545 s |= CB_IO_MODE;
546 break;
547 default:
548 nsp32_msg(KERN_ERR, "unknown trans_method");
549 break;
550 }
551 /*
552 * OR-ed BLIEND_MODE, FIFO intr is decreased, instead of PCI bus waits.
553 * For bus master transfer, it's taken off.
554 */
555 s |= (TRANSFER_GO | ALL_COUNTER_CLR);
556 param->transfer_control = cpu_to_le16(s);
557
558 /* sg table addr */
559 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr);
560
561 /*
562 * transfer parameter to ASIC
563 */
564 nsp32_write4(base, SGT_ADR, data->auto_paddr);
565 nsp32_write2(base, COMMAND_CONTROL,
566 CLEAR_CDB_FIFO_POINTER | AUTO_PARAMETER );
567
568 /*
569 * Check arbitration
570 */
571 ret = nsp32_arbitration(SCpnt, base);
572
573 return ret;
574}
575
576
577/*
578 * Selection with AUTO SCSI (without AUTO PARAMETER)
579 */
580static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt)
581{
582 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
583 unsigned int base = SCpnt->device->host->io_port;
584 unsigned int host_id = SCpnt->device->host->this_id;
585 unsigned char target = scmd_id(SCpnt);
586 unsigned char phase;
587 int status;
588 unsigned short command = 0;
589 unsigned int msgout = 0;
590 int i;
591
592 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
593
594 /*
595 * IRQ disable
596 */
597 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
598
599 /*
600 * check bus line
601 */
602 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
603 if ((phase & BUSMON_BSY) || (phase & BUSMON_SEL)) {
604 nsp32_msg(KERN_WARNING, "bus busy");
605 SCpnt->result = DID_BUS_BUSY << 16;
606 status = 1;
607 goto out;
608 }
609
610 /*
611 * clear execph
612 */
613 nsp32_read2(base, SCSI_EXECUTE_PHASE);
614
615 /*
616 * clear FIFO counter to set CDBs
617 */
618 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER);
619
620 /*
621 * set CDB0 - CDB15
622 */
623 for (i = 0; i < SCpnt->cmd_len; i++) {
624 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]);
625 }
626 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]);
627
628 /*
629 * set SCSIOUT LATCH(initiator)/TARGET(target) (OR-ed) ID
630 */
631 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID,
632 BIT(host_id) | BIT(target));
633
634 /*
635 * set SCSI MSGOUT REG
636 *
637 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
638 * over 3 messages needs another routine.
639 */
640 if (data->msgout_len == 0) {
641 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
642 SCpnt->result = DID_ERROR << 16;
643 status = 1;
644 goto out;
645 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
646 msgout = 0;
647 for (i = 0; i < data->msgout_len; i++) {
648 /*
649 * the sending order of the message is:
650 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
651 * MCNT 2: MSG#1 -> MSG#2
652 * MCNT 1: MSG#2
653 */
654 msgout >>= 8;
655 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
656 }
657 msgout |= MV_VALID; /* MV valid */
658 msgout |= (unsigned int)data->msgout_len; /* len */
659 nsp32_write4(base, SCSI_MSG_OUT, msgout);
660 } else {
661 /* data->msgout_len > 3 */
662 nsp32_write4(base, SCSI_MSG_OUT, 0);
663 }
664
665 /*
666 * set selection timeout(= 250ms)
667 */
668 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
669
670 /*
671 * set SREQ hazard killer sampling rate
672 *
673 * TODO: sample_rate (BASE+0F) is 0 when internal clock = 40MHz.
674 * check other internal clock!
675 */
676 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
677
678 /*
679 * clear Arbit
680 */
681 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
682
683 /*
684 * set SYNCREG
685 * Don't set BM_START_ADR before setting this register.
686 */
687 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
688
689 /*
690 * set ACKWIDTH
691 */
692 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
693
694 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
695 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x",
696 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH),
697 nsp32_read4(base, SGT_ADR),
698 nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID));
699 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x",
700 data->msgout_len, msgout);
701
702 /*
703 * set SGT ADDR (physical address)
704 */
705 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
706
707 /*
708 * set TRANSFER CONTROL REG
709 */
710 command = 0;
711 command |= (TRANSFER_GO | ALL_COUNTER_CLR);
712 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
713 if (scsi_bufflen(SCpnt) > 0) {
714 command |= BM_START;
715 }
716 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
717 command |= CB_MMIO_MODE;
718 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
719 command |= CB_IO_MODE;
720 }
721 nsp32_write2(base, TRANSFER_CONTROL, command);
722
723 /*
724 * start AUTO SCSI, kick off arbitration
725 */
726 command = (CLEAR_CDB_FIFO_POINTER |
727 AUTOSCSI_START |
728 AUTO_MSGIN_00_OR_04 |
729 AUTO_MSGIN_02 |
730 AUTO_ATN);
731 nsp32_write2(base, COMMAND_CONTROL, command);
732
733 /*
734 * Check arbitration
735 */
736 status = nsp32_arbitration(SCpnt, base);
737
738 out:
739 /*
740 * IRQ enable
741 */
742 nsp32_write2(base, IRQ_CONTROL, 0);
743
744 return status;
745}
746
747
748/*
749 * Arbitration Status Check
750 *
751 * Note: Arbitration counter is waited during ARBIT_GO is not lifting.
752 * Using udelay(1) consumes CPU time and system time, but
753 * arbitration delay time is defined minimal 2.4us in SCSI
754 * specification, thus udelay works as coarse grained wait timer.
755 */
756static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base)
757{
758 unsigned char arbit;
759 int status = TRUE;
760 int time = 0;
761
762 do {
763 arbit = nsp32_read1(base, ARBIT_STATUS);
764 time++;
765 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 &&
766 (time <= ARBIT_TIMEOUT_TIME));
767
768 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
769 "arbit: 0x%x, delay time: %d", arbit, time);
770
771 if (arbit & ARBIT_WIN) {
772 /* Arbitration succeeded */
773 SCpnt->result = DID_OK << 16;
774 nsp32_index_write1(base, EXT_PORT, LED_ON); /* PCI LED on */
775 } else if (arbit & ARBIT_FAIL) {
776 /* Arbitration failed */
777 SCpnt->result = DID_BUS_BUSY << 16;
778 status = FALSE;
779 } else {
780 /*
781 * unknown error or ARBIT_GO timeout,
782 * something lock up! guess no connection.
783 */
784 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout");
785 SCpnt->result = DID_NO_CONNECT << 16;
786 status = FALSE;
787 }
788
789 /*
790 * clear Arbit
791 */
792 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
793
794 return status;
795}
796
797
798/*
799 * reselection
800 *
801 * Note: This reselection routine is called from msgin_occur,
802 * reselection target id&lun must be already set.
803 * SCSI-2 says IDENTIFY implies RESTORE_POINTER operation.
804 */
805static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun)
806{
807 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
808 unsigned int host_id = SCpnt->device->host->this_id;
809 unsigned int base = SCpnt->device->host->io_port;
810 unsigned char tmpid, newid;
811
812 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter");
813
814 /*
815 * calculate reselected SCSI ID
816 */
817 tmpid = nsp32_read1(base, RESELECT_ID);
818 tmpid &= (~BIT(host_id));
819 newid = 0;
820 while (tmpid) {
821 if (tmpid & 1) {
822 break;
823 }
824 tmpid >>= 1;
825 newid++;
826 }
827
828 /*
829 * If reselected New ID:LUN is not existed
830 * or current nexus is not existed, unexpected
831 * reselection is occurred. Send reject message.
832 */
833 if (newid >= ARRAY_SIZE(data->lunt) ||
834 newlun >= ARRAY_SIZE(data->lunt[0])) {
835 nsp32_msg(KERN_WARNING, "unknown id/lun");
836 return FALSE;
837 } else if(data->lunt[newid][newlun].SCpnt == NULL) {
838 nsp32_msg(KERN_WARNING, "no SCSI command is processing");
839 return FALSE;
840 }
841
842 data->cur_id = newid;
843 data->cur_lun = newlun;
844 data->cur_target = &(data->target[newid]);
845 data->cur_lunt = &(data->lunt[newid][newlun]);
846
847 /* reset SACK/SavedACK counter (or ALL clear?) */
848 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
849
850 return TRUE;
851}
852
853
854/*
855 * nsp32_setup_sg_table - build scatter gather list for transfer data
856 * with bus master.
857 *
858 * Note: NinjaSCSI-32Bi/UDE bus master can not transfer over 64KB at a time.
859 */
860static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt)
861{
862 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
863 struct scatterlist *sg;
864 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
865 int num, i;
866 u32_le l;
867
868 if (sgt == NULL) {
869 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null");
870 return FALSE;
871 }
872
873 num = scsi_dma_map(SCpnt);
874 if (!num)
875 return TRUE;
876 else if (num < 0)
877 return FALSE;
878 else {
879 scsi_for_each_sg(SCpnt, sg, num, i) {
880 /*
881 * Build nsp32_sglist, substitute sg dma addresses.
882 */
883 sgt[i].addr = cpu_to_le32(sg_dma_address(sg));
884 sgt[i].len = cpu_to_le32(sg_dma_len(sg));
885
886 if (le32_to_cpu(sgt[i].len) > 0x10000) {
887 nsp32_msg(KERN_ERR,
888 "can't transfer over 64KB at a time, "
889 "size=0x%x", le32_to_cpu(sgt[i].len));
890 return FALSE;
891 }
892 nsp32_dbg(NSP32_DEBUG_SGLIST,
893 "num 0x%x : addr 0x%lx len 0x%lx",
894 i,
895 le32_to_cpu(sgt[i].addr),
896 le32_to_cpu(sgt[i].len ));
897 }
898
899 /* set end mark */
900 l = le32_to_cpu(sgt[num-1].len);
901 sgt[num-1].len = cpu_to_le32(l | SGTEND);
902 }
903
904 return TRUE;
905}
906
907static int nsp32_queuecommand_lck(struct scsi_cmnd *SCpnt,
908 void (*done)(struct scsi_cmnd *))
909{
910 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
911 nsp32_target *target;
912 nsp32_lunt *cur_lunt;
913 int ret;
914
915 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
916 "enter. target: 0x%x LUN: 0x%llx cmnd: 0x%x cmndlen: 0x%x "
917 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x",
918 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0],
919 SCpnt->cmd_len, scsi_sg_count(SCpnt), scsi_sglist(SCpnt),
920 scsi_bufflen(SCpnt));
921
922 if (data->CurrentSC != NULL) {
923 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request");
924 data->CurrentSC = NULL;
925 SCpnt->result = DID_NO_CONNECT << 16;
926 done(SCpnt);
927 return 0;
928 }
929
930 /* check target ID is not same as this initiator ID */
931 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) {
932 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "target==host???");
933 SCpnt->result = DID_BAD_TARGET << 16;
934 done(SCpnt);
935 return 0;
936 }
937
938 /* check target LUN is allowable value */
939 if (SCpnt->device->lun >= MAX_LUN) {
940 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun");
941 SCpnt->result = DID_BAD_TARGET << 16;
942 done(SCpnt);
943 return 0;
944 }
945
946 show_command(SCpnt);
947
948 SCpnt->scsi_done = done;
949 data->CurrentSC = SCpnt;
950 SCpnt->SCp.Status = SAM_STAT_CHECK_CONDITION;
951 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt));
952
953 SCpnt->SCp.ptr = (char *)scsi_sglist(SCpnt);
954 SCpnt->SCp.this_residual = scsi_bufflen(SCpnt);
955 SCpnt->SCp.buffer = NULL;
956 SCpnt->SCp.buffers_residual = 0;
957
958 /* initialize data */
959 data->msgout_len = 0;
960 data->msgin_len = 0;
961 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]);
962 cur_lunt->SCpnt = SCpnt;
963 cur_lunt->save_datp = 0;
964 cur_lunt->msgin03 = FALSE;
965 data->cur_lunt = cur_lunt;
966 data->cur_id = SCpnt->device->id;
967 data->cur_lun = SCpnt->device->lun;
968
969 ret = nsp32_setup_sg_table(SCpnt);
970 if (ret == FALSE) {
971 nsp32_msg(KERN_ERR, "SGT fail");
972 SCpnt->result = DID_ERROR << 16;
973 nsp32_scsi_done(SCpnt);
974 return 0;
975 }
976
977 /* Build IDENTIFY */
978 nsp32_build_identify(SCpnt);
979
980 /*
981 * If target is the first time to transfer after the reset
982 * (target don't have SDTR_DONE and SDTR_INITIATOR), sync
983 * message SDTR is needed to do synchronous transfer.
984 */
985 target = &data->target[scmd_id(SCpnt)];
986 data->cur_target = target;
987
988 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) {
989 unsigned char period, offset;
990
991 if (trans_mode != ASYNC_MODE) {
992 nsp32_set_max_sync(data, target, &period, &offset);
993 nsp32_build_sdtr(SCpnt, period, offset);
994 target->sync_flag |= SDTR_INITIATOR;
995 } else {
996 nsp32_set_async(data, target);
997 target->sync_flag |= SDTR_DONE;
998 }
999
1000 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1001 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n",
1002 target->limit_entry, period, offset);
1003 } else if (target->sync_flag & SDTR_INITIATOR) {
1004 /*
1005 * It was negotiating SDTR with target, sending from the
1006 * initiator, but there are no chance to remove this flag.
1007 * Set async because we don't get proper negotiation.
1008 */
1009 nsp32_set_async(data, target);
1010 target->sync_flag &= ~SDTR_INITIATOR;
1011 target->sync_flag |= SDTR_DONE;
1012
1013 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1014 "SDTR_INITIATOR: fall back to async");
1015 } else if (target->sync_flag & SDTR_TARGET) {
1016 /*
1017 * It was negotiating SDTR with target, sending from target,
1018 * but there are no chance to remove this flag. Set async
1019 * because we don't get proper negotiation.
1020 */
1021 nsp32_set_async(data, target);
1022 target->sync_flag &= ~SDTR_TARGET;
1023 target->sync_flag |= SDTR_DONE;
1024
1025 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1026 "Unknown SDTR from target is reached, fall back to async.");
1027 }
1028
1029 nsp32_dbg(NSP32_DEBUG_TARGETFLAG,
1030 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x",
1031 SCpnt->device->id, target->sync_flag, target->syncreg,
1032 target->ackwidth);
1033
1034 /* Selection */
1035 if (auto_param == 0) {
1036 ret = nsp32_selection_autopara(SCpnt);
1037 } else {
1038 ret = nsp32_selection_autoscsi(SCpnt);
1039 }
1040
1041 if (ret != TRUE) {
1042 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail");
1043 nsp32_scsi_done(SCpnt);
1044 }
1045
1046 return 0;
1047}
1048
1049static DEF_SCSI_QCMD(nsp32_queuecommand)
1050
1051/* initialize asic */
1052static int nsp32hw_init(nsp32_hw_data *data)
1053{
1054 unsigned int base = data->BaseAddress;
1055 unsigned short irq_stat;
1056 unsigned long lc_reg;
1057 unsigned char power;
1058
1059 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE);
1060 if ((lc_reg & 0xff00) == 0) {
1061 lc_reg |= (0x20 << 8);
1062 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff);
1063 }
1064
1065 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1066 nsp32_write2(base, TRANSFER_CONTROL, 0);
1067 nsp32_write4(base, BM_CNT, 0);
1068 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1069
1070 do {
1071 irq_stat = nsp32_read2(base, IRQ_STATUS);
1072 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat);
1073 } while (irq_stat & IRQSTATUS_ANY_IRQ);
1074
1075 /*
1076 * Fill FIFO_FULL_SHLD, FIFO_EMPTY_SHLD. Below parameter is
1077 * designated by specification.
1078 */
1079 if ((data->trans_method & NSP32_TRANSFER_PIO) ||
1080 (data->trans_method & NSP32_TRANSFER_MMIO)) {
1081 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40);
1082 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40);
1083 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1084 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10);
1085 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60);
1086 } else {
1087 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode");
1088 }
1089
1090 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x",
1091 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT),
1092 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT));
1093
1094 nsp32_index_write1(base, CLOCK_DIV, data->clock);
1095 nsp32_index_write1(base, BM_CYCLE,
1096 MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD);
1097 nsp32_write1(base, PARITY_CONTROL, 0); /* parity check is disable */
1098
1099 /*
1100 * initialize MISC_WRRD register
1101 *
1102 * Note: Designated parameters is obeyed as following:
1103 * MISC_SCSI_DIRECTION_DETECTOR_SELECT: It must be set.
1104 * MISC_MASTER_TERMINATION_SELECT: It must be set.
1105 * MISC_BMREQ_NEGATE_TIMING_SEL: It should be set.
1106 * MISC_AUTOSEL_TIMING_SEL: It should be set.
1107 * MISC_BMSTOP_CHANGE2_NONDATA_PHASE: It should be set.
1108 * MISC_DELAYED_BMSTART: It's selected for safety.
1109 *
1110 * Note: If MISC_BMSTOP_CHANGE2_NONDATA_PHASE is set, then
1111 * we have to set TRANSFERCONTROL_BM_START as 0 and set
1112 * appropriate value before restarting bus master transfer.
1113 */
1114 nsp32_index_write2(base, MISC_WR,
1115 (SCSI_DIRECTION_DETECTOR_SELECT |
1116 DELAYED_BMSTART |
1117 MASTER_TERMINATION_SELECT |
1118 BMREQ_NEGATE_TIMING_SEL |
1119 AUTOSEL_TIMING_SEL |
1120 BMSTOP_CHANGE2_NONDATA_PHASE));
1121
1122 nsp32_index_write1(base, TERM_PWR_CONTROL, 0);
1123 power = nsp32_index_read1(base, TERM_PWR_CONTROL);
1124 if (!(power & SENSE)) {
1125 nsp32_msg(KERN_INFO, "term power on");
1126 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR);
1127 }
1128
1129 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1130 nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */
1131
1132 nsp32_write1(base, SYNC_REG, 0);
1133 nsp32_write1(base, ACK_WIDTH, 0);
1134 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
1135
1136 /*
1137 * enable to select designated IRQ (except for
1138 * IRQSELECT_SERR, IRQSELECT_PERR, IRQSELECT_BMCNTERR)
1139 */
1140 nsp32_index_write2(base, IRQ_SELECT,
1141 IRQSELECT_TIMER_IRQ |
1142 IRQSELECT_SCSIRESET_IRQ |
1143 IRQSELECT_FIFO_SHLD_IRQ |
1144 IRQSELECT_RESELECT_IRQ |
1145 IRQSELECT_PHASE_CHANGE_IRQ |
1146 IRQSELECT_AUTO_SCSI_SEQ_IRQ |
1147 // IRQSELECT_BMCNTERR_IRQ |
1148 IRQSELECT_TARGET_ABORT_IRQ |
1149 IRQSELECT_MASTER_ABORT_IRQ );
1150 nsp32_write2(base, IRQ_CONTROL, 0);
1151
1152 /* PCI LED off */
1153 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF);
1154 nsp32_index_write1(base, EXT_PORT, LED_OFF);
1155
1156 return TRUE;
1157}
1158
1159
1160/* interrupt routine */
1161static irqreturn_t do_nsp32_isr(int irq, void *dev_id)
1162{
1163 nsp32_hw_data *data = dev_id;
1164 unsigned int base = data->BaseAddress;
1165 struct scsi_cmnd *SCpnt = data->CurrentSC;
1166 unsigned short auto_stat, irq_stat, trans_stat;
1167 unsigned char busmon, busphase;
1168 unsigned long flags;
1169 int ret;
1170 int handled = 0;
1171 struct Scsi_Host *host = data->Host;
1172
1173 spin_lock_irqsave(host->host_lock, flags);
1174
1175 /*
1176 * IRQ check, then enable IRQ mask
1177 */
1178 irq_stat = nsp32_read2(base, IRQ_STATUS);
1179 nsp32_dbg(NSP32_DEBUG_INTR,
1180 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat);
1181 /* is this interrupt comes from Ninja asic? */
1182 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) {
1183 nsp32_dbg(NSP32_DEBUG_INTR,
1184 "shared interrupt: irq other 0x%x", irq_stat);
1185 goto out2;
1186 }
1187 handled = 1;
1188 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1189
1190 busmon = nsp32_read1(base, SCSI_BUS_MONITOR);
1191 busphase = busmon & BUSMON_PHASE_MASK;
1192
1193 trans_stat = nsp32_read2(base, TRANSFER_STATUS);
1194 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) {
1195 nsp32_msg(KERN_INFO, "card disconnect");
1196 if (data->CurrentSC != NULL) {
1197 nsp32_msg(KERN_INFO, "clean up current SCSI command");
1198 SCpnt->result = DID_BAD_TARGET << 16;
1199 nsp32_scsi_done(SCpnt);
1200 }
1201 goto out;
1202 }
1203
1204 /* Timer IRQ */
1205 if (irq_stat & IRQSTATUS_TIMER_IRQ) {
1206 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1207 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1208 goto out;
1209 }
1210
1211 /* SCSI reset */
1212 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) {
1213 nsp32_msg(KERN_INFO, "detected someone do bus reset");
1214 nsp32_do_bus_reset(data);
1215 if (SCpnt != NULL) {
1216 SCpnt->result = DID_RESET << 16;
1217 nsp32_scsi_done(SCpnt);
1218 }
1219 goto out;
1220 }
1221
1222 if (SCpnt == NULL) {
1223 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened");
1224 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x",
1225 irq_stat, trans_stat);
1226 goto out;
1227 }
1228
1229 /*
1230 * AutoSCSI Interrupt.
1231 * Note: This interrupt is occurred when AutoSCSI is finished. Then
1232 * check SCSIEXECUTEPHASE, and do appropriate action. Each phases are
1233 * recorded when AutoSCSI sequencer has been processed.
1234 */
1235 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) {
1236 /* getting SCSI executed phase */
1237 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE);
1238 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1239
1240 /* Selection Timeout, go busfree phase. */
1241 if (auto_stat & SELECTION_TIMEOUT) {
1242 nsp32_dbg(NSP32_DEBUG_INTR,
1243 "selection timeout occurred");
1244
1245 SCpnt->result = DID_TIME_OUT << 16;
1246 nsp32_scsi_done(SCpnt);
1247 goto out;
1248 }
1249
1250 if (auto_stat & MSGOUT_PHASE) {
1251 /*
1252 * MsgOut phase was processed.
1253 * If MSG_IN_OCCUER is not set, then MsgOut phase is
1254 * completed. Thus, msgout_len must reset. Otherwise,
1255 * nothing to do here. If MSG_OUT_OCCUER is occurred,
1256 * then we will encounter the condition and check.
1257 */
1258 if (!(auto_stat & MSG_IN_OCCUER) &&
1259 (data->msgout_len <= 3)) {
1260 /*
1261 * !MSG_IN_OCCUER && msgout_len <=3
1262 * ---> AutoSCSI with MSGOUTreg is processed.
1263 */
1264 data->msgout_len = 0;
1265 }
1266
1267 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1268 }
1269
1270 if ((auto_stat & DATA_IN_PHASE) &&
1271 (scsi_get_resid(SCpnt) > 0) &&
1272 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) {
1273 printk( "auto+fifo\n");
1274 //nsp32_pio_read(SCpnt);
1275 }
1276
1277 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) {
1278 /* DATA_IN_PHASE/DATA_OUT_PHASE was processed. */
1279 nsp32_dbg(NSP32_DEBUG_INTR,
1280 "Data in/out phase processed");
1281
1282 /* read BMCNT, SGT pointer addr */
1283 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1284 nsp32_read4(base, BM_CNT));
1285 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1286 nsp32_read4(base, SGT_ADR));
1287 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1288 nsp32_read4(base, SACK_CNT));
1289 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1290 nsp32_read4(base, SAVED_SACK_CNT));
1291
1292 scsi_set_resid(SCpnt, 0); /* all data transferred! */
1293 }
1294
1295 /*
1296 * MsgIn Occur
1297 */
1298 if (auto_stat & MSG_IN_OCCUER) {
1299 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat);
1300 }
1301
1302 /*
1303 * MsgOut Occur
1304 */
1305 if (auto_stat & MSG_OUT_OCCUER) {
1306 nsp32_msgout_occur(SCpnt);
1307 }
1308
1309 /*
1310 * Bus Free Occur
1311 */
1312 if (auto_stat & BUS_FREE_OCCUER) {
1313 ret = nsp32_busfree_occur(SCpnt, auto_stat);
1314 if (ret == TRUE) {
1315 goto out;
1316 }
1317 }
1318
1319 if (auto_stat & STATUS_PHASE) {
1320 /*
1321 * Read CSB and substitute CSB for SCpnt->result
1322 * to save status phase stutas byte.
1323 * scsi error handler checks host_byte (DID_*:
1324 * low level driver to indicate status), then checks
1325 * status_byte (SCSI status byte).
1326 */
1327 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN);
1328 }
1329
1330 if (auto_stat & ILLEGAL_PHASE) {
1331 /* Illegal phase is detected. SACK is not back. */
1332 nsp32_msg(KERN_WARNING,
1333 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!");
1334
1335 /* TODO: currently we don't have any action... bus reset? */
1336
1337 /*
1338 * To send back SACK, assert, wait, and negate.
1339 */
1340 nsp32_sack_assert(data);
1341 nsp32_wait_req(data, NEGATE);
1342 nsp32_sack_negate(data);
1343
1344 }
1345
1346 if (auto_stat & COMMAND_PHASE) {
1347 /* nothing to do */
1348 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1349 }
1350
1351 if (auto_stat & AUTOSCSI_BUSY) {
1352 /* AutoSCSI is running */
1353 }
1354
1355 show_autophase(auto_stat);
1356 }
1357
1358 /* FIFO_SHLD_IRQ */
1359 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) {
1360 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1361
1362 switch(busphase) {
1363 case BUSPHASE_DATA_OUT:
1364 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1365
1366 //nsp32_pio_write(SCpnt);
1367
1368 break;
1369
1370 case BUSPHASE_DATA_IN:
1371 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1372
1373 //nsp32_pio_read(SCpnt);
1374
1375 break;
1376
1377 case BUSPHASE_STATUS:
1378 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1379
1380 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1381
1382 break;
1383 default:
1384 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1385 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x",
1386 irq_stat, trans_stat);
1387 show_busphase(busphase);
1388 break;
1389 }
1390
1391 goto out;
1392 }
1393
1394 /* Phase Change IRQ */
1395 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) {
1396 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1397
1398 switch(busphase) {
1399 case BUSPHASE_MESSAGE_IN:
1400 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1401 nsp32_msgin_occur(SCpnt, irq_stat, 0);
1402 break;
1403 default:
1404 nsp32_msg(KERN_WARNING, "phase chg/other phase?");
1405 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n",
1406 irq_stat, trans_stat);
1407 show_busphase(busphase);
1408 break;
1409 }
1410 goto out;
1411 }
1412
1413 /* PCI_IRQ */
1414 if (irq_stat & IRQSTATUS_PCI_IRQ) {
1415 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1416 /* Do nothing */
1417 }
1418
1419 /* BMCNTERR_IRQ */
1420 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) {
1421 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! ");
1422 /*
1423 * TODO: To be implemented improving bus master
1424 * transfer reliability when BMCNTERR is occurred in
1425 * AutoSCSI phase described in specification.
1426 */
1427 }
1428
1429#if 0
1430 nsp32_dbg(NSP32_DEBUG_INTR,
1431 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1432 show_busphase(busphase);
1433#endif
1434
1435 out:
1436 /* disable IRQ mask */
1437 nsp32_write2(base, IRQ_CONTROL, 0);
1438
1439 out2:
1440 spin_unlock_irqrestore(host->host_lock, flags);
1441
1442 nsp32_dbg(NSP32_DEBUG_INTR, "exit");
1443
1444 return IRQ_RETVAL(handled);
1445}
1446
1447
1448static int nsp32_show_info(struct seq_file *m, struct Scsi_Host *host)
1449{
1450 unsigned long flags;
1451 nsp32_hw_data *data;
1452 int hostno;
1453 unsigned int base;
1454 unsigned char mode_reg;
1455 int id, speed;
1456 long model;
1457
1458 hostno = host->host_no;
1459 data = (nsp32_hw_data *)host->hostdata;
1460 base = host->io_port;
1461
1462 seq_puts(m, "NinjaSCSI-32 status\n\n");
1463 seq_printf(m, "Driver version: %s, $Revision: 1.33 $\n",
1464 nsp32_release_version);
1465 seq_printf(m, "SCSI host No.: %d\n", hostno);
1466 seq_printf(m, "IRQ: %d\n", host->irq);
1467 seq_printf(m, "IO: 0x%lx-0x%lx\n",
1468 host->io_port, host->io_port + host->n_io_port - 1);
1469 seq_printf(m, "MMIO(virtual address): 0x%lx-0x%lx\n",
1470 host->base, host->base + data->MmioLength - 1);
1471 seq_printf(m, "sg_tablesize: %d\n",
1472 host->sg_tablesize);
1473 seq_printf(m, "Chip revision: 0x%x\n",
1474 (nsp32_read2(base, INDEX_REG) >> 8) & 0xff);
1475
1476 mode_reg = nsp32_index_read1(base, CHIP_MODE);
1477 model = data->pci_devid->driver_data;
1478
1479#ifdef CONFIG_PM
1480 seq_printf(m, "Power Management: %s\n",
1481 (mode_reg & OPTF) ? "yes" : "no");
1482#endif
1483 seq_printf(m, "OEM: %ld, %s\n",
1484 (mode_reg & (OEM0|OEM1)), nsp32_model[model]);
1485
1486 spin_lock_irqsave(&(data->Lock), flags);
1487 seq_printf(m, "CurrentSC: 0x%p\n\n", data->CurrentSC);
1488 spin_unlock_irqrestore(&(data->Lock), flags);
1489
1490
1491 seq_puts(m, "SDTR status\n");
1492 for (id = 0; id < ARRAY_SIZE(data->target); id++) {
1493
1494 seq_printf(m, "id %d: ", id);
1495
1496 if (id == host->this_id) {
1497 seq_puts(m, "----- NinjaSCSI-32 host adapter\n");
1498 continue;
1499 }
1500
1501 if (data->target[id].sync_flag == SDTR_DONE) {
1502 if (data->target[id].period == 0 &&
1503 data->target[id].offset == ASYNC_OFFSET ) {
1504 seq_puts(m, "async");
1505 } else {
1506 seq_puts(m, " sync");
1507 }
1508 } else {
1509 seq_puts(m, " none");
1510 }
1511
1512 if (data->target[id].period != 0) {
1513
1514 speed = 1000000 / (data->target[id].period * 4);
1515
1516 seq_printf(m, " transfer %d.%dMB/s, offset %d",
1517 speed / 1000,
1518 speed % 1000,
1519 data->target[id].offset
1520 );
1521 }
1522 seq_putc(m, '\n');
1523 }
1524 return 0;
1525}
1526
1527
1528
1529/*
1530 * Reset parameters and call scsi_done for data->cur_lunt.
1531 * Be careful setting SCpnt->result = DID_* before calling this function.
1532 */
1533static void nsp32_scsi_done(struct scsi_cmnd *SCpnt)
1534{
1535 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1536 unsigned int base = SCpnt->device->host->io_port;
1537
1538 scsi_dma_unmap(SCpnt);
1539
1540 /*
1541 * clear TRANSFERCONTROL_BM_START
1542 */
1543 nsp32_write2(base, TRANSFER_CONTROL, 0);
1544 nsp32_write4(base, BM_CNT, 0);
1545
1546 /*
1547 * call scsi_done
1548 */
1549 (*SCpnt->scsi_done)(SCpnt);
1550
1551 /*
1552 * reset parameters
1553 */
1554 data->cur_lunt->SCpnt = NULL;
1555 data->cur_lunt = NULL;
1556 data->cur_target = NULL;
1557 data->CurrentSC = NULL;
1558}
1559
1560
1561/*
1562 * Bus Free Occur
1563 *
1564 * Current Phase is BUSFREE. AutoSCSI is automatically execute BUSFREE phase
1565 * with ACK reply when below condition is matched:
1566 * MsgIn 00: Command Complete.
1567 * MsgIn 02: Save Data Pointer.
1568 * MsgIn 04: Disconnect.
1569 * In other case, unexpected BUSFREE is detected.
1570 */
1571static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph)
1572{
1573 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1574 unsigned int base = SCpnt->device->host->io_port;
1575
1576 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph);
1577 show_autophase(execph);
1578
1579 nsp32_write4(base, BM_CNT, 0);
1580 nsp32_write2(base, TRANSFER_CONTROL, 0);
1581
1582 /*
1583 * MsgIn 02: Save Data Pointer
1584 *
1585 * VALID:
1586 * Save Data Pointer is received. Adjust pointer.
1587 *
1588 * NO-VALID:
1589 * SCSI-3 says if Save Data Pointer is not received, then we restart
1590 * processing and we can't adjust any SCSI data pointer in next data
1591 * phase.
1592 */
1593 if (execph & MSGIN_02_VALID) {
1594 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid");
1595
1596 /*
1597 * Check sack_cnt/saved_sack_cnt, then adjust sg table if
1598 * needed.
1599 */
1600 if (!(execph & MSGIN_00_VALID) &&
1601 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) {
1602 unsigned int sacklen, s_sacklen;
1603
1604 /*
1605 * Read SACK count and SAVEDSACK count, then compare.
1606 */
1607 sacklen = nsp32_read4(base, SACK_CNT );
1608 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
1609
1610 /*
1611 * If SAVEDSACKCNT == 0, it means SavedDataPointer is
1612 * come after data transferring.
1613 */
1614 if (s_sacklen > 0) {
1615 /*
1616 * Comparing between sack and savedsack to
1617 * check the condition of AutoMsgIn03.
1618 *
1619 * If they are same, set msgin03 == TRUE,
1620 * COMMANDCONTROL_AUTO_MSGIN_03 is enabled at
1621 * reselection. On the other hand, if they
1622 * aren't same, set msgin03 == FALSE, and
1623 * COMMANDCONTROL_AUTO_MSGIN_03 is disabled at
1624 * reselection.
1625 */
1626 if (sacklen != s_sacklen) {
1627 data->cur_lunt->msgin03 = FALSE;
1628 } else {
1629 data->cur_lunt->msgin03 = TRUE;
1630 }
1631
1632 nsp32_adjust_busfree(SCpnt, s_sacklen);
1633 }
1634 }
1635
1636 /* This value has not substitude with valid value yet... */
1637 //data->cur_lunt->save_datp = data->cur_datp;
1638 } else {
1639 /*
1640 * no processing.
1641 */
1642 }
1643
1644 if (execph & MSGIN_03_VALID) {
1645 /* MsgIn03 was valid to be processed. No need processing. */
1646 }
1647
1648 /*
1649 * target SDTR check
1650 */
1651 if (data->cur_target->sync_flag & SDTR_INITIATOR) {
1652 /*
1653 * SDTR negotiation pulled by the initiator has not
1654 * finished yet. Fall back to ASYNC mode.
1655 */
1656 nsp32_set_async(data, data->cur_target);
1657 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
1658 data->cur_target->sync_flag |= SDTR_DONE;
1659 } else if (data->cur_target->sync_flag & SDTR_TARGET) {
1660 /*
1661 * SDTR negotiation pulled by the target has been
1662 * negotiating.
1663 */
1664 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) {
1665 /*
1666 * If valid message is received, then
1667 * negotiation is succeeded.
1668 */
1669 } else {
1670 /*
1671 * On the contrary, if unexpected bus free is
1672 * occurred, then negotiation is failed. Fall
1673 * back to ASYNC mode.
1674 */
1675 nsp32_set_async(data, data->cur_target);
1676 }
1677 data->cur_target->sync_flag &= ~SDTR_TARGET;
1678 data->cur_target->sync_flag |= SDTR_DONE;
1679 }
1680
1681 /*
1682 * It is always ensured by SCSI standard that initiator
1683 * switches into Bus Free Phase after
1684 * receiving message 00 (Command Complete), 04 (Disconnect).
1685 * It's the reason that processing here is valid.
1686 */
1687 if (execph & MSGIN_00_VALID) {
1688 /* MsgIn 00: Command Complete */
1689 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete");
1690
1691 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1692 nsp32_dbg(NSP32_DEBUG_BUSFREE,
1693 "normal end stat=0x%x resid=0x%x\n",
1694 SCpnt->SCp.Status, scsi_get_resid(SCpnt));
1695 SCpnt->result = (DID_OK << 16) |
1696 (SCpnt->SCp.Status << 0);
1697 nsp32_scsi_done(SCpnt);
1698 /* All operation is done */
1699 return TRUE;
1700 } else if (execph & MSGIN_04_VALID) {
1701 /* MsgIn 04: Disconnect */
1702 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1703
1704 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect");
1705 return TRUE;
1706 } else {
1707 /* Unexpected bus free */
1708 nsp32_msg(KERN_WARNING, "unexpected bus free occurred");
1709
1710 /* DID_ERROR? */
1711 //SCpnt->result = (DID_OK << 16) | (SCpnt->SCp.Status << 0);
1712 SCpnt->result = DID_ERROR << 16;
1713 nsp32_scsi_done(SCpnt);
1714 return TRUE;
1715 }
1716 return FALSE;
1717}
1718
1719
1720/*
1721 * nsp32_adjust_busfree - adjusting SG table
1722 *
1723 * Note: This driver adjust the SG table using SCSI ACK
1724 * counter instead of BMCNT counter!
1725 */
1726static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen)
1727{
1728 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1729 int old_entry = data->cur_entry;
1730 int new_entry;
1731 int sg_num = data->cur_lunt->sg_num;
1732 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
1733 unsigned int restlen, sentlen;
1734 u32_le len, addr;
1735
1736 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt));
1737
1738 /* adjust saved SACK count with 4 byte start address boundary */
1739 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3;
1740
1741 /*
1742 * calculate new_entry from sack count and each sgt[].len
1743 * calculate the byte which is intent to send
1744 */
1745 sentlen = 0;
1746 for (new_entry = old_entry; new_entry < sg_num; new_entry++) {
1747 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND);
1748 if (sentlen > s_sacklen) {
1749 break;
1750 }
1751 }
1752
1753 /* all sgt is processed */
1754 if (new_entry == sg_num) {
1755 goto last;
1756 }
1757
1758 if (sentlen == s_sacklen) {
1759 /* XXX: confirm it's ok or not */
1760 /* In this case, it's ok because we are at
1761 * the head element of the sg. restlen is correctly
1762 * calculated.
1763 */
1764 }
1765
1766 /* calculate the rest length for transferring */
1767 restlen = sentlen - s_sacklen;
1768
1769 /* update adjusting current SG table entry */
1770 len = le32_to_cpu(sgt[new_entry].len);
1771 addr = le32_to_cpu(sgt[new_entry].addr);
1772 addr += (len - restlen);
1773 sgt[new_entry].addr = cpu_to_le32(addr);
1774 sgt[new_entry].len = cpu_to_le32(restlen);
1775
1776 /* set cur_entry with new_entry */
1777 data->cur_entry = new_entry;
1778
1779 return;
1780
1781 last:
1782 if (scsi_get_resid(SCpnt) < sentlen) {
1783 nsp32_msg(KERN_ERR, "resid underflow");
1784 }
1785
1786 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen);
1787 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt));
1788
1789 /* update hostdata and lun */
1790
1791 return;
1792}
1793
1794
1795/*
1796 * It's called MsgOut phase occur.
1797 * NinjaSCSI-32Bi/UDE automatically processes up to 3 messages in
1798 * message out phase. It, however, has more than 3 messages,
1799 * HBA creates the interrupt and we have to process by hand.
1800 */
1801static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt)
1802{
1803 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1804 unsigned int base = SCpnt->device->host->io_port;
1805 int i;
1806
1807 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1808 "enter: msgout_len: 0x%x", data->msgout_len);
1809
1810 /*
1811 * If MsgOut phase is occurred without having any
1812 * message, then No_Operation is sent (SCSI-2).
1813 */
1814 if (data->msgout_len == 0) {
1815 nsp32_build_nop(SCpnt);
1816 }
1817
1818 /*
1819 * send messages
1820 */
1821 for (i = 0; i < data->msgout_len; i++) {
1822 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1823 "%d : 0x%x", i, data->msgoutbuf[i]);
1824
1825 /*
1826 * Check REQ is asserted.
1827 */
1828 nsp32_wait_req(data, ASSERT);
1829
1830 if (i == (data->msgout_len - 1)) {
1831 /*
1832 * If the last message, set the AutoSCSI restart
1833 * before send back the ack message. AutoSCSI
1834 * restart automatically negate ATN signal.
1835 */
1836 //command = (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
1837 //nsp32_restart_autoscsi(SCpnt, command);
1838 nsp32_write2(base, COMMAND_CONTROL,
1839 (CLEAR_CDB_FIFO_POINTER |
1840 AUTO_COMMAND_PHASE |
1841 AUTOSCSI_RESTART |
1842 AUTO_MSGIN_00_OR_04 |
1843 AUTO_MSGIN_02 ));
1844 }
1845 /*
1846 * Write data with SACK, then wait sack is
1847 * automatically negated.
1848 */
1849 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]);
1850 nsp32_wait_sack(data, NEGATE);
1851
1852 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n",
1853 nsp32_read1(base, SCSI_BUS_MONITOR));
1854 }
1855
1856 data->msgout_len = 0;
1857
1858 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit");
1859}
1860
1861/*
1862 * Restart AutoSCSI
1863 *
1864 * Note: Restarting AutoSCSI needs set:
1865 * SYNC_REG, ACK_WIDTH, SGT_ADR, TRANSFER_CONTROL
1866 */
1867static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command)
1868{
1869 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1870 unsigned int base = data->BaseAddress;
1871 unsigned short transfer = 0;
1872
1873 nsp32_dbg(NSP32_DEBUG_RESTART, "enter");
1874
1875 if (data->cur_target == NULL || data->cur_lunt == NULL) {
1876 nsp32_msg(KERN_ERR, "Target or Lun is invalid");
1877 }
1878
1879 /*
1880 * set SYNC_REG
1881 * Don't set BM_START_ADR before setting this register.
1882 */
1883 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
1884
1885 /*
1886 * set ACKWIDTH
1887 */
1888 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
1889
1890 /*
1891 * set SREQ hazard killer sampling rate
1892 */
1893 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
1894
1895 /*
1896 * set SGT ADDR (physical address)
1897 */
1898 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
1899
1900 /*
1901 * set TRANSFER CONTROL REG
1902 */
1903 transfer = 0;
1904 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR);
1905 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1906 if (scsi_bufflen(SCpnt) > 0) {
1907 transfer |= BM_START;
1908 }
1909 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
1910 transfer |= CB_MMIO_MODE;
1911 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
1912 transfer |= CB_IO_MODE;
1913 }
1914 nsp32_write2(base, TRANSFER_CONTROL, transfer);
1915
1916 /*
1917 * restart AutoSCSI
1918 *
1919 * TODO: COMMANDCONTROL_AUTO_COMMAND_PHASE is needed ?
1920 */
1921 command |= (CLEAR_CDB_FIFO_POINTER |
1922 AUTO_COMMAND_PHASE |
1923 AUTOSCSI_RESTART );
1924 nsp32_write2(base, COMMAND_CONTROL, command);
1925
1926 nsp32_dbg(NSP32_DEBUG_RESTART, "exit");
1927}
1928
1929
1930/*
1931 * cannot run automatically message in occur
1932 */
1933static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt,
1934 unsigned long irq_status,
1935 unsigned short execph)
1936{
1937 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1938 unsigned int base = SCpnt->device->host->io_port;
1939 unsigned char msg;
1940 unsigned char msgtype;
1941 unsigned char newlun;
1942 unsigned short command = 0;
1943 int msgclear = TRUE;
1944 long new_sgtp;
1945 int ret;
1946
1947 /*
1948 * read first message
1949 * Use SCSIDATA_W_ACK instead of SCSIDATAIN, because the procedure
1950 * of Message-In have to be processed before sending back SCSI ACK.
1951 */
1952 msg = nsp32_read1(base, SCSI_DATA_IN);
1953 data->msginbuf[(unsigned char)data->msgin_len] = msg;
1954 msgtype = data->msginbuf[0];
1955 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR,
1956 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x",
1957 data->msgin_len, msg, msgtype);
1958
1959 /*
1960 * TODO: We need checking whether bus phase is message in?
1961 */
1962
1963 /*
1964 * assert SCSI ACK
1965 */
1966 nsp32_sack_assert(data);
1967
1968 /*
1969 * processing IDENTIFY
1970 */
1971 if (msgtype & 0x80) {
1972 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) {
1973 /* Invalid (non reselect) phase */
1974 goto reject;
1975 }
1976
1977 newlun = msgtype & 0x1f; /* TODO: SPI-3 compliant? */
1978 ret = nsp32_reselection(SCpnt, newlun);
1979 if (ret == TRUE) {
1980 goto restart;
1981 } else {
1982 goto reject;
1983 }
1984 }
1985
1986 /*
1987 * processing messages except for IDENTIFY
1988 *
1989 * TODO: Messages are all SCSI-2 terminology. SCSI-3 compliance is TODO.
1990 */
1991 switch (msgtype) {
1992 /*
1993 * 1-byte message
1994 */
1995 case COMMAND_COMPLETE:
1996 case DISCONNECT:
1997 /*
1998 * These messages should not be occurred.
1999 * They should be processed on AutoSCSI sequencer.
2000 */
2001 nsp32_msg(KERN_WARNING,
2002 "unexpected message of AutoSCSI MsgIn: 0x%x", msg);
2003 break;
2004
2005 case RESTORE_POINTERS:
2006 /*
2007 * AutoMsgIn03 is disabled, and HBA gets this message.
2008 */
2009
2010 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) {
2011 unsigned int s_sacklen;
2012
2013 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
2014 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) {
2015 nsp32_adjust_busfree(SCpnt, s_sacklen);
2016 } else {
2017 /* No need to rewrite SGT */
2018 }
2019 }
2020 data->cur_lunt->msgin03 = FALSE;
2021
2022 /* Update with the new value */
2023
2024 /* reset SACK/SavedACK counter (or ALL clear?) */
2025 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2026
2027 /*
2028 * set new sg pointer
2029 */
2030 new_sgtp = data->cur_lunt->sglun_paddr +
2031 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
2032 nsp32_write4(base, SGT_ADR, new_sgtp);
2033
2034 break;
2035
2036 case SAVE_POINTERS:
2037 /*
2038 * These messages should not be occurred.
2039 * They should be processed on AutoSCSI sequencer.
2040 */
2041 nsp32_msg (KERN_WARNING,
2042 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS");
2043
2044 break;
2045
2046 case MESSAGE_REJECT:
2047 /* If previous message_out is sending SDTR, and get
2048 message_reject from target, SDTR negotiation is failed */
2049 if (data->cur_target->sync_flag &
2050 (SDTR_INITIATOR | SDTR_TARGET)) {
2051 /*
2052 * Current target is negotiating SDTR, but it's
2053 * failed. Fall back to async transfer mode, and set
2054 * SDTR_DONE.
2055 */
2056 nsp32_set_async(data, data->cur_target);
2057 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
2058 data->cur_target->sync_flag |= SDTR_DONE;
2059
2060 }
2061 break;
2062
2063 case LINKED_CMD_COMPLETE:
2064 case LINKED_FLG_CMD_COMPLETE:
2065 /* queue tag is not supported currently */
2066 nsp32_msg (KERN_WARNING,
2067 "unsupported message: 0x%x", msgtype);
2068 break;
2069
2070 case INITIATE_RECOVERY:
2071 /* staring ECA (Extended Contingent Allegiance) state. */
2072 /* This message is declined in SPI2 or later. */
2073
2074 goto reject;
2075
2076 /*
2077 * 2-byte message
2078 */
2079 case SIMPLE_QUEUE_TAG:
2080 case 0x23:
2081 /*
2082 * 0x23: Ignore_Wide_Residue is not declared in scsi.h.
2083 * No support is needed.
2084 */
2085 if (data->msgin_len >= 1) {
2086 goto reject;
2087 }
2088
2089 /* current position is 1-byte of 2 byte */
2090 msgclear = FALSE;
2091
2092 break;
2093
2094 /*
2095 * extended message
2096 */
2097 case EXTENDED_MESSAGE:
2098 if (data->msgin_len < 1) {
2099 /*
2100 * Current position does not reach 2-byte
2101 * (2-byte is extended message length).
2102 */
2103 msgclear = FALSE;
2104 break;
2105 }
2106
2107 if ((data->msginbuf[1] + 1) > data->msgin_len) {
2108 /*
2109 * Current extended message has msginbuf[1] + 2
2110 * (msgin_len starts counting from 0, so buf[1] + 1).
2111 * If current message position is not finished,
2112 * continue receiving message.
2113 */
2114 msgclear = FALSE;
2115 break;
2116 }
2117
2118 /*
2119 * Reach here means regular length of each type of
2120 * extended messages.
2121 */
2122 switch (data->msginbuf[2]) {
2123 case EXTENDED_MODIFY_DATA_POINTER:
2124 /* TODO */
2125 goto reject; /* not implemented yet */
2126 break;
2127
2128 case EXTENDED_SDTR:
2129 /*
2130 * Exchange this message between initiator and target.
2131 */
2132 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) {
2133 /*
2134 * received inappropriate message.
2135 */
2136 goto reject;
2137 break;
2138 }
2139
2140 nsp32_analyze_sdtr(SCpnt);
2141
2142 break;
2143
2144 case EXTENDED_EXTENDED_IDENTIFY:
2145 /* SCSI-I only, not supported. */
2146 goto reject; /* not implemented yet */
2147
2148 break;
2149
2150 case EXTENDED_WDTR:
2151 goto reject; /* not implemented yet */
2152
2153 break;
2154
2155 default:
2156 goto reject;
2157 }
2158 break;
2159
2160 default:
2161 goto reject;
2162 }
2163
2164 restart:
2165 if (msgclear == TRUE) {
2166 data->msgin_len = 0;
2167
2168 /*
2169 * If restarting AutoSCSI, but there are some message to out
2170 * (msgout_len > 0), set AutoATN, and set SCSIMSGOUT as 0
2171 * (MV_VALID = 0). When commandcontrol is written with
2172 * AutoSCSI restart, at the same time MsgOutOccur should be
2173 * happened (however, such situation is really possible...?).
2174 */
2175 if (data->msgout_len > 0) {
2176 nsp32_write4(base, SCSI_MSG_OUT, 0);
2177 command |= AUTO_ATN;
2178 }
2179
2180 /*
2181 * restart AutoSCSI
2182 * If it's failed, COMMANDCONTROL_AUTO_COMMAND_PHASE is needed.
2183 */
2184 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
2185
2186 /*
2187 * If current msgin03 is TRUE, then flag on.
2188 */
2189 if (data->cur_lunt->msgin03 == TRUE) {
2190 command |= AUTO_MSGIN_03;
2191 }
2192 data->cur_lunt->msgin03 = FALSE;
2193 } else {
2194 data->msgin_len++;
2195 }
2196
2197 /*
2198 * restart AutoSCSI
2199 */
2200 nsp32_restart_autoscsi(SCpnt, command);
2201
2202 /*
2203 * wait SCSI REQ negate for REQ-ACK handshake
2204 */
2205 nsp32_wait_req(data, NEGATE);
2206
2207 /*
2208 * negate SCSI ACK
2209 */
2210 nsp32_sack_negate(data);
2211
2212 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2213
2214 return;
2215
2216 reject:
2217 nsp32_msg(KERN_WARNING,
2218 "invalid or unsupported MessageIn, rejected. "
2219 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x",
2220 msg, data->msgin_len, msgtype);
2221 nsp32_build_reject(SCpnt);
2222 data->msgin_len = 0;
2223
2224 goto restart;
2225}
2226
2227/*
2228 *
2229 */
2230static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt)
2231{
2232 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2233 nsp32_target *target = data->cur_target;
2234 unsigned char get_period = data->msginbuf[3];
2235 unsigned char get_offset = data->msginbuf[4];
2236 int entry;
2237
2238 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter");
2239
2240 /*
2241 * If this inititor sent the SDTR message, then target responds SDTR,
2242 * initiator SYNCREG, ACKWIDTH from SDTR parameter.
2243 * Messages are not appropriate, then send back reject message.
2244 * If initiator did not send the SDTR, but target sends SDTR,
2245 * initiator calculator the appropriate parameter and send back SDTR.
2246 */
2247 if (target->sync_flag & SDTR_INITIATOR) {
2248 /*
2249 * Initiator sent SDTR, the target responds and
2250 * send back negotiation SDTR.
2251 */
2252 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR");
2253
2254 target->sync_flag &= ~SDTR_INITIATOR;
2255 target->sync_flag |= SDTR_DONE;
2256
2257 /*
2258 * offset:
2259 */
2260 if (get_offset > SYNC_OFFSET) {
2261 /*
2262 * Negotiation is failed, the target send back
2263 * unexpected offset value.
2264 */
2265 goto reject;
2266 }
2267
2268 if (get_offset == ASYNC_OFFSET) {
2269 /*
2270 * Negotiation is succeeded, the target want
2271 * to fall back into asynchronous transfer mode.
2272 */
2273 goto async;
2274 }
2275
2276 /*
2277 * period:
2278 * Check whether sync period is too short. If too short,
2279 * fall back to async mode. If it's ok, then investigate
2280 * the received sync period. If sync period is acceptable
2281 * between sync table start_period and end_period, then
2282 * set this I_T nexus as sent offset and period.
2283 * If it's not acceptable, send back reject and fall back
2284 * to async mode.
2285 */
2286 if (get_period < data->synct[0].period_num) {
2287 /*
2288 * Negotiation is failed, the target send back
2289 * unexpected period value.
2290 */
2291 goto reject;
2292 }
2293
2294 entry = nsp32_search_period_entry(data, target, get_period);
2295
2296 if (entry < 0) {
2297 /*
2298 * Target want to use long period which is not
2299 * acceptable NinjaSCSI-32Bi/UDE.
2300 */
2301 goto reject;
2302 }
2303
2304 /*
2305 * Set new sync table and offset in this I_T nexus.
2306 */
2307 nsp32_set_sync_entry(data, target, entry, get_offset);
2308 } else {
2309 /* Target send SDTR to initiator. */
2310 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR");
2311
2312 target->sync_flag |= SDTR_INITIATOR;
2313
2314 /* offset: */
2315 if (get_offset > SYNC_OFFSET) {
2316 /* send back as SYNC_OFFSET */
2317 get_offset = SYNC_OFFSET;
2318 }
2319
2320 /* period: */
2321 if (get_period < data->synct[0].period_num) {
2322 get_period = data->synct[0].period_num;
2323 }
2324
2325 entry = nsp32_search_period_entry(data, target, get_period);
2326
2327 if (get_offset == ASYNC_OFFSET || entry < 0) {
2328 nsp32_set_async(data, target);
2329 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET);
2330 } else {
2331 nsp32_set_sync_entry(data, target, entry, get_offset);
2332 nsp32_build_sdtr(SCpnt, get_period, get_offset);
2333 }
2334 }
2335
2336 target->period = get_period;
2337 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2338 return;
2339
2340 reject:
2341 /*
2342 * If the current message is unacceptable, send back to the target
2343 * with reject message.
2344 */
2345 nsp32_build_reject(SCpnt);
2346
2347 async:
2348 nsp32_set_async(data, target); /* set as ASYNC transfer mode */
2349
2350 target->period = 0;
2351 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async");
2352 return;
2353}
2354
2355
2356/*
2357 * Search config entry number matched in sync_table from given
2358 * target and speed period value. If failed to search, return negative value.
2359 */
2360static int nsp32_search_period_entry(nsp32_hw_data *data,
2361 nsp32_target *target,
2362 unsigned char period)
2363{
2364 int i;
2365
2366 if (target->limit_entry >= data->syncnum) {
2367 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!");
2368 target->limit_entry = 0;
2369 }
2370
2371 for (i = target->limit_entry; i < data->syncnum; i++) {
2372 if (period >= data->synct[i].start_period &&
2373 period <= data->synct[i].end_period) {
2374 break;
2375 }
2376 }
2377
2378 /*
2379 * Check given period value is over the sync_table value.
2380 * If so, return max value.
2381 */
2382 if (i == data->syncnum) {
2383 i = -1;
2384 }
2385
2386 return i;
2387}
2388
2389
2390/*
2391 * target <-> initiator use ASYNC transfer
2392 */
2393static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target)
2394{
2395 unsigned char period = data->synct[target->limit_entry].period_num;
2396
2397 target->offset = ASYNC_OFFSET;
2398 target->period = 0;
2399 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET);
2400 target->ackwidth = 0;
2401 target->sample_reg = 0;
2402
2403 nsp32_dbg(NSP32_DEBUG_SYNC, "set async");
2404}
2405
2406
2407/*
2408 * target <-> initiator use maximum SYNC transfer
2409 */
2410static void nsp32_set_max_sync(nsp32_hw_data *data,
2411 nsp32_target *target,
2412 unsigned char *period,
2413 unsigned char *offset)
2414{
2415 unsigned char period_num, ackwidth;
2416
2417 period_num = data->synct[target->limit_entry].period_num;
2418 *period = data->synct[target->limit_entry].start_period;
2419 ackwidth = data->synct[target->limit_entry].ackwidth;
2420 *offset = SYNC_OFFSET;
2421
2422 target->syncreg = TO_SYNCREG(period_num, *offset);
2423 target->ackwidth = ackwidth;
2424 target->offset = *offset;
2425 target->sample_reg = 0; /* disable SREQ sampling */
2426}
2427
2428
2429/*
2430 * target <-> initiator use entry number speed
2431 */
2432static void nsp32_set_sync_entry(nsp32_hw_data *data,
2433 nsp32_target *target,
2434 int entry,
2435 unsigned char offset)
2436{
2437 unsigned char period, ackwidth, sample_rate;
2438
2439 period = data->synct[entry].period_num;
2440 ackwidth = data->synct[entry].ackwidth;
2441 sample_rate = data->synct[entry].sample_rate;
2442
2443 target->syncreg = TO_SYNCREG(period, offset);
2444 target->ackwidth = ackwidth;
2445 target->offset = offset;
2446 target->sample_reg = sample_rate | SAMPLING_ENABLE;
2447
2448 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync");
2449}
2450
2451
2452/*
2453 * It waits until SCSI REQ becomes assertion or negation state.
2454 *
2455 * Note: If nsp32_msgin_occur is called, we asserts SCSI ACK. Then
2456 * connected target responds SCSI REQ negation. We have to wait
2457 * SCSI REQ becomes negation in order to negate SCSI ACK signal for
2458 * REQ-ACK handshake.
2459 */
2460static void nsp32_wait_req(nsp32_hw_data *data, int state)
2461{
2462 unsigned int base = data->BaseAddress;
2463 int wait_time = 0;
2464 unsigned char bus, req_bit;
2465
2466 if (!((state == ASSERT) || (state == NEGATE))) {
2467 nsp32_msg(KERN_ERR, "unknown state designation");
2468 }
2469 /* REQ is BIT(5) */
2470 req_bit = (state == ASSERT ? BUSMON_REQ : 0);
2471
2472 do {
2473 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2474 if ((bus & BUSMON_REQ) == req_bit) {
2475 nsp32_dbg(NSP32_DEBUG_WAIT,
2476 "wait_time: %d", wait_time);
2477 return;
2478 }
2479 udelay(1);
2480 wait_time++;
2481 } while (wait_time < REQSACK_TIMEOUT_TIME);
2482
2483 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit);
2484}
2485
2486/*
2487 * It waits until SCSI SACK becomes assertion or negation state.
2488 */
2489static void nsp32_wait_sack(nsp32_hw_data *data, int state)
2490{
2491 unsigned int base = data->BaseAddress;
2492 int wait_time = 0;
2493 unsigned char bus, ack_bit;
2494
2495 if (!((state == ASSERT) || (state == NEGATE))) {
2496 nsp32_msg(KERN_ERR, "unknown state designation");
2497 }
2498 /* ACK is BIT(4) */
2499 ack_bit = (state == ASSERT ? BUSMON_ACK : 0);
2500
2501 do {
2502 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2503 if ((bus & BUSMON_ACK) == ack_bit) {
2504 nsp32_dbg(NSP32_DEBUG_WAIT,
2505 "wait_time: %d", wait_time);
2506 return;
2507 }
2508 udelay(1);
2509 wait_time++;
2510 } while (wait_time < REQSACK_TIMEOUT_TIME);
2511
2512 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit);
2513}
2514
2515/*
2516 * assert SCSI ACK
2517 *
2518 * Note: SCSI ACK assertion needs with ACKENB=1, AUTODIRECTION=1.
2519 */
2520static void nsp32_sack_assert(nsp32_hw_data *data)
2521{
2522 unsigned int base = data->BaseAddress;
2523 unsigned char busctrl;
2524
2525 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2526 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB);
2527 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2528}
2529
2530/*
2531 * negate SCSI ACK
2532 */
2533static void nsp32_sack_negate(nsp32_hw_data *data)
2534{
2535 unsigned int base = data->BaseAddress;
2536 unsigned char busctrl;
2537
2538 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2539 busctrl &= ~BUSCTL_ACK;
2540 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2541}
2542
2543
2544
2545/*
2546 * Note: n_io_port is defined as 0x7f because I/O register port is
2547 * assigned as:
2548 * 0x800-0x8ff: memory mapped I/O port
2549 * 0x900-0xbff: (map same 0x800-0x8ff I/O port image repeatedly)
2550 * 0xc00-0xfff: CardBus status registers
2551 */
2552static int nsp32_detect(struct pci_dev *pdev)
2553{
2554 struct Scsi_Host *host; /* registered host structure */
2555 struct resource *res;
2556 nsp32_hw_data *data;
2557 int ret;
2558 int i, j;
2559
2560 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
2561
2562 /*
2563 * register this HBA as SCSI device
2564 */
2565 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data));
2566 if (host == NULL) {
2567 nsp32_msg (KERN_ERR, "failed to scsi register");
2568 goto err;
2569 }
2570
2571 /*
2572 * set nsp32_hw_data
2573 */
2574 data = (nsp32_hw_data *)host->hostdata;
2575
2576 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data));
2577
2578 host->irq = data->IrqNumber;
2579 host->io_port = data->BaseAddress;
2580 host->unique_id = data->BaseAddress;
2581 host->n_io_port = data->NumAddress;
2582 host->base = (unsigned long)data->MmioAddress;
2583
2584 data->Host = host;
2585 spin_lock_init(&(data->Lock));
2586
2587 data->cur_lunt = NULL;
2588 data->cur_target = NULL;
2589
2590 /*
2591 * Bus master transfer mode is supported currently.
2592 */
2593 data->trans_method = NSP32_TRANSFER_BUSMASTER;
2594
2595 /*
2596 * Set clock div, CLOCK_4 (HBA has own external clock, and
2597 * dividing * 100ns/4).
2598 * Currently CLOCK_4 has only tested, not for CLOCK_2/PCICLK yet.
2599 */
2600 data->clock = CLOCK_4;
2601
2602 /*
2603 * Select appropriate nsp32_sync_table and set I_CLOCKDIV.
2604 */
2605 switch (data->clock) {
2606 case CLOCK_4:
2607 /* If data->clock is CLOCK_4, then select 40M sync table. */
2608 data->synct = nsp32_sync_table_40M;
2609 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2610 break;
2611 case CLOCK_2:
2612 /* If data->clock is CLOCK_2, then select 20M sync table. */
2613 data->synct = nsp32_sync_table_20M;
2614 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M);
2615 break;
2616 case PCICLK:
2617 /* If data->clock is PCICLK, then select pci sync table. */
2618 data->synct = nsp32_sync_table_pci;
2619 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci);
2620 break;
2621 default:
2622 nsp32_msg(KERN_WARNING,
2623 "Invalid clock div is selected, set CLOCK_4.");
2624 /* Use default value CLOCK_4 */
2625 data->clock = CLOCK_4;
2626 data->synct = nsp32_sync_table_40M;
2627 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2628 }
2629
2630 /*
2631 * setup nsp32_lunt
2632 */
2633
2634 /*
2635 * setup DMA
2636 */
2637 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
2638 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask");
2639 goto scsi_unregister;
2640 }
2641
2642 /*
2643 * allocate autoparam DMA resource.
2644 */
2645 data->autoparam = dma_alloc_coherent(&pdev->dev,
2646 sizeof(nsp32_autoparam), &(data->auto_paddr),
2647 GFP_KERNEL);
2648 if (data->autoparam == NULL) {
2649 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2650 goto scsi_unregister;
2651 }
2652
2653 /*
2654 * allocate scatter-gather DMA resource.
2655 */
2656 data->sg_list = dma_alloc_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE,
2657 &data->sg_paddr, GFP_KERNEL);
2658 if (data->sg_list == NULL) {
2659 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2660 goto free_autoparam;
2661 }
2662
2663 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) {
2664 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) {
2665 int offset = i * ARRAY_SIZE(data->lunt[0]) + j;
2666 nsp32_lunt tmp = {
2667 .SCpnt = NULL,
2668 .save_datp = 0,
2669 .msgin03 = FALSE,
2670 .sg_num = 0,
2671 .cur_entry = 0,
2672 .sglun = &(data->sg_list[offset]),
2673 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)),
2674 };
2675
2676 data->lunt[i][j] = tmp;
2677 }
2678 }
2679
2680 /*
2681 * setup target
2682 */
2683 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2684 nsp32_target *target = &(data->target[i]);
2685
2686 target->limit_entry = 0;
2687 target->sync_flag = 0;
2688 nsp32_set_async(data, target);
2689 }
2690
2691 /*
2692 * EEPROM check
2693 */
2694 ret = nsp32_getprom_param(data);
2695 if (ret == FALSE) {
2696 data->resettime = 3; /* default 3 */
2697 }
2698
2699 /*
2700 * setup HBA
2701 */
2702 nsp32hw_init(data);
2703
2704 snprintf(data->info_str, sizeof(data->info_str),
2705 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x",
2706 host->irq, host->io_port, host->n_io_port);
2707
2708 /*
2709 * SCSI bus reset
2710 *
2711 * Note: It's important to reset SCSI bus in initialization phase.
2712 * NinjaSCSI-32Bi/UDE HBA EEPROM seems to exchange SDTR when
2713 * system is coming up, so SCSI devices connected to HBA is set as
2714 * un-asynchronous mode. It brings the merit that this HBA is
2715 * ready to start synchronous transfer without any preparation,
2716 * but we are difficult to control transfer speed. In addition,
2717 * it prevents device transfer speed from effecting EEPROM start-up
2718 * SDTR. NinjaSCSI-32Bi/UDE has the feature if EEPROM is set as
2719 * Auto Mode, then FAST-10M is selected when SCSI devices are
2720 * connected same or more than 4 devices. It should be avoided
2721 * depending on this specification. Thus, resetting the SCSI bus
2722 * restores all connected SCSI devices to asynchronous mode, then
2723 * this driver set SDTR safely later, and we can control all SCSI
2724 * device transfer mode.
2725 */
2726 nsp32_do_bus_reset(data);
2727
2728 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data);
2729 if (ret < 0) {
2730 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 "
2731 "SCSI PCI controller. Interrupt: %d", host->irq);
2732 goto free_sg_list;
2733 }
2734
2735 /*
2736 * PCI IO register
2737 */
2738 res = request_region(host->io_port, host->n_io_port, "nsp32");
2739 if (res == NULL) {
2740 nsp32_msg(KERN_ERR,
2741 "I/O region 0x%x+0x%x is already used",
2742 data->BaseAddress, data->NumAddress);
2743 goto free_irq;
2744 }
2745
2746 ret = scsi_add_host(host, &pdev->dev);
2747 if (ret) {
2748 nsp32_msg(KERN_ERR, "failed to add scsi host");
2749 goto free_region;
2750 }
2751 scsi_scan_host(host);
2752 pci_set_drvdata(pdev, host);
2753 return 0;
2754
2755 free_region:
2756 release_region(host->io_port, host->n_io_port);
2757
2758 free_irq:
2759 free_irq(host->irq, data);
2760
2761 free_sg_list:
2762 dma_free_coherent(&pdev->dev, NSP32_SG_TABLE_SIZE,
2763 data->sg_list, data->sg_paddr);
2764
2765 free_autoparam:
2766 dma_free_coherent(&pdev->dev, sizeof(nsp32_autoparam),
2767 data->autoparam, data->auto_paddr);
2768
2769 scsi_unregister:
2770 scsi_host_put(host);
2771
2772 err:
2773 return 1;
2774}
2775
2776static int nsp32_release(struct Scsi_Host *host)
2777{
2778 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2779
2780 if (data->autoparam) {
2781 dma_free_coherent(&data->Pci->dev, sizeof(nsp32_autoparam),
2782 data->autoparam, data->auto_paddr);
2783 }
2784
2785 if (data->sg_list) {
2786 dma_free_coherent(&data->Pci->dev, NSP32_SG_TABLE_SIZE,
2787 data->sg_list, data->sg_paddr);
2788 }
2789
2790 if (host->irq) {
2791 free_irq(host->irq, data);
2792 }
2793
2794 if (host->io_port && host->n_io_port) {
2795 release_region(host->io_port, host->n_io_port);
2796 }
2797
2798 if (data->MmioAddress) {
2799 iounmap(data->MmioAddress);
2800 }
2801
2802 return 0;
2803}
2804
2805static const char *nsp32_info(struct Scsi_Host *shpnt)
2806{
2807 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata;
2808
2809 return data->info_str;
2810}
2811
2812
2813/****************************************************************************
2814 * error handler
2815 */
2816static int nsp32_eh_abort(struct scsi_cmnd *SCpnt)
2817{
2818 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2819 unsigned int base = SCpnt->device->host->io_port;
2820
2821 nsp32_msg(KERN_WARNING, "abort");
2822
2823 if (data->cur_lunt->SCpnt == NULL) {
2824 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed");
2825 return FAILED;
2826 }
2827
2828 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) {
2829 /* reset SDTR negotiation */
2830 data->cur_target->sync_flag = 0;
2831 nsp32_set_async(data, data->cur_target);
2832 }
2833
2834 nsp32_write2(base, TRANSFER_CONTROL, 0);
2835 nsp32_write2(base, BM_CNT, 0);
2836
2837 SCpnt->result = DID_ABORT << 16;
2838 nsp32_scsi_done(SCpnt);
2839
2840 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success");
2841 return SUCCESS;
2842}
2843
2844static void nsp32_do_bus_reset(nsp32_hw_data *data)
2845{
2846 unsigned int base = data->BaseAddress;
2847 int i;
2848 unsigned short __maybe_unused intrdat;
2849
2850 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in");
2851
2852 /*
2853 * stop all transfer
2854 * clear TRANSFERCONTROL_BM_START
2855 * clear counter
2856 */
2857 nsp32_write2(base, TRANSFER_CONTROL, 0);
2858 nsp32_write4(base, BM_CNT, 0);
2859 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2860
2861 /*
2862 * fall back to asynchronous transfer mode
2863 * initialize SDTR negotiation flag
2864 */
2865 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2866 nsp32_target *target = &data->target[i];
2867
2868 target->sync_flag = 0;
2869 nsp32_set_async(data, target);
2870 }
2871
2872 /*
2873 * reset SCSI bus
2874 */
2875 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST);
2876 mdelay(RESET_HOLD_TIME / 1000);
2877 nsp32_write1(base, SCSI_BUS_CONTROL, 0);
2878 for(i = 0; i < 5; i++) {
2879 intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */
2880 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat);
2881 }
2882
2883 data->CurrentSC = NULL;
2884}
2885
2886static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt)
2887{
2888 struct Scsi_Host *host = SCpnt->device->host;
2889 unsigned int base = SCpnt->device->host->io_port;
2890 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2891
2892 nsp32_msg(KERN_INFO, "Host Reset");
2893 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2894
2895 spin_lock_irq(SCpnt->device->host->host_lock);
2896
2897 nsp32hw_init(data);
2898 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2899 nsp32_do_bus_reset(data);
2900 nsp32_write2(base, IRQ_CONTROL, 0);
2901
2902 spin_unlock_irq(SCpnt->device->host->host_lock);
2903 return SUCCESS; /* Host reset is succeeded at any time. */
2904}
2905
2906
2907/**************************************************************************
2908 * EEPROM handler
2909 */
2910
2911/*
2912 * getting EEPROM parameter
2913 */
2914static int nsp32_getprom_param(nsp32_hw_data *data)
2915{
2916 int vendor = data->pci_devid->vendor;
2917 int device = data->pci_devid->device;
2918 int ret, i;
2919 int __maybe_unused val;
2920
2921 /*
2922 * EEPROM checking.
2923 */
2924 ret = nsp32_prom_read(data, 0x7e);
2925 if (ret != 0x55) {
2926 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret);
2927 return FALSE;
2928 }
2929 ret = nsp32_prom_read(data, 0x7f);
2930 if (ret != 0xaa) {
2931 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret);
2932 return FALSE;
2933 }
2934
2935 /*
2936 * check EEPROM type
2937 */
2938 if (vendor == PCI_VENDOR_ID_WORKBIT &&
2939 device == PCI_DEVICE_ID_WORKBIT_STANDARD) {
2940 ret = nsp32_getprom_c16(data);
2941 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2942 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) {
2943 ret = nsp32_getprom_at24(data);
2944 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2945 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) {
2946 ret = nsp32_getprom_at24(data);
2947 } else {
2948 nsp32_msg(KERN_WARNING, "Unknown EEPROM");
2949 ret = FALSE;
2950 }
2951
2952 /* for debug : SPROM data full checking */
2953 for (i = 0; i <= 0x1f; i++) {
2954 val = nsp32_prom_read(data, i);
2955 nsp32_dbg(NSP32_DEBUG_EEPROM,
2956 "rom address 0x%x : 0x%x", i, val);
2957 }
2958
2959 return ret;
2960}
2961
2962
2963/*
2964 * AT24C01A (Logitec: LHA-600S), AT24C02 (Melco Buffalo: IFC-USLP) data map:
2965 *
2966 * ROMADDR
2967 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
2968 * Value 0x0: ASYNC, 0x0c: Ultra-20M, 0x19: Fast-10M
2969 * 0x07 : HBA Synchronous Transfer Period
2970 * Value 0: AutoSync, 1: Manual Setting
2971 * 0x08 - 0x0f : Not Used? (0x0)
2972 * 0x10 : Bus Termination
2973 * Value 0: Auto[ON], 1: ON, 2: OFF
2974 * 0x11 : Not Used? (0)
2975 * 0x12 : Bus Reset Delay Time (0x03)
2976 * 0x13 : Bootable CD Support
2977 * Value 0: Disable, 1: Enable
2978 * 0x14 : Device Scan
2979 * Bit 7 6 5 4 3 2 1 0
2980 * | <----------------->
2981 * | SCSI ID: Value 0: Skip, 1: YES
2982 * |-> Value 0: ALL scan, Value 1: Manual
2983 * 0x15 - 0x1b : Not Used? (0)
2984 * 0x1c : Constant? (0x01) (clock div?)
2985 * 0x1d - 0x7c : Not Used (0xff)
2986 * 0x7d : Not Used? (0xff)
2987 * 0x7e : Constant (0x55), Validity signature
2988 * 0x7f : Constant (0xaa), Validity signature
2989 */
2990static int nsp32_getprom_at24(nsp32_hw_data *data)
2991{
2992 int ret, i;
2993 int auto_sync;
2994 nsp32_target *target;
2995 int entry;
2996
2997 /*
2998 * Reset time which is designated by EEPROM.
2999 *
3000 * TODO: Not used yet.
3001 */
3002 data->resettime = nsp32_prom_read(data, 0x12);
3003
3004 /*
3005 * HBA Synchronous Transfer Period
3006 *
3007 * Note: auto_sync = 0: auto, 1: manual. Ninja SCSI HBA spec says
3008 * that if auto_sync is 0 (auto), and connected SCSI devices are
3009 * same or lower than 3, then transfer speed is set as ULTRA-20M.
3010 * On the contrary if connected SCSI devices are same or higher
3011 * than 4, then transfer speed is set as FAST-10M.
3012 *
3013 * I break this rule. The number of connected SCSI devices are
3014 * only ignored. If auto_sync is 0 (auto), then transfer speed is
3015 * forced as ULTRA-20M.
3016 */
3017 ret = nsp32_prom_read(data, 0x07);
3018 switch (ret) {
3019 case 0:
3020 auto_sync = TRUE;
3021 break;
3022 case 1:
3023 auto_sync = FALSE;
3024 break;
3025 default:
3026 nsp32_msg(KERN_WARNING,
3027 "Unsupported Auto Sync mode. Fall back to manual mode.");
3028 auto_sync = TRUE;
3029 }
3030
3031 if (trans_mode == ULTRA20M_MODE) {
3032 auto_sync = TRUE;
3033 }
3034
3035 /*
3036 * each device Synchronous Transfer Period
3037 */
3038 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3039 target = &data->target[i];
3040 if (auto_sync == TRUE) {
3041 target->limit_entry = 0; /* set as ULTRA20M */
3042 } else {
3043 ret = nsp32_prom_read(data, i);
3044 entry = nsp32_search_period_entry(data, target, ret);
3045 if (entry < 0) {
3046 /* search failed... set maximum speed */
3047 entry = 0;
3048 }
3049 target->limit_entry = entry;
3050 }
3051 }
3052
3053 return TRUE;
3054}
3055
3056
3057/*
3058 * C16 110 (I-O Data: SC-NBD) data map:
3059 *
3060 * ROMADDR
3061 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
3062 * Value 0x0: 20MB/S, 0x1: 10MB/S, 0x2: 5MB/S, 0x3: ASYNC
3063 * 0x07 : 0 (HBA Synchronous Transfer Period: Auto Sync)
3064 * 0x08 - 0x0f : Not Used? (0x0)
3065 * 0x10 : Transfer Mode
3066 * Value 0: PIO, 1: Busmater
3067 * 0x11 : Bus Reset Delay Time (0x00-0x20)
3068 * 0x12 : Bus Termination
3069 * Value 0: Disable, 1: Enable
3070 * 0x13 - 0x19 : Disconnection
3071 * Value 0: Disable, 1: Enable
3072 * 0x1a - 0x7c : Not Used? (0)
3073 * 0x7d : Not Used? (0xf8)
3074 * 0x7e : Constant (0x55), Validity signature
3075 * 0x7f : Constant (0xaa), Validity signature
3076 */
3077static int nsp32_getprom_c16(nsp32_hw_data *data)
3078{
3079 int ret, i;
3080 nsp32_target *target;
3081 int entry, val;
3082
3083 /*
3084 * Reset time which is designated by EEPROM.
3085 *
3086 * TODO: Not used yet.
3087 */
3088 data->resettime = nsp32_prom_read(data, 0x11);
3089
3090 /*
3091 * each device Synchronous Transfer Period
3092 */
3093 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3094 target = &data->target[i];
3095 ret = nsp32_prom_read(data, i);
3096 switch (ret) {
3097 case 0: /* 20MB/s */
3098 val = 0x0c;
3099 break;
3100 case 1: /* 10MB/s */
3101 val = 0x19;
3102 break;
3103 case 2: /* 5MB/s */
3104 val = 0x32;
3105 break;
3106 case 3: /* ASYNC */
3107 val = 0x00;
3108 break;
3109 default: /* default 20MB/s */
3110 val = 0x0c;
3111 break;
3112 }
3113 entry = nsp32_search_period_entry(data, target, val);
3114 if (entry < 0 || trans_mode == ULTRA20M_MODE) {
3115 /* search failed... set maximum speed */
3116 entry = 0;
3117 }
3118 target->limit_entry = entry;
3119 }
3120
3121 return TRUE;
3122}
3123
3124
3125/*
3126 * Atmel AT24C01A (drived in 5V) serial EEPROM routines
3127 */
3128static int nsp32_prom_read(nsp32_hw_data *data, int romaddr)
3129{
3130 int i, val;
3131
3132 /* start condition */
3133 nsp32_prom_start(data);
3134
3135 /* device address */
3136 nsp32_prom_write_bit(data, 1); /* 1 */
3137 nsp32_prom_write_bit(data, 0); /* 0 */
3138 nsp32_prom_write_bit(data, 1); /* 1 */
3139 nsp32_prom_write_bit(data, 0); /* 0 */
3140 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3141 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3142 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3143
3144 /* R/W: W for dummy write */
3145 nsp32_prom_write_bit(data, 0);
3146
3147 /* ack */
3148 nsp32_prom_write_bit(data, 0);
3149
3150 /* word address */
3151 for (i = 7; i >= 0; i--) {
3152 nsp32_prom_write_bit(data, ((romaddr >> i) & 1));
3153 }
3154
3155 /* ack */
3156 nsp32_prom_write_bit(data, 0);
3157
3158 /* start condition */
3159 nsp32_prom_start(data);
3160
3161 /* device address */
3162 nsp32_prom_write_bit(data, 1); /* 1 */
3163 nsp32_prom_write_bit(data, 0); /* 0 */
3164 nsp32_prom_write_bit(data, 1); /* 1 */
3165 nsp32_prom_write_bit(data, 0); /* 0 */
3166 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3167 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3168 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3169
3170 /* R/W: R */
3171 nsp32_prom_write_bit(data, 1);
3172
3173 /* ack */
3174 nsp32_prom_write_bit(data, 0);
3175
3176 /* data... */
3177 val = 0;
3178 for (i = 7; i >= 0; i--) {
3179 val += (nsp32_prom_read_bit(data) << i);
3180 }
3181
3182 /* no ack */
3183 nsp32_prom_write_bit(data, 1);
3184
3185 /* stop condition */
3186 nsp32_prom_stop(data);
3187
3188 return val;
3189}
3190
3191static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val)
3192{
3193 int base = data->BaseAddress;
3194 int tmp;
3195
3196 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL);
3197
3198 if (val == 0) {
3199 tmp &= ~bit;
3200 } else {
3201 tmp |= bit;
3202 }
3203
3204 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp);
3205
3206 udelay(10);
3207}
3208
3209static int nsp32_prom_get(nsp32_hw_data *data, int bit)
3210{
3211 int base = data->BaseAddress;
3212 int tmp, ret;
3213
3214 if (bit != SDA) {
3215 nsp32_msg(KERN_ERR, "return value is not appropriate");
3216 return 0;
3217 }
3218
3219
3220 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit;
3221
3222 if (tmp == 0) {
3223 ret = 0;
3224 } else {
3225 ret = 1;
3226 }
3227
3228 udelay(10);
3229
3230 return ret;
3231}
3232
3233static void nsp32_prom_start (nsp32_hw_data *data)
3234{
3235 /* start condition */
3236 nsp32_prom_set(data, SCL, 1);
3237 nsp32_prom_set(data, SDA, 1);
3238 nsp32_prom_set(data, ENA, 1); /* output mode */
3239 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting
3240 * SDA 1->0 is start condition */
3241 nsp32_prom_set(data, SCL, 0);
3242}
3243
3244static void nsp32_prom_stop (nsp32_hw_data *data)
3245{
3246 /* stop condition */
3247 nsp32_prom_set(data, SCL, 1);
3248 nsp32_prom_set(data, SDA, 0);
3249 nsp32_prom_set(data, ENA, 1); /* output mode */
3250 nsp32_prom_set(data, SDA, 1);
3251 nsp32_prom_set(data, SCL, 0);
3252}
3253
3254static void nsp32_prom_write_bit(nsp32_hw_data *data, int val)
3255{
3256 /* write */
3257 nsp32_prom_set(data, SDA, val);
3258 nsp32_prom_set(data, SCL, 1 );
3259 nsp32_prom_set(data, SCL, 0 );
3260}
3261
3262static int nsp32_prom_read_bit(nsp32_hw_data *data)
3263{
3264 int val;
3265
3266 /* read */
3267 nsp32_prom_set(data, ENA, 0); /* input mode */
3268 nsp32_prom_set(data, SCL, 1);
3269
3270 val = nsp32_prom_get(data, SDA);
3271
3272 nsp32_prom_set(data, SCL, 0);
3273 nsp32_prom_set(data, ENA, 1); /* output mode */
3274
3275 return val;
3276}
3277
3278
3279/**************************************************************************
3280 * Power Management
3281 */
3282#ifdef CONFIG_PM
3283
3284/* Device suspended */
3285static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state)
3286{
3287 struct Scsi_Host *host = pci_get_drvdata(pdev);
3288
3289 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state.event=%x, slot=%s, host=0x%p",
3290 pdev, state.event, pci_name(pdev), host);
3291
3292 pci_save_state (pdev);
3293 pci_disable_device (pdev);
3294 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3295
3296 return 0;
3297}
3298
3299/* Device woken up */
3300static int nsp32_resume(struct pci_dev *pdev)
3301{
3302 struct Scsi_Host *host = pci_get_drvdata(pdev);
3303 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
3304 unsigned short reg;
3305
3306 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p",
3307 pdev, pci_name(pdev), host);
3308
3309 pci_set_power_state(pdev, PCI_D0);
3310 pci_enable_wake (pdev, PCI_D0, 0);
3311 pci_restore_state (pdev);
3312
3313 reg = nsp32_read2(data->BaseAddress, INDEX_REG);
3314
3315 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg);
3316
3317 if (reg == 0xffff) {
3318 nsp32_msg(KERN_INFO, "missing device. abort resume.");
3319 return 0;
3320 }
3321
3322 nsp32hw_init (data);
3323 nsp32_do_bus_reset(data);
3324
3325 nsp32_msg(KERN_INFO, "resume success");
3326
3327 return 0;
3328}
3329
3330#endif
3331
3332/************************************************************************
3333 * PCI/Cardbus probe/remove routine
3334 */
3335static int nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3336{
3337 int ret;
3338 nsp32_hw_data *data = &nsp32_data_base;
3339
3340 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3341
3342 ret = pci_enable_device(pdev);
3343 if (ret) {
3344 nsp32_msg(KERN_ERR, "failed to enable pci device");
3345 return ret;
3346 }
3347
3348 data->Pci = pdev;
3349 data->pci_devid = id;
3350 data->IrqNumber = pdev->irq;
3351 data->BaseAddress = pci_resource_start(pdev, 0);
3352 data->NumAddress = pci_resource_len (pdev, 0);
3353 data->MmioAddress = pci_ioremap_bar(pdev, 1);
3354 data->MmioLength = pci_resource_len (pdev, 1);
3355
3356 pci_set_master(pdev);
3357
3358 ret = nsp32_detect(pdev);
3359
3360 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s",
3361 pdev->irq,
3362 data->MmioAddress, data->MmioLength,
3363 pci_name(pdev),
3364 nsp32_model[id->driver_data]);
3365
3366 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret);
3367
3368 return ret;
3369}
3370
3371static void nsp32_remove(struct pci_dev *pdev)
3372{
3373 struct Scsi_Host *host = pci_get_drvdata(pdev);
3374
3375 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3376
3377 scsi_remove_host(host);
3378
3379 nsp32_release(host);
3380
3381 scsi_host_put(host);
3382}
3383
3384static struct pci_driver nsp32_driver = {
3385 .name = "nsp32",
3386 .id_table = nsp32_pci_table,
3387 .probe = nsp32_probe,
3388 .remove = nsp32_remove,
3389#ifdef CONFIG_PM
3390 .suspend = nsp32_suspend,
3391 .resume = nsp32_resume,
3392#endif
3393};
3394
3395/*********************************************************************
3396 * Moule entry point
3397 */
3398static int __init init_nsp32(void) {
3399 nsp32_msg(KERN_INFO, "loading...");
3400 return pci_register_driver(&nsp32_driver);
3401}
3402
3403static void __exit exit_nsp32(void) {
3404 nsp32_msg(KERN_INFO, "unloading...");
3405 pci_unregister_driver(&nsp32_driver);
3406}
3407
3408module_init(init_nsp32);
3409module_exit(exit_nsp32);
3410
3411/* end */