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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 */
9
10#define pr_fmt(fmt) "irq-mips-gic: " fmt
11
12#include <linux/bitfield.h>
13#include <linux/bitmap.h>
14#include <linux/clocksource.h>
15#include <linux/cpuhotplug.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqchip.h>
20#include <linux/irqdomain.h>
21#include <linux/of_address.h>
22#include <linux/percpu.h>
23#include <linux/sched.h>
24#include <linux/smp.h>
25
26#include <asm/mips-cps.h>
27#include <asm/setup.h>
28#include <asm/traps.h>
29
30#include <dt-bindings/interrupt-controller/mips-gic.h>
31
32#define GIC_MAX_INTRS 256
33#define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS)
34
35/* Add 2 to convert GIC CPU pin to core interrupt */
36#define GIC_CPU_PIN_OFFSET 2
37
38/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
39#define GIC_PIN_TO_VEC_OFFSET 1
40
41/* Convert between local/shared IRQ number and GIC HW IRQ number. */
42#define GIC_LOCAL_HWIRQ_BASE 0
43#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
44#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
45#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
46#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
47#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
48
49void __iomem *mips_gic_base;
50
51static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
52
53static DEFINE_RAW_SPINLOCK(gic_lock);
54static struct irq_domain *gic_irq_domain;
55static int gic_shared_intrs;
56static unsigned int gic_cpu_pin;
57static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
58
59#ifdef CONFIG_GENERIC_IRQ_IPI
60static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
61static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
62#endif /* CONFIG_GENERIC_IRQ_IPI */
63
64static struct gic_all_vpes_chip_data {
65 u32 map;
66 bool mask;
67} gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
68
69static void gic_clear_pcpu_masks(unsigned int intr)
70{
71 unsigned int i;
72
73 /* Clear the interrupt's bit in all pcpu_masks */
74 for_each_possible_cpu(i)
75 clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
76}
77
78static bool gic_local_irq_is_routable(int intr)
79{
80 u32 vpe_ctl;
81
82 /* All local interrupts are routable in EIC mode. */
83 if (cpu_has_veic)
84 return true;
85
86 vpe_ctl = read_gic_vl_ctl();
87 switch (intr) {
88 case GIC_LOCAL_INT_TIMER:
89 return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
90 case GIC_LOCAL_INT_PERFCTR:
91 return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
92 case GIC_LOCAL_INT_FDC:
93 return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
94 case GIC_LOCAL_INT_SWINT0:
95 case GIC_LOCAL_INT_SWINT1:
96 return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
97 default:
98 return true;
99 }
100}
101
102static void gic_bind_eic_interrupt(int irq, int set)
103{
104 /* Convert irq vector # to hw int # */
105 irq -= GIC_PIN_TO_VEC_OFFSET;
106
107 /* Set irq to use shadow set */
108 write_gic_vl_eic_shadow_set(irq, set);
109}
110
111static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
112{
113 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
114
115 write_gic_wedge(GIC_WEDGE_RW | hwirq);
116}
117
118int gic_get_c0_compare_int(void)
119{
120 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
121 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
122 return irq_create_mapping(gic_irq_domain,
123 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
124}
125
126int gic_get_c0_perfcount_int(void)
127{
128 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
129 /* Is the performance counter shared with the timer? */
130 if (cp0_perfcount_irq < 0)
131 return -1;
132 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
133 }
134 return irq_create_mapping(gic_irq_domain,
135 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
136}
137
138int gic_get_c0_fdc_int(void)
139{
140 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
141 /* Is the FDC IRQ even present? */
142 if (cp0_fdc_irq < 0)
143 return -1;
144 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
145 }
146
147 return irq_create_mapping(gic_irq_domain,
148 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
149}
150
151static void gic_handle_shared_int(bool chained)
152{
153 unsigned int intr;
154 unsigned long *pcpu_mask;
155 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
156
157 /* Get per-cpu bitmaps */
158 pcpu_mask = this_cpu_ptr(pcpu_masks);
159
160 if (mips_cm_is64)
161 __ioread64_copy(pending, addr_gic_pend(),
162 DIV_ROUND_UP(gic_shared_intrs, 64));
163 else
164 __ioread32_copy(pending, addr_gic_pend(),
165 DIV_ROUND_UP(gic_shared_intrs, 32));
166
167 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
168
169 for_each_set_bit(intr, pending, gic_shared_intrs) {
170 if (chained)
171 generic_handle_domain_irq(gic_irq_domain,
172 GIC_SHARED_TO_HWIRQ(intr));
173 else
174 do_domain_IRQ(gic_irq_domain,
175 GIC_SHARED_TO_HWIRQ(intr));
176 }
177}
178
179static void gic_mask_irq(struct irq_data *d)
180{
181 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
182
183 write_gic_rmask(intr);
184 gic_clear_pcpu_masks(intr);
185}
186
187static void gic_unmask_irq(struct irq_data *d)
188{
189 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
190 unsigned int cpu;
191
192 write_gic_smask(intr);
193
194 gic_clear_pcpu_masks(intr);
195 cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
196 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
197}
198
199static void gic_ack_irq(struct irq_data *d)
200{
201 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
202
203 write_gic_wedge(irq);
204}
205
206static int gic_set_type(struct irq_data *d, unsigned int type)
207{
208 unsigned int irq, pol, trig, dual;
209 unsigned long flags;
210
211 irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
212
213 raw_spin_lock_irqsave(&gic_lock, flags);
214 switch (type & IRQ_TYPE_SENSE_MASK) {
215 case IRQ_TYPE_EDGE_FALLING:
216 pol = GIC_POL_FALLING_EDGE;
217 trig = GIC_TRIG_EDGE;
218 dual = GIC_DUAL_SINGLE;
219 break;
220 case IRQ_TYPE_EDGE_RISING:
221 pol = GIC_POL_RISING_EDGE;
222 trig = GIC_TRIG_EDGE;
223 dual = GIC_DUAL_SINGLE;
224 break;
225 case IRQ_TYPE_EDGE_BOTH:
226 pol = 0; /* Doesn't matter */
227 trig = GIC_TRIG_EDGE;
228 dual = GIC_DUAL_DUAL;
229 break;
230 case IRQ_TYPE_LEVEL_LOW:
231 pol = GIC_POL_ACTIVE_LOW;
232 trig = GIC_TRIG_LEVEL;
233 dual = GIC_DUAL_SINGLE;
234 break;
235 case IRQ_TYPE_LEVEL_HIGH:
236 default:
237 pol = GIC_POL_ACTIVE_HIGH;
238 trig = GIC_TRIG_LEVEL;
239 dual = GIC_DUAL_SINGLE;
240 break;
241 }
242
243 change_gic_pol(irq, pol);
244 change_gic_trig(irq, trig);
245 change_gic_dual(irq, dual);
246
247 if (trig == GIC_TRIG_EDGE)
248 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
249 handle_edge_irq, NULL);
250 else
251 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
252 handle_level_irq, NULL);
253 raw_spin_unlock_irqrestore(&gic_lock, flags);
254
255 return 0;
256}
257
258#ifdef CONFIG_SMP
259static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
260 bool force)
261{
262 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
263 unsigned long flags;
264 unsigned int cpu;
265
266 cpu = cpumask_first_and(cpumask, cpu_online_mask);
267 if (cpu >= NR_CPUS)
268 return -EINVAL;
269
270 /* Assumption : cpumask refers to a single CPU */
271 raw_spin_lock_irqsave(&gic_lock, flags);
272
273 /* Re-route this IRQ */
274 write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
275
276 /* Update the pcpu_masks */
277 gic_clear_pcpu_masks(irq);
278 if (read_gic_mask(irq))
279 set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
280
281 irq_data_update_effective_affinity(d, cpumask_of(cpu));
282 raw_spin_unlock_irqrestore(&gic_lock, flags);
283
284 return IRQ_SET_MASK_OK;
285}
286#endif
287
288static struct irq_chip gic_level_irq_controller = {
289 .name = "MIPS GIC",
290 .irq_mask = gic_mask_irq,
291 .irq_unmask = gic_unmask_irq,
292 .irq_set_type = gic_set_type,
293#ifdef CONFIG_SMP
294 .irq_set_affinity = gic_set_affinity,
295#endif
296};
297
298static struct irq_chip gic_edge_irq_controller = {
299 .name = "MIPS GIC",
300 .irq_ack = gic_ack_irq,
301 .irq_mask = gic_mask_irq,
302 .irq_unmask = gic_unmask_irq,
303 .irq_set_type = gic_set_type,
304#ifdef CONFIG_SMP
305 .irq_set_affinity = gic_set_affinity,
306#endif
307 .ipi_send_single = gic_send_ipi,
308};
309
310static void gic_handle_local_int(bool chained)
311{
312 unsigned long pending, masked;
313 unsigned int intr;
314
315 pending = read_gic_vl_pend();
316 masked = read_gic_vl_mask();
317
318 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
319
320 for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
321 if (chained)
322 generic_handle_domain_irq(gic_irq_domain,
323 GIC_LOCAL_TO_HWIRQ(intr));
324 else
325 do_domain_IRQ(gic_irq_domain,
326 GIC_LOCAL_TO_HWIRQ(intr));
327 }
328}
329
330static void gic_mask_local_irq(struct irq_data *d)
331{
332 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
333
334 write_gic_vl_rmask(BIT(intr));
335}
336
337static void gic_unmask_local_irq(struct irq_data *d)
338{
339 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
340
341 write_gic_vl_smask(BIT(intr));
342}
343
344static struct irq_chip gic_local_irq_controller = {
345 .name = "MIPS GIC Local",
346 .irq_mask = gic_mask_local_irq,
347 .irq_unmask = gic_unmask_local_irq,
348};
349
350static void gic_mask_local_irq_all_vpes(struct irq_data *d)
351{
352 struct gic_all_vpes_chip_data *cd;
353 unsigned long flags;
354 int intr, cpu;
355
356 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
357 cd = irq_data_get_irq_chip_data(d);
358 cd->mask = false;
359
360 raw_spin_lock_irqsave(&gic_lock, flags);
361 for_each_online_cpu(cpu) {
362 write_gic_vl_other(mips_cm_vp_id(cpu));
363 write_gic_vo_rmask(BIT(intr));
364 }
365 raw_spin_unlock_irqrestore(&gic_lock, flags);
366}
367
368static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
369{
370 struct gic_all_vpes_chip_data *cd;
371 unsigned long flags;
372 int intr, cpu;
373
374 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
375 cd = irq_data_get_irq_chip_data(d);
376 cd->mask = true;
377
378 raw_spin_lock_irqsave(&gic_lock, flags);
379 for_each_online_cpu(cpu) {
380 write_gic_vl_other(mips_cm_vp_id(cpu));
381 write_gic_vo_smask(BIT(intr));
382 }
383 raw_spin_unlock_irqrestore(&gic_lock, flags);
384}
385
386static void gic_all_vpes_irq_cpu_online(void)
387{
388 static const unsigned int local_intrs[] = {
389 GIC_LOCAL_INT_TIMER,
390 GIC_LOCAL_INT_PERFCTR,
391 GIC_LOCAL_INT_FDC,
392 };
393 unsigned long flags;
394 int i;
395
396 raw_spin_lock_irqsave(&gic_lock, flags);
397
398 for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
399 unsigned int intr = local_intrs[i];
400 struct gic_all_vpes_chip_data *cd;
401
402 if (!gic_local_irq_is_routable(intr))
403 continue;
404 cd = &gic_all_vpes_chip_data[intr];
405 write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
406 if (cd->mask)
407 write_gic_vl_smask(BIT(intr));
408 }
409
410 raw_spin_unlock_irqrestore(&gic_lock, flags);
411}
412
413static struct irq_chip gic_all_vpes_local_irq_controller = {
414 .name = "MIPS GIC Local",
415 .irq_mask = gic_mask_local_irq_all_vpes,
416 .irq_unmask = gic_unmask_local_irq_all_vpes,
417};
418
419static void __gic_irq_dispatch(void)
420{
421 gic_handle_local_int(false);
422 gic_handle_shared_int(false);
423}
424
425static void gic_irq_dispatch(struct irq_desc *desc)
426{
427 gic_handle_local_int(true);
428 gic_handle_shared_int(true);
429}
430
431static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
432 irq_hw_number_t hw, unsigned int cpu)
433{
434 int intr = GIC_HWIRQ_TO_SHARED(hw);
435 struct irq_data *data;
436 unsigned long flags;
437
438 data = irq_get_irq_data(virq);
439
440 raw_spin_lock_irqsave(&gic_lock, flags);
441 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
442 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
443 irq_data_update_effective_affinity(data, cpumask_of(cpu));
444 raw_spin_unlock_irqrestore(&gic_lock, flags);
445
446 return 0;
447}
448
449static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
450 const u32 *intspec, unsigned int intsize,
451 irq_hw_number_t *out_hwirq,
452 unsigned int *out_type)
453{
454 if (intsize != 3)
455 return -EINVAL;
456
457 if (intspec[0] == GIC_SHARED)
458 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
459 else if (intspec[0] == GIC_LOCAL)
460 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
461 else
462 return -EINVAL;
463 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
464
465 return 0;
466}
467
468static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
469 irq_hw_number_t hwirq)
470{
471 struct gic_all_vpes_chip_data *cd;
472 unsigned long flags;
473 unsigned int intr;
474 int err, cpu;
475 u32 map;
476
477 if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
478#ifdef CONFIG_GENERIC_IRQ_IPI
479 /* verify that shared irqs don't conflict with an IPI irq */
480 if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
481 return -EBUSY;
482#endif /* CONFIG_GENERIC_IRQ_IPI */
483
484 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
485 &gic_level_irq_controller,
486 NULL);
487 if (err)
488 return err;
489
490 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
491 return gic_shared_irq_domain_map(d, virq, hwirq, 0);
492 }
493
494 intr = GIC_HWIRQ_TO_LOCAL(hwirq);
495 map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
496
497 /*
498 * If adding support for more per-cpu interrupts, keep the
499 * array in gic_all_vpes_irq_cpu_online() in sync.
500 */
501 switch (intr) {
502 case GIC_LOCAL_INT_TIMER:
503 case GIC_LOCAL_INT_PERFCTR:
504 case GIC_LOCAL_INT_FDC:
505 /*
506 * HACK: These are all really percpu interrupts, but
507 * the rest of the MIPS kernel code does not use the
508 * percpu IRQ API for them.
509 */
510 cd = &gic_all_vpes_chip_data[intr];
511 cd->map = map;
512 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
513 &gic_all_vpes_local_irq_controller,
514 cd);
515 if (err)
516 return err;
517
518 irq_set_handler(virq, handle_percpu_irq);
519 break;
520
521 default:
522 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
523 &gic_local_irq_controller,
524 NULL);
525 if (err)
526 return err;
527
528 irq_set_handler(virq, handle_percpu_devid_irq);
529 irq_set_percpu_devid(virq);
530 break;
531 }
532
533 if (!gic_local_irq_is_routable(intr))
534 return -EPERM;
535
536 raw_spin_lock_irqsave(&gic_lock, flags);
537 for_each_online_cpu(cpu) {
538 write_gic_vl_other(mips_cm_vp_id(cpu));
539 write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
540 }
541 raw_spin_unlock_irqrestore(&gic_lock, flags);
542
543 return 0;
544}
545
546static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
547 unsigned int nr_irqs, void *arg)
548{
549 struct irq_fwspec *fwspec = arg;
550 irq_hw_number_t hwirq;
551
552 if (fwspec->param[0] == GIC_SHARED)
553 hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
554 else
555 hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
556
557 return gic_irq_domain_map(d, virq, hwirq);
558}
559
560static void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
561 unsigned int nr_irqs)
562{
563}
564
565static const struct irq_domain_ops gic_irq_domain_ops = {
566 .xlate = gic_irq_domain_xlate,
567 .alloc = gic_irq_domain_alloc,
568 .free = gic_irq_domain_free,
569 .map = gic_irq_domain_map,
570};
571
572#ifdef CONFIG_GENERIC_IRQ_IPI
573
574static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
575 const u32 *intspec, unsigned int intsize,
576 irq_hw_number_t *out_hwirq,
577 unsigned int *out_type)
578{
579 /*
580 * There's nothing to translate here. hwirq is dynamically allocated and
581 * the irq type is always edge triggered.
582 * */
583 *out_hwirq = 0;
584 *out_type = IRQ_TYPE_EDGE_RISING;
585
586 return 0;
587}
588
589static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
590 unsigned int nr_irqs, void *arg)
591{
592 struct cpumask *ipimask = arg;
593 irq_hw_number_t hwirq, base_hwirq;
594 int cpu, ret, i;
595
596 base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
597 if (base_hwirq == gic_shared_intrs)
598 return -ENOMEM;
599
600 /* check that we have enough space */
601 for (i = base_hwirq; i < nr_irqs; i++) {
602 if (!test_bit(i, ipi_available))
603 return -EBUSY;
604 }
605 bitmap_clear(ipi_available, base_hwirq, nr_irqs);
606
607 /* map the hwirq for each cpu consecutively */
608 i = 0;
609 for_each_cpu(cpu, ipimask) {
610 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
611
612 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
613 &gic_edge_irq_controller,
614 NULL);
615 if (ret)
616 goto error;
617
618 ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
619 &gic_edge_irq_controller,
620 NULL);
621 if (ret)
622 goto error;
623
624 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
625 if (ret)
626 goto error;
627
628 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
629 if (ret)
630 goto error;
631
632 i++;
633 }
634
635 return 0;
636error:
637 bitmap_set(ipi_available, base_hwirq, nr_irqs);
638 return ret;
639}
640
641static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
642 unsigned int nr_irqs)
643{
644 irq_hw_number_t base_hwirq;
645 struct irq_data *data;
646
647 data = irq_get_irq_data(virq);
648 if (!data)
649 return;
650
651 base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
652 bitmap_set(ipi_available, base_hwirq, nr_irqs);
653}
654
655static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
656 enum irq_domain_bus_token bus_token)
657{
658 bool is_ipi;
659
660 switch (bus_token) {
661 case DOMAIN_BUS_IPI:
662 is_ipi = d->bus_token == bus_token;
663 return (!node || to_of_node(d->fwnode) == node) && is_ipi;
664 break;
665 default:
666 return 0;
667 }
668}
669
670static const struct irq_domain_ops gic_ipi_domain_ops = {
671 .xlate = gic_ipi_domain_xlate,
672 .alloc = gic_ipi_domain_alloc,
673 .free = gic_ipi_domain_free,
674 .match = gic_ipi_domain_match,
675};
676
677static int gic_register_ipi_domain(struct device_node *node)
678{
679 struct irq_domain *gic_ipi_domain;
680 unsigned int v[2], num_ipis;
681
682 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
683 IRQ_DOMAIN_FLAG_IPI_PER_CPU,
684 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
685 node, &gic_ipi_domain_ops, NULL);
686 if (!gic_ipi_domain) {
687 pr_err("Failed to add IPI domain");
688 return -ENXIO;
689 }
690
691 irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
692
693 if (node &&
694 !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
695 bitmap_set(ipi_resrv, v[0], v[1]);
696 } else {
697 /*
698 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
699 * meeting the requirements of arch/mips SMP.
700 */
701 num_ipis = 2 * num_possible_cpus();
702 bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
703 }
704
705 bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
706
707 return 0;
708}
709
710#else /* !CONFIG_GENERIC_IRQ_IPI */
711
712static inline int gic_register_ipi_domain(struct device_node *node)
713{
714 return 0;
715}
716
717#endif /* !CONFIG_GENERIC_IRQ_IPI */
718
719static int gic_cpu_startup(unsigned int cpu)
720{
721 /* Enable or disable EIC */
722 change_gic_vl_ctl(GIC_VX_CTL_EIC,
723 cpu_has_veic ? GIC_VX_CTL_EIC : 0);
724
725 /* Clear all local IRQ masks (ie. disable all local interrupts) */
726 write_gic_vl_rmask(~0);
727
728 /* Enable desired interrupts */
729 gic_all_vpes_irq_cpu_online();
730
731 return 0;
732}
733
734static int __init gic_of_init(struct device_node *node,
735 struct device_node *parent)
736{
737 unsigned int cpu_vec, i, gicconfig;
738 unsigned long reserved;
739 phys_addr_t gic_base;
740 struct resource res;
741 size_t gic_len;
742 int ret;
743
744 /* Find the first available CPU vector. */
745 i = 0;
746 reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
747 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
748 i++, &cpu_vec))
749 reserved |= BIT(cpu_vec);
750
751 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
752 if (cpu_vec == hweight_long(ST0_IM)) {
753 pr_err("No CPU vectors available\n");
754 return -ENODEV;
755 }
756
757 if (of_address_to_resource(node, 0, &res)) {
758 /*
759 * Probe the CM for the GIC base address if not specified
760 * in the device-tree.
761 */
762 if (mips_cm_present()) {
763 gic_base = read_gcr_gic_base() &
764 ~CM_GCR_GIC_BASE_GICEN;
765 gic_len = 0x20000;
766 pr_warn("Using inherited base address %pa\n",
767 &gic_base);
768 } else {
769 pr_err("Failed to get memory range\n");
770 return -ENODEV;
771 }
772 } else {
773 gic_base = res.start;
774 gic_len = resource_size(&res);
775 }
776
777 if (mips_cm_present()) {
778 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
779 /* Ensure GIC region is enabled before trying to access it */
780 __sync();
781 }
782
783 mips_gic_base = ioremap(gic_base, gic_len);
784 if (!mips_gic_base) {
785 pr_err("Failed to ioremap gic_base\n");
786 return -ENOMEM;
787 }
788
789 gicconfig = read_gic_config();
790 gic_shared_intrs = FIELD_GET(GIC_CONFIG_NUMINTERRUPTS, gicconfig);
791 gic_shared_intrs = (gic_shared_intrs + 1) * 8;
792
793 if (cpu_has_veic) {
794 /* Always use vector 1 in EIC mode */
795 gic_cpu_pin = 0;
796 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
797 __gic_irq_dispatch);
798 } else {
799 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
800 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
801 gic_irq_dispatch);
802 }
803
804 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
805 gic_shared_intrs, 0,
806 &gic_irq_domain_ops, NULL);
807 if (!gic_irq_domain) {
808 pr_err("Failed to add IRQ domain");
809 return -ENXIO;
810 }
811
812 ret = gic_register_ipi_domain(node);
813 if (ret)
814 return ret;
815
816 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
817
818 /* Setup defaults */
819 for (i = 0; i < gic_shared_intrs; i++) {
820 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
821 change_gic_trig(i, GIC_TRIG_LEVEL);
822 write_gic_rmask(i);
823 }
824
825 return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
826 "irqchip/mips/gic:starting",
827 gic_cpu_startup, NULL);
828}
829IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 */
9
10#define pr_fmt(fmt) "irq-mips-gic: " fmt
11
12#include <linux/bitmap.h>
13#include <linux/clocksource.h>
14#include <linux/cpuhotplug.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/irqchip.h>
19#include <linux/irqdomain.h>
20#include <linux/of_address.h>
21#include <linux/percpu.h>
22#include <linux/sched.h>
23#include <linux/smp.h>
24
25#include <asm/mips-cps.h>
26#include <asm/setup.h>
27#include <asm/traps.h>
28
29#include <dt-bindings/interrupt-controller/mips-gic.h>
30
31#define GIC_MAX_INTRS 256
32#define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS)
33
34/* Add 2 to convert GIC CPU pin to core interrupt */
35#define GIC_CPU_PIN_OFFSET 2
36
37/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
38#define GIC_PIN_TO_VEC_OFFSET 1
39
40/* Convert between local/shared IRQ number and GIC HW IRQ number. */
41#define GIC_LOCAL_HWIRQ_BASE 0
42#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
43#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
44#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
45#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
46#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
47
48void __iomem *mips_gic_base;
49
50static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
51
52static DEFINE_SPINLOCK(gic_lock);
53static struct irq_domain *gic_irq_domain;
54static struct irq_domain *gic_ipi_domain;
55static int gic_shared_intrs;
56static unsigned int gic_cpu_pin;
57static unsigned int timer_cpu_pin;
58static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
59static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
60static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
61
62static struct gic_all_vpes_chip_data {
63 u32 map;
64 bool mask;
65} gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
66
67static void gic_clear_pcpu_masks(unsigned int intr)
68{
69 unsigned int i;
70
71 /* Clear the interrupt's bit in all pcpu_masks */
72 for_each_possible_cpu(i)
73 clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
74}
75
76static bool gic_local_irq_is_routable(int intr)
77{
78 u32 vpe_ctl;
79
80 /* All local interrupts are routable in EIC mode. */
81 if (cpu_has_veic)
82 return true;
83
84 vpe_ctl = read_gic_vl_ctl();
85 switch (intr) {
86 case GIC_LOCAL_INT_TIMER:
87 return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
88 case GIC_LOCAL_INT_PERFCTR:
89 return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
90 case GIC_LOCAL_INT_FDC:
91 return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
92 case GIC_LOCAL_INT_SWINT0:
93 case GIC_LOCAL_INT_SWINT1:
94 return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
95 default:
96 return true;
97 }
98}
99
100static void gic_bind_eic_interrupt(int irq, int set)
101{
102 /* Convert irq vector # to hw int # */
103 irq -= GIC_PIN_TO_VEC_OFFSET;
104
105 /* Set irq to use shadow set */
106 write_gic_vl_eic_shadow_set(irq, set);
107}
108
109static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
110{
111 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
112
113 write_gic_wedge(GIC_WEDGE_RW | hwirq);
114}
115
116int gic_get_c0_compare_int(void)
117{
118 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
119 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
120 return irq_create_mapping(gic_irq_domain,
121 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
122}
123
124int gic_get_c0_perfcount_int(void)
125{
126 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
127 /* Is the performance counter shared with the timer? */
128 if (cp0_perfcount_irq < 0)
129 return -1;
130 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
131 }
132 return irq_create_mapping(gic_irq_domain,
133 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
134}
135
136int gic_get_c0_fdc_int(void)
137{
138 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
139 /* Is the FDC IRQ even present? */
140 if (cp0_fdc_irq < 0)
141 return -1;
142 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
143 }
144
145 return irq_create_mapping(gic_irq_domain,
146 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
147}
148
149static void gic_handle_shared_int(bool chained)
150{
151 unsigned int intr;
152 unsigned long *pcpu_mask;
153 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
154
155 /* Get per-cpu bitmaps */
156 pcpu_mask = this_cpu_ptr(pcpu_masks);
157
158 if (mips_cm_is64)
159 __ioread64_copy(pending, addr_gic_pend(),
160 DIV_ROUND_UP(gic_shared_intrs, 64));
161 else
162 __ioread32_copy(pending, addr_gic_pend(),
163 DIV_ROUND_UP(gic_shared_intrs, 32));
164
165 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
166
167 for_each_set_bit(intr, pending, gic_shared_intrs) {
168 if (chained)
169 generic_handle_domain_irq(gic_irq_domain,
170 GIC_SHARED_TO_HWIRQ(intr));
171 else
172 do_domain_IRQ(gic_irq_domain,
173 GIC_SHARED_TO_HWIRQ(intr));
174 }
175}
176
177static void gic_mask_irq(struct irq_data *d)
178{
179 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
180
181 write_gic_rmask(intr);
182 gic_clear_pcpu_masks(intr);
183}
184
185static void gic_unmask_irq(struct irq_data *d)
186{
187 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
188 unsigned int cpu;
189
190 write_gic_smask(intr);
191
192 gic_clear_pcpu_masks(intr);
193 cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
194 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
195}
196
197static void gic_ack_irq(struct irq_data *d)
198{
199 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
200
201 write_gic_wedge(irq);
202}
203
204static int gic_set_type(struct irq_data *d, unsigned int type)
205{
206 unsigned int irq, pol, trig, dual;
207 unsigned long flags;
208
209 irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
210
211 spin_lock_irqsave(&gic_lock, flags);
212 switch (type & IRQ_TYPE_SENSE_MASK) {
213 case IRQ_TYPE_EDGE_FALLING:
214 pol = GIC_POL_FALLING_EDGE;
215 trig = GIC_TRIG_EDGE;
216 dual = GIC_DUAL_SINGLE;
217 break;
218 case IRQ_TYPE_EDGE_RISING:
219 pol = GIC_POL_RISING_EDGE;
220 trig = GIC_TRIG_EDGE;
221 dual = GIC_DUAL_SINGLE;
222 break;
223 case IRQ_TYPE_EDGE_BOTH:
224 pol = 0; /* Doesn't matter */
225 trig = GIC_TRIG_EDGE;
226 dual = GIC_DUAL_DUAL;
227 break;
228 case IRQ_TYPE_LEVEL_LOW:
229 pol = GIC_POL_ACTIVE_LOW;
230 trig = GIC_TRIG_LEVEL;
231 dual = GIC_DUAL_SINGLE;
232 break;
233 case IRQ_TYPE_LEVEL_HIGH:
234 default:
235 pol = GIC_POL_ACTIVE_HIGH;
236 trig = GIC_TRIG_LEVEL;
237 dual = GIC_DUAL_SINGLE;
238 break;
239 }
240
241 change_gic_pol(irq, pol);
242 change_gic_trig(irq, trig);
243 change_gic_dual(irq, dual);
244
245 if (trig == GIC_TRIG_EDGE)
246 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
247 handle_edge_irq, NULL);
248 else
249 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
250 handle_level_irq, NULL);
251 spin_unlock_irqrestore(&gic_lock, flags);
252
253 return 0;
254}
255
256#ifdef CONFIG_SMP
257static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
258 bool force)
259{
260 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
261 unsigned long flags;
262 unsigned int cpu;
263
264 cpu = cpumask_first_and(cpumask, cpu_online_mask);
265 if (cpu >= NR_CPUS)
266 return -EINVAL;
267
268 /* Assumption : cpumask refers to a single CPU */
269 spin_lock_irqsave(&gic_lock, flags);
270
271 /* Re-route this IRQ */
272 write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
273
274 /* Update the pcpu_masks */
275 gic_clear_pcpu_masks(irq);
276 if (read_gic_mask(irq))
277 set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
278
279 irq_data_update_effective_affinity(d, cpumask_of(cpu));
280 spin_unlock_irqrestore(&gic_lock, flags);
281
282 return IRQ_SET_MASK_OK;
283}
284#endif
285
286static struct irq_chip gic_level_irq_controller = {
287 .name = "MIPS GIC",
288 .irq_mask = gic_mask_irq,
289 .irq_unmask = gic_unmask_irq,
290 .irq_set_type = gic_set_type,
291#ifdef CONFIG_SMP
292 .irq_set_affinity = gic_set_affinity,
293#endif
294};
295
296static struct irq_chip gic_edge_irq_controller = {
297 .name = "MIPS GIC",
298 .irq_ack = gic_ack_irq,
299 .irq_mask = gic_mask_irq,
300 .irq_unmask = gic_unmask_irq,
301 .irq_set_type = gic_set_type,
302#ifdef CONFIG_SMP
303 .irq_set_affinity = gic_set_affinity,
304#endif
305 .ipi_send_single = gic_send_ipi,
306};
307
308static void gic_handle_local_int(bool chained)
309{
310 unsigned long pending, masked;
311 unsigned int intr;
312
313 pending = read_gic_vl_pend();
314 masked = read_gic_vl_mask();
315
316 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
317
318 for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
319 if (chained)
320 generic_handle_domain_irq(gic_irq_domain,
321 GIC_LOCAL_TO_HWIRQ(intr));
322 else
323 do_domain_IRQ(gic_irq_domain,
324 GIC_LOCAL_TO_HWIRQ(intr));
325 }
326}
327
328static void gic_mask_local_irq(struct irq_data *d)
329{
330 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
331
332 write_gic_vl_rmask(BIT(intr));
333}
334
335static void gic_unmask_local_irq(struct irq_data *d)
336{
337 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
338
339 write_gic_vl_smask(BIT(intr));
340}
341
342static struct irq_chip gic_local_irq_controller = {
343 .name = "MIPS GIC Local",
344 .irq_mask = gic_mask_local_irq,
345 .irq_unmask = gic_unmask_local_irq,
346};
347
348static void gic_mask_local_irq_all_vpes(struct irq_data *d)
349{
350 struct gic_all_vpes_chip_data *cd;
351 unsigned long flags;
352 int intr, cpu;
353
354 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
355 cd = irq_data_get_irq_chip_data(d);
356 cd->mask = false;
357
358 spin_lock_irqsave(&gic_lock, flags);
359 for_each_online_cpu(cpu) {
360 write_gic_vl_other(mips_cm_vp_id(cpu));
361 write_gic_vo_rmask(BIT(intr));
362 }
363 spin_unlock_irqrestore(&gic_lock, flags);
364}
365
366static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
367{
368 struct gic_all_vpes_chip_data *cd;
369 unsigned long flags;
370 int intr, cpu;
371
372 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
373 cd = irq_data_get_irq_chip_data(d);
374 cd->mask = true;
375
376 spin_lock_irqsave(&gic_lock, flags);
377 for_each_online_cpu(cpu) {
378 write_gic_vl_other(mips_cm_vp_id(cpu));
379 write_gic_vo_smask(BIT(intr));
380 }
381 spin_unlock_irqrestore(&gic_lock, flags);
382}
383
384static void gic_all_vpes_irq_cpu_online(struct irq_data *d)
385{
386 struct gic_all_vpes_chip_data *cd;
387 unsigned int intr;
388
389 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
390 cd = irq_data_get_irq_chip_data(d);
391
392 write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
393 if (cd->mask)
394 write_gic_vl_smask(BIT(intr));
395}
396
397static struct irq_chip gic_all_vpes_local_irq_controller = {
398 .name = "MIPS GIC Local",
399 .irq_mask = gic_mask_local_irq_all_vpes,
400 .irq_unmask = gic_unmask_local_irq_all_vpes,
401 .irq_cpu_online = gic_all_vpes_irq_cpu_online,
402};
403
404static void __gic_irq_dispatch(void)
405{
406 gic_handle_local_int(false);
407 gic_handle_shared_int(false);
408}
409
410static void gic_irq_dispatch(struct irq_desc *desc)
411{
412 gic_handle_local_int(true);
413 gic_handle_shared_int(true);
414}
415
416static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
417 irq_hw_number_t hw, unsigned int cpu)
418{
419 int intr = GIC_HWIRQ_TO_SHARED(hw);
420 struct irq_data *data;
421 unsigned long flags;
422
423 data = irq_get_irq_data(virq);
424
425 spin_lock_irqsave(&gic_lock, flags);
426 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
427 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
428 irq_data_update_effective_affinity(data, cpumask_of(cpu));
429 spin_unlock_irqrestore(&gic_lock, flags);
430
431 return 0;
432}
433
434static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
435 const u32 *intspec, unsigned int intsize,
436 irq_hw_number_t *out_hwirq,
437 unsigned int *out_type)
438{
439 if (intsize != 3)
440 return -EINVAL;
441
442 if (intspec[0] == GIC_SHARED)
443 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
444 else if (intspec[0] == GIC_LOCAL)
445 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
446 else
447 return -EINVAL;
448 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
449
450 return 0;
451}
452
453static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
454 irq_hw_number_t hwirq)
455{
456 struct gic_all_vpes_chip_data *cd;
457 unsigned long flags;
458 unsigned int intr;
459 int err, cpu;
460 u32 map;
461
462 if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
463 /* verify that shared irqs don't conflict with an IPI irq */
464 if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
465 return -EBUSY;
466
467 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
468 &gic_level_irq_controller,
469 NULL);
470 if (err)
471 return err;
472
473 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
474 return gic_shared_irq_domain_map(d, virq, hwirq, 0);
475 }
476
477 intr = GIC_HWIRQ_TO_LOCAL(hwirq);
478 map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
479
480 switch (intr) {
481 case GIC_LOCAL_INT_TIMER:
482 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
483 map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
484 fallthrough;
485 case GIC_LOCAL_INT_PERFCTR:
486 case GIC_LOCAL_INT_FDC:
487 /*
488 * HACK: These are all really percpu interrupts, but
489 * the rest of the MIPS kernel code does not use the
490 * percpu IRQ API for them.
491 */
492 cd = &gic_all_vpes_chip_data[intr];
493 cd->map = map;
494 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
495 &gic_all_vpes_local_irq_controller,
496 cd);
497 if (err)
498 return err;
499
500 irq_set_handler(virq, handle_percpu_irq);
501 break;
502
503 default:
504 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
505 &gic_local_irq_controller,
506 NULL);
507 if (err)
508 return err;
509
510 irq_set_handler(virq, handle_percpu_devid_irq);
511 irq_set_percpu_devid(virq);
512 break;
513 }
514
515 if (!gic_local_irq_is_routable(intr))
516 return -EPERM;
517
518 spin_lock_irqsave(&gic_lock, flags);
519 for_each_online_cpu(cpu) {
520 write_gic_vl_other(mips_cm_vp_id(cpu));
521 write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
522 }
523 spin_unlock_irqrestore(&gic_lock, flags);
524
525 return 0;
526}
527
528static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
529 unsigned int nr_irqs, void *arg)
530{
531 struct irq_fwspec *fwspec = arg;
532 irq_hw_number_t hwirq;
533
534 if (fwspec->param[0] == GIC_SHARED)
535 hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
536 else
537 hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
538
539 return gic_irq_domain_map(d, virq, hwirq);
540}
541
542void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
543 unsigned int nr_irqs)
544{
545}
546
547static const struct irq_domain_ops gic_irq_domain_ops = {
548 .xlate = gic_irq_domain_xlate,
549 .alloc = gic_irq_domain_alloc,
550 .free = gic_irq_domain_free,
551 .map = gic_irq_domain_map,
552};
553
554static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
555 const u32 *intspec, unsigned int intsize,
556 irq_hw_number_t *out_hwirq,
557 unsigned int *out_type)
558{
559 /*
560 * There's nothing to translate here. hwirq is dynamically allocated and
561 * the irq type is always edge triggered.
562 * */
563 *out_hwirq = 0;
564 *out_type = IRQ_TYPE_EDGE_RISING;
565
566 return 0;
567}
568
569static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
570 unsigned int nr_irqs, void *arg)
571{
572 struct cpumask *ipimask = arg;
573 irq_hw_number_t hwirq, base_hwirq;
574 int cpu, ret, i;
575
576 base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
577 if (base_hwirq == gic_shared_intrs)
578 return -ENOMEM;
579
580 /* check that we have enough space */
581 for (i = base_hwirq; i < nr_irqs; i++) {
582 if (!test_bit(i, ipi_available))
583 return -EBUSY;
584 }
585 bitmap_clear(ipi_available, base_hwirq, nr_irqs);
586
587 /* map the hwirq for each cpu consecutively */
588 i = 0;
589 for_each_cpu(cpu, ipimask) {
590 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
591
592 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
593 &gic_edge_irq_controller,
594 NULL);
595 if (ret)
596 goto error;
597
598 ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
599 &gic_edge_irq_controller,
600 NULL);
601 if (ret)
602 goto error;
603
604 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
605 if (ret)
606 goto error;
607
608 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
609 if (ret)
610 goto error;
611
612 i++;
613 }
614
615 return 0;
616error:
617 bitmap_set(ipi_available, base_hwirq, nr_irqs);
618 return ret;
619}
620
621static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
622 unsigned int nr_irqs)
623{
624 irq_hw_number_t base_hwirq;
625 struct irq_data *data;
626
627 data = irq_get_irq_data(virq);
628 if (!data)
629 return;
630
631 base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
632 bitmap_set(ipi_available, base_hwirq, nr_irqs);
633}
634
635static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
636 enum irq_domain_bus_token bus_token)
637{
638 bool is_ipi;
639
640 switch (bus_token) {
641 case DOMAIN_BUS_IPI:
642 is_ipi = d->bus_token == bus_token;
643 return (!node || to_of_node(d->fwnode) == node) && is_ipi;
644 break;
645 default:
646 return 0;
647 }
648}
649
650static const struct irq_domain_ops gic_ipi_domain_ops = {
651 .xlate = gic_ipi_domain_xlate,
652 .alloc = gic_ipi_domain_alloc,
653 .free = gic_ipi_domain_free,
654 .match = gic_ipi_domain_match,
655};
656
657static int gic_cpu_startup(unsigned int cpu)
658{
659 /* Enable or disable EIC */
660 change_gic_vl_ctl(GIC_VX_CTL_EIC,
661 cpu_has_veic ? GIC_VX_CTL_EIC : 0);
662
663 /* Clear all local IRQ masks (ie. disable all local interrupts) */
664 write_gic_vl_rmask(~0);
665
666 /* Invoke irq_cpu_online callbacks to enable desired interrupts */
667 irq_cpu_online();
668
669 return 0;
670}
671
672static int __init gic_of_init(struct device_node *node,
673 struct device_node *parent)
674{
675 unsigned int cpu_vec, i, gicconfig, v[2], num_ipis;
676 unsigned long reserved;
677 phys_addr_t gic_base;
678 struct resource res;
679 size_t gic_len;
680
681 /* Find the first available CPU vector. */
682 i = 0;
683 reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
684 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
685 i++, &cpu_vec))
686 reserved |= BIT(cpu_vec);
687
688 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
689 if (cpu_vec == hweight_long(ST0_IM)) {
690 pr_err("No CPU vectors available\n");
691 return -ENODEV;
692 }
693
694 if (of_address_to_resource(node, 0, &res)) {
695 /*
696 * Probe the CM for the GIC base address if not specified
697 * in the device-tree.
698 */
699 if (mips_cm_present()) {
700 gic_base = read_gcr_gic_base() &
701 ~CM_GCR_GIC_BASE_GICEN;
702 gic_len = 0x20000;
703 pr_warn("Using inherited base address %pa\n",
704 &gic_base);
705 } else {
706 pr_err("Failed to get memory range\n");
707 return -ENODEV;
708 }
709 } else {
710 gic_base = res.start;
711 gic_len = resource_size(&res);
712 }
713
714 if (mips_cm_present()) {
715 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
716 /* Ensure GIC region is enabled before trying to access it */
717 __sync();
718 }
719
720 mips_gic_base = ioremap(gic_base, gic_len);
721
722 gicconfig = read_gic_config();
723 gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
724 gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS);
725 gic_shared_intrs = (gic_shared_intrs + 1) * 8;
726
727 if (cpu_has_veic) {
728 /* Always use vector 1 in EIC mode */
729 gic_cpu_pin = 0;
730 timer_cpu_pin = gic_cpu_pin;
731 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
732 __gic_irq_dispatch);
733 } else {
734 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
735 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
736 gic_irq_dispatch);
737 /*
738 * With the CMP implementation of SMP (deprecated), other CPUs
739 * are started by the bootloader and put into a timer based
740 * waiting poll loop. We must not re-route those CPU's local
741 * timer interrupts as the wait instruction will never finish,
742 * so just handle whatever CPU interrupt it is routed to by
743 * default.
744 *
745 * This workaround should be removed when CMP support is
746 * dropped.
747 */
748 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
749 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
750 timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
751 irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
752 GIC_CPU_PIN_OFFSET +
753 timer_cpu_pin,
754 gic_irq_dispatch);
755 } else {
756 timer_cpu_pin = gic_cpu_pin;
757 }
758 }
759
760 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
761 gic_shared_intrs, 0,
762 &gic_irq_domain_ops, NULL);
763 if (!gic_irq_domain) {
764 pr_err("Failed to add IRQ domain");
765 return -ENXIO;
766 }
767
768 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
769 IRQ_DOMAIN_FLAG_IPI_PER_CPU,
770 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
771 node, &gic_ipi_domain_ops, NULL);
772 if (!gic_ipi_domain) {
773 pr_err("Failed to add IPI domain");
774 return -ENXIO;
775 }
776
777 irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
778
779 if (node &&
780 !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
781 bitmap_set(ipi_resrv, v[0], v[1]);
782 } else {
783 /*
784 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
785 * meeting the requirements of arch/mips SMP.
786 */
787 num_ipis = 2 * num_possible_cpus();
788 bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
789 }
790
791 bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
792
793 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
794
795 /* Setup defaults */
796 for (i = 0; i < gic_shared_intrs; i++) {
797 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
798 change_gic_trig(i, GIC_TRIG_LEVEL);
799 write_gic_rmask(i);
800 }
801
802 return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
803 "irqchip/mips/gic:starting",
804 gic_cpu_startup, NULL);
805}
806IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);