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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 */
5
6#ifndef __ASM_ARC_CMPXCHG_H
7#define __ASM_ARC_CMPXCHG_H
8
9#include <linux/build_bug.h>
10#include <linux/types.h>
11
12#include <asm/barrier.h>
13#include <asm/smp.h>
14
15#ifdef CONFIG_ARC_HAS_LLSC
16
17/*
18 * if (*ptr == @old)
19 * *ptr = @new
20 */
21#define __cmpxchg(ptr, old, new) \
22({ \
23 __typeof__(*(ptr)) _prev; \
24 \
25 __asm__ __volatile__( \
26 "1: llock %0, [%1] \n" \
27 " brne %0, %2, 2f \n" \
28 " scond %3, [%1] \n" \
29 " bnz 1b \n" \
30 "2: \n" \
31 : "=&r"(_prev) /* Early clobber prevent reg reuse */ \
32 : "r"(ptr), /* Not "m": llock only supports reg */ \
33 "ir"(old), \
34 "r"(new) /* Not "ir": scond can't take LIMM */ \
35 : "cc", \
36 "memory"); /* gcc knows memory is clobbered */ \
37 \
38 _prev; \
39})
40
41#define arch_cmpxchg_relaxed(ptr, old, new) \
42({ \
43 __typeof__(ptr) _p_ = (ptr); \
44 __typeof__(*(ptr)) _o_ = (old); \
45 __typeof__(*(ptr)) _n_ = (new); \
46 __typeof__(*(ptr)) _prev_; \
47 \
48 switch(sizeof((_p_))) { \
49 case 4: \
50 _prev_ = __cmpxchg(_p_, _o_, _n_); \
51 break; \
52 default: \
53 BUILD_BUG(); \
54 } \
55 _prev_; \
56})
57
58#else
59
60#define arch_cmpxchg(ptr, old, new) \
61({ \
62 volatile __typeof__(ptr) _p_ = (ptr); \
63 __typeof__(*(ptr)) _o_ = (old); \
64 __typeof__(*(ptr)) _n_ = (new); \
65 __typeof__(*(ptr)) _prev_; \
66 unsigned long __flags; \
67 \
68 BUILD_BUG_ON(sizeof(_p_) != 4); \
69 \
70 /* \
71 * spin lock/unlock provide the needed smp_mb() before/after \
72 */ \
73 atomic_ops_lock(__flags); \
74 _prev_ = *_p_; \
75 if (_prev_ == _o_) \
76 *_p_ = _n_; \
77 atomic_ops_unlock(__flags); \
78 _prev_; \
79})
80
81#endif
82
83/*
84 * xchg
85 */
86#ifdef CONFIG_ARC_HAS_LLSC
87
88#define __arch_xchg(ptr, val) \
89({ \
90 __asm__ __volatile__( \
91 " ex %0, [%1] \n" /* set new value */ \
92 : "+r"(val) \
93 : "r"(ptr) \
94 : "memory"); \
95 _val_; /* get old value */ \
96})
97
98#define arch_xchg_relaxed(ptr, val) \
99({ \
100 __typeof__(ptr) _p_ = (ptr); \
101 __typeof__(*(ptr)) _val_ = (val); \
102 \
103 switch(sizeof(*(_p_))) { \
104 case 4: \
105 _val_ = __arch_xchg(_p_, _val_); \
106 break; \
107 default: \
108 BUILD_BUG(); \
109 } \
110 _val_; \
111})
112
113#else /* !CONFIG_ARC_HAS_LLSC */
114
115/*
116 * EX instructions is baseline and present in !LLSC too. But in this
117 * regime it still needs use @atomic_ops_lock spinlock to allow interop
118 * with cmpxchg() which uses spinlock in !LLSC
119 * (llist.h use xchg and cmpxchg on sama data)
120 */
121
122#define arch_xchg(ptr, val) \
123({ \
124 __typeof__(ptr) _p_ = (ptr); \
125 __typeof__(*(ptr)) _val_ = (val); \
126 \
127 unsigned long __flags; \
128 \
129 atomic_ops_lock(__flags); \
130 \
131 __asm__ __volatile__( \
132 " ex %0, [%1] \n" \
133 : "+r"(_val_) \
134 : "r"(_p_) \
135 : "memory"); \
136 \
137 atomic_ops_unlock(__flags); \
138 _val_; \
139})
140
141#endif
142
143#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 */
5
6#ifndef __ASM_ARC_CMPXCHG_H
7#define __ASM_ARC_CMPXCHG_H
8
9#include <linux/types.h>
10
11#include <asm/barrier.h>
12#include <asm/smp.h>
13
14#ifdef CONFIG_ARC_HAS_LLSC
15
16static inline unsigned long
17__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
18{
19 unsigned long prev;
20
21 /*
22 * Explicit full memory barrier needed before/after as
23 * LLOCK/SCOND themselves don't provide any such semantics
24 */
25 smp_mb();
26
27 __asm__ __volatile__(
28 "1: llock %0, [%1] \n"
29 " brne %0, %2, 2f \n"
30 " scond %3, [%1] \n"
31 " bnz 1b \n"
32 "2: \n"
33 : "=&r"(prev) /* Early clobber, to prevent reg reuse */
34 : "r"(ptr), /* Not "m": llock only supports reg direct addr mode */
35 "ir"(expected),
36 "r"(new) /* can't be "ir". scond can't take LIMM for "b" */
37 : "cc", "memory"); /* so that gcc knows memory is being written here */
38
39 smp_mb();
40
41 return prev;
42}
43
44#else /* !CONFIG_ARC_HAS_LLSC */
45
46static inline unsigned long
47__cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new)
48{
49 unsigned long flags;
50 int prev;
51 volatile unsigned long *p = ptr;
52
53 /*
54 * spin lock/unlock provide the needed smp_mb() before/after
55 */
56 atomic_ops_lock(flags);
57 prev = *p;
58 if (prev == expected)
59 *p = new;
60 atomic_ops_unlock(flags);
61 return prev;
62}
63
64#endif
65
66#define arch_cmpxchg(ptr, o, n) ({ \
67 (typeof(*(ptr)))__cmpxchg((ptr), \
68 (unsigned long)(o), \
69 (unsigned long)(n)); \
70})
71
72/*
73 * atomic_cmpxchg is same as cmpxchg
74 * LLSC: only different in data-type, semantics are exactly same
75 * !LLSC: cmpxchg() has to use an external lock atomic_ops_lock to guarantee
76 * semantics, and this lock also happens to be used by atomic_*()
77 */
78#define arch_atomic_cmpxchg(v, o, n) ((int)arch_cmpxchg(&((v)->counter), (o), (n)))
79
80
81/*
82 * xchg (reg with memory) based on "Native atomic" EX insn
83 */
84static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
85 int size)
86{
87 extern unsigned long __xchg_bad_pointer(void);
88
89 switch (size) {
90 case 4:
91 smp_mb();
92
93 __asm__ __volatile__(
94 " ex %0, [%1] \n"
95 : "+r"(val)
96 : "r"(ptr)
97 : "memory");
98
99 smp_mb();
100
101 return val;
102 }
103 return __xchg_bad_pointer();
104}
105
106#define _xchg(ptr, with) ((typeof(*(ptr)))__xchg((unsigned long)(with), (ptr), \
107 sizeof(*(ptr))))
108
109/*
110 * xchg() maps directly to ARC EX instruction which guarantees atomicity.
111 * However in !LLSC config, it also needs to be use @atomic_ops_lock spinlock
112 * due to a subtle reason:
113 * - For !LLSC, cmpxchg() needs to use that lock (see above) and there is lot
114 * of kernel code which calls xchg()/cmpxchg() on same data (see llist.h)
115 * Hence xchg() needs to follow same locking rules.
116 *
117 * Technically the lock is also needed for UP (boils down to irq save/restore)
118 * but we can cheat a bit since cmpxchg() atomic_ops_lock() would cause irqs to
119 * be disabled thus can't possibly be interrupted/preempted/clobbered by xchg()
120 * Other way around, xchg is one instruction anyways, so can't be interrupted
121 * as such
122 */
123
124#if !defined(CONFIG_ARC_HAS_LLSC) && defined(CONFIG_SMP)
125
126#define arch_xchg(ptr, with) \
127({ \
128 unsigned long flags; \
129 typeof(*(ptr)) old_val; \
130 \
131 atomic_ops_lock(flags); \
132 old_val = _xchg(ptr, with); \
133 atomic_ops_unlock(flags); \
134 old_val; \
135})
136
137#else
138
139#define arch_xchg(ptr, with) _xchg(ptr, with)
140
141#endif
142
143/*
144 * "atomic" variant of xchg()
145 * REQ: It needs to follow the same serialization rules as other atomic_xxx()
146 * Since xchg() doesn't always do that, it would seem that following definition
147 * is incorrect. But here's the rationale:
148 * SMP : Even xchg() takes the atomic_ops_lock, so OK.
149 * LLSC: atomic_ops_lock are not relevant at all (even if SMP, since LLSC
150 * is natively "SMP safe", no serialization required).
151 * UP : other atomics disable IRQ, so no way a difft ctxt atomic_xchg()
152 * could clobber them. atomic_xchg() itself would be 1 insn, so it
153 * can't be clobbered by others. Thus no serialization required when
154 * atomic_xchg is involved.
155 */
156#define arch_atomic_xchg(v, new) (arch_xchg(&((v)->counter), new))
157
158#endif