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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2001 by David Brownell
4 */
5
6/* this file is part of ehci-hcd.c */
7
8/*-------------------------------------------------------------------------*/
9
10/*
11 * There's basically three types of memory:
12 * - data used only by the HCD ... kmalloc is fine
13 * - async and periodic schedules, shared by HC and HCD ... these
14 * need to use dma_pool or dma_alloc_coherent
15 * - driver buffers, read/written by HC ... single shot DMA mapped
16 *
17 * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
18 * No memory seen by this driver is pageable.
19 */
20
21/*-------------------------------------------------------------------------*/
22
23/* Allocate the key transfer structures from the previously allocated pool */
24
25static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
26 dma_addr_t dma)
27{
28 memset (qtd, 0, sizeof *qtd);
29 qtd->qtd_dma = dma;
30 qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
31 qtd->hw_next = EHCI_LIST_END(ehci);
32 qtd->hw_alt_next = EHCI_LIST_END(ehci);
33 INIT_LIST_HEAD (&qtd->qtd_list);
34}
35
36static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
37{
38 struct ehci_qtd *qtd;
39 dma_addr_t dma;
40
41 qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
42 if (qtd != NULL) {
43 ehci_qtd_init(ehci, qtd, dma);
44 }
45 return qtd;
46}
47
48static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
49{
50 dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
51}
52
53
54static void qh_destroy(struct ehci_hcd *ehci, struct ehci_qh *qh)
55{
56 /* clean qtds first, and know this is not linked */
57 if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
58 ehci_dbg (ehci, "unused qh not empty!\n");
59 BUG ();
60 }
61 if (qh->dummy)
62 ehci_qtd_free (ehci, qh->dummy);
63 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
64 kfree(qh);
65}
66
67static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
68{
69 struct ehci_qh *qh;
70 dma_addr_t dma;
71
72 qh = kzalloc(sizeof *qh, GFP_ATOMIC);
73 if (!qh)
74 goto done;
75 qh->hw = (struct ehci_qh_hw *)
76 dma_pool_zalloc(ehci->qh_pool, flags, &dma);
77 if (!qh->hw)
78 goto fail;
79 qh->qh_dma = dma;
80 // INIT_LIST_HEAD (&qh->qh_list);
81 INIT_LIST_HEAD (&qh->qtd_list);
82 INIT_LIST_HEAD(&qh->unlink_node);
83
84 /* dummy td enables safe urb queuing */
85 qh->dummy = ehci_qtd_alloc (ehci, flags);
86 if (qh->dummy == NULL) {
87 ehci_dbg (ehci, "no dummy td\n");
88 goto fail1;
89 }
90done:
91 return qh;
92fail1:
93 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
94fail:
95 kfree(qh);
96 return NULL;
97}
98
99/*-------------------------------------------------------------------------*/
100
101/* The queue heads and transfer descriptors are managed from pools tied
102 * to each of the "per device" structures.
103 * This is the initialisation and cleanup code.
104 */
105
106static void ehci_mem_cleanup (struct ehci_hcd *ehci)
107{
108 if (ehci->async)
109 qh_destroy(ehci, ehci->async);
110 ehci->async = NULL;
111
112 if (ehci->dummy)
113 qh_destroy(ehci, ehci->dummy);
114 ehci->dummy = NULL;
115
116 /* DMA consistent memory and pools */
117 dma_pool_destroy(ehci->qtd_pool);
118 ehci->qtd_pool = NULL;
119 dma_pool_destroy(ehci->qh_pool);
120 ehci->qh_pool = NULL;
121 dma_pool_destroy(ehci->itd_pool);
122 ehci->itd_pool = NULL;
123 dma_pool_destroy(ehci->sitd_pool);
124 ehci->sitd_pool = NULL;
125
126 if (ehci->periodic)
127 dma_free_coherent(ehci_to_hcd(ehci)->self.sysdev,
128 ehci->periodic_size * sizeof (u32),
129 ehci->periodic, ehci->periodic_dma);
130 ehci->periodic = NULL;
131
132 /* shadow periodic table */
133 kfree(ehci->pshadow);
134 ehci->pshadow = NULL;
135}
136
137/* remember to add cleanup code (above) if you add anything here */
138static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
139{
140 int i;
141
142 /* QTDs for control/bulk/intr transfers */
143 ehci->qtd_pool = dma_pool_create ("ehci_qtd",
144 ehci_to_hcd(ehci)->self.sysdev,
145 sizeof (struct ehci_qtd),
146 32 /* byte alignment (for hw parts) */,
147 4096 /* can't cross 4K */);
148 if (!ehci->qtd_pool) {
149 goto fail;
150 }
151
152 /* QHs for control/bulk/intr transfers */
153 ehci->qh_pool = dma_pool_create ("ehci_qh",
154 ehci_to_hcd(ehci)->self.sysdev,
155 sizeof(struct ehci_qh_hw),
156 32 /* byte alignment (for hw parts) */,
157 4096 /* can't cross 4K */);
158 if (!ehci->qh_pool) {
159 goto fail;
160 }
161 ehci->async = ehci_qh_alloc (ehci, flags);
162 if (!ehci->async) {
163 goto fail;
164 }
165
166 /* ITD for high speed ISO transfers */
167 ehci->itd_pool = dma_pool_create ("ehci_itd",
168 ehci_to_hcd(ehci)->self.sysdev,
169 sizeof (struct ehci_itd),
170 32 /* byte alignment (for hw parts) */,
171 4096 /* can't cross 4K */);
172 if (!ehci->itd_pool) {
173 goto fail;
174 }
175
176 /* SITD for full/low speed split ISO transfers */
177 ehci->sitd_pool = dma_pool_create ("ehci_sitd",
178 ehci_to_hcd(ehci)->self.sysdev,
179 sizeof (struct ehci_sitd),
180 32 /* byte alignment (for hw parts) */,
181 4096 /* can't cross 4K */);
182 if (!ehci->sitd_pool) {
183 goto fail;
184 }
185
186 /* Hardware periodic table */
187 ehci->periodic = (__le32 *)
188 dma_alloc_coherent(ehci_to_hcd(ehci)->self.sysdev,
189 ehci->periodic_size * sizeof(__le32),
190 &ehci->periodic_dma, flags);
191 if (ehci->periodic == NULL) {
192 goto fail;
193 }
194
195 if (ehci->use_dummy_qh) {
196 struct ehci_qh_hw *hw;
197 ehci->dummy = ehci_qh_alloc(ehci, flags);
198 if (!ehci->dummy)
199 goto fail;
200
201 hw = ehci->dummy->hw;
202 hw->hw_next = EHCI_LIST_END(ehci);
203 hw->hw_qtd_next = EHCI_LIST_END(ehci);
204 hw->hw_alt_next = EHCI_LIST_END(ehci);
205 ehci->dummy->hw = hw;
206
207 for (i = 0; i < ehci->periodic_size; i++)
208 ehci->periodic[i] = cpu_to_hc32(ehci,
209 ehci->dummy->qh_dma);
210 } else {
211 for (i = 0; i < ehci->periodic_size; i++)
212 ehci->periodic[i] = EHCI_LIST_END(ehci);
213 }
214
215 /* software shadow of hardware table */
216 ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
217 if (ehci->pshadow != NULL)
218 return 0;
219
220fail:
221 ehci_dbg (ehci, "couldn't init memory\n");
222 ehci_mem_cleanup (ehci);
223 return -ENOMEM;
224}
1/*
2 * Copyright (c) 2001 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/* this file is part of ehci-hcd.c */
20
21/*-------------------------------------------------------------------------*/
22
23/*
24 * There's basically three types of memory:
25 * - data used only by the HCD ... kmalloc is fine
26 * - async and periodic schedules, shared by HC and HCD ... these
27 * need to use dma_pool or dma_alloc_coherent
28 * - driver buffers, read/written by HC ... single shot DMA mapped
29 *
30 * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
31 * No memory seen by this driver is pageable.
32 */
33
34/*-------------------------------------------------------------------------*/
35
36/* Allocate the key transfer structures from the previously allocated pool */
37
38static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
39 dma_addr_t dma)
40{
41 memset (qtd, 0, sizeof *qtd);
42 qtd->qtd_dma = dma;
43 qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
44 qtd->hw_next = EHCI_LIST_END(ehci);
45 qtd->hw_alt_next = EHCI_LIST_END(ehci);
46 INIT_LIST_HEAD (&qtd->qtd_list);
47}
48
49static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
50{
51 struct ehci_qtd *qtd;
52 dma_addr_t dma;
53
54 qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
55 if (qtd != NULL) {
56 ehci_qtd_init(ehci, qtd, dma);
57 }
58 return qtd;
59}
60
61static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
62{
63 dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
64}
65
66
67static void qh_destroy(struct ehci_hcd *ehci, struct ehci_qh *qh)
68{
69 /* clean qtds first, and know this is not linked */
70 if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
71 ehci_dbg (ehci, "unused qh not empty!\n");
72 BUG ();
73 }
74 if (qh->dummy)
75 ehci_qtd_free (ehci, qh->dummy);
76 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
77 kfree(qh);
78}
79
80static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
81{
82 struct ehci_qh *qh;
83 dma_addr_t dma;
84
85 qh = kzalloc(sizeof *qh, GFP_ATOMIC);
86 if (!qh)
87 goto done;
88 qh->hw = (struct ehci_qh_hw *)
89 dma_pool_alloc(ehci->qh_pool, flags, &dma);
90 if (!qh->hw)
91 goto fail;
92 memset(qh->hw, 0, sizeof *qh->hw);
93 qh->qh_dma = dma;
94 // INIT_LIST_HEAD (&qh->qh_list);
95 INIT_LIST_HEAD (&qh->qtd_list);
96 INIT_LIST_HEAD(&qh->unlink_node);
97
98 /* dummy td enables safe urb queuing */
99 qh->dummy = ehci_qtd_alloc (ehci, flags);
100 if (qh->dummy == NULL) {
101 ehci_dbg (ehci, "no dummy td\n");
102 goto fail1;
103 }
104done:
105 return qh;
106fail1:
107 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
108fail:
109 kfree(qh);
110 return NULL;
111}
112
113/*-------------------------------------------------------------------------*/
114
115/* The queue heads and transfer descriptors are managed from pools tied
116 * to each of the "per device" structures.
117 * This is the initialisation and cleanup code.
118 */
119
120static void ehci_mem_cleanup (struct ehci_hcd *ehci)
121{
122 if (ehci->async)
123 qh_destroy(ehci, ehci->async);
124 ehci->async = NULL;
125
126 if (ehci->dummy)
127 qh_destroy(ehci, ehci->dummy);
128 ehci->dummy = NULL;
129
130 /* DMA consistent memory and pools */
131 dma_pool_destroy(ehci->qtd_pool);
132 ehci->qtd_pool = NULL;
133 dma_pool_destroy(ehci->qh_pool);
134 ehci->qh_pool = NULL;
135 dma_pool_destroy(ehci->itd_pool);
136 ehci->itd_pool = NULL;
137 dma_pool_destroy(ehci->sitd_pool);
138 ehci->sitd_pool = NULL;
139
140 if (ehci->periodic)
141 dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
142 ehci->periodic_size * sizeof (u32),
143 ehci->periodic, ehci->periodic_dma);
144 ehci->periodic = NULL;
145
146 /* shadow periodic table */
147 kfree(ehci->pshadow);
148 ehci->pshadow = NULL;
149}
150
151/* remember to add cleanup code (above) if you add anything here */
152static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
153{
154 int i;
155
156 /* QTDs for control/bulk/intr transfers */
157 ehci->qtd_pool = dma_pool_create ("ehci_qtd",
158 ehci_to_hcd(ehci)->self.controller,
159 sizeof (struct ehci_qtd),
160 32 /* byte alignment (for hw parts) */,
161 4096 /* can't cross 4K */);
162 if (!ehci->qtd_pool) {
163 goto fail;
164 }
165
166 /* QHs for control/bulk/intr transfers */
167 ehci->qh_pool = dma_pool_create ("ehci_qh",
168 ehci_to_hcd(ehci)->self.controller,
169 sizeof(struct ehci_qh_hw),
170 32 /* byte alignment (for hw parts) */,
171 4096 /* can't cross 4K */);
172 if (!ehci->qh_pool) {
173 goto fail;
174 }
175 ehci->async = ehci_qh_alloc (ehci, flags);
176 if (!ehci->async) {
177 goto fail;
178 }
179
180 /* ITD for high speed ISO transfers */
181 ehci->itd_pool = dma_pool_create ("ehci_itd",
182 ehci_to_hcd(ehci)->self.controller,
183 sizeof (struct ehci_itd),
184 32 /* byte alignment (for hw parts) */,
185 4096 /* can't cross 4K */);
186 if (!ehci->itd_pool) {
187 goto fail;
188 }
189
190 /* SITD for full/low speed split ISO transfers */
191 ehci->sitd_pool = dma_pool_create ("ehci_sitd",
192 ehci_to_hcd(ehci)->self.controller,
193 sizeof (struct ehci_sitd),
194 32 /* byte alignment (for hw parts) */,
195 4096 /* can't cross 4K */);
196 if (!ehci->sitd_pool) {
197 goto fail;
198 }
199
200 /* Hardware periodic table */
201 ehci->periodic = (__le32 *)
202 dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
203 ehci->periodic_size * sizeof(__le32),
204 &ehci->periodic_dma, flags);
205 if (ehci->periodic == NULL) {
206 goto fail;
207 }
208
209 if (ehci->use_dummy_qh) {
210 struct ehci_qh_hw *hw;
211 ehci->dummy = ehci_qh_alloc(ehci, flags);
212 if (!ehci->dummy)
213 goto fail;
214
215 hw = ehci->dummy->hw;
216 hw->hw_next = EHCI_LIST_END(ehci);
217 hw->hw_qtd_next = EHCI_LIST_END(ehci);
218 hw->hw_alt_next = EHCI_LIST_END(ehci);
219 ehci->dummy->hw = hw;
220
221 for (i = 0; i < ehci->periodic_size; i++)
222 ehci->periodic[i] = cpu_to_hc32(ehci,
223 ehci->dummy->qh_dma);
224 } else {
225 for (i = 0; i < ehci->periodic_size; i++)
226 ehci->periodic[i] = EHCI_LIST_END(ehci);
227 }
228
229 /* software shadow of hardware table */
230 ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
231 if (ehci->pshadow != NULL)
232 return 0;
233
234fail:
235 ehci_dbg (ehci, "couldn't init memory\n");
236 ehci_mem_cleanup (ehci);
237 return -ENOMEM;
238}