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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (C) 2005-2014, 2018-2021, 2023 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
5 */
6#ifndef __iwl_fh_h__
7#define __iwl_fh_h__
8
9#include <linux/types.h>
10#include <linux/bitfield.h>
11
12#include "iwl-trans.h"
13
14/****************************/
15/* Flow Handler Definitions */
16/****************************/
17
18/**
19 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
20 * Addresses are offsets from device's PCI hardware base address.
21 */
22#define FH_MEM_LOWER_BOUND (0x1000)
23#define FH_MEM_UPPER_BOUND (0x2000)
24#define FH_MEM_LOWER_BOUND_GEN2 (0xa06000)
25#define FH_MEM_UPPER_BOUND_GEN2 (0xa08000)
26
27/**
28 * Keep-Warm (KW) buffer base address.
29 *
30 * Driver must allocate a 4KByte buffer that is for keeping the
31 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
32 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
33 * from going into a power-savings mode that would cause higher DRAM latency,
34 * and possible data over/under-runs, before all Tx/Rx is complete.
35 *
36 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
37 * of the buffer, which must be 4K aligned. Once this is set up, the device
38 * automatically invokes keep-warm accesses when normal accesses might not
39 * be sufficient to maintain fast DRAM response.
40 *
41 * Bit fields:
42 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
43 */
44#define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
45
46
47/**
48 * TFD Circular Buffers Base (CBBC) addresses
49 *
50 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
51 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
52 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
53 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
54 * aligned (address bits 0-7 must be 0).
55 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
56 * for them are in different places.
57 *
58 * Bit fields in each pointer register:
59 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
60 */
61#define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
62#define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
63#define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0)
64#define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
65#define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20)
66#define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80)
67/* 22000 TFD table address, 64 bit */
68#define TFH_TFDQ_CBB_TABLE (0x1C00)
69
70/* Find TFD CB base pointer for given queue */
71static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans,
72 unsigned int chnl)
73{
74 if (trans->trans_cfg->gen2) {
75 WARN_ON_ONCE(chnl >= 64);
76 return TFH_TFDQ_CBB_TABLE + 8 * chnl;
77 }
78 if (chnl < 16)
79 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
80 if (chnl < 20)
81 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
82 WARN_ON_ONCE(chnl >= 32);
83 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
84}
85
86/* 22000 configuration registers */
87
88/*
89 * TFH Configuration register.
90 *
91 * BIT fields:
92 *
93 * Bits 3:0:
94 * Define the maximum number of pending read requests.
95 * Maximum configuration value allowed is 0xC
96 * Bits 9:8:
97 * Define the maximum transfer size. (64 / 128 / 256)
98 * Bit 10:
99 * When bit is set and transfer size is set to 128B, the TFH will enable
100 * reading chunks of more than 64B only if the read address is aligned to 128B.
101 * In case of DRAM read address which is not aligned to 128B, the TFH will
102 * enable transfer size which doesn't cross 64B DRAM address boundary.
103*/
104#define TFH_TRANSFER_MODE (0x1F40)
105#define TFH_TRANSFER_MAX_PENDING_REQ 0xc
106#define TFH_CHUNK_SIZE_128 BIT(8)
107#define TFH_CHUNK_SPLIT_MODE BIT(10)
108/*
109 * Defines the offset address in dwords referring from the beginning of the
110 * Tx CMD which will be updated in DRAM.
111 * Note that the TFH offset address for Tx CMD update is always referring to
112 * the start of the TFD first TB.
113 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID
114 */
115#define TFH_TXCMD_UPDATE_CFG (0x1F48)
116/*
117 * Controls TX DMA operation
118 *
119 * BIT fields:
120 *
121 * Bits 31:30: Enable the SRAM DMA channel.
122 * Turning on bit 31 will kick the SRAM2DRAM DMA.
123 * Note that the sram2dram may be enabled only after configuring the DRAM and
124 * SRAM addresses registers and the byte count register.
125 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When
126 * set to 1 - interrupt is sent to the driver
127 * Bit 0: Indicates the snoop configuration
128*/
129#define TFH_SRV_DMA_CHNL0_CTRL (0x1F60)
130#define TFH_SRV_DMA_SNOOP BIT(0)
131#define TFH_SRV_DMA_TO_DRIVER BIT(24)
132#define TFH_SRV_DMA_START BIT(31)
133
134/* Defines the DMA SRAM write start address to transfer a data block */
135#define TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64)
136
137/* Defines the 64bits DRAM start address to read the DMA data block from */
138#define TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68)
139
140/*
141 * Defines the number of bytes to transfer from DRAM to SRAM.
142 * Note that this register may be configured with non-dword aligned size.
143 */
144#define TFH_SRV_DMA_CHNL0_BC (0x1F70)
145
146/**
147 * Rx SRAM Control and Status Registers (RSCSR)
148 *
149 * These registers provide handshake between driver and device for the Rx queue
150 * (this queue handles *all* command responses, notifications, Rx data, etc.
151 * sent from uCode to host driver). Unlike Tx, there is only one Rx
152 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
153 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
154 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
155 * mapping between RBDs and RBs.
156 *
157 * Driver must allocate host DRAM memory for the following, and set the
158 * physical address of each into device registers:
159 *
160 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
161 * entries (although any power of 2, up to 4096, is selectable by driver).
162 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
163 * (typically 4K, although 8K or 16K are also selectable by driver).
164 * Driver sets up RB size and number of RBDs in the CB via Rx config
165 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
166 *
167 * Bit fields within one RBD:
168 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
169 *
170 * Driver sets physical address [35:8] of base of RBD circular buffer
171 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
172 *
173 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
174 * (RBs) have been filled, via a "write pointer", actually the index of
175 * the RB's corresponding RBD within the circular buffer. Driver sets
176 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
177 *
178 * Bit fields in lower dword of Rx status buffer (upper dword not used
179 * by driver:
180 * 31-12: Not used by driver
181 * 11- 0: Index of last filled Rx buffer descriptor
182 * (device writes, driver reads this value)
183 *
184 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
185 * enter pointers to these RBs into contiguous RBD circular buffer entries,
186 * and update the device's "write" index register,
187 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
188 *
189 * This "write" index corresponds to the *next* RBD that the driver will make
190 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
191 * the circular buffer. This value should initially be 0 (before preparing any
192 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
193 * wrap back to 0 at the end of the circular buffer (but don't wrap before
194 * "read" index has advanced past 1! See below).
195 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
196 *
197 * As the device fills RBs (referenced from contiguous RBDs within the circular
198 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
199 * to tell the driver the index of the latest filled RBD. The driver must
200 * read this "read" index from DRAM after receiving an Rx interrupt from device
201 *
202 * The driver must also internally keep track of a third index, which is the
203 * next RBD to process. When receiving an Rx interrupt, driver should process
204 * all filled but unprocessed RBs up to, but not including, the RB
205 * corresponding to the "read" index. For example, if "read" index becomes "1",
206 * driver may process the RB pointed to by RBD 0. Depending on volume of
207 * traffic, there may be many RBs to process.
208 *
209 * If read index == write index, device thinks there is no room to put new data.
210 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
211 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
212 * and "read" indexes; that is, make sure that there are no more than 254
213 * buffers waiting to be filled.
214 */
215#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
216#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
217#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
218
219/**
220 * Physical base address of 8-byte Rx Status buffer.
221 * Bit fields:
222 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
223 */
224#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
225
226/**
227 * Physical base address of Rx Buffer Descriptor Circular Buffer.
228 * Bit fields:
229 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
230 */
231#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
232
233/**
234 * Rx write pointer (index, really!).
235 * Bit fields:
236 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
237 * NOTE: For 256-entry circular buffer, use only bits [7:0].
238 */
239#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
240#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
241
242#define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c)
243#define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
244
245/**
246 * Rx Config/Status Registers (RCSR)
247 * Rx Config Reg for channel 0 (only channel used)
248 *
249 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
250 * normal operation (see bit fields).
251 *
252 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
253 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
254 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
255 *
256 * Bit fields:
257 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
258 * '10' operate normally
259 * 29-24: reserved
260 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
261 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
262 * 19-18: reserved
263 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
264 * '10' 12K, '11' 16K.
265 * 15-14: reserved
266 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
267 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
268 * typical value 0x10 (about 1/2 msec)
269 * 3- 0: reserved
270 */
271#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
272#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
273#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
274
275#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
276#define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8)
277#define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10)
278
279#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
280#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
281#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
282#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
283#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
284#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
285
286#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
287#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
288#define RX_RB_TIMEOUT (0x11)
289
290#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
291#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
292#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
293
294#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
295#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
296#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
297#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
298
299#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
300#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
301#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
302
303/**
304 * Rx Shared Status Registers (RSSR)
305 *
306 * After stopping Rx DMA channel (writing 0 to
307 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
308 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
309 *
310 * Bit fields:
311 * 24: 1 = Channel 0 is idle
312 *
313 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
314 * contain default values that should not be altered by the driver.
315 */
316#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
317#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
318
319#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
320#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
321#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
322 (FH_MEM_RSSR_LOWER_BOUND + 0x008)
323
324#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
325
326#define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
327#define FH_MEM_TB_MAX_LENGTH (0x00020000)
328
329/* 9000 rx series registers */
330
331#define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
332#define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
333/* Write index table */
334#define RFH_Q0_FRBDCB_WIDX 0xA08080
335#define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4)
336/* Write index table - shadow registers */
337#define RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
338#define RFH_Q_FRBDCB_WIDX_TRG(q) (RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
339/* Read index table */
340#define RFH_Q0_FRBDCB_RIDX 0xA080C0
341#define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4)
342/* Used list table */
343#define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
344#define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8)
345/* Write index table */
346#define RFH_Q0_URBDCB_WIDX 0xA08180
347#define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4)
348#define RFH_Q0_URBDCB_VAID 0xA081C0
349#define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4)
350/* stts */
351#define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
352#define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
353
354#define RFH_Q0_ORB_WPTR_LSB 0xA08280
355#define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8)
356#define RFH_RBDBUF_RBD0_LSB 0xA08300
357#define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8)
358
359/**
360 * RFH Status Register
361 *
362 * Bit fields:
363 *
364 * Bit 29: RBD_FETCH_IDLE
365 * This status flag is set by the RFH when there is no active RBD fetch from
366 * DRAM.
367 * Once the RFH RBD controller starts fetching (or when there is a pending
368 * RBD read response from DRAM), this flag is immediately turned off.
369 *
370 * Bit 30: SRAM_DMA_IDLE
371 * This status flag is set by the RFH when there is no active transaction from
372 * SRAM to DRAM.
373 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off.
374 *
375 * Bit 31: RXF_DMA_IDLE
376 * This status flag is set by the RFH when there is no active transaction from
377 * RXF to DRAM.
378 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
379 */
380#define RFH_GEN_STATUS 0xA09808
381#define RFH_GEN_STATUS_GEN3 0xA07824
382#define RBD_FETCH_IDLE BIT(29)
383#define SRAM_DMA_IDLE BIT(30)
384#define RXF_DMA_IDLE BIT(31)
385
386/* DMA configuration */
387#define RFH_RXF_DMA_CFG 0xA09820
388#define RFH_RXF_DMA_CFG_GEN3 0xA07880
389/* RB size */
390#define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
391#define RFH_RXF_DMA_RB_SIZE_POS 16
392#define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS)
393#define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS)
394#define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS)
395#define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS)
396#define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS)
397#define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS)
398#define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS)
399#define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS)
400#define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS)
401#define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS)
402/* RB Circular Buffer size:defines the table sizes in RBD units */
403#define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
404#define RFH_RXF_DMA_RBDCB_SIZE_POS 20
405#define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS)
406#define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS)
407#define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS)
408#define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS)
409#define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS)
410#define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS)
411#define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS)
412#define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS)
413#define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS)
414#define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
415#define RFH_RXF_DMA_MIN_RB_SIZE_POS 24
416#define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS)
417#define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
418#define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
419#define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
420#define RFH_DMA_EN_ENABLE_VAL BIT(31)
421
422#define RFH_RXF_RXQ_ACTIVE 0xA0980C
423
424#define RFH_GEN_CFG 0xA09800
425#define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0)
426#define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1)
427#define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4)
428#define RFH_GEN_CFG_RB_CHUNK_SIZE_128 1
429#define RFH_GEN_CFG_RB_CHUNK_SIZE_64 0
430/* the driver assumes everywhere that the default RXQ is 0 */
431#define RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00
432#define RFH_GEN_CFG_VAL(_n, _v) FIELD_PREP(RFH_GEN_CFG_ ## _n, _v)
433
434/* end of 9000 rx series registers */
435
436/* TFDB Area - TFDs buffer table */
437#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
438#define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900)
439#define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958)
440#define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
441#define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
442
443/**
444 * Transmit DMA Channel Control/Status Registers (TCSR)
445 *
446 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
447 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
448 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
449 *
450 * To use a Tx DMA channel, driver must initialize its
451 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
452 *
453 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
454 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
455 *
456 * All other bits should be 0.
457 *
458 * Bit fields:
459 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
460 * '10' operate normally
461 * 29- 4: Reserved, set to "0"
462 * 3: Enable internal DMA requests (1, normal operation), disable (0)
463 * 2- 0: Reserved, set to "0"
464 */
465#define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
466#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
467
468/* Find Control/Status reg for given Tx DMA/FIFO channel */
469#define FH_TCSR_CHNL_NUM (8)
470
471/* TCSR: tx_config register values */
472#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
473 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
474#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
475 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
476#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
477 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
478
479#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
480#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
481
482#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
483#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
484
485#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
486#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
487#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
488
489#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
490#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
491#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
492
493#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
494#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
495#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
496
497#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
498#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
499#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
500
501#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
502#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
503
504/**
505 * Tx Shared Status Registers (TSSR)
506 *
507 * After stopping Tx DMA channel (writing 0 to
508 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
509 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
510 * (channel's buffers empty | no pending requests).
511 *
512 * Bit fields:
513 * 31-24: 1 = Channel buffers empty (channel 7:0)
514 * 23-16: 1 = No pending requests (channel 7:0)
515 */
516#define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
517#define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
518
519#define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010)
520
521/**
522 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
523 * 31: Indicates an address error when accessed to internal memory
524 * uCode/driver must write "1" in order to clear this flag
525 * 30: Indicates that Host did not send the expected number of dwords to FH
526 * uCode/driver must write "1" in order to clear this flag
527 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
528 * command was received from the scheduler while the TRB was already full
529 * with previous command
530 * uCode/driver must write "1" in order to clear this flag
531 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
532 * bit is set, it indicates that the FH has received a full indication
533 * from the RTC TxFIFO and the current value of the TxCredit counter was
534 * not equal to zero. This mean that the credit mechanism was not
535 * synchronized to the TxFIFO status
536 * uCode/driver must write "1" in order to clear this flag
537 */
538#define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018)
539#define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008)
540
541#define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
542
543/* Tx service channels */
544#define FH_SRVC_CHNL (9)
545#define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8)
546#define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
547#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
548 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
549
550#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
551#define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4)
552
553/* Instruct FH to increment the retry count of a packet when
554 * it is brought from the memory to TX-FIFO
555 */
556#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
557
558#define RX_POOL_SIZE(rbds) ((rbds) - 1 + \
559 IWL_MAX_RX_HW_QUEUES * \
560 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC))
561/* cb size is the exponent */
562#define RX_QUEUE_CB_SIZE(x) ilog2(x)
563
564#define RX_QUEUE_SIZE 256
565#define RX_QUEUE_MASK 255
566#define RX_QUEUE_SIZE_LOG 8
567
568#define IWL_DEFAULT_RX_QUEUE 0
569
570/**
571 * struct iwl_rb_status - reserve buffer status
572 * host memory mapped FH registers
573 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
574 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
575 * @finished_rb_num [0:11] - Indicates the index of the current RB
576 * in which the last frame was written to
577 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
578 * which was transferred
579 */
580struct iwl_rb_status {
581 __le16 closed_rb_num;
582 __le16 closed_fr_num;
583 __le16 finished_rb_num;
584 __le16 finished_fr_nam;
585 __le32 __spare;
586} __packed;
587
588
589#define TFD_QUEUE_SIZE_MAX (256)
590#define TFD_QUEUE_SIZE_MAX_GEN3 (65536)
591/* cb size is the exponent - 3 */
592#define TFD_QUEUE_CB_SIZE(x) (ilog2(x) - 3)
593#define TFD_QUEUE_SIZE_BC_DUP (64)
594#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
595#define TFD_QUEUE_BC_SIZE_GEN3_AX210 1024
596#define TFD_QUEUE_BC_SIZE_GEN3_BZ (1024 * 4)
597#define IWL_TX_DMA_MASK DMA_BIT_MASK(36)
598#define IWL_NUM_OF_TBS 20
599#define IWL_TFH_NUM_TBS 25
600
601/* IMR DMA registers */
602#define IMR_TFH_SRV_DMA_CHNL0_CTRL 0x00a0a51c
603#define IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR 0x00a0a520
604#define IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB 0x00a0a524
605#define IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB 0x00a0a528
606#define IMR_TFH_SRV_DMA_CHNL0_BC 0x00a0a52c
607#define TFH_SRV_DMA_CHNL0_LEFT_BC 0x00a0a530
608
609/* RFH S2D DMA registers */
610#define IMR_RFH_GEN_CFG_SERVICE_DMA_RS_MSK 0x0000000c
611#define IMR_RFH_GEN_CFG_SERVICE_DMA_SNOOP_MSK 0x00000002
612
613/* TFH D2S DMA registers */
614#define IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK 0x80000000
615#define IMR_UREG_CHICK 0x00d05c00
616#define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS 0x00800000
617#define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK 0x00000030
618#define IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS 0x80000000
619
620static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr)
621{
622 return (sizeof(addr) > sizeof(u32) ? upper_32_bits(addr) : 0) & 0xF;
623}
624
625/**
626 * enum iwl_tfd_tb_hi_n_len - TB hi_n_len bits
627 * @TB_HI_N_LEN_ADDR_HI_MSK: high 4 bits (to make it 36) of DMA address
628 * @TB_HI_N_LEN_LEN_MSK: length of the TB
629 */
630enum iwl_tfd_tb_hi_n_len {
631 TB_HI_N_LEN_ADDR_HI_MSK = 0xf,
632 TB_HI_N_LEN_LEN_MSK = 0xfff0,
633};
634
635/**
636 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor
637 *
638 * This structure contains dma address and length of transmission address
639 *
640 * @lo: low [31:0] portion of the dma address of TX buffer
641 * every even is unaligned on 16 bit boundary
642 * @hi_n_len: &enum iwl_tfd_tb_hi_n_len
643 */
644struct iwl_tfd_tb {
645 __le32 lo;
646 __le16 hi_n_len;
647} __packed;
648
649/**
650 * struct iwl_tfh_tb transmit buffer descriptor within transmit frame descriptor
651 *
652 * This structure contains dma address and length of transmission address
653 *
654 * @tb_len length of the tx buffer
655 * @addr 64 bits dma address
656 */
657struct iwl_tfh_tb {
658 __le16 tb_len;
659 __le64 addr;
660} __packed;
661
662/**
663 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
664 * Both driver and device share these circular buffers, each of which must be
665 * contiguous 256 TFDs.
666 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes
667 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes
668 *
669 * Driver must indicate the physical address of the base of each
670 * circular buffer via the FH_MEM_CBBC_QUEUE registers.
671 *
672 * Each TFD contains pointer/size information for up to 20 / 25 data buffers
673 * in host DRAM. These buffers collectively contain the (one) frame described
674 * by the TFD. Each buffer must be a single contiguous block of memory within
675 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
676 * of (4K - 4). The concatenates all of a TFD's buffers into a single
677 * Tx frame, up to 8 KBytes in size.
678 *
679 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
680 */
681
682/**
683 * struct iwl_tfd - Transmit Frame Descriptor (TFD)
684 * @__reserved1: reserved
685 * @num_tbs:
686 * 0-4 number of active tbs
687 * 5 reserved
688 * 6-7 padding (not used)
689 * @tbs: transmit frame buffer descriptors
690 * @__pad: padding
691 */
692struct iwl_tfd {
693 u8 __reserved1[3];
694 u8 num_tbs;
695 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS];
696 __le32 __pad;
697} __packed;
698
699/**
700 * struct iwl_tfh_tfd - Transmit Frame Descriptor (TFD)
701 * @ num_tbs 0-4 number of active tbs
702 * 5 -15 reserved
703 * @ tbs[25] transmit frame buffer descriptors
704 * @ __pad padding
705 */
706struct iwl_tfh_tfd {
707 __le16 num_tbs;
708 struct iwl_tfh_tb tbs[IWL_TFH_NUM_TBS];
709 __le32 __pad;
710} __packed;
711
712/* Keep Warm Size */
713#define IWL_KW_SIZE 0x1000 /* 4k */
714
715/* Fixed (non-configurable) rx data from phy */
716
717/**
718 * struct iwlagn_schedq_bc_tbl scheduler byte count table
719 * base physical address provided by SCD_DRAM_BASE_ADDR
720 * For devices up to 22000:
721 * @tfd_offset 0-12 - tx command byte count
722 * 12-16 - station index
723 * For 22000:
724 * @tfd_offset 0-12 - tx command byte count
725 * 12-13 - number of 64 byte chunks
726 * 14-16 - reserved
727 */
728struct iwlagn_scd_bc_tbl {
729 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
730} __packed;
731
732/**
733 * struct iwl_gen3_bc_tbl_entry scheduler byte count table entry gen3
734 * For AX210 and on:
735 * @tfd_offset: 0-12 - tx command byte count
736 * 12-13 - number of 64 byte chunks
737 * 14-16 - reserved
738 */
739struct iwl_gen3_bc_tbl_entry {
740 __le16 tfd_offset;
741} __packed;
742
743#endif /* !__iwl_fh_h__ */
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
23 * USA
24 *
25 * The full GNU General Public License is included in this distribution
26 * in the file called COPYING.
27 *
28 * Contact Information:
29 * Intel Linux Wireless <linuxwifi@intel.com>
30 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 *
32 * BSD LICENSE
33 *
34 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
35 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 *
42 * * Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * * Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in
46 * the documentation and/or other materials provided with the
47 * distribution.
48 * * Neither the name Intel Corporation nor the names of its
49 * contributors may be used to endorse or promote products derived
50 * from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
53 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
54 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
55 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
56 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
57 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
58 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 *****************************************************************************/
65#ifndef __iwl_fh_h__
66#define __iwl_fh_h__
67
68#include <linux/types.h>
69
70/****************************/
71/* Flow Handler Definitions */
72/****************************/
73
74/**
75 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
76 * Addresses are offsets from device's PCI hardware base address.
77 */
78#define FH_MEM_LOWER_BOUND (0x1000)
79#define FH_MEM_UPPER_BOUND (0x2000)
80
81/**
82 * Keep-Warm (KW) buffer base address.
83 *
84 * Driver must allocate a 4KByte buffer that is for keeping the
85 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
86 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
87 * from going into a power-savings mode that would cause higher DRAM latency,
88 * and possible data over/under-runs, before all Tx/Rx is complete.
89 *
90 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
91 * of the buffer, which must be 4K aligned. Once this is set up, the device
92 * automatically invokes keep-warm accesses when normal accesses might not
93 * be sufficient to maintain fast DRAM response.
94 *
95 * Bit fields:
96 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
97 */
98#define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
99
100
101/**
102 * TFD Circular Buffers Base (CBBC) addresses
103 *
104 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
105 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
106 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
107 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
108 * aligned (address bits 0-7 must be 0).
109 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
110 * for them are in different places.
111 *
112 * Bit fields in each pointer register:
113 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
114 */
115#define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
116#define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
117#define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0)
118#define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
119#define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20)
120#define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80)
121
122/* Find TFD CB base pointer for given queue */
123static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl)
124{
125 if (chnl < 16)
126 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
127 if (chnl < 20)
128 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
129 WARN_ON_ONCE(chnl >= 32);
130 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
131}
132
133
134/**
135 * Rx SRAM Control and Status Registers (RSCSR)
136 *
137 * These registers provide handshake between driver and device for the Rx queue
138 * (this queue handles *all* command responses, notifications, Rx data, etc.
139 * sent from uCode to host driver). Unlike Tx, there is only one Rx
140 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
141 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
142 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
143 * mapping between RBDs and RBs.
144 *
145 * Driver must allocate host DRAM memory for the following, and set the
146 * physical address of each into device registers:
147 *
148 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
149 * entries (although any power of 2, up to 4096, is selectable by driver).
150 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
151 * (typically 4K, although 8K or 16K are also selectable by driver).
152 * Driver sets up RB size and number of RBDs in the CB via Rx config
153 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
154 *
155 * Bit fields within one RBD:
156 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
157 *
158 * Driver sets physical address [35:8] of base of RBD circular buffer
159 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
160 *
161 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
162 * (RBs) have been filled, via a "write pointer", actually the index of
163 * the RB's corresponding RBD within the circular buffer. Driver sets
164 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
165 *
166 * Bit fields in lower dword of Rx status buffer (upper dword not used
167 * by driver:
168 * 31-12: Not used by driver
169 * 11- 0: Index of last filled Rx buffer descriptor
170 * (device writes, driver reads this value)
171 *
172 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
173 * enter pointers to these RBs into contiguous RBD circular buffer entries,
174 * and update the device's "write" index register,
175 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
176 *
177 * This "write" index corresponds to the *next* RBD that the driver will make
178 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
179 * the circular buffer. This value should initially be 0 (before preparing any
180 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
181 * wrap back to 0 at the end of the circular buffer (but don't wrap before
182 * "read" index has advanced past 1! See below).
183 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
184 *
185 * As the device fills RBs (referenced from contiguous RBDs within the circular
186 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
187 * to tell the driver the index of the latest filled RBD. The driver must
188 * read this "read" index from DRAM after receiving an Rx interrupt from device
189 *
190 * The driver must also internally keep track of a third index, which is the
191 * next RBD to process. When receiving an Rx interrupt, driver should process
192 * all filled but unprocessed RBs up to, but not including, the RB
193 * corresponding to the "read" index. For example, if "read" index becomes "1",
194 * driver may process the RB pointed to by RBD 0. Depending on volume of
195 * traffic, there may be many RBs to process.
196 *
197 * If read index == write index, device thinks there is no room to put new data.
198 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
199 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
200 * and "read" indexes; that is, make sure that there are no more than 254
201 * buffers waiting to be filled.
202 */
203#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
204#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
205#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
206
207/**
208 * Physical base address of 8-byte Rx Status buffer.
209 * Bit fields:
210 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
211 */
212#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
213
214/**
215 * Physical base address of Rx Buffer Descriptor Circular Buffer.
216 * Bit fields:
217 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
218 */
219#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
220
221/**
222 * Rx write pointer (index, really!).
223 * Bit fields:
224 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
225 * NOTE: For 256-entry circular buffer, use only bits [7:0].
226 */
227#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
228#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
229
230#define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c)
231#define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
232
233/**
234 * Rx Config/Status Registers (RCSR)
235 * Rx Config Reg for channel 0 (only channel used)
236 *
237 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
238 * normal operation (see bit fields).
239 *
240 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
241 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
242 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
243 *
244 * Bit fields:
245 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
246 * '10' operate normally
247 * 29-24: reserved
248 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
249 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
250 * 19-18: reserved
251 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
252 * '10' 12K, '11' 16K.
253 * 15-14: reserved
254 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
255 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
256 * typical value 0x10 (about 1/2 msec)
257 * 3- 0: reserved
258 */
259#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
260#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
261#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
262
263#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
264#define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8)
265#define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10)
266
267#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
268#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
269#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
270#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
271#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
272#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
273
274#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
275#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
276#define RX_RB_TIMEOUT (0x11)
277
278#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
279#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
280#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
281
282#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
283#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
284#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
285#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
286
287#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
288#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
289#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
290
291/**
292 * Rx Shared Status Registers (RSSR)
293 *
294 * After stopping Rx DMA channel (writing 0 to
295 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
296 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
297 *
298 * Bit fields:
299 * 24: 1 = Channel 0 is idle
300 *
301 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
302 * contain default values that should not be altered by the driver.
303 */
304#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
305#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
306
307#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
308#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
309#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
310 (FH_MEM_RSSR_LOWER_BOUND + 0x008)
311
312#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
313
314#define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
315#define FH_MEM_TB_MAX_LENGTH (0x00020000)
316
317/* 9000 rx series registers */
318
319#define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
320#define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
321/* Write index table */
322#define RFH_Q0_FRBDCB_WIDX 0xA08080
323#define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4)
324/* Read index table */
325#define RFH_Q0_FRBDCB_RIDX 0xA080C0
326#define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4)
327/* Used list table */
328#define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
329#define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8)
330/* Write index table */
331#define RFH_Q0_URBDCB_WIDX 0xA08180
332#define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4)
333#define RFH_Q0_URBDCB_VAID 0xA081C0
334#define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4)
335/* stts */
336#define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
337#define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
338
339#define RFH_Q0_ORB_WPTR_LSB 0xA08280
340#define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8)
341#define RFH_RBDBUF_RBD0_LSB 0xA08300
342#define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8)
343
344/* DMA configuration */
345#define RFH_RXF_DMA_CFG 0xA09820
346/* RB size */
347#define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
348#define RFH_RXF_DMA_RB_SIZE_POS 16
349#define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS)
350#define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS)
351#define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS)
352#define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS)
353#define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS)
354#define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS)
355#define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS)
356#define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS)
357#define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS)
358#define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS)
359/* RB Circular Buffer size:defines the table sizes in RBD units */
360#define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
361#define RFH_RXF_DMA_RBDCB_SIZE_POS 20
362#define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS)
363#define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS)
364#define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS)
365#define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS)
366#define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS)
367#define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS)
368#define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS)
369#define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS)
370#define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS)
371#define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
372#define RFH_RXF_DMA_MIN_RB_SIZE_POS 24
373#define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS)
374#define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
375#define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
376#define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
377#define RFH_DMA_EN_ENABLE_VAL BIT(31)
378
379#define RFH_RXF_RXQ_ACTIVE 0xA0980C
380
381#define RFH_GEN_CFG 0xA09800
382#define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0)
383#define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1)
384#define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4) /* 0 - 64B, 1- 128B */
385#define RFH_GEN_CFG_DEFAULT_RXQ_NUM_MASK 0xF00
386#define RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS 8
387
388#define DEFAULT_RXQ_NUM 0
389
390/* end of 9000 rx series registers */
391
392/* TFDB Area - TFDs buffer table */
393#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
394#define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900)
395#define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958)
396#define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
397#define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
398
399/**
400 * Transmit DMA Channel Control/Status Registers (TCSR)
401 *
402 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
403 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
404 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
405 *
406 * To use a Tx DMA channel, driver must initialize its
407 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
408 *
409 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
410 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
411 *
412 * All other bits should be 0.
413 *
414 * Bit fields:
415 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
416 * '10' operate normally
417 * 29- 4: Reserved, set to "0"
418 * 3: Enable internal DMA requests (1, normal operation), disable (0)
419 * 2- 0: Reserved, set to "0"
420 */
421#define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
422#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
423
424/* Find Control/Status reg for given Tx DMA/FIFO channel */
425#define FH_TCSR_CHNL_NUM (8)
426
427/* TCSR: tx_config register values */
428#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
429 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
430#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
431 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
432#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
433 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
434
435#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
436#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
437
438#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
439#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
440
441#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
442#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
443#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
444
445#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
446#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
447#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
448
449#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
450#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
451#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
452
453#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
454#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
455#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
456
457#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
458#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
459
460/**
461 * Tx Shared Status Registers (TSSR)
462 *
463 * After stopping Tx DMA channel (writing 0 to
464 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
465 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
466 * (channel's buffers empty | no pending requests).
467 *
468 * Bit fields:
469 * 31-24: 1 = Channel buffers empty (channel 7:0)
470 * 23-16: 1 = No pending requests (channel 7:0)
471 */
472#define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
473#define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
474
475#define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010)
476
477/**
478 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
479 * 31: Indicates an address error when accessed to internal memory
480 * uCode/driver must write "1" in order to clear this flag
481 * 30: Indicates that Host did not send the expected number of dwords to FH
482 * uCode/driver must write "1" in order to clear this flag
483 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
484 * command was received from the scheduler while the TRB was already full
485 * with previous command
486 * uCode/driver must write "1" in order to clear this flag
487 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
488 * bit is set, it indicates that the FH has received a full indication
489 * from the RTC TxFIFO and the current value of the TxCredit counter was
490 * not equal to zero. This mean that the credit mechanism was not
491 * synchronized to the TxFIFO status
492 * uCode/driver must write "1" in order to clear this flag
493 */
494#define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018)
495#define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008)
496
497#define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
498
499/* Tx service channels */
500#define FH_SRVC_CHNL (9)
501#define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8)
502#define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
503#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
504 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
505
506#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
507#define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4)
508
509/* Instruct FH to increment the retry count of a packet when
510 * it is brought from the memory to TX-FIFO
511 */
512#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
513
514#define MQ_RX_TABLE_SIZE 512
515#define MQ_RX_TABLE_MASK (MQ_RX_TABLE_SIZE - 1)
516#define MQ_RX_NUM_RBDS (MQ_RX_TABLE_SIZE - 1)
517#define RX_POOL_SIZE (MQ_RX_NUM_RBDS + \
518 IWL_MAX_RX_HW_QUEUES * \
519 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC))
520
521#define RX_QUEUE_SIZE 256
522#define RX_QUEUE_MASK 255
523#define RX_QUEUE_SIZE_LOG 8
524
525/**
526 * struct iwl_rb_status - reserve buffer status
527 * host memory mapped FH registers
528 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
529 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
530 * @finished_rb_num [0:11] - Indicates the index of the current RB
531 * in which the last frame was written to
532 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
533 * which was transferred
534 */
535struct iwl_rb_status {
536 __le16 closed_rb_num;
537 __le16 closed_fr_num;
538 __le16 finished_rb_num;
539 __le16 finished_fr_nam;
540 __le32 __unused;
541} __packed;
542
543
544#define TFD_QUEUE_SIZE_MAX (256)
545#define TFD_QUEUE_SIZE_BC_DUP (64)
546#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
547#define IWL_TX_DMA_MASK DMA_BIT_MASK(36)
548#define IWL_NUM_OF_TBS 20
549
550static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr)
551{
552 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
553}
554/**
555 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor
556 *
557 * This structure contains dma address and length of transmission address
558 *
559 * @lo: low [31:0] portion of the dma address of TX buffer
560 * every even is unaligned on 16 bit boundary
561 * @hi_n_len 0-3 [35:32] portion of dma
562 * 4-15 length of the tx buffer
563 */
564struct iwl_tfd_tb {
565 __le32 lo;
566 __le16 hi_n_len;
567} __packed;
568
569/**
570 * struct iwl_tfd
571 *
572 * Transmit Frame Descriptor (TFD)
573 *
574 * @ __reserved1[3] reserved
575 * @ num_tbs 0-4 number of active tbs
576 * 5 reserved
577 * 6-7 padding (not used)
578 * @ tbs[20] transmit frame buffer descriptors
579 * @ __pad padding
580 *
581 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
582 * Both driver and device share these circular buffers, each of which must be
583 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
584 *
585 * Driver must indicate the physical address of the base of each
586 * circular buffer via the FH_MEM_CBBC_QUEUE registers.
587 *
588 * Each TFD contains pointer/size information for up to 20 data buffers
589 * in host DRAM. These buffers collectively contain the (one) frame described
590 * by the TFD. Each buffer must be a single contiguous block of memory within
591 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
592 * of (4K - 4). The concatenates all of a TFD's buffers into a single
593 * Tx frame, up to 8 KBytes in size.
594 *
595 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
596 */
597struct iwl_tfd {
598 u8 __reserved1[3];
599 u8 num_tbs;
600 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS];
601 __le32 __pad;
602} __packed;
603
604/* Keep Warm Size */
605#define IWL_KW_SIZE 0x1000 /* 4k */
606
607/* Fixed (non-configurable) rx data from phy */
608
609/**
610 * struct iwlagn_schedq_bc_tbl scheduler byte count table
611 * base physical address provided by SCD_DRAM_BASE_ADDR
612 * @tfd_offset 0-12 - tx command byte count
613 * 12-16 - station index
614 */
615struct iwlagn_scd_bc_tbl {
616 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
617} __packed;
618
619#endif /* !__iwl_fh_h__ */