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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3
4 Broadcom B43 wireless driver
5 Common PHY routines
6
7 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
8 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
9 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
10 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
11 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12
13
14*/
15
16#include "phy_common.h"
17#include "phy_g.h"
18#include "phy_a.h"
19#include "phy_n.h"
20#include "phy_lp.h"
21#include "phy_ht.h"
22#include "phy_lcn.h"
23#include "phy_ac.h"
24#include "b43.h"
25#include "main.h"
26
27
28int b43_phy_allocate(struct b43_wldev *dev)
29{
30 struct b43_phy *phy = &(dev->phy);
31 int err;
32
33 phy->ops = NULL;
34
35 switch (phy->type) {
36 case B43_PHYTYPE_G:
37#ifdef CONFIG_B43_PHY_G
38 phy->ops = &b43_phyops_g;
39#endif
40 break;
41 case B43_PHYTYPE_N:
42#ifdef CONFIG_B43_PHY_N
43 phy->ops = &b43_phyops_n;
44#endif
45 break;
46 case B43_PHYTYPE_LP:
47#ifdef CONFIG_B43_PHY_LP
48 phy->ops = &b43_phyops_lp;
49#endif
50 break;
51 case B43_PHYTYPE_HT:
52#ifdef CONFIG_B43_PHY_HT
53 phy->ops = &b43_phyops_ht;
54#endif
55 break;
56 case B43_PHYTYPE_LCN:
57#ifdef CONFIG_B43_PHY_LCN
58 phy->ops = &b43_phyops_lcn;
59#endif
60 break;
61 case B43_PHYTYPE_AC:
62#ifdef CONFIG_B43_PHY_AC
63 phy->ops = &b43_phyops_ac;
64#endif
65 break;
66 }
67 if (B43_WARN_ON(!phy->ops))
68 return -ENODEV;
69
70 err = phy->ops->allocate(dev);
71 if (err)
72 phy->ops = NULL;
73
74 return err;
75}
76
77void b43_phy_free(struct b43_wldev *dev)
78{
79 dev->phy.ops->free(dev);
80 dev->phy.ops = NULL;
81}
82
83int b43_phy_init(struct b43_wldev *dev)
84{
85 struct b43_phy *phy = &dev->phy;
86 const struct b43_phy_operations *ops = phy->ops;
87 int err;
88
89 /* During PHY init we need to use some channel. On the first init this
90 * function is called *before* b43_op_config, so our pointer is NULL.
91 */
92 if (!phy->chandef) {
93 phy->chandef = &dev->wl->hw->conf.chandef;
94 phy->channel = phy->chandef->chan->hw_value;
95 }
96
97 phy->ops->switch_analog(dev, true);
98 b43_software_rfkill(dev, false);
99
100 err = ops->init(dev);
101 if (err) {
102 b43err(dev->wl, "PHY init failed\n");
103 goto err_block_rf;
104 }
105 phy->do_full_init = false;
106
107 err = b43_switch_channel(dev, phy->channel);
108 if (err) {
109 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
110 goto err_phy_exit;
111 }
112
113 return 0;
114
115err_phy_exit:
116 phy->do_full_init = true;
117 if (ops->exit)
118 ops->exit(dev);
119err_block_rf:
120 b43_software_rfkill(dev, true);
121
122 return err;
123}
124
125void b43_phy_exit(struct b43_wldev *dev)
126{
127 const struct b43_phy_operations *ops = dev->phy.ops;
128
129 b43_software_rfkill(dev, true);
130 dev->phy.do_full_init = true;
131 if (ops->exit)
132 ops->exit(dev);
133}
134
135bool b43_has_hardware_pctl(struct b43_wldev *dev)
136{
137 if (!dev->phy.hardware_power_control)
138 return false;
139 if (!dev->phy.ops->supports_hwpctl)
140 return false;
141 return dev->phy.ops->supports_hwpctl(dev);
142}
143
144void b43_radio_lock(struct b43_wldev *dev)
145{
146 u32 macctl;
147
148#if B43_DEBUG
149 B43_WARN_ON(dev->phy.radio_locked);
150 dev->phy.radio_locked = true;
151#endif
152
153 macctl = b43_read32(dev, B43_MMIO_MACCTL);
154 macctl |= B43_MACCTL_RADIOLOCK;
155 b43_write32(dev, B43_MMIO_MACCTL, macctl);
156 /* Commit the write and wait for the firmware
157 * to finish any radio register access. */
158 b43_read32(dev, B43_MMIO_MACCTL);
159 udelay(10);
160}
161
162void b43_radio_unlock(struct b43_wldev *dev)
163{
164 u32 macctl;
165
166#if B43_DEBUG
167 B43_WARN_ON(!dev->phy.radio_locked);
168 dev->phy.radio_locked = false;
169#endif
170
171 /* Commit any write */
172 b43_read16(dev, B43_MMIO_PHY_VER);
173 /* unlock */
174 macctl = b43_read32(dev, B43_MMIO_MACCTL);
175 macctl &= ~B43_MACCTL_RADIOLOCK;
176 b43_write32(dev, B43_MMIO_MACCTL, macctl);
177}
178
179void b43_phy_lock(struct b43_wldev *dev)
180{
181#if B43_DEBUG
182 B43_WARN_ON(dev->phy.phy_locked);
183 dev->phy.phy_locked = true;
184#endif
185 B43_WARN_ON(dev->dev->core_rev < 3);
186
187 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
188 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
189}
190
191void b43_phy_unlock(struct b43_wldev *dev)
192{
193#if B43_DEBUG
194 B43_WARN_ON(!dev->phy.phy_locked);
195 dev->phy.phy_locked = false;
196#endif
197 B43_WARN_ON(dev->dev->core_rev < 3);
198
199 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
200 b43_power_saving_ctl_bits(dev, 0);
201}
202
203static inline void assert_mac_suspended(struct b43_wldev *dev)
204{
205 if (!B43_DEBUG)
206 return;
207 if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
208 (dev->mac_suspended <= 0)) {
209 b43dbg(dev->wl, "PHY/RADIO register access with "
210 "enabled MAC.\n");
211 dump_stack();
212 }
213}
214
215u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
216{
217 assert_mac_suspended(dev);
218 dev->phy.writes_counter = 0;
219 return dev->phy.ops->radio_read(dev, reg);
220}
221
222void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
223{
224 assert_mac_suspended(dev);
225 if (b43_bus_host_is_pci(dev->dev) &&
226 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
227 b43_read32(dev, B43_MMIO_MACCTL);
228 dev->phy.writes_counter = 1;
229 }
230 dev->phy.ops->radio_write(dev, reg, value);
231}
232
233void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
234{
235 b43_radio_write16(dev, offset,
236 b43_radio_read16(dev, offset) & mask);
237}
238
239void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
240{
241 b43_radio_write16(dev, offset,
242 b43_radio_read16(dev, offset) | set);
243}
244
245void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
246{
247 b43_radio_write16(dev, offset,
248 (b43_radio_read16(dev, offset) & mask) | set);
249}
250
251bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
252 u16 value, int delay, int timeout)
253{
254 u16 val;
255 int i;
256
257 for (i = 0; i < timeout; i += delay) {
258 val = b43_radio_read(dev, offset);
259 if ((val & mask) == value)
260 return true;
261 udelay(delay);
262 }
263 return false;
264}
265
266u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
267{
268 assert_mac_suspended(dev);
269 dev->phy.writes_counter = 0;
270
271 if (dev->phy.ops->phy_read)
272 return dev->phy.ops->phy_read(dev, reg);
273
274 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
275 return b43_read16(dev, B43_MMIO_PHY_DATA);
276}
277
278void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
279{
280 assert_mac_suspended(dev);
281 if (b43_bus_host_is_pci(dev->dev) &&
282 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
283 b43_read16(dev, B43_MMIO_PHY_VER);
284 dev->phy.writes_counter = 1;
285 }
286
287 if (dev->phy.ops->phy_write)
288 return dev->phy.ops->phy_write(dev, reg, value);
289
290 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
291 b43_write16(dev, B43_MMIO_PHY_DATA, value);
292}
293
294void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
295{
296 b43_phy_write(dev, destreg, b43_phy_read(dev, srcreg));
297}
298
299void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
300{
301 if (dev->phy.ops->phy_maskset) {
302 assert_mac_suspended(dev);
303 dev->phy.ops->phy_maskset(dev, offset, mask, 0);
304 } else {
305 b43_phy_write(dev, offset,
306 b43_phy_read(dev, offset) & mask);
307 }
308}
309
310void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
311{
312 if (dev->phy.ops->phy_maskset) {
313 assert_mac_suspended(dev);
314 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
315 } else {
316 b43_phy_write(dev, offset,
317 b43_phy_read(dev, offset) | set);
318 }
319}
320
321void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
322{
323 if (dev->phy.ops->phy_maskset) {
324 assert_mac_suspended(dev);
325 dev->phy.ops->phy_maskset(dev, offset, mask, set);
326 } else {
327 b43_phy_write(dev, offset,
328 (b43_phy_read(dev, offset) & mask) | set);
329 }
330}
331
332void b43_phy_put_into_reset(struct b43_wldev *dev)
333{
334 u32 tmp;
335
336 switch (dev->dev->bus_type) {
337#ifdef CONFIG_B43_BCMA
338 case B43_BUS_BCMA:
339 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
340 tmp &= ~B43_BCMA_IOCTL_GMODE;
341 tmp |= B43_BCMA_IOCTL_PHY_RESET;
342 tmp |= BCMA_IOCTL_FGC;
343 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
344 udelay(1);
345
346 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
347 tmp &= ~BCMA_IOCTL_FGC;
348 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
349 udelay(1);
350 break;
351#endif
352#ifdef CONFIG_B43_SSB
353 case B43_BUS_SSB:
354 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
355 tmp &= ~B43_TMSLOW_GMODE;
356 tmp |= B43_TMSLOW_PHYRESET;
357 tmp |= SSB_TMSLOW_FGC;
358 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
359 usleep_range(1000, 2000);
360
361 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
362 tmp &= ~SSB_TMSLOW_FGC;
363 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
364 usleep_range(1000, 2000);
365
366 break;
367#endif
368 }
369}
370
371void b43_phy_take_out_of_reset(struct b43_wldev *dev)
372{
373 u32 tmp;
374
375 switch (dev->dev->bus_type) {
376#ifdef CONFIG_B43_BCMA
377 case B43_BUS_BCMA:
378 /* Unset reset bit (with forcing clock) */
379 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
380 tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
381 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
382 tmp |= BCMA_IOCTL_FGC;
383 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
384 udelay(1);
385
386 /* Do not force clock anymore */
387 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
388 tmp &= ~BCMA_IOCTL_FGC;
389 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
390 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
391 udelay(1);
392 break;
393#endif
394#ifdef CONFIG_B43_SSB
395 case B43_BUS_SSB:
396 /* Unset reset bit (with forcing clock) */
397 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
398 tmp &= ~B43_TMSLOW_PHYRESET;
399 tmp &= ~B43_TMSLOW_PHYCLKEN;
400 tmp |= SSB_TMSLOW_FGC;
401 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
402 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
403 usleep_range(1000, 2000);
404
405 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
406 tmp &= ~SSB_TMSLOW_FGC;
407 tmp |= B43_TMSLOW_PHYCLKEN;
408 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
409 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
410 usleep_range(1000, 2000);
411 break;
412#endif
413 }
414}
415
416int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
417{
418 struct b43_phy *phy = &(dev->phy);
419 u16 channelcookie, savedcookie;
420 int err;
421
422 /* First we set the channel radio code to prevent the
423 * firmware from sending ghost packets.
424 */
425 channelcookie = new_channel;
426 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ)
427 channelcookie |= B43_SHM_SH_CHAN_5GHZ;
428 /* FIXME: set 40Mhz flag if required */
429 if (0)
430 channelcookie |= B43_SHM_SH_CHAN_40MHZ;
431 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
432 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
433
434 /* Now try to switch the PHY hardware channel. */
435 err = phy->ops->switch_channel(dev, new_channel);
436 if (err)
437 goto err_restore_cookie;
438
439 /* Wait for the radio to tune to the channel and stabilize. */
440 msleep(8);
441
442 return 0;
443
444err_restore_cookie:
445 b43_shm_write16(dev, B43_SHM_SHARED,
446 B43_SHM_SH_CHAN, savedcookie);
447
448 return err;
449}
450
451void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
452{
453 struct b43_phy *phy = &dev->phy;
454
455 b43_mac_suspend(dev);
456 phy->ops->software_rfkill(dev, blocked);
457 phy->radio_on = !blocked;
458 b43_mac_enable(dev);
459}
460
461/*
462 * b43_phy_txpower_adjust_work - TX power workqueue.
463 *
464 * Workqueue for updating the TX power parameters in hardware.
465 */
466void b43_phy_txpower_adjust_work(struct work_struct *work)
467{
468 struct b43_wl *wl = container_of(work, struct b43_wl,
469 txpower_adjust_work);
470 struct b43_wldev *dev;
471
472 mutex_lock(&wl->mutex);
473 dev = wl->current_dev;
474
475 if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
476 dev->phy.ops->adjust_txpower(dev);
477
478 mutex_unlock(&wl->mutex);
479}
480
481void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
482{
483 struct b43_phy *phy = &dev->phy;
484 unsigned long now = jiffies;
485 enum b43_txpwr_result result;
486
487 if (!(flags & B43_TXPWR_IGNORE_TIME)) {
488 /* Check if it's time for a TXpower check. */
489 if (time_before(now, phy->next_txpwr_check_time))
490 return; /* Not yet */
491 }
492 /* The next check will be needed in two seconds, or later. */
493 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
494
495 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
496 (dev->dev->board_type == SSB_BOARD_BU4306))
497 return; /* No software txpower adjustment needed */
498
499 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
500 if (result == B43_TXPWR_RES_DONE)
501 return; /* We are done. */
502 B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
503 B43_WARN_ON(phy->ops->adjust_txpower == NULL);
504
505 /* We must adjust the transmission power in hardware.
506 * Schedule b43_phy_txpower_adjust_work(). */
507 ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
508}
509
510int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
511{
512 const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
513 unsigned int a, b, c, d;
514 unsigned int average;
515 u32 tmp;
516
517 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
518 a = tmp & 0xFF;
519 b = (tmp >> 8) & 0xFF;
520 c = (tmp >> 16) & 0xFF;
521 d = (tmp >> 24) & 0xFF;
522 if (a == 0 || a == B43_TSSI_MAX ||
523 b == 0 || b == B43_TSSI_MAX ||
524 c == 0 || c == B43_TSSI_MAX ||
525 d == 0 || d == B43_TSSI_MAX)
526 return -ENOENT;
527 /* The values are OK. Clear them. */
528 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
529 (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
530 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
531
532 if (is_ofdm) {
533 a = (a + 32) & 0x3F;
534 b = (b + 32) & 0x3F;
535 c = (c + 32) & 0x3F;
536 d = (d + 32) & 0x3F;
537 }
538
539 /* Get the average of the values with 0.5 added to each value. */
540 average = (a + b + c + d + 2) / 4;
541 if (is_ofdm) {
542 /* Adjust for CCK-boost */
543 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
544 & B43_HF_CCKBOOST)
545 average = (average >= 13) ? (average - 13) : 0;
546 }
547
548 return average;
549}
550
551void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
552{
553 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
554}
555
556
557bool b43_is_40mhz(struct b43_wldev *dev)
558{
559 return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
560}
561
562/* https://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
563void b43_phy_force_clock(struct b43_wldev *dev, bool force)
564{
565 u32 tmp;
566
567 WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
568 dev->phy.type != B43_PHYTYPE_HT &&
569 dev->phy.type != B43_PHYTYPE_AC);
570
571 switch (dev->dev->bus_type) {
572#ifdef CONFIG_B43_BCMA
573 case B43_BUS_BCMA:
574 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
575 if (force)
576 tmp |= BCMA_IOCTL_FGC;
577 else
578 tmp &= ~BCMA_IOCTL_FGC;
579 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
580 break;
581#endif
582#ifdef CONFIG_B43_SSB
583 case B43_BUS_SSB:
584 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
585 if (force)
586 tmp |= SSB_TMSLOW_FGC;
587 else
588 tmp &= ~SSB_TMSLOW_FGC;
589 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
590 break;
591#endif
592 }
593}
1/*
2
3 Broadcom B43 wireless driver
4 Common PHY routines
5
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
26
27*/
28
29#include "phy_common.h"
30#include "phy_g.h"
31#include "phy_a.h"
32#include "phy_n.h"
33#include "phy_lp.h"
34#include "phy_ht.h"
35#include "phy_lcn.h"
36#include "phy_ac.h"
37#include "b43.h"
38#include "main.h"
39
40
41int b43_phy_allocate(struct b43_wldev *dev)
42{
43 struct b43_phy *phy = &(dev->phy);
44 int err;
45
46 phy->ops = NULL;
47
48 switch (phy->type) {
49 case B43_PHYTYPE_G:
50#ifdef CONFIG_B43_PHY_G
51 phy->ops = &b43_phyops_g;
52#endif
53 break;
54 case B43_PHYTYPE_N:
55#ifdef CONFIG_B43_PHY_N
56 phy->ops = &b43_phyops_n;
57#endif
58 break;
59 case B43_PHYTYPE_LP:
60#ifdef CONFIG_B43_PHY_LP
61 phy->ops = &b43_phyops_lp;
62#endif
63 break;
64 case B43_PHYTYPE_HT:
65#ifdef CONFIG_B43_PHY_HT
66 phy->ops = &b43_phyops_ht;
67#endif
68 break;
69 case B43_PHYTYPE_LCN:
70#ifdef CONFIG_B43_PHY_LCN
71 phy->ops = &b43_phyops_lcn;
72#endif
73 break;
74 case B43_PHYTYPE_AC:
75#ifdef CONFIG_B43_PHY_AC
76 phy->ops = &b43_phyops_ac;
77#endif
78 break;
79 }
80 if (B43_WARN_ON(!phy->ops))
81 return -ENODEV;
82
83 err = phy->ops->allocate(dev);
84 if (err)
85 phy->ops = NULL;
86
87 return err;
88}
89
90void b43_phy_free(struct b43_wldev *dev)
91{
92 dev->phy.ops->free(dev);
93 dev->phy.ops = NULL;
94}
95
96int b43_phy_init(struct b43_wldev *dev)
97{
98 struct b43_phy *phy = &dev->phy;
99 const struct b43_phy_operations *ops = phy->ops;
100 int err;
101
102 /* During PHY init we need to use some channel. On the first init this
103 * function is called *before* b43_op_config, so our pointer is NULL.
104 */
105 if (!phy->chandef) {
106 phy->chandef = &dev->wl->hw->conf.chandef;
107 phy->channel = phy->chandef->chan->hw_value;
108 }
109
110 phy->ops->switch_analog(dev, true);
111 b43_software_rfkill(dev, false);
112
113 err = ops->init(dev);
114 if (err) {
115 b43err(dev->wl, "PHY init failed\n");
116 goto err_block_rf;
117 }
118 phy->do_full_init = false;
119
120 err = b43_switch_channel(dev, phy->channel);
121 if (err) {
122 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
123 goto err_phy_exit;
124 }
125
126 return 0;
127
128err_phy_exit:
129 phy->do_full_init = true;
130 if (ops->exit)
131 ops->exit(dev);
132err_block_rf:
133 b43_software_rfkill(dev, true);
134
135 return err;
136}
137
138void b43_phy_exit(struct b43_wldev *dev)
139{
140 const struct b43_phy_operations *ops = dev->phy.ops;
141
142 b43_software_rfkill(dev, true);
143 dev->phy.do_full_init = true;
144 if (ops->exit)
145 ops->exit(dev);
146}
147
148bool b43_has_hardware_pctl(struct b43_wldev *dev)
149{
150 if (!dev->phy.hardware_power_control)
151 return false;
152 if (!dev->phy.ops->supports_hwpctl)
153 return false;
154 return dev->phy.ops->supports_hwpctl(dev);
155}
156
157void b43_radio_lock(struct b43_wldev *dev)
158{
159 u32 macctl;
160
161#if B43_DEBUG
162 B43_WARN_ON(dev->phy.radio_locked);
163 dev->phy.radio_locked = true;
164#endif
165
166 macctl = b43_read32(dev, B43_MMIO_MACCTL);
167 macctl |= B43_MACCTL_RADIOLOCK;
168 b43_write32(dev, B43_MMIO_MACCTL, macctl);
169 /* Commit the write and wait for the firmware
170 * to finish any radio register access. */
171 b43_read32(dev, B43_MMIO_MACCTL);
172 udelay(10);
173}
174
175void b43_radio_unlock(struct b43_wldev *dev)
176{
177 u32 macctl;
178
179#if B43_DEBUG
180 B43_WARN_ON(!dev->phy.radio_locked);
181 dev->phy.radio_locked = false;
182#endif
183
184 /* Commit any write */
185 b43_read16(dev, B43_MMIO_PHY_VER);
186 /* unlock */
187 macctl = b43_read32(dev, B43_MMIO_MACCTL);
188 macctl &= ~B43_MACCTL_RADIOLOCK;
189 b43_write32(dev, B43_MMIO_MACCTL, macctl);
190}
191
192void b43_phy_lock(struct b43_wldev *dev)
193{
194#if B43_DEBUG
195 B43_WARN_ON(dev->phy.phy_locked);
196 dev->phy.phy_locked = true;
197#endif
198 B43_WARN_ON(dev->dev->core_rev < 3);
199
200 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
201 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
202}
203
204void b43_phy_unlock(struct b43_wldev *dev)
205{
206#if B43_DEBUG
207 B43_WARN_ON(!dev->phy.phy_locked);
208 dev->phy.phy_locked = false;
209#endif
210 B43_WARN_ON(dev->dev->core_rev < 3);
211
212 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
213 b43_power_saving_ctl_bits(dev, 0);
214}
215
216static inline void assert_mac_suspended(struct b43_wldev *dev)
217{
218 if (!B43_DEBUG)
219 return;
220 if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
221 (dev->mac_suspended <= 0)) {
222 b43dbg(dev->wl, "PHY/RADIO register access with "
223 "enabled MAC.\n");
224 dump_stack();
225 }
226}
227
228u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
229{
230 assert_mac_suspended(dev);
231 dev->phy.writes_counter = 0;
232 return dev->phy.ops->radio_read(dev, reg);
233}
234
235void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
236{
237 assert_mac_suspended(dev);
238 if (b43_bus_host_is_pci(dev->dev) &&
239 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
240 b43_read32(dev, B43_MMIO_MACCTL);
241 dev->phy.writes_counter = 1;
242 }
243 dev->phy.ops->radio_write(dev, reg, value);
244}
245
246void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
247{
248 b43_radio_write16(dev, offset,
249 b43_radio_read16(dev, offset) & mask);
250}
251
252void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
253{
254 b43_radio_write16(dev, offset,
255 b43_radio_read16(dev, offset) | set);
256}
257
258void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
259{
260 b43_radio_write16(dev, offset,
261 (b43_radio_read16(dev, offset) & mask) | set);
262}
263
264bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask,
265 u16 value, int delay, int timeout)
266{
267 u16 val;
268 int i;
269
270 for (i = 0; i < timeout; i += delay) {
271 val = b43_radio_read(dev, offset);
272 if ((val & mask) == value)
273 return true;
274 udelay(delay);
275 }
276 return false;
277}
278
279u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
280{
281 assert_mac_suspended(dev);
282 dev->phy.writes_counter = 0;
283
284 if (dev->phy.ops->phy_read)
285 return dev->phy.ops->phy_read(dev, reg);
286
287 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
288 return b43_read16(dev, B43_MMIO_PHY_DATA);
289}
290
291void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
292{
293 assert_mac_suspended(dev);
294 if (b43_bus_host_is_pci(dev->dev) &&
295 ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
296 b43_read16(dev, B43_MMIO_PHY_VER);
297 dev->phy.writes_counter = 1;
298 }
299
300 if (dev->phy.ops->phy_write)
301 return dev->phy.ops->phy_write(dev, reg, value);
302
303 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
304 b43_write16(dev, B43_MMIO_PHY_DATA, value);
305}
306
307void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
308{
309 b43_phy_write(dev, destreg, b43_phy_read(dev, srcreg));
310}
311
312void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
313{
314 if (dev->phy.ops->phy_maskset) {
315 assert_mac_suspended(dev);
316 dev->phy.ops->phy_maskset(dev, offset, mask, 0);
317 } else {
318 b43_phy_write(dev, offset,
319 b43_phy_read(dev, offset) & mask);
320 }
321}
322
323void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
324{
325 if (dev->phy.ops->phy_maskset) {
326 assert_mac_suspended(dev);
327 dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set);
328 } else {
329 b43_phy_write(dev, offset,
330 b43_phy_read(dev, offset) | set);
331 }
332}
333
334void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
335{
336 if (dev->phy.ops->phy_maskset) {
337 assert_mac_suspended(dev);
338 dev->phy.ops->phy_maskset(dev, offset, mask, set);
339 } else {
340 b43_phy_write(dev, offset,
341 (b43_phy_read(dev, offset) & mask) | set);
342 }
343}
344
345void b43_phy_put_into_reset(struct b43_wldev *dev)
346{
347 u32 tmp;
348
349 switch (dev->dev->bus_type) {
350#ifdef CONFIG_B43_BCMA
351 case B43_BUS_BCMA:
352 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
353 tmp &= ~B43_BCMA_IOCTL_GMODE;
354 tmp |= B43_BCMA_IOCTL_PHY_RESET;
355 tmp |= BCMA_IOCTL_FGC;
356 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
357 udelay(1);
358
359 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
360 tmp &= ~BCMA_IOCTL_FGC;
361 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
362 udelay(1);
363 break;
364#endif
365#ifdef CONFIG_B43_SSB
366 case B43_BUS_SSB:
367 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
368 tmp &= ~B43_TMSLOW_GMODE;
369 tmp |= B43_TMSLOW_PHYRESET;
370 tmp |= SSB_TMSLOW_FGC;
371 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
372 usleep_range(1000, 2000);
373
374 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
375 tmp &= ~SSB_TMSLOW_FGC;
376 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
377 usleep_range(1000, 2000);
378
379 break;
380#endif
381 }
382}
383
384void b43_phy_take_out_of_reset(struct b43_wldev *dev)
385{
386 u32 tmp;
387
388 switch (dev->dev->bus_type) {
389#ifdef CONFIG_B43_BCMA
390 case B43_BUS_BCMA:
391 /* Unset reset bit (with forcing clock) */
392 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
393 tmp &= ~B43_BCMA_IOCTL_PHY_RESET;
394 tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN;
395 tmp |= BCMA_IOCTL_FGC;
396 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
397 udelay(1);
398
399 /* Do not force clock anymore */
400 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
401 tmp &= ~BCMA_IOCTL_FGC;
402 tmp |= B43_BCMA_IOCTL_PHY_CLKEN;
403 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
404 udelay(1);
405 break;
406#endif
407#ifdef CONFIG_B43_SSB
408 case B43_BUS_SSB:
409 /* Unset reset bit (with forcing clock) */
410 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
411 tmp &= ~B43_TMSLOW_PHYRESET;
412 tmp &= ~B43_TMSLOW_PHYCLKEN;
413 tmp |= SSB_TMSLOW_FGC;
414 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
415 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
416 usleep_range(1000, 2000);
417
418 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
419 tmp &= ~SSB_TMSLOW_FGC;
420 tmp |= B43_TMSLOW_PHYCLKEN;
421 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
422 ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */
423 usleep_range(1000, 2000);
424 break;
425#endif
426 }
427}
428
429int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
430{
431 struct b43_phy *phy = &(dev->phy);
432 u16 channelcookie, savedcookie;
433 int err;
434
435 /* First we set the channel radio code to prevent the
436 * firmware from sending ghost packets.
437 */
438 channelcookie = new_channel;
439 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
440 channelcookie |= B43_SHM_SH_CHAN_5GHZ;
441 /* FIXME: set 40Mhz flag if required */
442 if (0)
443 channelcookie |= B43_SHM_SH_CHAN_40MHZ;
444 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
445 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
446
447 /* Now try to switch the PHY hardware channel. */
448 err = phy->ops->switch_channel(dev, new_channel);
449 if (err)
450 goto err_restore_cookie;
451
452 /* Wait for the radio to tune to the channel and stabilize. */
453 msleep(8);
454
455 return 0;
456
457err_restore_cookie:
458 b43_shm_write16(dev, B43_SHM_SHARED,
459 B43_SHM_SH_CHAN, savedcookie);
460
461 return err;
462}
463
464void b43_software_rfkill(struct b43_wldev *dev, bool blocked)
465{
466 struct b43_phy *phy = &dev->phy;
467
468 b43_mac_suspend(dev);
469 phy->ops->software_rfkill(dev, blocked);
470 phy->radio_on = !blocked;
471 b43_mac_enable(dev);
472}
473
474/**
475 * b43_phy_txpower_adjust_work - TX power workqueue.
476 *
477 * Workqueue for updating the TX power parameters in hardware.
478 */
479void b43_phy_txpower_adjust_work(struct work_struct *work)
480{
481 struct b43_wl *wl = container_of(work, struct b43_wl,
482 txpower_adjust_work);
483 struct b43_wldev *dev;
484
485 mutex_lock(&wl->mutex);
486 dev = wl->current_dev;
487
488 if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
489 dev->phy.ops->adjust_txpower(dev);
490
491 mutex_unlock(&wl->mutex);
492}
493
494void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
495{
496 struct b43_phy *phy = &dev->phy;
497 unsigned long now = jiffies;
498 enum b43_txpwr_result result;
499
500 if (!(flags & B43_TXPWR_IGNORE_TIME)) {
501 /* Check if it's time for a TXpower check. */
502 if (time_before(now, phy->next_txpwr_check_time))
503 return; /* Not yet */
504 }
505 /* The next check will be needed in two seconds, or later. */
506 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
507
508 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
509 (dev->dev->board_type == SSB_BOARD_BU4306))
510 return; /* No software txpower adjustment needed */
511
512 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
513 if (result == B43_TXPWR_RES_DONE)
514 return; /* We are done. */
515 B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
516 B43_WARN_ON(phy->ops->adjust_txpower == NULL);
517
518 /* We must adjust the transmission power in hardware.
519 * Schedule b43_phy_txpower_adjust_work(). */
520 ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work);
521}
522
523int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
524{
525 const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
526 unsigned int a, b, c, d;
527 unsigned int average;
528 u32 tmp;
529
530 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
531 a = tmp & 0xFF;
532 b = (tmp >> 8) & 0xFF;
533 c = (tmp >> 16) & 0xFF;
534 d = (tmp >> 24) & 0xFF;
535 if (a == 0 || a == B43_TSSI_MAX ||
536 b == 0 || b == B43_TSSI_MAX ||
537 c == 0 || c == B43_TSSI_MAX ||
538 d == 0 || d == B43_TSSI_MAX)
539 return -ENOENT;
540 /* The values are OK. Clear them. */
541 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
542 (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
543 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
544
545 if (is_ofdm) {
546 a = (a + 32) & 0x3F;
547 b = (b + 32) & 0x3F;
548 c = (c + 32) & 0x3F;
549 d = (d + 32) & 0x3F;
550 }
551
552 /* Get the average of the values with 0.5 added to each value. */
553 average = (a + b + c + d + 2) / 4;
554 if (is_ofdm) {
555 /* Adjust for CCK-boost */
556 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1)
557 & B43_HF_CCKBOOST)
558 average = (average >= 13) ? (average - 13) : 0;
559 }
560
561 return average;
562}
563
564void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
565{
566 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
567}
568
569
570bool b43_is_40mhz(struct b43_wldev *dev)
571{
572 return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
573}
574
575/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
576void b43_phy_force_clock(struct b43_wldev *dev, bool force)
577{
578 u32 tmp;
579
580 WARN_ON(dev->phy.type != B43_PHYTYPE_N &&
581 dev->phy.type != B43_PHYTYPE_HT &&
582 dev->phy.type != B43_PHYTYPE_AC);
583
584 switch (dev->dev->bus_type) {
585#ifdef CONFIG_B43_BCMA
586 case B43_BUS_BCMA:
587 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
588 if (force)
589 tmp |= BCMA_IOCTL_FGC;
590 else
591 tmp &= ~BCMA_IOCTL_FGC;
592 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
593 break;
594#endif
595#ifdef CONFIG_B43_SSB
596 case B43_BUS_SSB:
597 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
598 if (force)
599 tmp |= SSB_TMSLOW_FGC;
600 else
601 tmp &= ~SSB_TMSLOW_FGC;
602 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
603 break;
604#endif
605 }
606}
607
608/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
609struct b43_c32 b43_cordic(int theta)
610{
611 static const u32 arctg[] = {
612 2949120, 1740967, 919879, 466945, 234379, 117304,
613 58666, 29335, 14668, 7334, 3667, 1833,
614 917, 458, 229, 115, 57, 29,
615 };
616 u8 i;
617 s32 tmp;
618 s8 signx = 1;
619 u32 angle = 0;
620 struct b43_c32 ret = { .i = 39797, .q = 0, };
621
622 while (theta > (180 << 16))
623 theta -= (360 << 16);
624 while (theta < -(180 << 16))
625 theta += (360 << 16);
626
627 if (theta > (90 << 16)) {
628 theta -= (180 << 16);
629 signx = -1;
630 } else if (theta < -(90 << 16)) {
631 theta += (180 << 16);
632 signx = -1;
633 }
634
635 for (i = 0; i <= 17; i++) {
636 if (theta > angle) {
637 tmp = ret.i - (ret.q >> i);
638 ret.q += ret.i >> i;
639 ret.i = tmp;
640 angle += arctg[i];
641 } else {
642 tmp = ret.i + (ret.q >> i);
643 ret.q -= ret.i >> i;
644 ret.i = tmp;
645 angle -= arctg[i];
646 }
647 }
648
649 ret.i *= signx;
650 ret.q *= signx;
651
652 return ret;
653}