Loading...
1/* CoreChip-sz SR9800 one chip USB 2.0 Ethernet Devices
2 *
3 * Author : Liu Junliang <liujunliang_ljl@163.com>
4 *
5 * This file is licensed under the terms of the GNU General Public License
6 * version 2. This program is licensed "as is" without any warranty of any
7 * kind, whether express or implied.
8 */
9
10#ifndef _SR9800_H
11#define _SR9800_H
12
13/* SR9800 spec. command table on Linux Platform */
14
15/* command : Software Station Management Control Reg */
16#define SR_CMD_SET_SW_MII 0x06
17/* command : PHY Read Reg */
18#define SR_CMD_READ_MII_REG 0x07
19/* command : PHY Write Reg */
20#define SR_CMD_WRITE_MII_REG 0x08
21/* command : Hardware Station Management Control Reg */
22#define SR_CMD_SET_HW_MII 0x0a
23/* command : SROM Read Reg */
24#define SR_CMD_READ_EEPROM 0x0b
25/* command : SROM Write Reg */
26#define SR_CMD_WRITE_EEPROM 0x0c
27/* command : SROM Write Enable Reg */
28#define SR_CMD_WRITE_ENABLE 0x0d
29/* command : SROM Write Disable Reg */
30#define SR_CMD_WRITE_DISABLE 0x0e
31/* command : RX Control Read Reg */
32#define SR_CMD_READ_RX_CTL 0x0f
33#define SR_RX_CTL_PRO (1 << 0)
34#define SR_RX_CTL_AMALL (1 << 1)
35#define SR_RX_CTL_SEP (1 << 2)
36#define SR_RX_CTL_AB (1 << 3)
37#define SR_RX_CTL_AM (1 << 4)
38#define SR_RX_CTL_AP (1 << 5)
39#define SR_RX_CTL_ARP (1 << 6)
40#define SR_RX_CTL_SO (1 << 7)
41#define SR_RX_CTL_RH1M (1 << 8)
42#define SR_RX_CTL_RH2M (1 << 9)
43#define SR_RX_CTL_RH3M (1 << 10)
44/* command : RX Control Write Reg */
45#define SR_CMD_WRITE_RX_CTL 0x10
46/* command : IPG0/IPG1/IPG2 Control Read Reg */
47#define SR_CMD_READ_IPG012 0x11
48/* command : IPG0/IPG1/IPG2 Control Write Reg */
49#define SR_CMD_WRITE_IPG012 0x12
50/* command : Node ID Read Reg */
51#define SR_CMD_READ_NODE_ID 0x13
52/* command : Node ID Write Reg */
53#define SR_CMD_WRITE_NODE_ID 0x14
54/* command : Multicast Filter Array Read Reg */
55#define SR_CMD_READ_MULTI_FILTER 0x15
56/* command : Multicast Filter Array Write Reg */
57#define SR_CMD_WRITE_MULTI_FILTER 0x16
58/* command : Eth/HomePNA PHY Address Reg */
59#define SR_CMD_READ_PHY_ID 0x19
60/* command : Medium Status Read Reg */
61#define SR_CMD_READ_MEDIUM_STATUS 0x1a
62#define SR_MONITOR_LINK (1 << 1)
63#define SR_MONITOR_MAGIC (1 << 2)
64#define SR_MONITOR_HSFS (1 << 4)
65/* command : Medium Status Write Reg */
66#define SR_CMD_WRITE_MEDIUM_MODE 0x1b
67#define SR_MEDIUM_GM (1 << 0)
68#define SR_MEDIUM_FD (1 << 1)
69#define SR_MEDIUM_AC (1 << 2)
70#define SR_MEDIUM_ENCK (1 << 3)
71#define SR_MEDIUM_RFC (1 << 4)
72#define SR_MEDIUM_TFC (1 << 5)
73#define SR_MEDIUM_JFE (1 << 6)
74#define SR_MEDIUM_PF (1 << 7)
75#define SR_MEDIUM_RE (1 << 8)
76#define SR_MEDIUM_PS (1 << 9)
77#define SR_MEDIUM_RSV (1 << 10)
78#define SR_MEDIUM_SBP (1 << 11)
79#define SR_MEDIUM_SM (1 << 12)
80/* command : Monitor Mode Status Read Reg */
81#define SR_CMD_READ_MONITOR_MODE 0x1c
82/* command : Monitor Mode Status Write Reg */
83#define SR_CMD_WRITE_MONITOR_MODE 0x1d
84/* command : GPIO Status Read Reg */
85#define SR_CMD_READ_GPIOS 0x1e
86#define SR_GPIO_GPO0EN (1 << 0) /* GPIO0 Output enable */
87#define SR_GPIO_GPO_0 (1 << 1) /* GPIO0 Output value */
88#define SR_GPIO_GPO1EN (1 << 2) /* GPIO1 Output enable */
89#define SR_GPIO_GPO_1 (1 << 3) /* GPIO1 Output value */
90#define SR_GPIO_GPO2EN (1 << 4) /* GPIO2 Output enable */
91#define SR_GPIO_GPO_2 (1 << 5) /* GPIO2 Output value */
92#define SR_GPIO_RESERVED (1 << 6) /* Reserved */
93#define SR_GPIO_RSE (1 << 7) /* Reload serial EEPROM */
94/* command : GPIO Status Write Reg */
95#define SR_CMD_WRITE_GPIOS 0x1f
96/* command : Eth PHY Power and Reset Control Reg */
97#define SR_CMD_SW_RESET 0x20
98#define SR_SWRESET_CLEAR 0x00
99#define SR_SWRESET_RR (1 << 0)
100#define SR_SWRESET_RT (1 << 1)
101#define SR_SWRESET_PRTE (1 << 2)
102#define SR_SWRESET_PRL (1 << 3)
103#define SR_SWRESET_BZ (1 << 4)
104#define SR_SWRESET_IPRL (1 << 5)
105#define SR_SWRESET_IPPD (1 << 6)
106/* command : Software Interface Selection Status Read Reg */
107#define SR_CMD_SW_PHY_STATUS 0x21
108/* command : Software Interface Selection Status Write Reg */
109#define SR_CMD_SW_PHY_SELECT 0x22
110/* command : BULK in Buffer Size Reg */
111#define SR_CMD_BULKIN_SIZE 0x2A
112/* command : LED_MUX Control Reg */
113#define SR_CMD_LED_MUX 0x70
114#define SR_LED_MUX_TX_ACTIVE (1 << 0)
115#define SR_LED_MUX_RX_ACTIVE (1 << 1)
116#define SR_LED_MUX_COLLISION (1 << 2)
117#define SR_LED_MUX_DUP_COL (1 << 3)
118#define SR_LED_MUX_DUP (1 << 4)
119#define SR_LED_MUX_SPEED (1 << 5)
120#define SR_LED_MUX_LINK_ACTIVE (1 << 6)
121#define SR_LED_MUX_LINK (1 << 7)
122
123/* Register Access Flags */
124#define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
125#define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
126
127/* Multicast Filter Array size & Max Number */
128#define SR_MCAST_FILTER_SIZE 8
129#define SR_MAX_MCAST 64
130
131/* IPG0/1/2 Default Value */
132#define SR9800_IPG0_DEFAULT 0x15
133#define SR9800_IPG1_DEFAULT 0x0c
134#define SR9800_IPG2_DEFAULT 0x12
135
136/* Medium Status Default Mode */
137#define SR9800_MEDIUM_DEFAULT \
138 (SR_MEDIUM_FD | SR_MEDIUM_RFC | \
139 SR_MEDIUM_TFC | SR_MEDIUM_PS | \
140 SR_MEDIUM_AC | SR_MEDIUM_RE)
141
142/* RX Control Default Setting */
143#define SR_DEFAULT_RX_CTL \
144 (SR_RX_CTL_SO | SR_RX_CTL_AB | SR_RX_CTL_RH1M)
145
146/* EEPROM Magic Number & EEPROM Size */
147#define SR_EEPROM_MAGIC 0xdeadbeef
148#define SR9800_EEPROM_LEN 0xff
149
150/* SR9800 Driver Version and Driver Name */
151#define DRIVER_VERSION "11-Nov-2013"
152#define DRIVER_NAME "CoreChips"
153#define DRIVER_FLAG \
154 (FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET)
155
156/* SR9800 BULKIN Buffer Size */
157#define SR9800_MAX_BULKIN_2K 0
158#define SR9800_MAX_BULKIN_4K 1
159#define SR9800_MAX_BULKIN_6K 2
160#define SR9800_MAX_BULKIN_8K 3
161#define SR9800_MAX_BULKIN_16K 4
162#define SR9800_MAX_BULKIN_20K 5
163#define SR9800_MAX_BULKIN_24K 6
164#define SR9800_MAX_BULKIN_32K 7
165
166static const struct {unsigned short size, byte_cnt, threshold; } SR9800_BULKIN_SIZE[] = {
167 /* 2k */
168 {2048, 0x8000, 0x8001},
169 /* 4k */
170 {4096, 0x8100, 0x8147},
171 /* 6k */
172 {6144, 0x8200, 0x81EB},
173 /* 8k */
174 {8192, 0x8300, 0x83D7},
175 /* 16 */
176 {16384, 0x8400, 0x851E},
177 /* 20k */
178 {20480, 0x8500, 0x8666},
179 /* 24k */
180 {24576, 0x8600, 0x87AE},
181 /* 32k */
182 {32768, 0x8700, 0x8A3D},
183};
184
185/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
186struct sr_data {
187 u8 multi_filter[SR_MCAST_FILTER_SIZE];
188 u8 mac_addr[ETH_ALEN];
189 u8 phymode;
190 u8 ledmode;
191 u8 eeprom_len;
192};
193
194struct sr9800_int_data {
195 __le16 res1;
196 u8 link;
197 __le16 res2;
198 u8 status;
199 __le16 res3;
200} __packed;
201
202#endif /* _SR9800_H */
1/* CoreChip-sz SR9800 one chip USB 2.0 Ethernet Devices
2 *
3 * Author : Liu Junliang <liujunliang_ljl@163.com>
4 *
5 * This file is licensed under the terms of the GNU General Public License
6 * version 2. This program is licensed "as is" without any warranty of any
7 * kind, whether express or implied.
8 */
9
10#ifndef _SR9800_H
11#define _SR9800_H
12
13/* SR9800 spec. command table on Linux Platform */
14
15/* command : Software Station Management Control Reg */
16#define SR_CMD_SET_SW_MII 0x06
17/* command : PHY Read Reg */
18#define SR_CMD_READ_MII_REG 0x07
19/* command : PHY Write Reg */
20#define SR_CMD_WRITE_MII_REG 0x08
21/* command : Hardware Station Management Control Reg */
22#define SR_CMD_SET_HW_MII 0x0a
23/* command : SROM Read Reg */
24#define SR_CMD_READ_EEPROM 0x0b
25/* command : SROM Write Reg */
26#define SR_CMD_WRITE_EEPROM 0x0c
27/* command : SROM Write Enable Reg */
28#define SR_CMD_WRITE_ENABLE 0x0d
29/* command : SROM Write Disable Reg */
30#define SR_CMD_WRITE_DISABLE 0x0e
31/* command : RX Control Read Reg */
32#define SR_CMD_READ_RX_CTL 0x0f
33#define SR_RX_CTL_PRO (1 << 0)
34#define SR_RX_CTL_AMALL (1 << 1)
35#define SR_RX_CTL_SEP (1 << 2)
36#define SR_RX_CTL_AB (1 << 3)
37#define SR_RX_CTL_AM (1 << 4)
38#define SR_RX_CTL_AP (1 << 5)
39#define SR_RX_CTL_ARP (1 << 6)
40#define SR_RX_CTL_SO (1 << 7)
41#define SR_RX_CTL_RH1M (1 << 8)
42#define SR_RX_CTL_RH2M (1 << 9)
43#define SR_RX_CTL_RH3M (1 << 10)
44/* command : RX Control Write Reg */
45#define SR_CMD_WRITE_RX_CTL 0x10
46/* command : IPG0/IPG1/IPG2 Control Read Reg */
47#define SR_CMD_READ_IPG012 0x11
48/* command : IPG0/IPG1/IPG2 Control Write Reg */
49#define SR_CMD_WRITE_IPG012 0x12
50/* command : Node ID Read Reg */
51#define SR_CMD_READ_NODE_ID 0x13
52/* command : Node ID Write Reg */
53#define SR_CMD_WRITE_NODE_ID 0x14
54/* command : Multicast Filter Array Read Reg */
55#define SR_CMD_READ_MULTI_FILTER 0x15
56/* command : Multicast Filter Array Write Reg */
57#define SR_CMD_WRITE_MULTI_FILTER 0x16
58/* command : Eth/HomePNA PHY Address Reg */
59#define SR_CMD_READ_PHY_ID 0x19
60/* command : Medium Status Read Reg */
61#define SR_CMD_READ_MEDIUM_STATUS 0x1a
62#define SR_MONITOR_LINK (1 << 1)
63#define SR_MONITOR_MAGIC (1 << 2)
64#define SR_MONITOR_HSFS (1 << 4)
65/* command : Medium Status Write Reg */
66#define SR_CMD_WRITE_MEDIUM_MODE 0x1b
67#define SR_MEDIUM_GM (1 << 0)
68#define SR_MEDIUM_FD (1 << 1)
69#define SR_MEDIUM_AC (1 << 2)
70#define SR_MEDIUM_ENCK (1 << 3)
71#define SR_MEDIUM_RFC (1 << 4)
72#define SR_MEDIUM_TFC (1 << 5)
73#define SR_MEDIUM_JFE (1 << 6)
74#define SR_MEDIUM_PF (1 << 7)
75#define SR_MEDIUM_RE (1 << 8)
76#define SR_MEDIUM_PS (1 << 9)
77#define SR_MEDIUM_RSV (1 << 10)
78#define SR_MEDIUM_SBP (1 << 11)
79#define SR_MEDIUM_SM (1 << 12)
80/* command : Monitor Mode Status Read Reg */
81#define SR_CMD_READ_MONITOR_MODE 0x1c
82/* command : Monitor Mode Status Write Reg */
83#define SR_CMD_WRITE_MONITOR_MODE 0x1d
84/* command : GPIO Status Read Reg */
85#define SR_CMD_READ_GPIOS 0x1e
86#define SR_GPIO_GPO0EN (1 << 0) /* GPIO0 Output enable */
87#define SR_GPIO_GPO_0 (1 << 1) /* GPIO0 Output value */
88#define SR_GPIO_GPO1EN (1 << 2) /* GPIO1 Output enable */
89#define SR_GPIO_GPO_1 (1 << 3) /* GPIO1 Output value */
90#define SR_GPIO_GPO2EN (1 << 4) /* GPIO2 Output enable */
91#define SR_GPIO_GPO_2 (1 << 5) /* GPIO2 Output value */
92#define SR_GPIO_RESERVED (1 << 6) /* Reserved */
93#define SR_GPIO_RSE (1 << 7) /* Reload serial EEPROM */
94/* command : GPIO Status Write Reg */
95#define SR_CMD_WRITE_GPIOS 0x1f
96/* command : Eth PHY Power and Reset Control Reg */
97#define SR_CMD_SW_RESET 0x20
98#define SR_SWRESET_CLEAR 0x00
99#define SR_SWRESET_RR (1 << 0)
100#define SR_SWRESET_RT (1 << 1)
101#define SR_SWRESET_PRTE (1 << 2)
102#define SR_SWRESET_PRL (1 << 3)
103#define SR_SWRESET_BZ (1 << 4)
104#define SR_SWRESET_IPRL (1 << 5)
105#define SR_SWRESET_IPPD (1 << 6)
106/* command : Software Interface Selection Status Read Reg */
107#define SR_CMD_SW_PHY_STATUS 0x21
108/* command : Software Interface Selection Status Write Reg */
109#define SR_CMD_SW_PHY_SELECT 0x22
110/* command : BULK in Buffer Size Reg */
111#define SR_CMD_BULKIN_SIZE 0x2A
112/* command : LED_MUX Control Reg */
113#define SR_CMD_LED_MUX 0x70
114#define SR_LED_MUX_TX_ACTIVE (1 << 0)
115#define SR_LED_MUX_RX_ACTIVE (1 << 1)
116#define SR_LED_MUX_COLLISION (1 << 2)
117#define SR_LED_MUX_DUP_COL (1 << 3)
118#define SR_LED_MUX_DUP (1 << 4)
119#define SR_LED_MUX_SPEED (1 << 5)
120#define SR_LED_MUX_LINK_ACTIVE (1 << 6)
121#define SR_LED_MUX_LINK (1 << 7)
122
123/* Register Access Flags */
124#define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
125#define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
126
127/* Multicast Filter Array size & Max Number */
128#define SR_MCAST_FILTER_SIZE 8
129#define SR_MAX_MCAST 64
130
131/* IPG0/1/2 Default Value */
132#define SR9800_IPG0_DEFAULT 0x15
133#define SR9800_IPG1_DEFAULT 0x0c
134#define SR9800_IPG2_DEFAULT 0x12
135
136/* Medium Status Default Mode */
137#define SR9800_MEDIUM_DEFAULT \
138 (SR_MEDIUM_FD | SR_MEDIUM_RFC | \
139 SR_MEDIUM_TFC | SR_MEDIUM_PS | \
140 SR_MEDIUM_AC | SR_MEDIUM_RE)
141
142/* RX Control Default Setting */
143#define SR_DEFAULT_RX_CTL \
144 (SR_RX_CTL_SO | SR_RX_CTL_AB | SR_RX_CTL_RH1M)
145
146/* EEPROM Magic Number & EEPROM Size */
147#define SR_EEPROM_MAGIC 0xdeadbeef
148#define SR9800_EEPROM_LEN 0xff
149
150/* SR9800 Driver Version and Driver Name */
151#define DRIVER_VERSION "11-Nov-2013"
152#define DRIVER_NAME "CoreChips"
153#define DRIVER_FLAG \
154 (FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET)
155
156/* SR9800 BULKIN Buffer Size */
157#define SR9800_MAX_BULKIN_2K 0
158#define SR9800_MAX_BULKIN_4K 1
159#define SR9800_MAX_BULKIN_6K 2
160#define SR9800_MAX_BULKIN_8K 3
161#define SR9800_MAX_BULKIN_16K 4
162#define SR9800_MAX_BULKIN_20K 5
163#define SR9800_MAX_BULKIN_24K 6
164#define SR9800_MAX_BULKIN_32K 7
165
166struct {unsigned short size, byte_cnt, threshold; } SR9800_BULKIN_SIZE[] = {
167 /* 2k */
168 {2048, 0x8000, 0x8001},
169 /* 4k */
170 {4096, 0x8100, 0x8147},
171 /* 6k */
172 {6144, 0x8200, 0x81EB},
173 /* 8k */
174 {8192, 0x8300, 0x83D7},
175 /* 16 */
176 {16384, 0x8400, 0x851E},
177 /* 20k */
178 {20480, 0x8500, 0x8666},
179 /* 24k */
180 {24576, 0x8600, 0x87AE},
181 /* 32k */
182 {32768, 0x8700, 0x8A3D},
183};
184
185/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
186struct sr_data {
187 u8 multi_filter[SR_MCAST_FILTER_SIZE];
188 u8 mac_addr[ETH_ALEN];
189 u8 phymode;
190 u8 ledmode;
191 u8 eeprom_len;
192};
193
194struct sr9800_int_data {
195 __le16 res1;
196 u8 link;
197 __le16 res2;
198 u8 status;
199 __le16 res3;
200} __packed;
201
202#endif /* _SR9800_H */