1#define RCS_ID "$Id: scc.c,v 1.75 1998/11/04 15:15:01 jreuter Exp jreuter $"
   2
   3#define VERSION "3.0"
   4
   5/*
   6 * Please use z8530drv-utils-3.0 with this version.
   7 *            ------------------
   8 *
   9 * You can find a subset of the documentation in 
  10 * Documentation/networking/device_drivers/hamradio/z8530drv.rst.
  11 */
  12
  13/*
  14   ********************************************************************
  15   *   SCC.C - Linux driver for Z8530 based HDLC cards for AX.25      *
  16   ********************************************************************
  17
  18
  19   ********************************************************************
  20
  21	Copyright (c) 1993, 2000 Joerg Reuter DL1BKE
  22
  23	portions (c) 1993 Guido ten Dolle PE1NNZ
  24
  25   ********************************************************************
  26   
  27   The driver and the programs in the archive are UNDER CONSTRUCTION.
  28   The code is likely to fail, and so your kernel could --- even 
  29   a whole network. 
  30
  31   This driver is intended for Amateur Radio use. If you are running it
  32   for commercial purposes, please drop me a note. I am nosy...
  33
  34   ...BUT:
  35 
  36   ! You  m u s t  recognize the appropriate legislations of your country !
  37   ! before you connect a radio to the SCC board and start to transmit or !
  38   ! receive. The GPL allows you to use the  d r i v e r,  NOT the RADIO! !
  39
  40   For non-Amateur-Radio use please note that you might need a special
  41   allowance/licence from the designer of the SCC Board and/or the
  42   MODEM. 
  43
  44   This program is free software; you can redistribute it and/or modify 
  45   it under the terms of the (modified) GNU General Public License 
  46   delivered with the Linux kernel source.
  47   
  48   This program is distributed in the hope that it will be useful,
  49   but WITHOUT ANY WARRANTY; without even the implied warranty of
  50   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  51   GNU General Public License for more details.
  52
  53   You should find a copy of the GNU General Public License in 
  54   /usr/src/linux/COPYING; 
  55   
  56   ******************************************************************** 
  57
  58		
  59   Incomplete history of z8530drv:
  60   -------------------------------
  61
  62   1994-09-13	started to write the driver, rescued most of my own
  63		code (and Hans Alblas' memory buffer pool concept) from 
  64		an earlier project "sccdrv" which was initiated by 
  65		Guido ten Dolle. Not much of the old driver survived, 
  66		though. The first version I put my hands on was sccdrv1.3
  67		from August 1993. The memory buffer pool concept
  68		appeared in an unauthorized sccdrv version (1.5) from
  69		August 1994.
  70
  71   1995-01-31	changed copyright notice to GPL without limitations.
  72   
  73     .
  74     .	<SNIP>
  75     .
  76   		  
  77   1996-10-05	New semester, new driver... 
  78
  79   		  * KISS TNC emulator removed (TTY driver)
  80   		  * Source moved to drivers/net/
  81   		  * Includes Z8530 defines from drivers/net/z8530.h
  82   		  * Uses sk_buffer memory management
  83   		  * Reduced overhead of /proc/net/z8530drv output
  84   		  * Streamlined quite a lot things
  85   		  * Invents brand new bugs... ;-)
  86
  87   		  The move to version number 3.0 reflects theses changes.
  88   		  You can use 'kissbridge' if you need a KISS TNC emulator.
  89
  90   1996-12-13	Fixed for Linux networking changes. (G4KLX)
  91   1997-01-08	Fixed the remaining problems.
  92   1997-04-02	Hopefully fixed the problems with the new *_timer()
  93   		routines, added calibration code.
  94   1997-10-12	Made SCC_DELAY a CONFIG option, added CONFIG_SCC_TRXECHO
  95   1998-01-29	Small fix to avoid lock-up on initialization
  96   1998-09-29	Fixed the "grouping" bugs, tx_inhibit works again,
  97   		using dev->tx_queue_len now instead of MAXQUEUE now.
  98   1998-10-21	Postponed the spinlock changes, would need a lot of
  99   		testing I currently don't have the time to. Softdcd doesn't
 100   		work.
 101   1998-11-04	Softdcd does not work correctly in DPLL mode, in fact it 
 102   		never did. The DPLL locks on noise, the SYNC unit sees
 103   		flags that aren't... Restarting the DPLL does not help
 104   		either, it resynchronizes too slow and the first received
 105   		frame gets lost.
 106   2000-02-13	Fixed for new network driver interface changes, still
 107   		does TX timeouts itself since it uses its own queue
 108   		scheme.
 109
 110   Thanks to all who contributed to this driver with ideas and bug
 111   reports!
 112   
 113   NB -- if you find errors, change something, please let me know
 114      	 first before you distribute it... And please don't touch
 115   	 the version number. Just replace my callsign in
 116   	 "v3.0.dl1bke" with your own. Just to avoid confusion...
 117
 118   If you want to add your modification to the linux distribution
 119   please (!) contact me first.
 120   
 121   New versions of the driver will be announced on the linux-hams
 122   mailing list on vger.kernel.org. To subscribe send an e-mail
 123   to majordomo@vger.kernel.org with the following line in
 124   the body of the mail:
 125   
 126	   subscribe linux-hams
 127	   
 128   The content of the "Subject" field will be ignored.
 129
 130   vy 73,
 131   Joerg Reuter	ampr-net: dl1bke@db0pra.ampr.org
 132		AX-25   : DL1BKE @ DB0ABH.#BAY.DEU.EU
 133		Internet: jreuter@yaina.de
 134		www     : http://yaina.de/jreuter
 135*/
 136
 137/* ----------------------------------------------------------------------- */
 138
 139#undef  SCC_LDELAY		/* slow it even a bit more down */
 140#undef  SCC_DONT_CHECK		/* don't look if the SCCs you specified are available */
 141
 142#define SCC_MAXCHIPS	4       /* number of max. supported chips */
 143#define SCC_BUFSIZE	384     /* must not exceed 4096 */
 144#undef	SCC_DEBUG
 145
 146#define SCC_DEFAULT_CLOCK	4915200 
 147				/* default pclock if nothing is specified */
 148
 149/* ----------------------------------------------------------------------- */
 150
 151#include <linux/compat.h>
 152#include <linux/module.h>
 153#include <linux/errno.h>
 154#include <linux/signal.h>
 155#include <linux/timer.h>
 156#include <linux/interrupt.h>
 157#include <linux/ioport.h>
 158#include <linux/string.h>
 159#include <linux/in.h>
 160#include <linux/fcntl.h>
 161#include <linux/ptrace.h>
 162#include <linux/delay.h>
 163#include <linux/skbuff.h>
 164#include <linux/netdevice.h>
 165#include <linux/rtnetlink.h>
 166#include <linux/if_ether.h>
 167#include <linux/if_arp.h>
 168#include <linux/socket.h>
 169#include <linux/init.h>
 170#include <linux/scc.h>
 171#include <linux/ctype.h>
 172#include <linux/kernel.h>
 173#include <linux/proc_fs.h>
 174#include <linux/seq_file.h>
 175#include <linux/bitops.h>
 176
 177#include <net/net_namespace.h>
 178#include <net/ax25.h>
 179
 180#include <asm/irq.h>
 181#include <asm/io.h>
 182#include <linux/uaccess.h>
 183
 184#include "z8530.h"
 185
 186static const char banner[] __initconst = KERN_INFO \
 187	"AX.25: Z8530 SCC driver version "VERSION".dl1bke\n";
 188
 189static void t_dwait(struct timer_list *t);
 190static void t_txdelay(struct timer_list *t);
 191static void t_tail(struct timer_list *t);
 192static void t_busy(struct timer_list *);
 193static void t_maxkeyup(struct timer_list *);
 194static void t_idle(struct timer_list *t);
 195static void scc_tx_done(struct scc_channel *);
 196static void scc_start_tx_timer(struct scc_channel *,
 197			       void (*)(struct timer_list *), unsigned long);
 198static void scc_start_maxkeyup(struct scc_channel *);
 199static void scc_start_defer(struct scc_channel *);
 200
 201static void z8530_init(void);
 202
 203static void init_channel(struct scc_channel *scc);
 204static void scc_key_trx (struct scc_channel *scc, char tx);
 205static void scc_init_timer(struct scc_channel *scc);
 206
 207static int scc_net_alloc(const char *name, struct scc_channel *scc);
 208static void scc_net_setup(struct net_device *dev);
 209static int scc_net_open(struct net_device *dev);
 210static int scc_net_close(struct net_device *dev);
 211static void scc_net_rx(struct scc_channel *scc, struct sk_buff *skb);
 212static netdev_tx_t scc_net_tx(struct sk_buff *skb,
 213			      struct net_device *dev);
 214static int scc_net_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
 215				  void __user *data, int cmd);
 216static int scc_net_set_mac_address(struct net_device *dev, void *addr);
 217static struct net_device_stats * scc_net_get_stats(struct net_device *dev);
 218
 219static unsigned char SCC_DriverName[] = "scc";
 220
 221static struct irqflags { unsigned char used : 1; } Ivec[NR_IRQS];
 222	
 223static struct scc_channel SCC_Info[2 * SCC_MAXCHIPS];	/* information per channel */
 224
 225static struct scc_ctrl {
 226	io_port chan_A;
 227	io_port chan_B;
 228	int irq;
 229} SCC_ctrl[SCC_MAXCHIPS+1];
 230
 231static unsigned char Driver_Initialized;
 232static int Nchips;
 233static io_port Vector_Latch;
 234
 235
 236/* ******************************************************************** */
 237/* *			Port Access Functions			      * */
 238/* ******************************************************************** */
 239
 240/* These provide interrupt save 2-step access to the Z8530 registers */
 241
 242static DEFINE_SPINLOCK(iolock);	/* Guards paired accesses */
 243
 244static inline unsigned char InReg(io_port port, unsigned char reg)
 245{
 246	unsigned long flags;
 247	unsigned char r;
 248
 249	spin_lock_irqsave(&iolock, flags);	
 250#ifdef SCC_LDELAY
 251	Outb(port, reg);
 252	udelay(SCC_LDELAY);
 253	r=Inb(port);
 254	udelay(SCC_LDELAY);
 255#else
 256	Outb(port, reg);
 257	r=Inb(port);
 258#endif
 259	spin_unlock_irqrestore(&iolock, flags);
 260	return r;
 261}
 262
 263static inline void OutReg(io_port port, unsigned char reg, unsigned char val)
 264{
 265	unsigned long flags;
 266
 267	spin_lock_irqsave(&iolock, flags);
 268#ifdef SCC_LDELAY
 269	Outb(port, reg); udelay(SCC_LDELAY);
 270	Outb(port, val); udelay(SCC_LDELAY);
 271#else
 272	Outb(port, reg);
 273	Outb(port, val);
 274#endif
 275	spin_unlock_irqrestore(&iolock, flags);
 276}
 277
 278static inline void wr(struct scc_channel *scc, unsigned char reg,
 279	unsigned char val)
 280{
 281	OutReg(scc->ctrl, reg, (scc->wreg[reg] = val));
 282}
 283
 284static inline void or(struct scc_channel *scc, unsigned char reg, unsigned char val)
 285{
 286	OutReg(scc->ctrl, reg, (scc->wreg[reg] |= val));
 287}
 288
 289static inline void cl(struct scc_channel *scc, unsigned char reg, unsigned char val)
 290{
 291	OutReg(scc->ctrl, reg, (scc->wreg[reg] &= ~val));
 292}
 293
 294/* ******************************************************************** */
 295/* *			Some useful macros			      * */
 296/* ******************************************************************** */
 297
 298static inline void scc_discard_buffers(struct scc_channel *scc)
 299{
 300	unsigned long flags;
 301	
 302	spin_lock_irqsave(&scc->lock, flags);	
 303	if (scc->tx_buff != NULL)
 304	{
 305		dev_kfree_skb_irq(scc->tx_buff);
 306		scc->tx_buff = NULL;
 307	}
 308	
 309	while (!skb_queue_empty(&scc->tx_queue))
 310		dev_kfree_skb_irq(skb_dequeue(&scc->tx_queue));
 311
 312	spin_unlock_irqrestore(&scc->lock, flags);
 313}
 314
 315
 316
 317/* ******************************************************************** */
 318/* *			Interrupt Service Routines		      * */
 319/* ******************************************************************** */
 320
 321
 322/* ----> subroutines for the interrupt handlers <---- */
 323
 324static inline void scc_notify(struct scc_channel *scc, int event)
 325{
 326	struct sk_buff *skb;
 327	char *bp;
 328	
 329        if (scc->kiss.fulldup != KISS_DUPLEX_OPTIMA)
 330		return;
 331
 332	skb = dev_alloc_skb(2);
 333	if (skb != NULL)
 334	{
 335		bp = skb_put(skb, 2);
 336		*bp++ = PARAM_HWEVENT;
 337		*bp++ = event;
 338		scc_net_rx(scc, skb);
 339	} else
 340		scc->stat.nospace++;
 341}
 342
 343static inline void flush_rx_FIFO(struct scc_channel *scc)
 344{
 345	int k;
 346	
 347	for (k=0; k<3; k++)
 348		Inb(scc->data);
 349		
 350	if(scc->rx_buff != NULL)		/* did we receive something? */
 351	{
 352		scc->stat.rxerrs++;  /* then count it as an error */
 353		dev_kfree_skb_irq(scc->rx_buff);
 354		scc->rx_buff = NULL;
 355	}
 356}
 357
 358static void start_hunt(struct scc_channel *scc)
 359{
 360	if ((scc->modem.clocksrc != CLK_EXTERNAL))
 361		OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
 362	or(scc,R3,ENT_HM|RxENABLE);  /* enable the receiver, hunt mode */
 363}
 364
 365/* ----> four different interrupt handlers for Tx, Rx, changing of	*/
 366/*       DCD/CTS and Rx/Tx errors					*/
 367
 368/* Transmitter interrupt handler */
 369static inline void scc_txint(struct scc_channel *scc)
 370{
 371	struct sk_buff *skb;
 372
 373	scc->stat.txints++;
 374	skb = scc->tx_buff;
 375	
 376	/* send first octet */
 377	
 378	if (skb == NULL)
 379	{
 380		skb = skb_dequeue(&scc->tx_queue);
 381		scc->tx_buff = skb;
 382		netif_wake_queue(scc->dev);
 383
 384		if (skb == NULL)
 385		{
 386			scc_tx_done(scc);
 387			Outb(scc->ctrl, RES_Tx_P);
 388			return;
 389		}
 390		
 391		if (skb->len == 0)		/* Paranoia... */
 392		{
 393			dev_kfree_skb_irq(skb);
 394			scc->tx_buff = NULL;
 395			scc_tx_done(scc);
 396			Outb(scc->ctrl, RES_Tx_P);
 397			return;
 398		}
 399
 400		scc->stat.tx_state = TXS_ACTIVE;
 401
 402		OutReg(scc->ctrl, R0, RES_Tx_CRC);
 403						/* reset CRC generator */
 404		or(scc,R10,ABUNDER);		/* re-install underrun protection */
 405		Outb(scc->data,*skb->data);	/* send byte */
 406		skb_pull(skb, 1);
 407
 408		if (!scc->enhanced)		/* reset EOM latch */
 409			Outb(scc->ctrl,RES_EOM_L);
 410		return;
 411	}
 412	
 413	/* End Of Frame... */
 414	
 415	if (skb->len == 0)
 416	{
 417		Outb(scc->ctrl, RES_Tx_P);	/* reset pending int */
 418		cl(scc, R10, ABUNDER);		/* send CRC */
 419		dev_kfree_skb_irq(skb);
 420		scc->tx_buff = NULL;
 421		scc->stat.tx_state = TXS_NEWFRAME; /* next frame... */
 422		return;
 423	} 
 424	
 425	/* send octet */
 426	
 427	Outb(scc->data,*skb->data);		
 428	skb_pull(skb, 1);
 429}
 430
 431
 432/* External/Status interrupt handler */
 433static inline void scc_exint(struct scc_channel *scc)
 434{
 435	unsigned char status,changes,chg_and_stat;
 436
 437	scc->stat.exints++;
 438
 439	status = InReg(scc->ctrl,R0);
 440	changes = status ^ scc->status;
 441	chg_and_stat = changes & status;
 442	
 443	/* ABORT: generated whenever DCD drops while receiving */
 444
 445	if (chg_and_stat & BRK_ABRT)		/* Received an ABORT */
 446		flush_rx_FIFO(scc);
 447
 448	/* HUNT: software DCD; on = waiting for SYNC, off = receiving frame */
 449
 450	if ((changes & SYNC_HUNT) && scc->kiss.softdcd)
 451	{
 452		if (status & SYNC_HUNT)
 453		{
 454			scc->dcd = 0;
 455			flush_rx_FIFO(scc);
 456			if ((scc->modem.clocksrc != CLK_EXTERNAL))
 457				OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
 458		} else {
 459			scc->dcd = 1;
 460		}
 461
 462		scc_notify(scc, scc->dcd? HWEV_DCD_OFF:HWEV_DCD_ON);
 463	}
 464
 465	/* DCD: on = start to receive packet, off = ABORT condition */
 466	/* (a successfully received packet generates a special condition int) */
 467	
 468	if((changes & DCD) && !scc->kiss.softdcd) /* DCD input changed state */
 469	{
 470		if(status & DCD)                /* DCD is now ON */
 471		{
 472			start_hunt(scc);
 473			scc->dcd = 1;
 474		} else {                        /* DCD is now OFF */
 475			cl(scc,R3,ENT_HM|RxENABLE); /* disable the receiver */
 476			flush_rx_FIFO(scc);
 477			scc->dcd = 0;
 478		}
 479		
 480		scc_notify(scc, scc->dcd? HWEV_DCD_ON:HWEV_DCD_OFF);
 481	}
 482
 483#ifdef notdef
 484	/* CTS: use external TxDelay (what's that good for?!)
 485	 * Anyway: If we _could_ use it (BayCom USCC uses CTS for
 486	 * own purposes) we _should_ use the "autoenable" feature
 487	 * of the Z8530 and not this interrupt...
 488	 */
 489	 
 490	if (chg_and_stat & CTS)			/* CTS is now ON */
 491	{
 492		if (scc->kiss.txdelay == 0)	/* zero TXDELAY = wait for CTS */
 493			scc_start_tx_timer(scc, t_txdelay, 0);
 494	}
 495#endif
 496	
 497	if (scc->stat.tx_state == TXS_ACTIVE && (status & TxEOM))
 498	{
 499		scc->stat.tx_under++;	  /* oops, an underrun! count 'em */
 500		Outb(scc->ctrl, RES_EXT_INT);	/* reset ext/status interrupts */
 501
 502		if (scc->tx_buff != NULL)
 503		{
 504			dev_kfree_skb_irq(scc->tx_buff);
 505			scc->tx_buff = NULL;
 506		}
 507		
 508		or(scc,R10,ABUNDER);
 509		scc_start_tx_timer(scc, t_txdelay, 0);	/* restart transmission */
 510	}
 511		
 512	scc->status = status;
 513	Outb(scc->ctrl,RES_EXT_INT);
 514}
 515
 516
 517/* Receiver interrupt handler */
 518static inline void scc_rxint(struct scc_channel *scc)
 519{
 520	struct sk_buff *skb;
 521
 522	scc->stat.rxints++;
 523
 524	if((scc->wreg[5] & RTS) && scc->kiss.fulldup == KISS_DUPLEX_HALF)
 525	{
 526		Inb(scc->data);		/* discard char */
 527		or(scc,R3,ENT_HM);	/* enter hunt mode for next flag */
 528		return;
 529	}
 530
 531	skb = scc->rx_buff;
 532	
 533	if (skb == NULL)
 534	{
 535		skb = dev_alloc_skb(scc->stat.bufsize);
 536		if (skb == NULL)
 537		{
 538			scc->dev_stat.rx_dropped++;
 539			scc->stat.nospace++;
 540			Inb(scc->data);
 541			or(scc, R3, ENT_HM);
 542			return;
 543		}
 544		
 545		scc->rx_buff = skb;
 546		skb_put_u8(skb, 0);	/* KISS data */
 547	}
 548	
 549	if (skb->len >= scc->stat.bufsize)
 550	{
 551#ifdef notdef
 552		printk(KERN_DEBUG "z8530drv: oops, scc_rxint() received huge frame...\n");
 553#endif
 554		dev_kfree_skb_irq(skb);
 555		scc->rx_buff = NULL;
 556		Inb(scc->data);
 557		or(scc, R3, ENT_HM);
 558		return;
 559	}
 560
 561	skb_put_u8(skb, Inb(scc->data));
 562}
 563
 564
 565/* Receive Special Condition interrupt handler */
 566static inline void scc_spint(struct scc_channel *scc)
 567{
 568	unsigned char status;
 569	struct sk_buff *skb;
 570
 571	scc->stat.spints++;
 572
 573	status = InReg(scc->ctrl,R1);		/* read receiver status */
 574	
 575	Inb(scc->data);				/* throw away Rx byte */
 576	skb = scc->rx_buff;
 577
 578	if(status & Rx_OVR)			/* receiver overrun */
 579	{
 580		scc->stat.rx_over++;             /* count them */
 581		or(scc,R3,ENT_HM);               /* enter hunt mode for next flag */
 582		
 583		if (skb != NULL) 
 584			dev_kfree_skb_irq(skb);
 585		scc->rx_buff = skb = NULL;
 586	}
 587
 588	if(status & END_FR && skb != NULL)	/* end of frame */
 589	{
 590		/* CRC okay, frame ends on 8 bit boundary and received something ? */
 591		
 592		if (!(status & CRC_ERR) && (status & 0xe) == RES8 && skb->len > 0)
 593		{
 594			/* ignore last received byte (first of the CRC bytes) */
 595			skb_trim(skb, skb->len-1);
 596			scc_net_rx(scc, skb);
 597			scc->rx_buff = NULL;
 598			scc->stat.rxframes++;
 599		} else {				/* a bad frame */
 600			dev_kfree_skb_irq(skb);
 601			scc->rx_buff = NULL;
 602			scc->stat.rxerrs++;
 603		}
 604	} 
 605
 606	Outb(scc->ctrl,ERR_RES);
 607}
 608
 609
 610/* ----> interrupt service routine for the Z8530 <---- */
 611
 612static void scc_isr_dispatch(struct scc_channel *scc, int vector)
 613{
 614	spin_lock(&scc->lock);
 615	switch (vector & VECTOR_MASK)
 616	{
 617		case TXINT: scc_txint(scc); break;
 618		case EXINT: scc_exint(scc); break;
 619		case RXINT: scc_rxint(scc); break;
 620		case SPINT: scc_spint(scc); break;
 621	}
 622	spin_unlock(&scc->lock);
 623}
 624
 625/* If the card has a latch for the interrupt vector (like the PA0HZP card)
 626   use it to get the number of the chip that generated the int.
 627   If not: poll all defined chips.
 628 */
 629
 630#define SCC_IRQTIMEOUT 30000
 631
 632static irqreturn_t scc_isr(int irq, void *dev_id)
 633{
 634	int chip_irq = (long) dev_id;
 635	unsigned char vector;	
 636	struct scc_channel *scc;
 637	struct scc_ctrl *ctrl;
 638	int k;
 639	
 640	if (Vector_Latch)
 641	{
 642	    	for(k=0; k < SCC_IRQTIMEOUT; k++)
 643    		{
 644			Outb(Vector_Latch, 0);      /* Generate INTACK */
 645        
 646			/* Read the vector */
 647			if((vector=Inb(Vector_Latch)) >= 16 * Nchips) break; 
 648			if (vector & 0x01) break;
 649        	 
 650		        scc=&SCC_Info[vector >> 3 ^ 0x01];
 651			if (!scc->dev) break;
 652
 653			scc_isr_dispatch(scc, vector);
 654
 655			OutReg(scc->ctrl,R0,RES_H_IUS);              /* Reset Highest IUS */
 656		}  
 657
 658		if (k == SCC_IRQTIMEOUT)
 659			printk(KERN_WARNING "z8530drv: endless loop in scc_isr()?\n");
 660
 661		return IRQ_HANDLED;
 662	}
 663
 664	/* Find the SCC generating the interrupt by polling all attached SCCs
 665	 * reading RR3A (the interrupt pending register)
 666	 */
 667
 668	ctrl = SCC_ctrl;
 669	while (ctrl->chan_A)
 670	{
 671		if (ctrl->irq != chip_irq)
 672		{
 673			ctrl++;
 674			continue;
 675		}
 676
 677		scc = NULL;
 678		for (k = 0; InReg(ctrl->chan_A,R3) && k < SCC_IRQTIMEOUT; k++)
 679		{
 680			vector=InReg(ctrl->chan_B,R2);	/* Read the vector */
 681			if (vector & 0x01) break; 
 682
 683			scc = &SCC_Info[vector >> 3 ^ 0x01];
 684		        if (!scc->dev) break;
 685
 686			scc_isr_dispatch(scc, vector);
 687		}
 688
 689		if (k == SCC_IRQTIMEOUT)
 690		{
 691			printk(KERN_WARNING "z8530drv: endless loop in scc_isr()?!\n");
 692			break;
 693		}
 694
 695		/* This looks weird and it is. At least the BayCom USCC doesn't
 696		 * use the Interrupt Daisy Chain, thus we'll have to start
 697		 * all over again to be sure not to miss an interrupt from 
 698		 * (any of) the other chip(s)...
 699		 * Honestly, the situation *is* braindamaged...
 700		 */
 701
 702		if (scc != NULL)
 703		{
 704			OutReg(scc->ctrl,R0,RES_H_IUS);
 705			ctrl = SCC_ctrl; 
 706		} else
 707			ctrl++;
 708	}
 709	return IRQ_HANDLED;
 710}
 711
 712
 713
 714/* ******************************************************************** */
 715/* *			Init Channel					*/
 716/* ******************************************************************** */
 717
 718
 719/* ----> set SCC channel speed <---- */
 720
 721static inline void set_brg(struct scc_channel *scc, unsigned int tc)
 722{
 723	cl(scc,R14,BRENABL);		/* disable baudrate generator */
 724	wr(scc,R12,tc & 255);		/* brg rate LOW */
 725	wr(scc,R13,tc >> 8);   		/* brg rate HIGH */
 726	or(scc,R14,BRENABL);		/* enable baudrate generator */
 727}
 728
 729static inline void set_speed(struct scc_channel *scc)
 730{
 731	unsigned long flags;
 732	spin_lock_irqsave(&scc->lock, flags);
 733
 734	if (scc->modem.speed > 0)	/* paranoia... */
 735		set_brg(scc, (unsigned) (scc->clock / (scc->modem.speed * 64)) - 2);
 736		
 737	spin_unlock_irqrestore(&scc->lock, flags);
 738}
 739
 740
 741/* ----> initialize a SCC channel <---- */
 742
 743static inline void init_brg(struct scc_channel *scc)
 744{
 745	wr(scc, R14, BRSRC);				/* BRG source = PCLK */
 746	OutReg(scc->ctrl, R14, SSBR|scc->wreg[R14]);	/* DPLL source = BRG */
 747	OutReg(scc->ctrl, R14, SNRZI|scc->wreg[R14]);	/* DPLL NRZI mode */
 748}
 749
 750/*
 751 * Initialization according to the Z8530 manual (SGS-Thomson's version):
 752 *
 753 * 1. Modes and constants
 754 *
 755 * WR9	11000000	chip reset
 756 * WR4	XXXXXXXX	Tx/Rx control, async or sync mode
 757 * WR1	0XX00X00	select W/REQ (optional)
 758 * WR2	XXXXXXXX	program interrupt vector
 759 * WR3	XXXXXXX0	select Rx control
 760 * WR5	XXXX0XXX	select Tx control
 761 * WR6	XXXXXXXX	sync character
 762 * WR7	XXXXXXXX	sync character
 763 * WR9	000X0XXX	select interrupt control
 764 * WR10	XXXXXXXX	miscellaneous control (optional)
 765 * WR11	XXXXXXXX	clock control
 766 * WR12	XXXXXXXX	time constant lower byte (optional)
 767 * WR13	XXXXXXXX	time constant upper byte (optional)
 768 * WR14	XXXXXXX0	miscellaneous control
 769 * WR14	XXXSSSSS	commands (optional)
 770 *
 771 * 2. Enables
 772 *
 773 * WR14	000SSSS1	baud rate enable
 774 * WR3	SSSSSSS1	Rx enable
 775 * WR5	SSSS1SSS	Tx enable
 776 * WR0	10000000	reset Tx CRG (optional)
 777 * WR1	XSS00S00	DMA enable (optional)
 778 *
 779 * 3. Interrupt status
 780 *
 781 * WR15	XXXXXXXX	enable external/status
 782 * WR0	00010000	reset external status
 783 * WR0	00010000	reset external status twice
 784 * WR1	SSSXXSXX	enable Rx, Tx and Ext/status
 785 * WR9	000SXSSS	enable master interrupt enable
 786 *
 787 * 1 = set to one, 0 = reset to zero
 788 * X = user defined, S = same as previous init
 789 *
 790 *
 791 * Note that the implementation differs in some points from above scheme.
 792 *
 793 */
 794 
 795static void init_channel(struct scc_channel *scc)
 796{
 797	del_timer(&scc->tx_t);
 798	del_timer(&scc->tx_wdog);
 799
 800	disable_irq(scc->irq);
 801
 802	wr(scc,R4,X1CLK|SDLC);		/* *1 clock, SDLC mode */
 803	wr(scc,R1,0);			/* no W/REQ operation */
 804	wr(scc,R3,Rx8|RxCRC_ENAB);	/* RX 8 bits/char, CRC, disabled */	
 805	wr(scc,R5,Tx8|DTR|TxCRC_ENAB);	/* TX 8 bits/char, disabled, DTR */
 806	wr(scc,R6,0);			/* SDLC address zero (not used) */
 807	wr(scc,R7,FLAG);		/* SDLC flag value */
 808	wr(scc,R9,VIS);			/* vector includes status */
 809	wr(scc,R10,(scc->modem.nrz? NRZ : NRZI)|CRCPS|ABUNDER); /* abort on underrun, preset CRC generator, NRZ(I) */
 810	wr(scc,R14, 0);
 811
 812
 813/* set clock sources:
 814
 815   CLK_DPLL: normal halfduplex operation
 816   
 817		RxClk: use DPLL
 818		TxClk: use DPLL
 819		TRxC mode DPLL output
 820		
 821   CLK_EXTERNAL: external clocking (G3RUH or DF9IC modem)
 822   
 823  	        BayCom: 		others:
 824  	        
 825  	        TxClk = pin RTxC	TxClk = pin TRxC
 826  	        RxClk = pin TRxC 	RxClk = pin RTxC
 827  	     
 828
 829   CLK_DIVIDER:
 830   		RxClk = use DPLL
 831   		TxClk = pin RTxC
 832   		
 833   		BayCom:			others:
 834   		pin TRxC = DPLL		pin TRxC = BRG
 835   		(RxClk * 1)		(RxClk * 32)
 836*/  
 837
 838   		
 839	switch(scc->modem.clocksrc)
 840	{
 841		case CLK_DPLL:
 842			wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP);
 843			init_brg(scc);
 844			break;
 845
 846		case CLK_DIVIDER:
 847			wr(scc, R11, ((scc->brand & BAYCOM)? TRxCDP : TRxCBR) | RCDPLL|TCRTxCP|TRxCOI);
 848			init_brg(scc);
 849			break;
 850
 851		case CLK_EXTERNAL:
 852			wr(scc, R11, (scc->brand & BAYCOM)? RCTRxCP|TCRTxCP : RCRTxCP|TCTRxCP);
 853			OutReg(scc->ctrl, R14, DISDPLL);
 854			break;
 855
 856	}
 857	
 858	set_speed(scc);			/* set baudrate */
 859	
 860	if(scc->enhanced)
 861	{
 862		or(scc,R15,SHDLCE|FIFOE);	/* enable FIFO, SDLC/HDLC Enhancements (From now R7 is R7') */
 863		wr(scc,R7,AUTOEOM);
 864	}
 865
 866	if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD))
 867						/* DCD is now ON */
 868	{
 869		start_hunt(scc);
 870	}
 871	
 872	/* enable ABORT, DCD & SYNC/HUNT interrupts */
 873
 874	wr(scc,R15, BRKIE|TxUIE|(scc->kiss.softdcd? SYNCIE:DCDIE));
 875
 876	Outb(scc->ctrl,RES_EXT_INT);	/* reset ext/status interrupts */
 877	Outb(scc->ctrl,RES_EXT_INT);	/* must be done twice */
 878
 879	or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */
 880	
 881	scc->status = InReg(scc->ctrl,R0);	/* read initial status */
 882	
 883	or(scc,R9,MIE);			/* master interrupt enable */
 884	
 885	scc_init_timer(scc);
 886			
 887	enable_irq(scc->irq);
 888}
 889
 890
 891
 892
 893/* ******************************************************************** */
 894/* *			SCC timer functions			      * */
 895/* ******************************************************************** */
 896
 897
 898/* ----> scc_key_trx sets the time constant for the baudrate 
 899         generator and keys the transmitter		     <---- */
 900
 901static void scc_key_trx(struct scc_channel *scc, char tx)
 902{
 903	unsigned int time_const;
 904		
 905	if (scc->brand & PRIMUS)
 906		Outb(scc->ctrl + 4, scc->option | (tx? 0x80 : 0));
 907
 908	if (scc->modem.speed < 300) 
 909		scc->modem.speed = 1200;
 910
 911	time_const = (unsigned) (scc->clock / (scc->modem.speed * (tx? 2:64))) - 2;
 912
 913	disable_irq(scc->irq);
 914
 915	if (tx)
 916	{
 917		or(scc, R1, TxINT_ENAB);	/* t_maxkeyup may have reset these */
 918		or(scc, R15, TxUIE);
 919	}
 920
 921	if (scc->modem.clocksrc == CLK_DPLL)
 922	{				/* force simplex operation */
 923		if (tx)
 924		{
 925#ifdef CONFIG_SCC_TRXECHO
 926			cl(scc, R3, RxENABLE|ENT_HM);	/* switch off receiver */
 927			cl(scc, R15, DCDIE|SYNCIE);	/* No DCD changes, please */
 928#endif
 929			set_brg(scc, time_const);	/* reprogram baudrate generator */
 930
 931			/* DPLL -> Rx clk, BRG -> Tx CLK, TRxC mode output, TRxC = BRG */
 932			wr(scc, R11, RCDPLL|TCBR|TRxCOI|TRxCBR);
 933			
 934			/* By popular demand: tx_inhibit */
 935			if (scc->kiss.tx_inhibit)
 936			{
 937				or(scc,R5, TxENAB);
 938				scc->wreg[R5] |= RTS;
 939			} else {
 940				or(scc,R5,RTS|TxENAB);	/* set the RTS line and enable TX */
 941			}
 942		} else {
 943			cl(scc,R5,RTS|TxENAB);
 944			
 945			set_brg(scc, time_const);	/* reprogram baudrate generator */
 946			
 947			/* DPLL -> Rx clk, DPLL -> Tx CLK, TRxC mode output, TRxC = DPLL */
 948			wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP);
 949
 950#ifndef CONFIG_SCC_TRXECHO
 951			if (scc->kiss.softdcd)
 952#endif
 953			{
 954				or(scc,R15, scc->kiss.softdcd? SYNCIE:DCDIE);
 955				start_hunt(scc);
 956			}
 957		}
 958	} else {
 959		if (tx)
 960		{
 961#ifdef CONFIG_SCC_TRXECHO
 962			if (scc->kiss.fulldup == KISS_DUPLEX_HALF)
 963			{
 964				cl(scc, R3, RxENABLE);
 965				cl(scc, R15, DCDIE|SYNCIE);
 966			}
 967#endif
 968				
 969			if (scc->kiss.tx_inhibit)
 970			{
 971				or(scc,R5, TxENAB);
 972				scc->wreg[R5] |= RTS;
 973			} else {	
 974				or(scc,R5,RTS|TxENAB);	/* enable tx */
 975			}
 976		} else {
 977			cl(scc,R5,RTS|TxENAB);		/* disable tx */
 978
 979			if ((scc->kiss.fulldup == KISS_DUPLEX_HALF) &&
 980#ifndef CONFIG_SCC_TRXECHO
 981			    scc->kiss.softdcd)
 982#else
 983			    1)
 984#endif
 985			{
 986				or(scc, R15, scc->kiss.softdcd? SYNCIE:DCDIE);
 987				start_hunt(scc);
 988			}
 989		}
 990	}
 991
 992	enable_irq(scc->irq);
 993}
 994
 995
 996/* ----> SCC timer interrupt handler and friends. <---- */
 997
 998static void __scc_start_tx_timer(struct scc_channel *scc,
 999				 void (*handler)(struct timer_list *t),
1000				 unsigned long when)
1001{
1002	del_timer(&scc->tx_t);
1003
1004	if (when == 0)
1005	{
1006		handler(&scc->tx_t);
1007	} else 
1008	if (when != TIMER_OFF)
1009	{
 
1010		scc->tx_t.function = handler;
1011		scc->tx_t.expires = jiffies + (when*HZ)/100;
1012		add_timer(&scc->tx_t);
1013	}
1014}
1015
1016static void scc_start_tx_timer(struct scc_channel *scc,
1017			       void (*handler)(struct timer_list *t),
1018			       unsigned long when)
1019{
1020	unsigned long flags;
1021	
1022	spin_lock_irqsave(&scc->lock, flags);
1023	__scc_start_tx_timer(scc, handler, when);
1024	spin_unlock_irqrestore(&scc->lock, flags);
1025}
1026
1027static void scc_start_defer(struct scc_channel *scc)
1028{
1029	unsigned long flags;
1030	
1031	spin_lock_irqsave(&scc->lock, flags);
1032	del_timer(&scc->tx_wdog);
1033	
1034	if (scc->kiss.maxdefer != 0 && scc->kiss.maxdefer != TIMER_OFF)
1035	{
 
1036		scc->tx_wdog.function = t_busy;
1037		scc->tx_wdog.expires = jiffies + HZ*scc->kiss.maxdefer;
1038		add_timer(&scc->tx_wdog);
1039	}
1040	spin_unlock_irqrestore(&scc->lock, flags);
1041}
1042
1043static void scc_start_maxkeyup(struct scc_channel *scc)
1044{
1045	unsigned long flags;
1046	
1047	spin_lock_irqsave(&scc->lock, flags);
1048	del_timer(&scc->tx_wdog);
1049	
1050	if (scc->kiss.maxkeyup != 0 && scc->kiss.maxkeyup != TIMER_OFF)
1051	{
 
1052		scc->tx_wdog.function = t_maxkeyup;
1053		scc->tx_wdog.expires = jiffies + HZ*scc->kiss.maxkeyup;
1054		add_timer(&scc->tx_wdog);
1055	}
1056	spin_unlock_irqrestore(&scc->lock, flags);
1057}
1058
1059/* 
1060 * This is called from scc_txint() when there are no more frames to send.
1061 * Not exactly a timer function, but it is a close friend of the family...
1062 */
1063
1064static void scc_tx_done(struct scc_channel *scc)
1065{
1066	/* 
1067	 * trx remains keyed in fulldup mode 2 until t_idle expires.
1068	 */
1069				 
1070	switch (scc->kiss.fulldup)
1071	{
1072		case KISS_DUPLEX_LINK:
1073			scc->stat.tx_state = TXS_IDLE2;
1074			if (scc->kiss.idletime != TIMER_OFF)
1075				scc_start_tx_timer(scc, t_idle,
1076						   scc->kiss.idletime*100);
1077			break;
1078		case KISS_DUPLEX_OPTIMA:
1079			scc_notify(scc, HWEV_ALL_SENT);
1080			break;
1081		default:
1082			scc->stat.tx_state = TXS_BUSY;
1083			scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime);
1084	}
1085
1086	netif_wake_queue(scc->dev);
1087}
1088
1089
1090static unsigned char Rand = 17;
1091
1092static inline int is_grouped(struct scc_channel *scc)
1093{
1094	int k;
1095	struct scc_channel *scc2;
1096	unsigned char grp1, grp2;
1097
1098	grp1 = scc->kiss.group;
1099	
1100	for (k = 0; k < (Nchips * 2); k++)
1101	{
1102		scc2 = &SCC_Info[k];
1103		grp2 = scc2->kiss.group;
1104		
1105		if (scc2 == scc || !(scc2->dev && grp2))
1106			continue;
1107		
1108		if ((grp1 & 0x3f) == (grp2 & 0x3f))
1109		{
1110			if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) )
1111				return 1;
1112			
1113			if ( (grp1 & RXGROUP) && scc2->dcd )
1114				return 1;
1115		}
1116	}
1117	return 0;
1118}
1119
1120/* DWAIT and SLOTTIME expired
1121 *
1122 * fulldup == 0:  DCD is active or Rand > P-persistence: start t_busy timer
1123 *                else key trx and start txdelay
1124 * fulldup == 1:  key trx and start txdelay
1125 * fulldup == 2:  mintime expired, reset status or key trx and start txdelay
1126 */
1127
1128static void t_dwait(struct timer_list *t)
1129{
1130	struct scc_channel *scc = from_timer(scc, t, tx_t);
1131	
1132	if (scc->stat.tx_state == TXS_WAIT)	/* maxkeyup or idle timeout */
1133	{
1134		if (skb_queue_empty(&scc->tx_queue)) {	/* nothing to send */
1135			scc->stat.tx_state = TXS_IDLE;
1136			netif_wake_queue(scc->dev);	/* t_maxkeyup locked it. */
1137			return;
1138		}
1139
1140		scc->stat.tx_state = TXS_BUSY;
1141	}
1142
1143	if (scc->kiss.fulldup == KISS_DUPLEX_HALF)
1144	{
1145		Rand = Rand * 17 + 31;
1146		
1147		if (scc->dcd || (scc->kiss.persist) < Rand || (scc->kiss.group && is_grouped(scc)) )
1148		{
1149			scc_start_defer(scc);
1150			scc_start_tx_timer(scc, t_dwait, scc->kiss.slottime);
1151			return ;
1152		}
1153	}
1154
1155	if ( !(scc->wreg[R5] & RTS) )
1156	{
1157		scc_key_trx(scc, TX_ON);
1158		scc_start_tx_timer(scc, t_txdelay, scc->kiss.txdelay);
1159	} else {
1160		scc_start_tx_timer(scc, t_txdelay, 0);
1161	}
1162}
1163
1164
1165/* TXDELAY expired
1166 *
1167 * kick transmission by a fake scc_txint(scc), start 'maxkeyup' watchdog.
1168 */
1169
1170static void t_txdelay(struct timer_list *t)
1171{
1172	struct scc_channel *scc = from_timer(scc, t, tx_t);
1173
1174	scc_start_maxkeyup(scc);
1175
1176	if (scc->tx_buff == NULL)
1177	{
1178		disable_irq(scc->irq);
1179		scc_txint(scc);	
1180		enable_irq(scc->irq);
1181	}
1182}
1183	
1184
1185/* TAILTIME expired
1186 *
1187 * switch off transmitter. If we were stopped by Maxkeyup restart
1188 * transmission after 'mintime' seconds
1189 */
1190
1191static void t_tail(struct timer_list *t)
1192{
1193	struct scc_channel *scc = from_timer(scc, t, tx_t);
1194	unsigned long flags;
1195	
1196	spin_lock_irqsave(&scc->lock, flags); 
1197	del_timer(&scc->tx_wdog);
1198	scc_key_trx(scc, TX_OFF);
1199	spin_unlock_irqrestore(&scc->lock, flags);
1200
1201	if (scc->stat.tx_state == TXS_TIMEOUT)		/* we had a timeout? */
1202	{
1203		scc->stat.tx_state = TXS_WAIT;
1204		scc_start_tx_timer(scc, t_dwait, scc->kiss.mintime*100);
1205		return;
1206	}
1207
1208	scc->stat.tx_state = TXS_IDLE;
1209	netif_wake_queue(scc->dev);
1210}
1211
1212
1213/* BUSY timeout
1214 *
1215 * throw away send buffers if DCD remains active too long.
1216 */
1217
1218static void t_busy(struct timer_list *t)
1219{
1220	struct scc_channel *scc = from_timer(scc, t, tx_wdog);
1221
1222	del_timer(&scc->tx_t);
1223	netif_stop_queue(scc->dev);	/* don't pile on the wabbit! */
1224
1225	scc_discard_buffers(scc);
1226	scc->stat.txerrs++;
1227	scc->stat.tx_state = TXS_IDLE;
1228
1229	netif_wake_queue(scc->dev);	
1230}
1231
1232/* MAXKEYUP timeout
1233 *
1234 * this is our watchdog.
1235 */
1236
1237static void t_maxkeyup(struct timer_list *t)
1238{
1239	struct scc_channel *scc = from_timer(scc, t, tx_wdog);
1240	unsigned long flags;
1241
1242	spin_lock_irqsave(&scc->lock, flags);
1243	/* 
1244	 * let things settle down before we start to
1245	 * accept new data.
1246	 */
1247
1248	netif_stop_queue(scc->dev);
1249	scc_discard_buffers(scc);
1250
1251	del_timer(&scc->tx_t);
1252
1253	cl(scc, R1, TxINT_ENAB);	/* force an ABORT, but don't */
1254	cl(scc, R15, TxUIE);		/* count it. */
1255	OutReg(scc->ctrl, R0, RES_Tx_P);
1256
1257	spin_unlock_irqrestore(&scc->lock, flags);
1258
1259	scc->stat.txerrs++;
1260	scc->stat.tx_state = TXS_TIMEOUT;
1261	scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime);
1262}
1263
1264/* IDLE timeout
1265 *
1266 * in fulldup mode 2 it keys down the transmitter after 'idle' seconds
1267 * of inactivity. We will not restart transmission before 'mintime'
1268 * expires.
1269 */
1270
1271static void t_idle(struct timer_list *t)
1272{
1273	struct scc_channel *scc = from_timer(scc, t, tx_t);
1274	
1275	del_timer(&scc->tx_wdog);
1276
1277	scc_key_trx(scc, TX_OFF);
1278	if(scc->kiss.mintime)
1279		scc_start_tx_timer(scc, t_dwait, scc->kiss.mintime*100);
1280	scc->stat.tx_state = TXS_WAIT;
1281}
1282
1283static void scc_init_timer(struct scc_channel *scc)
1284{
1285	unsigned long flags;
1286
1287	spin_lock_irqsave(&scc->lock, flags);	
1288	scc->stat.tx_state = TXS_IDLE;
1289	spin_unlock_irqrestore(&scc->lock, flags);
1290}
1291
1292
1293/* ******************************************************************** */
1294/* *			Set/get L1 parameters			      * */
1295/* ******************************************************************** */
1296
1297
1298/*
1299 * this will set the "hardware" parameters through KISS commands or ioctl()
1300 */
1301
1302#define CAST(x) (unsigned long)(x)
1303
1304static unsigned int scc_set_param(struct scc_channel *scc, unsigned int cmd, unsigned int arg)
1305{
1306	switch (cmd)
1307	{
1308		case PARAM_TXDELAY:	scc->kiss.txdelay=arg;		break;
1309		case PARAM_PERSIST:	scc->kiss.persist=arg;		break;
1310		case PARAM_SLOTTIME:	scc->kiss.slottime=arg;		break;
1311		case PARAM_TXTAIL:	scc->kiss.tailtime=arg;		break;
1312		case PARAM_FULLDUP:	scc->kiss.fulldup=arg;		break;
1313		case PARAM_DTR:		break; /* does someone need this? */
1314		case PARAM_GROUP:	scc->kiss.group=arg;		break;
1315		case PARAM_IDLE:	scc->kiss.idletime=arg;		break;
1316		case PARAM_MIN:		scc->kiss.mintime=arg;		break;
1317		case PARAM_MAXKEY:	scc->kiss.maxkeyup=arg;		break;
1318		case PARAM_WAIT:	scc->kiss.waittime=arg;		break;
1319		case PARAM_MAXDEFER:	scc->kiss.maxdefer=arg;		break;
1320		case PARAM_TX:		scc->kiss.tx_inhibit=arg;	break;
1321
1322		case PARAM_SOFTDCD:	
1323			scc->kiss.softdcd=arg;
1324			if (arg)
1325			{
1326				or(scc, R15, SYNCIE);
1327				cl(scc, R15, DCDIE);
1328				start_hunt(scc);
1329			} else {
1330				or(scc, R15, DCDIE);
1331				cl(scc, R15, SYNCIE);
1332			}
1333			break;
1334				
1335		case PARAM_SPEED:
1336			if (arg < 256)
1337				scc->modem.speed=arg*100;
1338			else
1339				scc->modem.speed=arg;
1340
1341			if (scc->stat.tx_state == 0)	/* only switch baudrate on rx... ;-) */
1342				set_speed(scc);
1343			break;
1344			
1345		case PARAM_RTS:	
1346			if ( !(scc->wreg[R5] & RTS) )
1347			{
1348				if (arg != TX_OFF) {
1349					scc_key_trx(scc, TX_ON);
1350					scc_start_tx_timer(scc, t_txdelay, scc->kiss.txdelay);
1351				}
1352			} else {
1353				if (arg == TX_OFF)
1354				{
1355					scc->stat.tx_state = TXS_BUSY;
1356					scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime);
1357				}
1358			}
1359			break;
1360			
1361		case PARAM_HWEVENT:
1362			scc_notify(scc, scc->dcd? HWEV_DCD_ON:HWEV_DCD_OFF);
1363			break;
1364
1365		default:		return -EINVAL;
1366	}
1367	
1368	return 0;
1369}
1370
1371
1372 
1373static unsigned long scc_get_param(struct scc_channel *scc, unsigned int cmd)
1374{
1375	switch (cmd)
1376	{
1377		case PARAM_TXDELAY:	return CAST(scc->kiss.txdelay);
1378		case PARAM_PERSIST:	return CAST(scc->kiss.persist);
1379		case PARAM_SLOTTIME:	return CAST(scc->kiss.slottime);
1380		case PARAM_TXTAIL:	return CAST(scc->kiss.tailtime);
1381		case PARAM_FULLDUP:	return CAST(scc->kiss.fulldup);
1382		case PARAM_SOFTDCD:	return CAST(scc->kiss.softdcd);
1383		case PARAM_DTR:		return CAST((scc->wreg[R5] & DTR)? 1:0);
1384		case PARAM_RTS:		return CAST((scc->wreg[R5] & RTS)? 1:0);
1385		case PARAM_SPEED:	return CAST(scc->modem.speed);
1386		case PARAM_GROUP:	return CAST(scc->kiss.group);
1387		case PARAM_IDLE:	return CAST(scc->kiss.idletime);
1388		case PARAM_MIN:		return CAST(scc->kiss.mintime);
1389		case PARAM_MAXKEY:	return CAST(scc->kiss.maxkeyup);
1390		case PARAM_WAIT:	return CAST(scc->kiss.waittime);
1391		case PARAM_MAXDEFER:	return CAST(scc->kiss.maxdefer);
1392		case PARAM_TX:		return CAST(scc->kiss.tx_inhibit);
1393		default:		return NO_SUCH_PARAM;
1394	}
1395
1396}
1397
1398#undef CAST
1399
1400/* ******************************************************************* */
1401/* *			Send calibration pattern		     * */
1402/* ******************************************************************* */
1403
1404static void scc_stop_calibrate(struct timer_list *t)
1405{
1406	struct scc_channel *scc = from_timer(scc, t, tx_wdog);
1407	unsigned long flags;
1408	
1409	spin_lock_irqsave(&scc->lock, flags);
1410	del_timer(&scc->tx_wdog);
1411	scc_key_trx(scc, TX_OFF);
1412	wr(scc, R6, 0);
1413	wr(scc, R7, FLAG);
1414	Outb(scc->ctrl,RES_EXT_INT);	/* reset ext/status interrupts */
1415	Outb(scc->ctrl,RES_EXT_INT);
1416
1417	netif_wake_queue(scc->dev);
1418	spin_unlock_irqrestore(&scc->lock, flags);
1419}
1420
1421
1422static void
1423scc_start_calibrate(struct scc_channel *scc, int duration, unsigned char pattern)
1424{
1425	unsigned long flags;
1426	
1427	spin_lock_irqsave(&scc->lock, flags);
1428	netif_stop_queue(scc->dev);
1429	scc_discard_buffers(scc);
1430
1431	del_timer(&scc->tx_wdog);
1432
 
1433	scc->tx_wdog.function = scc_stop_calibrate;
1434	scc->tx_wdog.expires = jiffies + HZ*duration;
1435	add_timer(&scc->tx_wdog);
1436
1437	/* This doesn't seem to work. Why not? */	
1438	wr(scc, R6, 0);
1439	wr(scc, R7, pattern);
1440
1441	/* 
1442	 * Don't know if this works. 
1443	 * Damn, where is my Z8530 programming manual...? 
1444	 */
1445
1446	Outb(scc->ctrl,RES_EXT_INT);	/* reset ext/status interrupts */
1447	Outb(scc->ctrl,RES_EXT_INT);
1448
1449	scc_key_trx(scc, TX_ON);
1450	spin_unlock_irqrestore(&scc->lock, flags);
1451}
1452
1453/* ******************************************************************* */
1454/* *		Init channel structures, special HW, etc...	     * */
1455/* ******************************************************************* */
1456
1457/*
1458 * Reset the Z8530s and setup special hardware
1459 */
1460
1461static void z8530_init(void)
1462{
1463	struct scc_channel *scc;
1464	int chip, k;
1465	unsigned long flags;
1466	char *flag;
1467
1468
1469	printk(KERN_INFO "Init Z8530 driver: %u channels, IRQ", Nchips*2);
1470	
1471	flag=" ";
1472	for (k = 0; k < nr_irqs; k++)
1473		if (Ivec[k].used) 
1474		{
1475			printk("%s%d", flag, k);
1476			flag=",";
1477		}
1478	printk("\n");
1479
1480
1481	/* reset and pre-init all chips in the system */
1482	for (chip = 0; chip < Nchips; chip++)
1483	{
1484		scc=&SCC_Info[2*chip];
1485		if (!scc->ctrl) continue;
1486
1487		/* Special SCC cards */
1488
1489		if(scc->brand & EAGLE)			/* this is an EAGLE card */
1490			Outb(scc->special,0x08);	/* enable interrupt on the board */
1491			
1492		if(scc->brand & (PC100 | PRIMUS))	/* this is a PC100/PRIMUS card */
1493			Outb(scc->special,scc->option);	/* set the MODEM mode (0x22) */
1494
1495			
1496		/* Reset and pre-init Z8530 */
1497
1498		spin_lock_irqsave(&scc->lock, flags);
1499				
1500		Outb(scc->ctrl, 0);
1501		OutReg(scc->ctrl,R9,FHWRES);		/* force hardware reset */
1502		udelay(100);				/* give it 'a bit' more time than required */
1503		wr(scc, R2, chip*16);			/* interrupt vector */
1504		wr(scc, R9, VIS);			/* vector includes status */
1505		spin_unlock_irqrestore(&scc->lock, flags);		
1506        }
1507
1508 
1509	Driver_Initialized = 1;
1510}
1511
1512/*
1513 * Allocate device structure, err, instance, and register driver
1514 */
1515
1516static int scc_net_alloc(const char *name, struct scc_channel *scc)
1517{
1518	int err;
1519	struct net_device *dev;
1520
1521	dev = alloc_netdev(0, name, NET_NAME_UNKNOWN, scc_net_setup);
1522	if (!dev) 
1523		return -ENOMEM;
1524
1525	dev->ml_priv = scc;
1526	scc->dev = dev;
1527	spin_lock_init(&scc->lock);
1528	timer_setup(&scc->tx_t, NULL, 0);
1529	timer_setup(&scc->tx_wdog, NULL, 0);
1530
1531	err = register_netdevice(dev);
1532	if (err) {
1533		printk(KERN_ERR "%s: can't register network device (%d)\n", 
1534		       name, err);
1535		free_netdev(dev);
1536		scc->dev = NULL;
1537		return err;
1538	}
1539
1540	return 0;
1541}
1542
1543
1544
1545/* ******************************************************************** */
1546/* *			    Network driver methods		      * */
1547/* ******************************************************************** */
1548
1549static const struct net_device_ops scc_netdev_ops = {
1550	.ndo_open            = scc_net_open,
1551	.ndo_stop	     = scc_net_close,
1552	.ndo_start_xmit	     = scc_net_tx,
1553	.ndo_set_mac_address = scc_net_set_mac_address,
1554	.ndo_get_stats       = scc_net_get_stats,
1555	.ndo_siocdevprivate  = scc_net_siocdevprivate,
1556};
1557
1558/* ----> Initialize device <----- */
1559
1560static void scc_net_setup(struct net_device *dev)
1561{
1562	dev->tx_queue_len    = 16;	/* should be enough... */
1563
1564	dev->netdev_ops	     = &scc_netdev_ops;
1565	dev->header_ops      = &ax25_header_ops;
1566
 
 
 
1567	dev->flags      = 0;
1568
1569	dev->type = ARPHRD_AX25;
1570	dev->hard_header_len = AX25_MAX_HEADER_LEN + AX25_BPQ_HEADER_LEN;
1571	dev->mtu = AX25_DEF_PACLEN;
1572	dev->addr_len = AX25_ADDR_LEN;
1573
1574	memcpy(dev->broadcast, &ax25_bcast,  AX25_ADDR_LEN);
1575	dev_addr_set(dev, (u8 *)&ax25_defaddr);
1576}
1577
1578/* ----> open network device <---- */
1579
1580static int scc_net_open(struct net_device *dev)
1581{
1582	struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
1583
1584	if (!scc->init)
1585		return -EINVAL;
1586
1587	scc->tx_buff = NULL;
1588	skb_queue_head_init(&scc->tx_queue);
1589 
1590	init_channel(scc);
1591
1592	netif_start_queue(dev);
1593	return 0;
1594}
1595
1596/* ----> close network device <---- */
1597
1598static int scc_net_close(struct net_device *dev)
1599{
1600	struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
1601	unsigned long flags;
1602
1603	netif_stop_queue(dev);
1604
1605	spin_lock_irqsave(&scc->lock, flags);	
1606	Outb(scc->ctrl,0);		/* Make sure pointer is written */
1607	wr(scc,R1,0);			/* disable interrupts */
1608	wr(scc,R3,0);
1609	spin_unlock_irqrestore(&scc->lock, flags);
1610
1611	del_timer_sync(&scc->tx_t);
1612	del_timer_sync(&scc->tx_wdog);
1613	
1614	scc_discard_buffers(scc);
1615
1616	return 0;
1617}
1618
1619/* ----> receive frame, called from scc_rxint() <---- */
1620
1621static void scc_net_rx(struct scc_channel *scc, struct sk_buff *skb)
1622{
1623	if (skb->len == 0) {
1624		dev_kfree_skb_irq(skb);
1625		return;
1626	}
1627		
1628	scc->dev_stat.rx_packets++;
1629	scc->dev_stat.rx_bytes += skb->len;
1630
1631	skb->protocol = ax25_type_trans(skb, scc->dev);
1632	
1633	netif_rx(skb);
1634}
1635
1636/* ----> transmit frame <---- */
1637
1638static netdev_tx_t scc_net_tx(struct sk_buff *skb, struct net_device *dev)
1639{
1640	struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
1641	unsigned long flags;
1642	char kisscmd;
1643
1644	if (skb->protocol == htons(ETH_P_IP))
1645		return ax25_ip_xmit(skb);
1646
1647	if (skb->len > scc->stat.bufsize || skb->len < 2) {
1648		scc->dev_stat.tx_dropped++;	/* bogus frame */
1649		dev_kfree_skb(skb);
1650		return NETDEV_TX_OK;
1651	}
1652	
1653	scc->dev_stat.tx_packets++;
1654	scc->dev_stat.tx_bytes += skb->len;
1655	scc->stat.txframes++;
1656	
1657	kisscmd = *skb->data & 0x1f;
1658	skb_pull(skb, 1);
1659
1660	if (kisscmd) {
1661		scc_set_param(scc, kisscmd, *skb->data);
1662		dev_kfree_skb(skb);
1663		return NETDEV_TX_OK;
1664	}
1665
1666	spin_lock_irqsave(&scc->lock, flags);
1667		
1668	if (skb_queue_len(&scc->tx_queue) > scc->dev->tx_queue_len) {
1669		struct sk_buff *skb_del;
1670		skb_del = skb_dequeue(&scc->tx_queue);
1671		dev_kfree_skb_irq(skb_del);
1672	}
1673	skb_queue_tail(&scc->tx_queue, skb);
1674	netif_trans_update(dev);
1675	
1676
1677	/*
1678	 * Start transmission if the trx state is idle or
1679	 * t_idle hasn't expired yet. Use dwait/persistence/slottime
1680	 * algorithm for normal halfduplex operation.
1681	 */
1682
1683	if(scc->stat.tx_state == TXS_IDLE || scc->stat.tx_state == TXS_IDLE2) {
1684		scc->stat.tx_state = TXS_BUSY;
1685		if (scc->kiss.fulldup == KISS_DUPLEX_HALF)
1686			__scc_start_tx_timer(scc, t_dwait, scc->kiss.waittime);
1687		else
1688			__scc_start_tx_timer(scc, t_dwait, 0);
1689	}
1690	spin_unlock_irqrestore(&scc->lock, flags);
1691	return NETDEV_TX_OK;
1692}
1693
1694/* ----> ioctl functions <---- */
1695
1696/*
1697 * SIOCSCCCFG		- configure driver	arg: (struct scc_hw_config *) arg
1698 * SIOCSCCINI		- initialize driver	arg: ---
1699 * SIOCSCCCHANINI	- initialize channel	arg: (struct scc_modem *) arg
1700 * SIOCSCCSMEM		- set memory		arg: (struct scc_mem_config *) arg
1701 * SIOCSCCGKISS		- get level 1 parameter	arg: (struct scc_kiss_cmd *) arg
1702 * SIOCSCCSKISS		- set level 1 parameter arg: (struct scc_kiss_cmd *) arg
1703 * SIOCSCCGSTAT		- get driver status	arg: (struct scc_stat *) arg
1704 * SIOCSCCCAL		- send calib. pattern	arg: (struct scc_calibrate *) arg
1705 */
1706
1707static int scc_net_siocdevprivate(struct net_device *dev,
1708				  struct ifreq *ifr, void __user *arg, int cmd)
1709{
1710	struct scc_kiss_cmd kiss_cmd;
1711	struct scc_mem_config memcfg;
1712	struct scc_hw_config hwcfg;
1713	struct scc_calibrate cal;
1714	struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
1715	int chan;
1716	unsigned char device_name[IFNAMSIZ];
 
 
1717	
1718	if (!Driver_Initialized)
1719	{
1720		if (cmd == SIOCSCCCFG)
1721		{
1722			int found = 1;
1723
1724			if (!capable(CAP_SYS_RAWIO)) return -EPERM;
1725			if (in_compat_syscall())
1726				return -EOPNOTSUPP;
1727
1728			if (!arg) return -EFAULT;
1729
1730			if (Nchips >= SCC_MAXCHIPS) 
1731				return -EINVAL;
1732
1733			if (copy_from_user(&hwcfg, arg, sizeof(hwcfg)))
1734				return -EFAULT;
1735
1736			if (hwcfg.irq == 2) hwcfg.irq = 9;
1737
1738			if (hwcfg.irq < 0 || hwcfg.irq >= nr_irqs)
1739				return -EINVAL;
1740				
1741			if (!Ivec[hwcfg.irq].used && hwcfg.irq)
1742			{
1743				if (request_irq(hwcfg.irq, scc_isr,
1744						0, "AX.25 SCC",
1745						(void *)(long) hwcfg.irq))
1746					printk(KERN_WARNING "z8530drv: warning, cannot get IRQ %d\n", hwcfg.irq);
1747				else
1748					Ivec[hwcfg.irq].used = 1;
1749			}
1750
1751			if (hwcfg.vector_latch && !Vector_Latch) {
1752				if (!request_region(hwcfg.vector_latch, 1, "scc vector latch"))
1753					printk(KERN_WARNING "z8530drv: warning, cannot reserve vector latch port 0x%lx\n, disabled.", hwcfg.vector_latch);
1754				else
1755					Vector_Latch = hwcfg.vector_latch;
1756			}
1757
1758			if (hwcfg.clock == 0)
1759				hwcfg.clock = SCC_DEFAULT_CLOCK;
1760
1761#ifndef SCC_DONT_CHECK
1762
1763			if(request_region(hwcfg.ctrl_a, 1, "scc-probe"))
1764			{
1765				disable_irq(hwcfg.irq);
1766				Outb(hwcfg.ctrl_a, 0);
1767				OutReg(hwcfg.ctrl_a, R9, FHWRES);
1768				udelay(100);
1769				OutReg(hwcfg.ctrl_a,R13,0x55);		/* is this chip really there? */
1770				udelay(5);
1771
1772				if (InReg(hwcfg.ctrl_a,R13) != 0x55)
1773					found = 0;
1774				enable_irq(hwcfg.irq);
1775				release_region(hwcfg.ctrl_a, 1);
1776			}
1777			else
1778				found = 0;
1779#endif
1780
1781			if (found)
1782			{
1783				SCC_Info[2*Nchips  ].ctrl = hwcfg.ctrl_a;
1784				SCC_Info[2*Nchips  ].data = hwcfg.data_a;
1785				SCC_Info[2*Nchips  ].irq  = hwcfg.irq;
1786				SCC_Info[2*Nchips+1].ctrl = hwcfg.ctrl_b;
1787				SCC_Info[2*Nchips+1].data = hwcfg.data_b;
1788				SCC_Info[2*Nchips+1].irq  = hwcfg.irq;
1789			
1790				SCC_ctrl[Nchips].chan_A = hwcfg.ctrl_a;
1791				SCC_ctrl[Nchips].chan_B = hwcfg.ctrl_b;
1792				SCC_ctrl[Nchips].irq    = hwcfg.irq;
1793			}
1794
1795
1796			for (chan = 0; chan < 2; chan++)
1797			{
1798				sprintf(device_name, "%s%i", SCC_DriverName, 2*Nchips+chan);
1799
1800				SCC_Info[2*Nchips+chan].special = hwcfg.special;
1801				SCC_Info[2*Nchips+chan].clock = hwcfg.clock;
1802				SCC_Info[2*Nchips+chan].brand = hwcfg.brand;
1803				SCC_Info[2*Nchips+chan].option = hwcfg.option;
1804				SCC_Info[2*Nchips+chan].enhanced = hwcfg.escc;
1805
1806#ifdef SCC_DONT_CHECK
1807				printk(KERN_INFO "%s: data port = 0x%3.3x  control port = 0x%3.3x\n",
1808					device_name, 
1809					SCC_Info[2*Nchips+chan].data, 
1810					SCC_Info[2*Nchips+chan].ctrl);
1811
1812#else
1813				printk(KERN_INFO "%s: data port = 0x%3.3lx  control port = 0x%3.3lx -- %s\n",
1814					device_name,
1815					chan? hwcfg.data_b : hwcfg.data_a, 
1816					chan? hwcfg.ctrl_b : hwcfg.ctrl_a,
1817					found? "found" : "missing");
1818#endif
1819
1820				if (found)
1821				{
1822					request_region(SCC_Info[2*Nchips+chan].ctrl, 1, "scc ctrl");
1823					request_region(SCC_Info[2*Nchips+chan].data, 1, "scc data");
1824					if (Nchips+chan != 0 &&
1825					    scc_net_alloc(device_name, 
1826							  &SCC_Info[2*Nchips+chan]))
1827					    return -EINVAL;
1828				}
1829			}
1830			
1831			if (found) Nchips++;
1832			
1833			return 0;
1834		}
1835		
1836		if (cmd == SIOCSCCINI)
1837		{
1838			if (!capable(CAP_SYS_RAWIO))
1839				return -EPERM;
1840				
1841			if (Nchips == 0)
1842				return -EINVAL;
1843
1844			z8530_init();
1845			return 0;
1846		}
1847		
1848		return -EINVAL;	/* confuse the user */
1849	}
1850	
1851	if (!scc->init)
1852	{
1853		if (cmd == SIOCSCCCHANINI)
1854		{
1855			if (!capable(CAP_NET_ADMIN)) return -EPERM;
1856			if (!arg) return -EINVAL;
1857			
1858			scc->stat.bufsize   = SCC_BUFSIZE;
1859
1860			if (copy_from_user(&scc->modem, arg, sizeof(struct scc_modem)))
1861				return -EINVAL;
1862			
1863			/* default KISS Params */
1864		
1865			if (scc->modem.speed < 4800)
1866			{
1867				scc->kiss.txdelay = 36;		/* 360 ms */
1868				scc->kiss.persist = 42;		/* 25% persistence */			/* was 25 */
1869				scc->kiss.slottime = 16;	/* 160 ms */
1870				scc->kiss.tailtime = 4;		/* minimal reasonable value */
1871				scc->kiss.fulldup = 0;		/* CSMA */
1872				scc->kiss.waittime = 50;	/* 500 ms */
1873				scc->kiss.maxkeyup = 10;	/* 10 s */
1874				scc->kiss.mintime = 3;		/* 3 s */
1875				scc->kiss.idletime = 30;	/* 30 s */
1876				scc->kiss.maxdefer = 120;	/* 2 min */
1877				scc->kiss.softdcd = 0;		/* hardware dcd */
1878			} else {
1879				scc->kiss.txdelay = 10;		/* 100 ms */
1880				scc->kiss.persist = 64;		/* 25% persistence */			/* was 25 */
1881				scc->kiss.slottime = 8;		/* 160 ms */
1882				scc->kiss.tailtime = 1;		/* minimal reasonable value */
1883				scc->kiss.fulldup = 0;		/* CSMA */
1884				scc->kiss.waittime = 50;	/* 500 ms */
1885				scc->kiss.maxkeyup = 7;		/* 7 s */
1886				scc->kiss.mintime = 3;		/* 3 s */
1887				scc->kiss.idletime = 30;	/* 30 s */
1888				scc->kiss.maxdefer = 120;	/* 2 min */
1889				scc->kiss.softdcd = 0;		/* hardware dcd */
1890			}
1891			
1892			scc->tx_buff = NULL;
1893			skb_queue_head_init(&scc->tx_queue);
1894			scc->init = 1;
1895			
1896			return 0;
1897		}
1898		
1899		return -EINVAL;
1900	}
1901	
1902	switch(cmd)
1903	{
1904		case SIOCSCCRESERVED:
1905			return -ENOIOCTLCMD;
1906
1907		case SIOCSCCSMEM:
1908			if (!capable(CAP_SYS_RAWIO)) return -EPERM;
1909			if (!arg || copy_from_user(&memcfg, arg, sizeof(memcfg)))
1910				return -EINVAL;
1911			scc->stat.bufsize   = memcfg.bufsize;
1912			return 0;
1913		
1914		case SIOCSCCGSTAT:
1915			if (!arg || copy_to_user(arg, &scc->stat, sizeof(scc->stat)))
1916				return -EINVAL;
1917			return 0;
1918		
1919		case SIOCSCCGKISS:
1920			if (!arg || copy_from_user(&kiss_cmd, arg, sizeof(kiss_cmd)))
1921				return -EINVAL;
1922			kiss_cmd.param = scc_get_param(scc, kiss_cmd.command);
1923			if (copy_to_user(arg, &kiss_cmd, sizeof(kiss_cmd)))
1924				return -EINVAL;
1925			return 0;
1926		
1927		case SIOCSCCSKISS:
1928			if (!capable(CAP_NET_ADMIN)) return -EPERM;
1929			if (!arg || copy_from_user(&kiss_cmd, arg, sizeof(kiss_cmd)))
1930				return -EINVAL;
1931			return scc_set_param(scc, kiss_cmd.command, kiss_cmd.param);
1932		
1933		case SIOCSCCCAL:
1934			if (!capable(CAP_SYS_RAWIO)) return -EPERM;
1935			if (!arg || copy_from_user(&cal, arg, sizeof(cal)) || cal.time == 0)
1936				return -EINVAL;
1937
1938			scc_start_calibrate(scc, cal.time, cal.pattern);
1939			return 0;
1940
1941		default:
1942			return -ENOIOCTLCMD;
1943		
1944	}
1945	
1946	return -EINVAL;
1947}
1948
1949/* ----> set interface callsign <---- */
1950
1951static int scc_net_set_mac_address(struct net_device *dev, void *addr)
1952{
1953	struct sockaddr *sa = (struct sockaddr *) addr;
1954	dev_addr_set(dev, sa->sa_data);
1955	return 0;
1956}
1957
1958/* ----> get statistics <---- */
1959
1960static struct net_device_stats *scc_net_get_stats(struct net_device *dev)
1961{
1962	struct scc_channel *scc = (struct scc_channel *) dev->ml_priv;
1963	
1964	scc->dev_stat.rx_errors = scc->stat.rxerrs + scc->stat.rx_over;
1965	scc->dev_stat.tx_errors = scc->stat.txerrs + scc->stat.tx_under;
1966	scc->dev_stat.rx_fifo_errors = scc->stat.rx_over;
1967	scc->dev_stat.tx_fifo_errors = scc->stat.tx_under;
1968
1969	return &scc->dev_stat;
1970}
1971
1972/* ******************************************************************** */
1973/* *		dump statistics to /proc/net/z8530drv		      * */
1974/* ******************************************************************** */
1975
1976#ifdef CONFIG_PROC_FS
1977
1978static inline struct scc_channel *scc_net_seq_idx(loff_t pos)
1979{
1980	int k;
1981
1982	for (k = 0; k < Nchips*2; ++k) {
1983		if (!SCC_Info[k].init) 
1984			continue;
1985		if (pos-- == 0)
1986			return &SCC_Info[k];
1987	}
1988	return NULL;
1989}
1990
1991static void *scc_net_seq_start(struct seq_file *seq, loff_t *pos)
1992{
1993	return *pos ? scc_net_seq_idx(*pos - 1) : SEQ_START_TOKEN;
1994	
1995}
1996
1997static void *scc_net_seq_next(struct seq_file *seq, void *v, loff_t *pos)
1998{
1999	unsigned k;
2000	struct scc_channel *scc = v;
2001	++*pos;
2002	
2003	for (k = (v == SEQ_START_TOKEN) ? 0 : (scc - SCC_Info)+1;
2004	     k < Nchips*2; ++k) {
2005		if (SCC_Info[k].init) 
2006			return &SCC_Info[k];
2007	}
2008	return NULL;
2009}
2010
2011static void scc_net_seq_stop(struct seq_file *seq, void *v)
2012{
2013}
2014
2015static int scc_net_seq_show(struct seq_file *seq, void *v)
2016{
2017	if (v == SEQ_START_TOKEN) {
2018		seq_puts(seq, "z8530drv-"VERSION"\n");
2019	} else if (!Driver_Initialized) {
2020		seq_puts(seq, "not initialized\n");
2021	} else if (!Nchips) {
2022		seq_puts(seq, "chips missing\n");
2023	} else {
2024		const struct scc_channel *scc = v;
2025		const struct scc_stat *stat = &scc->stat;
2026		const struct scc_kiss *kiss = &scc->kiss;
2027
2028
2029		/* dev	data ctrl irq clock brand enh vector special option 
2030		 *	baud nrz clocksrc softdcd bufsize
2031		 *	rxints txints exints spints
2032		 *	rcvd rxerrs over / xmit txerrs under / nospace bufsize
2033		 *	txd pers slot tail ful wait min maxk idl defr txof grp
2034		 *	W ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ##
2035		 *	R ## ## XX ## ## ## ## ## XX ## ## ## ## ## ## ##
2036		 */
2037
2038		seq_printf(seq, "%s\t%3.3lx %3.3lx %d %lu %2.2x %d %3.3lx %3.3lx %d\n",
2039				scc->dev->name,
2040				scc->data, scc->ctrl, scc->irq, scc->clock, scc->brand,
2041				scc->enhanced, Vector_Latch, scc->special,
2042				scc->option);
2043		seq_printf(seq, "\t%lu %d %d %d %d\n",
2044				scc->modem.speed, scc->modem.nrz,
2045				scc->modem.clocksrc, kiss->softdcd,
2046				stat->bufsize);
2047		seq_printf(seq, "\t%lu %lu %lu %lu\n",
2048				stat->rxints, stat->txints, stat->exints, stat->spints);
2049		seq_printf(seq, "\t%lu %lu %d / %lu %lu %d / %d %d\n",
2050				stat->rxframes, stat->rxerrs, stat->rx_over,
2051				stat->txframes, stat->txerrs, stat->tx_under,
2052				stat->nospace,  stat->tx_state);
2053
2054#define K(x) kiss->x
2055		seq_printf(seq, "\t%d %d %d %d %d %d %d %d %d %d %d %d\n",
2056				K(txdelay), K(persist), K(slottime), K(tailtime),
2057				K(fulldup), K(waittime), K(mintime), K(maxkeyup),
2058				K(idletime), K(maxdefer), K(tx_inhibit), K(group));
2059#undef K
2060#ifdef SCC_DEBUG
2061		{
2062			int reg;
2063
2064		seq_printf(seq, "\tW ");
2065			for (reg = 0; reg < 16; reg++)
2066				seq_printf(seq, "%2.2x ", scc->wreg[reg]);
2067			seq_printf(seq, "\n");
2068			
2069		seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1));
2070			for (reg = 3; reg < 8; reg++)
2071				seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg));
2072			seq_printf(seq, "XX ");
2073			for (reg = 9; reg < 16; reg++)
2074				seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg));
2075			seq_printf(seq, "\n");
2076		}
2077#endif
2078		seq_putc(seq, '\n');
2079	}
2080
2081        return 0;
2082}
2083
2084static const struct seq_operations scc_net_seq_ops = {
2085	.start  = scc_net_seq_start,
2086	.next   = scc_net_seq_next,
2087	.stop   = scc_net_seq_stop,
2088	.show   = scc_net_seq_show,
2089};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2090#endif /* CONFIG_PROC_FS */
2091
2092 
2093/* ******************************************************************** */
2094/* * 			Init SCC driver 			      * */
2095/* ******************************************************************** */
2096
2097static int __init scc_init_driver (void)
2098{
2099	char devname[IFNAMSIZ];
2100	
2101	printk(banner);
2102	
2103	sprintf(devname,"%s0", SCC_DriverName);
2104	
2105	rtnl_lock();
2106	if (scc_net_alloc(devname, SCC_Info)) {
2107		rtnl_unlock();
2108		printk(KERN_ERR "z8530drv: cannot initialize module\n");
2109		return -EIO;
2110	}
2111	rtnl_unlock();
2112
2113	proc_create_seq("z8530drv", 0, init_net.proc_net, &scc_net_seq_ops);
2114
2115	return 0;
2116}
2117
2118static void __exit scc_cleanup_driver(void)
2119{
2120	io_port ctrl;
2121	int k;
2122	struct scc_channel *scc;
2123	struct net_device *dev;
2124	
2125	if (Nchips == 0 && (dev = SCC_Info[0].dev)) 
2126	{
2127		unregister_netdev(dev);
2128		free_netdev(dev);
2129	}
2130
2131	/* Guard against chip prattle */
2132	local_irq_disable();
2133	
2134	for (k = 0; k < Nchips; k++)
2135		if ( (ctrl = SCC_ctrl[k].chan_A) )
2136		{
2137			Outb(ctrl, 0);
2138			OutReg(ctrl,R9,FHWRES);	/* force hardware reset */
2139			udelay(50);
2140		}
2141		
2142	/* To unload the port must be closed so no real IRQ pending */
2143	for (k = 0; k < nr_irqs ; k++)
2144		if (Ivec[k].used) free_irq(k, NULL);
2145		
2146	local_irq_enable();
2147		
2148	/* Now clean up */
2149	for (k = 0; k < Nchips*2; k++)
2150	{
2151		scc = &SCC_Info[k];
2152		if (scc->ctrl)
2153		{
2154			release_region(scc->ctrl, 1);
2155			release_region(scc->data, 1);
2156		}
2157		if (scc->dev)
2158		{
2159			unregister_netdev(scc->dev);
2160			free_netdev(scc->dev);
2161		}
2162	}
2163	
2164		
2165	if (Vector_Latch)
2166		release_region(Vector_Latch, 1);
2167
2168	remove_proc_entry("z8530drv", init_net.proc_net);
2169}
2170
2171MODULE_AUTHOR("Joerg Reuter <jreuter@yaina.de>");
2172MODULE_DESCRIPTION("AX.25 Device Driver for Z8530 based HDLC cards");
 
2173MODULE_LICENSE("GPL");
2174module_init(scc_init_driver);
2175module_exit(scc_cleanup_driver);