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1/* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
2/*
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
18
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
21 number Y1-LM-2015-01.
22
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
25
26 KNOWN ISSUES:
27 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
28 issue. Hopefully 3Com will fix it.
29 *) Waiting for a command response takes 8ms due to non-preemptable
30 polling. Only significant for getting stats and creating
31 SAs, but an ugly wart never the less.
32
33 TODO:
34 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
35 *) Add more support for ethtool (especially for NIC stats)
36 *) Allow disabling of RX checksum offloading
37 *) Fix MAC changing to work while the interface is up
38 (Need to put commands on the TX ring, which changes
39 the locking)
40 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
41 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
42*/
43
44/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
45 * Setting to > 1518 effectively disables this feature.
46 */
47static int rx_copybreak = 200;
48
49/* Should we use MMIO or Port IO?
50 * 0: Port IO
51 * 1: MMIO
52 * 2: Try MMIO, fallback to Port IO
53 */
54static unsigned int use_mmio = 2;
55
56/* end user-configurable values */
57
58/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
59 */
60static const int multicast_filter_limit = 32;
61
62/* Operational parameters that are set at compile time. */
63
64/* Keep the ring sizes a power of two for compile efficiency.
65 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
66 * Making the Tx ring too large decreases the effectiveness of channel
67 * bonding and packet priority.
68 * There are no ill effects from too-large receive rings.
69 *
70 * We don't currently use the Hi Tx ring so, don't make it very big.
71 *
72 * Beware that if we start using the Hi Tx ring, we will need to change
73 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
74 */
75#define TXHI_ENTRIES 2
76#define TXLO_ENTRIES 128
77#define RX_ENTRIES 32
78#define COMMAND_ENTRIES 16
79#define RESPONSE_ENTRIES 32
80
81#define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
82#define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
83
84/* The 3XP will preload and remove 64 entries from the free buffer
85 * list, and we need one entry to keep the ring from wrapping, so
86 * to keep this a power of two, we use 128 entries.
87 */
88#define RXFREE_ENTRIES 128
89#define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
90
91/* Operational parameters that usually are not changed. */
92
93/* Time in jiffies before concluding the transmitter is hung. */
94#define TX_TIMEOUT (2*HZ)
95
96#define PKT_BUF_SZ 1536
97#define FIRMWARE_NAME "3com/typhoon.bin"
98
99#define pr_fmt(fmt) KBUILD_MODNAME " " fmt
100
101#include <linux/module.h>
102#include <linux/kernel.h>
103#include <linux/sched.h>
104#include <linux/string.h>
105#include <linux/timer.h>
106#include <linux/errno.h>
107#include <linux/ioport.h>
108#include <linux/interrupt.h>
109#include <linux/pci.h>
110#include <linux/netdevice.h>
111#include <linux/etherdevice.h>
112#include <linux/skbuff.h>
113#include <linux/mm.h>
114#include <linux/init.h>
115#include <linux/delay.h>
116#include <linux/ethtool.h>
117#include <linux/if_vlan.h>
118#include <linux/crc32.h>
119#include <linux/bitops.h>
120#include <asm/processor.h>
121#include <asm/io.h>
122#include <linux/uaccess.h>
123#include <linux/in6.h>
124#include <linux/dma-mapping.h>
125#include <linux/firmware.h>
126
127#include "typhoon.h"
128
129MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
130MODULE_LICENSE("GPL");
131MODULE_FIRMWARE(FIRMWARE_NAME);
132MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
133MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
134 "the buffer given back to the NIC. Default "
135 "is 200.");
136MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
137 "Default is to try MMIO and fallback to PIO.");
138module_param(rx_copybreak, int, 0);
139module_param(use_mmio, int, 0);
140
141#if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
142#error TX ring too small!
143#endif
144
145struct typhoon_card_info {
146 const char *name;
147 const int capabilities;
148};
149
150#define TYPHOON_CRYPTO_NONE 0x00
151#define TYPHOON_CRYPTO_DES 0x01
152#define TYPHOON_CRYPTO_3DES 0x02
153#define TYPHOON_CRYPTO_VARIABLE 0x04
154#define TYPHOON_FIBER 0x08
155#define TYPHOON_WAKEUP_NEEDS_RESET 0x10
156
157enum typhoon_cards {
158 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
159 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
160 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
161 TYPHOON_FXM,
162};
163
164/* directly indexed by enum typhoon_cards, above */
165static struct typhoon_card_info typhoon_card_info[] = {
166 { "3Com Typhoon (3C990-TX)",
167 TYPHOON_CRYPTO_NONE},
168 { "3Com Typhoon (3CR990-TX-95)",
169 TYPHOON_CRYPTO_DES},
170 { "3Com Typhoon (3CR990-TX-97)",
171 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
172 { "3Com Typhoon (3C990SVR)",
173 TYPHOON_CRYPTO_NONE},
174 { "3Com Typhoon (3CR990SVR95)",
175 TYPHOON_CRYPTO_DES},
176 { "3Com Typhoon (3CR990SVR97)",
177 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
178 { "3Com Typhoon2 (3C990B-TX-M)",
179 TYPHOON_CRYPTO_VARIABLE},
180 { "3Com Typhoon2 (3C990BSVR)",
181 TYPHOON_CRYPTO_VARIABLE},
182 { "3Com Typhoon (3CR990-FX-95)",
183 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
184 { "3Com Typhoon (3CR990-FX-97)",
185 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
186 { "3Com Typhoon (3CR990-FX-95 Server)",
187 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
188 { "3Com Typhoon (3CR990-FX-97 Server)",
189 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
190 { "3Com Typhoon2 (3C990B-FX-97)",
191 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
192};
193
194/* Notes on the new subsystem numbering scheme:
195 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
196 * bit 4 indicates if this card has secured firmware (we don't support it)
197 * bit 8 indicates if this is a (0) copper or (1) fiber card
198 * bits 12-16 indicate card type: (0) client and (1) server
199 */
200static const struct pci_device_id typhoon_pci_tbl[] = {
201 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
203 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
205 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
207 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
208 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
209 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
210 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
211 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
212 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
213 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
214 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
215 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
216 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
217 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
218 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
220 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
227 { 0, }
228};
229MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
230
231/* Define the shared memory area
232 * Align everything the 3XP will normally be using.
233 * We'll need to move/align txHi if we start using that ring.
234 */
235#define __3xp_aligned ____cacheline_aligned
236struct typhoon_shared {
237 struct typhoon_interface iface;
238 struct typhoon_indexes indexes __3xp_aligned;
239 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
240 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
241 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
242 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
243 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
244 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
245 u32 zeroWord;
246 struct tx_desc txHi[TXHI_ENTRIES];
247} __packed;
248
249struct rxbuff_ent {
250 struct sk_buff *skb;
251 dma_addr_t dma_addr;
252};
253
254struct typhoon {
255 /* Tx cache line section */
256 struct transmit_ring txLoRing ____cacheline_aligned;
257 struct pci_dev * tx_pdev;
258 void __iomem *tx_ioaddr;
259 u32 txlo_dma_addr;
260
261 /* Irq/Rx cache line section */
262 void __iomem *ioaddr ____cacheline_aligned;
263 struct typhoon_indexes *indexes;
264 u8 awaiting_resp;
265 u8 duplex;
266 u8 speed;
267 u8 card_state;
268 struct basic_ring rxLoRing;
269 struct pci_dev * pdev;
270 struct net_device * dev;
271 struct napi_struct napi;
272 struct basic_ring rxHiRing;
273 struct basic_ring rxBuffRing;
274 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
275
276 /* general section */
277 spinlock_t command_lock ____cacheline_aligned;
278 struct basic_ring cmdRing;
279 struct basic_ring respRing;
280 struct net_device_stats stats_saved;
281 struct typhoon_shared * shared;
282 dma_addr_t shared_dma;
283 __le16 xcvr_select;
284 __le16 wol_events;
285 __le32 offload;
286
287 /* unused stuff (future use) */
288 int capabilities;
289 struct transmit_ring txHiRing;
290};
291
292enum completion_wait_values {
293 NoWait = 0, WaitNoSleep, WaitSleep,
294};
295
296/* These are the values for the typhoon.card_state variable.
297 * These determine where the statistics will come from in get_stats().
298 * The sleep image does not support the statistics we need.
299 */
300enum state_values {
301 Sleeping = 0, Running,
302};
303
304/* PCI writes are not guaranteed to be posted in order, but outstanding writes
305 * cannot pass a read, so this forces current writes to post.
306 */
307#define typhoon_post_pci_writes(x) \
308 do { if (likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while (0)
309
310/* We'll wait up to six seconds for a reset, and half a second normally.
311 */
312#define TYPHOON_UDELAY 50
313#define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
314#define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
315#define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
316
317#if defined(NETIF_F_TSO)
318#define skb_tso_size(x) (skb_shinfo(x)->gso_size)
319#define TSO_NUM_DESCRIPTORS 2
320#define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
321#else
322#define NETIF_F_TSO 0
323#define skb_tso_size(x) 0
324#define TSO_NUM_DESCRIPTORS 0
325#define TSO_OFFLOAD_ON 0
326#endif
327
328static inline void
329typhoon_inc_index(u32 *index, const int count, const int num_entries)
330{
331 /* Increment a ring index -- we can use this for all rings execept
332 * the Rx rings, as they use different size descriptors
333 * otherwise, everything is the same size as a cmd_desc
334 */
335 *index += count * sizeof(struct cmd_desc);
336 *index %= num_entries * sizeof(struct cmd_desc);
337}
338
339static inline void
340typhoon_inc_cmd_index(u32 *index, const int count)
341{
342 typhoon_inc_index(index, count, COMMAND_ENTRIES);
343}
344
345static inline void
346typhoon_inc_resp_index(u32 *index, const int count)
347{
348 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
349}
350
351static inline void
352typhoon_inc_rxfree_index(u32 *index, const int count)
353{
354 typhoon_inc_index(index, count, RXFREE_ENTRIES);
355}
356
357static inline void
358typhoon_inc_tx_index(u32 *index, const int count)
359{
360 /* if we start using the Hi Tx ring, this needs updating */
361 typhoon_inc_index(index, count, TXLO_ENTRIES);
362}
363
364static inline void
365typhoon_inc_rx_index(u32 *index, const int count)
366{
367 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
368 *index += count * sizeof(struct rx_desc);
369 *index %= RX_ENTRIES * sizeof(struct rx_desc);
370}
371
372static int
373typhoon_reset(void __iomem *ioaddr, int wait_type)
374{
375 int i, err = 0;
376 int timeout;
377
378 if (wait_type == WaitNoSleep)
379 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
380 else
381 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
382
383 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
384 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
385
386 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
387 typhoon_post_pci_writes(ioaddr);
388 udelay(1);
389 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
390
391 if (wait_type != NoWait) {
392 for (i = 0; i < timeout; i++) {
393 if (ioread32(ioaddr + TYPHOON_REG_STATUS) ==
394 TYPHOON_STATUS_WAITING_FOR_HOST)
395 goto out;
396
397 if (wait_type == WaitSleep)
398 schedule_timeout_uninterruptible(1);
399 else
400 udelay(TYPHOON_UDELAY);
401 }
402
403 err = -ETIMEDOUT;
404 }
405
406out:
407 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
408 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
409
410 /* The 3XP seems to need a little extra time to complete the load
411 * of the sleep image before we can reliably boot it. Failure to
412 * do this occasionally results in a hung adapter after boot in
413 * typhoon_init_one() while trying to read the MAC address or
414 * putting the card to sleep. 3Com's driver waits 5ms, but
415 * that seems to be overkill. However, if we can sleep, we might
416 * as well give it that much time. Otherwise, we'll give it 500us,
417 * which should be enough (I've see it work well at 100us, but still
418 * saw occasional problems.)
419 */
420 if (wait_type == WaitSleep)
421 msleep(5);
422 else
423 udelay(500);
424 return err;
425}
426
427static int
428typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
429{
430 int i, err = 0;
431
432 for (i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
433 if (ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
434 goto out;
435 udelay(TYPHOON_UDELAY);
436 }
437
438 err = -ETIMEDOUT;
439
440out:
441 return err;
442}
443
444static inline void
445typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
446{
447 if (resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
448 netif_carrier_off(dev);
449 else
450 netif_carrier_on(dev);
451}
452
453static inline void
454typhoon_hello(struct typhoon *tp)
455{
456 struct basic_ring *ring = &tp->cmdRing;
457 struct cmd_desc *cmd;
458
459 /* We only get a hello request if we've not sent anything to the
460 * card in a long while. If the lock is held, then we're in the
461 * process of issuing a command, so we don't need to respond.
462 */
463 if (spin_trylock(&tp->command_lock)) {
464 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
465 typhoon_inc_cmd_index(&ring->lastWrite, 1);
466
467 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
468 wmb();
469 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
470 spin_unlock(&tp->command_lock);
471 }
472}
473
474static int
475typhoon_process_response(struct typhoon *tp, int resp_size,
476 struct resp_desc *resp_save)
477{
478 struct typhoon_indexes *indexes = tp->indexes;
479 struct resp_desc *resp;
480 u8 *base = tp->respRing.ringBase;
481 int count, len, wrap_len;
482 u32 cleared;
483 u32 ready;
484
485 cleared = le32_to_cpu(indexes->respCleared);
486 ready = le32_to_cpu(indexes->respReady);
487 while (cleared != ready) {
488 resp = (struct resp_desc *)(base + cleared);
489 count = resp->numDesc + 1;
490 if (resp_save && resp->seqNo) {
491 if (count > resp_size) {
492 resp_save->flags = TYPHOON_RESP_ERROR;
493 goto cleanup;
494 }
495
496 wrap_len = 0;
497 len = count * sizeof(*resp);
498 if (unlikely(cleared + len > RESPONSE_RING_SIZE)) {
499 wrap_len = cleared + len - RESPONSE_RING_SIZE;
500 len = RESPONSE_RING_SIZE - cleared;
501 }
502
503 memcpy(resp_save, resp, len);
504 if (unlikely(wrap_len)) {
505 resp_save += len / sizeof(*resp);
506 memcpy(resp_save, base, wrap_len);
507 }
508
509 resp_save = NULL;
510 } else if (resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
511 typhoon_media_status(tp->dev, resp);
512 } else if (resp->cmd == TYPHOON_CMD_HELLO_RESP) {
513 typhoon_hello(tp);
514 } else {
515 netdev_err(tp->dev,
516 "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
517 le16_to_cpu(resp->cmd),
518 resp->numDesc, resp->flags,
519 le16_to_cpu(resp->parm1),
520 le32_to_cpu(resp->parm2),
521 le32_to_cpu(resp->parm3));
522 }
523
524cleanup:
525 typhoon_inc_resp_index(&cleared, count);
526 }
527
528 indexes->respCleared = cpu_to_le32(cleared);
529 wmb();
530 return resp_save == NULL;
531}
532
533static inline int
534typhoon_num_free(int lastWrite, int lastRead, int ringSize)
535{
536 /* this works for all descriptors but rx_desc, as they are a
537 * different size than the cmd_desc -- everyone else is the same
538 */
539 lastWrite /= sizeof(struct cmd_desc);
540 lastRead /= sizeof(struct cmd_desc);
541 return (ringSize + lastRead - lastWrite - 1) % ringSize;
542}
543
544static inline int
545typhoon_num_free_cmd(struct typhoon *tp)
546{
547 int lastWrite = tp->cmdRing.lastWrite;
548 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
549
550 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
551}
552
553static inline int
554typhoon_num_free_resp(struct typhoon *tp)
555{
556 int respReady = le32_to_cpu(tp->indexes->respReady);
557 int respCleared = le32_to_cpu(tp->indexes->respCleared);
558
559 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
560}
561
562static inline int
563typhoon_num_free_tx(struct transmit_ring *ring)
564{
565 /* if we start using the Hi Tx ring, this needs updating */
566 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
567}
568
569static int
570typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
571 int num_resp, struct resp_desc *resp)
572{
573 struct typhoon_indexes *indexes = tp->indexes;
574 struct basic_ring *ring = &tp->cmdRing;
575 struct resp_desc local_resp;
576 int i, err = 0;
577 int got_resp;
578 int freeCmd, freeResp;
579 int len, wrap_len;
580
581 spin_lock(&tp->command_lock);
582
583 freeCmd = typhoon_num_free_cmd(tp);
584 freeResp = typhoon_num_free_resp(tp);
585
586 if (freeCmd < num_cmd || freeResp < num_resp) {
587 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
588 freeCmd, num_cmd, freeResp, num_resp);
589 err = -ENOMEM;
590 goto out;
591 }
592
593 if (cmd->flags & TYPHOON_CMD_RESPOND) {
594 /* If we're expecting a response, but the caller hasn't given
595 * us a place to put it, we'll provide one.
596 */
597 tp->awaiting_resp = 1;
598 if (resp == NULL) {
599 resp = &local_resp;
600 num_resp = 1;
601 }
602 }
603
604 wrap_len = 0;
605 len = num_cmd * sizeof(*cmd);
606 if (unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
607 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
608 len = COMMAND_RING_SIZE - ring->lastWrite;
609 }
610
611 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
612 if (unlikely(wrap_len)) {
613 struct cmd_desc *wrap_ptr = cmd;
614 wrap_ptr += len / sizeof(*cmd);
615 memcpy(ring->ringBase, wrap_ptr, wrap_len);
616 }
617
618 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
619
620 /* "I feel a presence... another warrior is on the mesa."
621 */
622 wmb();
623 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
624 typhoon_post_pci_writes(tp->ioaddr);
625
626 if ((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
627 goto out;
628
629 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
630 * preempt or do anything other than take interrupts. So, don't
631 * wait for a response unless you have to.
632 *
633 * I've thought about trying to sleep here, but we're called
634 * from many contexts that don't allow that. Also, given the way
635 * 3Com has implemented irq coalescing, we would likely timeout --
636 * this has been observed in real life!
637 *
638 * The big killer is we have to wait to get stats from the card,
639 * though we could go to a periodic refresh of those if we don't
640 * mind them getting somewhat stale. The rest of the waiting
641 * commands occur during open/close/suspend/resume, so they aren't
642 * time critical. Creating SAs in the future will also have to
643 * wait here.
644 */
645 got_resp = 0;
646 for (i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
647 if (indexes->respCleared != indexes->respReady)
648 got_resp = typhoon_process_response(tp, num_resp,
649 resp);
650 udelay(TYPHOON_UDELAY);
651 }
652
653 if (!got_resp) {
654 err = -ETIMEDOUT;
655 goto out;
656 }
657
658 /* Collect the error response even if we don't care about the
659 * rest of the response
660 */
661 if (resp->flags & TYPHOON_RESP_ERROR)
662 err = -EIO;
663
664out:
665 if (tp->awaiting_resp) {
666 tp->awaiting_resp = 0;
667 smp_wmb();
668
669 /* Ugh. If a response was added to the ring between
670 * the call to typhoon_process_response() and the clearing
671 * of tp->awaiting_resp, we could have missed the interrupt
672 * and it could hang in the ring an indeterminate amount of
673 * time. So, check for it, and interrupt ourselves if this
674 * is the case.
675 */
676 if (indexes->respCleared != indexes->respReady)
677 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
678 }
679
680 spin_unlock(&tp->command_lock);
681 return err;
682}
683
684static inline void
685typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
686 u32 ring_dma)
687{
688 struct tcpopt_desc *tcpd;
689 u32 tcpd_offset = ring_dma;
690
691 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
692 tcpd_offset += txRing->lastWrite;
693 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
694 typhoon_inc_tx_index(&txRing->lastWrite, 1);
695
696 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
697 tcpd->numDesc = 1;
698 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
699 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
700 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
701 tcpd->bytesTx = cpu_to_le32(skb->len);
702 tcpd->status = 0;
703}
704
705static netdev_tx_t
706typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
707{
708 struct typhoon *tp = netdev_priv(dev);
709 struct transmit_ring *txRing;
710 struct tx_desc *txd, *first_txd;
711 dma_addr_t skb_dma;
712 int numDesc;
713
714 /* we have two rings to choose from, but we only use txLo for now
715 * If we start using the Hi ring as well, we'll need to update
716 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
717 * and TXHI_ENTRIES to match, as well as update the TSO code below
718 * to get the right DMA address
719 */
720 txRing = &tp->txLoRing;
721
722 /* We need one descriptor for each fragment of the sk_buff, plus the
723 * one for the ->data area of it.
724 *
725 * The docs say a maximum of 16 fragment descriptors per TCP option
726 * descriptor, then make a new packet descriptor and option descriptor
727 * for the next 16 fragments. The engineers say just an option
728 * descriptor is needed. I've tested up to 26 fragments with a single
729 * packet descriptor/option descriptor combo, so I use that for now.
730 *
731 * If problems develop with TSO, check this first.
732 */
733 numDesc = skb_shinfo(skb)->nr_frags + 1;
734 if (skb_is_gso(skb))
735 numDesc++;
736
737 /* When checking for free space in the ring, we need to also
738 * account for the initial Tx descriptor, and we always must leave
739 * at least one descriptor unused in the ring so that it doesn't
740 * wrap and look empty.
741 *
742 * The only time we should loop here is when we hit the race
743 * between marking the queue awake and updating the cleared index.
744 * Just loop and it will appear. This comes from the acenic driver.
745 */
746 while (unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
747 smp_rmb();
748
749 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
750 typhoon_inc_tx_index(&txRing->lastWrite, 1);
751
752 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
753 first_txd->numDesc = 0;
754 first_txd->len = 0;
755 first_txd->tx_addr = (u64)((unsigned long) skb);
756 first_txd->processFlags = 0;
757
758 if (skb->ip_summed == CHECKSUM_PARTIAL) {
759 /* The 3XP will figure out if this is UDP/TCP */
760 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
761 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
762 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
763 }
764
765 if (skb_vlan_tag_present(skb)) {
766 first_txd->processFlags |=
767 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
768 first_txd->processFlags |=
769 cpu_to_le32(htons(skb_vlan_tag_get(skb)) <<
770 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
771 }
772
773 if (skb_is_gso(skb)) {
774 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
775 first_txd->numDesc++;
776
777 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
778 }
779
780 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
781 typhoon_inc_tx_index(&txRing->lastWrite, 1);
782
783 /* No need to worry about padding packet -- the firmware pads
784 * it with zeros to ETH_ZLEN for us.
785 */
786 if (skb_shinfo(skb)->nr_frags == 0) {
787 skb_dma = dma_map_single(&tp->tx_pdev->dev, skb->data,
788 skb->len, DMA_TO_DEVICE);
789 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
790 txd->len = cpu_to_le16(skb->len);
791 txd->frag.addr = cpu_to_le32(skb_dma);
792 txd->frag.addrHi = 0;
793 first_txd->numDesc++;
794 } else {
795 int i, len;
796
797 len = skb_headlen(skb);
798 skb_dma = dma_map_single(&tp->tx_pdev->dev, skb->data, len,
799 DMA_TO_DEVICE);
800 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
801 txd->len = cpu_to_le16(len);
802 txd->frag.addr = cpu_to_le32(skb_dma);
803 txd->frag.addrHi = 0;
804 first_txd->numDesc++;
805
806 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
807 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
808 void *frag_addr;
809
810 txd = (struct tx_desc *) (txRing->ringBase +
811 txRing->lastWrite);
812 typhoon_inc_tx_index(&txRing->lastWrite, 1);
813
814 len = skb_frag_size(frag);
815 frag_addr = skb_frag_address(frag);
816 skb_dma = dma_map_single(&tp->tx_pdev->dev, frag_addr,
817 len, DMA_TO_DEVICE);
818 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
819 txd->len = cpu_to_le16(len);
820 txd->frag.addr = cpu_to_le32(skb_dma);
821 txd->frag.addrHi = 0;
822 first_txd->numDesc++;
823 }
824 }
825
826 /* Kick the 3XP
827 */
828 wmb();
829 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
830
831 /* If we don't have room to put the worst case packet on the
832 * queue, then we must stop the queue. We need 2 extra
833 * descriptors -- one to prevent ring wrap, and one for the
834 * Tx header.
835 */
836 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
837
838 if (typhoon_num_free_tx(txRing) < (numDesc + 2)) {
839 netif_stop_queue(dev);
840
841 /* A Tx complete IRQ could have gotten between, making
842 * the ring free again. Only need to recheck here, since
843 * Tx is serialized.
844 */
845 if (typhoon_num_free_tx(txRing) >= (numDesc + 2))
846 netif_wake_queue(dev);
847 }
848
849 return NETDEV_TX_OK;
850}
851
852static void
853typhoon_set_rx_mode(struct net_device *dev)
854{
855 struct typhoon *tp = netdev_priv(dev);
856 struct cmd_desc xp_cmd;
857 u32 mc_filter[2];
858 __le16 filter;
859
860 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
861 if (dev->flags & IFF_PROMISC) {
862 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
863 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
864 (dev->flags & IFF_ALLMULTI)) {
865 /* Too many to match, or accept all multicasts. */
866 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
867 } else if (!netdev_mc_empty(dev)) {
868 struct netdev_hw_addr *ha;
869
870 memset(mc_filter, 0, sizeof(mc_filter));
871 netdev_for_each_mc_addr(ha, dev) {
872 int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
873 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
874 }
875
876 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
877 TYPHOON_CMD_SET_MULTICAST_HASH);
878 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
879 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
880 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
881 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
882
883 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
884 }
885
886 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
887 xp_cmd.parm1 = filter;
888 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
889}
890
891static int
892typhoon_do_get_stats(struct typhoon *tp)
893{
894 struct net_device_stats *stats = &tp->dev->stats;
895 struct net_device_stats *saved = &tp->stats_saved;
896 struct cmd_desc xp_cmd;
897 struct resp_desc xp_resp[7];
898 struct stats_resp *s = (struct stats_resp *) xp_resp;
899 int err;
900
901 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
902 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
903 if (err < 0)
904 return err;
905
906 /* 3Com's Linux driver uses txMultipleCollisions as it's
907 * collisions value, but there is some other collision info as well...
908 *
909 * The extra status reported would be a good candidate for
910 * ethtool_ops->get_{strings,stats}()
911 */
912 stats->tx_packets = le32_to_cpu(s->txPackets) +
913 saved->tx_packets;
914 stats->tx_bytes = le64_to_cpu(s->txBytes) +
915 saved->tx_bytes;
916 stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
917 saved->tx_errors;
918 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
919 saved->tx_carrier_errors;
920 stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
921 saved->collisions;
922 stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
923 saved->rx_packets;
924 stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
925 saved->rx_bytes;
926 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
927 saved->rx_fifo_errors;
928 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
929 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
930 saved->rx_errors;
931 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
932 saved->rx_crc_errors;
933 stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
934 saved->rx_length_errors;
935 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
936 SPEED_100 : SPEED_10;
937 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
938 DUPLEX_FULL : DUPLEX_HALF;
939
940 return 0;
941}
942
943static struct net_device_stats *
944typhoon_get_stats(struct net_device *dev)
945{
946 struct typhoon *tp = netdev_priv(dev);
947 struct net_device_stats *stats = &tp->dev->stats;
948 struct net_device_stats *saved = &tp->stats_saved;
949
950 smp_rmb();
951 if (tp->card_state == Sleeping)
952 return saved;
953
954 if (typhoon_do_get_stats(tp) < 0) {
955 netdev_err(dev, "error getting stats\n");
956 return saved;
957 }
958
959 return stats;
960}
961
962static void
963typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
964{
965 struct typhoon *tp = netdev_priv(dev);
966 struct pci_dev *pci_dev = tp->pdev;
967 struct cmd_desc xp_cmd;
968 struct resp_desc xp_resp[3];
969
970 smp_rmb();
971 if (tp->card_state == Sleeping) {
972 strscpy(info->fw_version, "Sleep image",
973 sizeof(info->fw_version));
974 } else {
975 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
976 if (typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
977 strscpy(info->fw_version, "Unknown runtime",
978 sizeof(info->fw_version));
979 } else {
980 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
981 snprintf(info->fw_version, sizeof(info->fw_version),
982 "%02x.%03x.%03x", sleep_ver >> 24,
983 (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff);
984 }
985 }
986
987 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
988 strscpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
989}
990
991static int
992typhoon_get_link_ksettings(struct net_device *dev,
993 struct ethtool_link_ksettings *cmd)
994{
995 struct typhoon *tp = netdev_priv(dev);
996 u32 supported, advertising = 0;
997
998 supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
999 SUPPORTED_Autoneg;
1000
1001 switch (tp->xcvr_select) {
1002 case TYPHOON_XCVR_10HALF:
1003 advertising = ADVERTISED_10baseT_Half;
1004 break;
1005 case TYPHOON_XCVR_10FULL:
1006 advertising = ADVERTISED_10baseT_Full;
1007 break;
1008 case TYPHOON_XCVR_100HALF:
1009 advertising = ADVERTISED_100baseT_Half;
1010 break;
1011 case TYPHOON_XCVR_100FULL:
1012 advertising = ADVERTISED_100baseT_Full;
1013 break;
1014 case TYPHOON_XCVR_AUTONEG:
1015 advertising = ADVERTISED_10baseT_Half |
1016 ADVERTISED_10baseT_Full |
1017 ADVERTISED_100baseT_Half |
1018 ADVERTISED_100baseT_Full |
1019 ADVERTISED_Autoneg;
1020 break;
1021 }
1022
1023 if (tp->capabilities & TYPHOON_FIBER) {
1024 supported |= SUPPORTED_FIBRE;
1025 advertising |= ADVERTISED_FIBRE;
1026 cmd->base.port = PORT_FIBRE;
1027 } else {
1028 supported |= SUPPORTED_10baseT_Half |
1029 SUPPORTED_10baseT_Full |
1030 SUPPORTED_TP;
1031 advertising |= ADVERTISED_TP;
1032 cmd->base.port = PORT_TP;
1033 }
1034
1035 /* need to get stats to make these link speed/duplex valid */
1036 typhoon_do_get_stats(tp);
1037 cmd->base.speed = tp->speed;
1038 cmd->base.duplex = tp->duplex;
1039 cmd->base.phy_address = 0;
1040 if (tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1041 cmd->base.autoneg = AUTONEG_ENABLE;
1042 else
1043 cmd->base.autoneg = AUTONEG_DISABLE;
1044
1045 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1046 supported);
1047 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1048 advertising);
1049
1050 return 0;
1051}
1052
1053static int
1054typhoon_set_link_ksettings(struct net_device *dev,
1055 const struct ethtool_link_ksettings *cmd)
1056{
1057 struct typhoon *tp = netdev_priv(dev);
1058 u32 speed = cmd->base.speed;
1059 struct cmd_desc xp_cmd;
1060 __le16 xcvr;
1061 int err;
1062
1063 err = -EINVAL;
1064 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1065 xcvr = TYPHOON_XCVR_AUTONEG;
1066 } else {
1067 if (cmd->base.duplex == DUPLEX_HALF) {
1068 if (speed == SPEED_10)
1069 xcvr = TYPHOON_XCVR_10HALF;
1070 else if (speed == SPEED_100)
1071 xcvr = TYPHOON_XCVR_100HALF;
1072 else
1073 goto out;
1074 } else if (cmd->base.duplex == DUPLEX_FULL) {
1075 if (speed == SPEED_10)
1076 xcvr = TYPHOON_XCVR_10FULL;
1077 else if (speed == SPEED_100)
1078 xcvr = TYPHOON_XCVR_100FULL;
1079 else
1080 goto out;
1081 } else
1082 goto out;
1083 }
1084
1085 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1086 xp_cmd.parm1 = xcvr;
1087 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1088 if (err < 0)
1089 goto out;
1090
1091 tp->xcvr_select = xcvr;
1092 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1093 tp->speed = 0xff; /* invalid */
1094 tp->duplex = 0xff; /* invalid */
1095 } else {
1096 tp->speed = speed;
1097 tp->duplex = cmd->base.duplex;
1098 }
1099
1100out:
1101 return err;
1102}
1103
1104static void
1105typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1106{
1107 struct typhoon *tp = netdev_priv(dev);
1108
1109 wol->supported = WAKE_PHY | WAKE_MAGIC;
1110 wol->wolopts = 0;
1111 if (tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1112 wol->wolopts |= WAKE_PHY;
1113 if (tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1114 wol->wolopts |= WAKE_MAGIC;
1115 memset(&wol->sopass, 0, sizeof(wol->sopass));
1116}
1117
1118static int
1119typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1120{
1121 struct typhoon *tp = netdev_priv(dev);
1122
1123 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1124 return -EINVAL;
1125
1126 tp->wol_events = 0;
1127 if (wol->wolopts & WAKE_PHY)
1128 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1129 if (wol->wolopts & WAKE_MAGIC)
1130 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1131
1132 return 0;
1133}
1134
1135static void
1136typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering,
1137 struct kernel_ethtool_ringparam *kernel_ering,
1138 struct netlink_ext_ack *extack)
1139{
1140 ering->rx_max_pending = RXENT_ENTRIES;
1141 ering->tx_max_pending = TXLO_ENTRIES - 1;
1142
1143 ering->rx_pending = RXENT_ENTRIES;
1144 ering->tx_pending = TXLO_ENTRIES - 1;
1145}
1146
1147static const struct ethtool_ops typhoon_ethtool_ops = {
1148 .get_drvinfo = typhoon_get_drvinfo,
1149 .get_wol = typhoon_get_wol,
1150 .set_wol = typhoon_set_wol,
1151 .get_link = ethtool_op_get_link,
1152 .get_ringparam = typhoon_get_ringparam,
1153 .get_link_ksettings = typhoon_get_link_ksettings,
1154 .set_link_ksettings = typhoon_set_link_ksettings,
1155};
1156
1157static int
1158typhoon_wait_interrupt(void __iomem *ioaddr)
1159{
1160 int i, err = 0;
1161
1162 for (i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1163 if (ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1164 TYPHOON_INTR_BOOTCMD)
1165 goto out;
1166 udelay(TYPHOON_UDELAY);
1167 }
1168
1169 err = -ETIMEDOUT;
1170
1171out:
1172 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1173 return err;
1174}
1175
1176#define shared_offset(x) offsetof(struct typhoon_shared, x)
1177
1178static void
1179typhoon_init_interface(struct typhoon *tp)
1180{
1181 struct typhoon_interface *iface = &tp->shared->iface;
1182 dma_addr_t shared_dma;
1183
1184 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1185
1186 /* The *Hi members of iface are all init'd to zero by the memset().
1187 */
1188 shared_dma = tp->shared_dma + shared_offset(indexes);
1189 iface->ringIndex = cpu_to_le32(shared_dma);
1190
1191 shared_dma = tp->shared_dma + shared_offset(txLo);
1192 iface->txLoAddr = cpu_to_le32(shared_dma);
1193 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1194
1195 shared_dma = tp->shared_dma + shared_offset(txHi);
1196 iface->txHiAddr = cpu_to_le32(shared_dma);
1197 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1198
1199 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1200 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1201 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1202 sizeof(struct rx_free));
1203
1204 shared_dma = tp->shared_dma + shared_offset(rxLo);
1205 iface->rxLoAddr = cpu_to_le32(shared_dma);
1206 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1207
1208 shared_dma = tp->shared_dma + shared_offset(rxHi);
1209 iface->rxHiAddr = cpu_to_le32(shared_dma);
1210 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1211
1212 shared_dma = tp->shared_dma + shared_offset(cmd);
1213 iface->cmdAddr = cpu_to_le32(shared_dma);
1214 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1215
1216 shared_dma = tp->shared_dma + shared_offset(resp);
1217 iface->respAddr = cpu_to_le32(shared_dma);
1218 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1219
1220 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1221 iface->zeroAddr = cpu_to_le32(shared_dma);
1222
1223 tp->indexes = &tp->shared->indexes;
1224 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1225 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1226 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1227 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1228 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1229 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1230 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1231
1232 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1233 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1234
1235 tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1236 tp->card_state = Sleeping;
1237
1238 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1239 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1240 tp->offload |= TYPHOON_OFFLOAD_VLAN;
1241
1242 spin_lock_init(&tp->command_lock);
1243
1244 /* Force the writes to the shared memory area out before continuing. */
1245 wmb();
1246}
1247
1248static void
1249typhoon_init_rings(struct typhoon *tp)
1250{
1251 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1252
1253 tp->txLoRing.lastWrite = 0;
1254 tp->txHiRing.lastWrite = 0;
1255 tp->rxLoRing.lastWrite = 0;
1256 tp->rxHiRing.lastWrite = 0;
1257 tp->rxBuffRing.lastWrite = 0;
1258 tp->cmdRing.lastWrite = 0;
1259 tp->respRing.lastWrite = 0;
1260
1261 tp->txLoRing.lastRead = 0;
1262 tp->txHiRing.lastRead = 0;
1263}
1264
1265static const struct firmware *typhoon_fw;
1266
1267static int
1268typhoon_request_firmware(struct typhoon *tp)
1269{
1270 const struct typhoon_file_header *fHdr;
1271 const struct typhoon_section_header *sHdr;
1272 const u8 *image_data;
1273 u32 numSections;
1274 u32 section_len;
1275 u32 remaining;
1276 int err;
1277
1278 if (typhoon_fw)
1279 return 0;
1280
1281 err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1282 if (err) {
1283 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1284 FIRMWARE_NAME);
1285 return err;
1286 }
1287
1288 image_data = typhoon_fw->data;
1289 remaining = typhoon_fw->size;
1290 if (remaining < sizeof(struct typhoon_file_header))
1291 goto invalid_fw;
1292
1293 fHdr = (struct typhoon_file_header *) image_data;
1294 if (memcmp(fHdr->tag, "TYPHOON", 8))
1295 goto invalid_fw;
1296
1297 numSections = le32_to_cpu(fHdr->numSections);
1298 image_data += sizeof(struct typhoon_file_header);
1299 remaining -= sizeof(struct typhoon_file_header);
1300
1301 while (numSections--) {
1302 if (remaining < sizeof(struct typhoon_section_header))
1303 goto invalid_fw;
1304
1305 sHdr = (struct typhoon_section_header *) image_data;
1306 image_data += sizeof(struct typhoon_section_header);
1307 section_len = le32_to_cpu(sHdr->len);
1308
1309 if (remaining < section_len)
1310 goto invalid_fw;
1311
1312 image_data += section_len;
1313 remaining -= section_len;
1314 }
1315
1316 return 0;
1317
1318invalid_fw:
1319 netdev_err(tp->dev, "Invalid firmware image\n");
1320 release_firmware(typhoon_fw);
1321 typhoon_fw = NULL;
1322 return -EINVAL;
1323}
1324
1325static int
1326typhoon_download_firmware(struct typhoon *tp)
1327{
1328 void __iomem *ioaddr = tp->ioaddr;
1329 struct pci_dev *pdev = tp->pdev;
1330 const struct typhoon_file_header *fHdr;
1331 const struct typhoon_section_header *sHdr;
1332 const u8 *image_data;
1333 void *dpage;
1334 dma_addr_t dpage_dma;
1335 __sum16 csum;
1336 u32 irqEnabled;
1337 u32 irqMasked;
1338 u32 numSections;
1339 u32 section_len;
1340 u32 len;
1341 u32 load_addr;
1342 u32 hmac;
1343 int i;
1344 int err;
1345
1346 image_data = typhoon_fw->data;
1347 fHdr = (struct typhoon_file_header *) image_data;
1348
1349 /* Cannot just map the firmware image using dma_map_single() as
1350 * the firmware is vmalloc()'d and may not be physically contiguous,
1351 * so we allocate some coherent memory to copy the sections into.
1352 */
1353 err = -ENOMEM;
1354 dpage = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &dpage_dma, GFP_ATOMIC);
1355 if (!dpage) {
1356 netdev_err(tp->dev, "no DMA mem for firmware\n");
1357 goto err_out;
1358 }
1359
1360 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1361 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1362 ioaddr + TYPHOON_REG_INTR_ENABLE);
1363 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1364 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1365 ioaddr + TYPHOON_REG_INTR_MASK);
1366
1367 err = -ETIMEDOUT;
1368 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1369 netdev_err(tp->dev, "card ready timeout\n");
1370 goto err_out_irq;
1371 }
1372
1373 numSections = le32_to_cpu(fHdr->numSections);
1374 load_addr = le32_to_cpu(fHdr->startAddr);
1375
1376 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1377 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1378 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1379 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1380 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1381 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1382 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1383 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1384 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1385 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1386 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1387 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1388 typhoon_post_pci_writes(ioaddr);
1389 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1390
1391 image_data += sizeof(struct typhoon_file_header);
1392
1393 /* The ioread32() in typhoon_wait_interrupt() will force the
1394 * last write to the command register to post, so
1395 * we don't need a typhoon_post_pci_writes() after it.
1396 */
1397 for (i = 0; i < numSections; i++) {
1398 sHdr = (struct typhoon_section_header *) image_data;
1399 image_data += sizeof(struct typhoon_section_header);
1400 load_addr = le32_to_cpu(sHdr->startAddr);
1401 section_len = le32_to_cpu(sHdr->len);
1402
1403 while (section_len) {
1404 len = min_t(u32, section_len, PAGE_SIZE);
1405
1406 if (typhoon_wait_interrupt(ioaddr) < 0 ||
1407 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1408 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1409 netdev_err(tp->dev, "segment ready timeout\n");
1410 goto err_out_irq;
1411 }
1412
1413 /* Do an pseudo IPv4 checksum on the data -- first
1414 * need to convert each u16 to cpu order before
1415 * summing. Fortunately, due to the properties of
1416 * the checksum, we can do this once, at the end.
1417 */
1418 csum = csum_fold(csum_partial_copy_nocheck(image_data,
1419 dpage, len));
1420
1421 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1422 iowrite32(le16_to_cpu((__force __le16)csum),
1423 ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1424 iowrite32(load_addr,
1425 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1426 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1427 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1428 typhoon_post_pci_writes(ioaddr);
1429 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1430 ioaddr + TYPHOON_REG_COMMAND);
1431
1432 image_data += len;
1433 load_addr += len;
1434 section_len -= len;
1435 }
1436 }
1437
1438 if (typhoon_wait_interrupt(ioaddr) < 0 ||
1439 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1440 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1441 netdev_err(tp->dev, "final segment ready timeout\n");
1442 goto err_out_irq;
1443 }
1444
1445 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1446
1447 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1448 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1449 ioread32(ioaddr + TYPHOON_REG_STATUS));
1450 goto err_out_irq;
1451 }
1452
1453 err = 0;
1454
1455err_out_irq:
1456 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1457 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1458
1459 dma_free_coherent(&pdev->dev, PAGE_SIZE, dpage, dpage_dma);
1460
1461err_out:
1462 return err;
1463}
1464
1465static int
1466typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1467{
1468 void __iomem *ioaddr = tp->ioaddr;
1469
1470 if (typhoon_wait_status(ioaddr, initial_status) < 0) {
1471 netdev_err(tp->dev, "boot ready timeout\n");
1472 goto out_timeout;
1473 }
1474
1475 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1476 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1477 typhoon_post_pci_writes(ioaddr);
1478 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1479 ioaddr + TYPHOON_REG_COMMAND);
1480
1481 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1482 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1483 ioread32(ioaddr + TYPHOON_REG_STATUS));
1484 goto out_timeout;
1485 }
1486
1487 /* Clear the Transmit and Command ready registers
1488 */
1489 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1490 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1491 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1492 typhoon_post_pci_writes(ioaddr);
1493 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1494
1495 return 0;
1496
1497out_timeout:
1498 return -ETIMEDOUT;
1499}
1500
1501static u32
1502typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1503 volatile __le32 * index)
1504{
1505 u32 lastRead = txRing->lastRead;
1506 struct tx_desc *tx;
1507 dma_addr_t skb_dma;
1508 int dma_len;
1509 int type;
1510
1511 while (lastRead != le32_to_cpu(*index)) {
1512 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1513 type = tx->flags & TYPHOON_TYPE_MASK;
1514
1515 if (type == TYPHOON_TX_DESC) {
1516 /* This tx_desc describes a packet.
1517 */
1518 unsigned long ptr = tx->tx_addr;
1519 struct sk_buff *skb = (struct sk_buff *) ptr;
1520 dev_kfree_skb_irq(skb);
1521 } else if (type == TYPHOON_FRAG_DESC) {
1522 /* This tx_desc describes a memory mapping. Free it.
1523 */
1524 skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1525 dma_len = le16_to_cpu(tx->len);
1526 dma_unmap_single(&tp->pdev->dev, skb_dma, dma_len,
1527 DMA_TO_DEVICE);
1528 }
1529
1530 tx->flags = 0;
1531 typhoon_inc_tx_index(&lastRead, 1);
1532 }
1533
1534 return lastRead;
1535}
1536
1537static void
1538typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1539 volatile __le32 * index)
1540{
1541 u32 lastRead;
1542 int numDesc = MAX_SKB_FRAGS + 1;
1543
1544 /* This will need changing if we start to use the Hi Tx ring. */
1545 lastRead = typhoon_clean_tx(tp, txRing, index);
1546 if (netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1547 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1548 netif_wake_queue(tp->dev);
1549
1550 txRing->lastRead = lastRead;
1551 smp_wmb();
1552}
1553
1554static void
1555typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1556{
1557 struct typhoon_indexes *indexes = tp->indexes;
1558 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1559 struct basic_ring *ring = &tp->rxBuffRing;
1560 struct rx_free *r;
1561
1562 if ((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1563 le32_to_cpu(indexes->rxBuffCleared)) {
1564 /* no room in ring, just drop the skb
1565 */
1566 dev_kfree_skb_any(rxb->skb);
1567 rxb->skb = NULL;
1568 return;
1569 }
1570
1571 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1572 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1573 r->virtAddr = idx;
1574 r->physAddr = cpu_to_le32(rxb->dma_addr);
1575
1576 /* Tell the card about it */
1577 wmb();
1578 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1579}
1580
1581static int
1582typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1583{
1584 struct typhoon_indexes *indexes = tp->indexes;
1585 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1586 struct basic_ring *ring = &tp->rxBuffRing;
1587 struct rx_free *r;
1588 struct sk_buff *skb;
1589 dma_addr_t dma_addr;
1590
1591 rxb->skb = NULL;
1592
1593 if ((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1594 le32_to_cpu(indexes->rxBuffCleared))
1595 return -ENOMEM;
1596
1597 skb = netdev_alloc_skb(tp->dev, PKT_BUF_SZ);
1598 if (!skb)
1599 return -ENOMEM;
1600
1601#if 0
1602 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1603 * address! Pretty please?
1604 */
1605 skb_reserve(skb, 2);
1606#endif
1607
1608 dma_addr = dma_map_single(&tp->pdev->dev, skb->data, PKT_BUF_SZ,
1609 DMA_FROM_DEVICE);
1610
1611 /* Since no card does 64 bit DAC, the high bits will never
1612 * change from zero.
1613 */
1614 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1615 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1616 r->virtAddr = idx;
1617 r->physAddr = cpu_to_le32(dma_addr);
1618 rxb->skb = skb;
1619 rxb->dma_addr = dma_addr;
1620
1621 /* Tell the card about it */
1622 wmb();
1623 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1624 return 0;
1625}
1626
1627static int
1628typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1629 volatile __le32 * cleared, int budget)
1630{
1631 struct rx_desc *rx;
1632 struct sk_buff *skb, *new_skb;
1633 struct rxbuff_ent *rxb;
1634 dma_addr_t dma_addr;
1635 u32 local_ready;
1636 u32 rxaddr;
1637 int pkt_len;
1638 u32 idx;
1639 __le32 csum_bits;
1640 int received;
1641
1642 received = 0;
1643 local_ready = le32_to_cpu(*ready);
1644 rxaddr = le32_to_cpu(*cleared);
1645 while (rxaddr != local_ready && budget > 0) {
1646 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1647 idx = rx->addr;
1648 rxb = &tp->rxbuffers[idx];
1649 skb = rxb->skb;
1650 dma_addr = rxb->dma_addr;
1651
1652 typhoon_inc_rx_index(&rxaddr, 1);
1653
1654 if (rx->flags & TYPHOON_RX_ERROR) {
1655 typhoon_recycle_rx_skb(tp, idx);
1656 continue;
1657 }
1658
1659 pkt_len = le16_to_cpu(rx->frameLen);
1660
1661 if (pkt_len < rx_copybreak &&
1662 (new_skb = netdev_alloc_skb(tp->dev, pkt_len + 2)) != NULL) {
1663 skb_reserve(new_skb, 2);
1664 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr,
1665 PKT_BUF_SZ, DMA_FROM_DEVICE);
1666 skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1667 dma_sync_single_for_device(&tp->pdev->dev, dma_addr,
1668 PKT_BUF_SZ,
1669 DMA_FROM_DEVICE);
1670 skb_put(new_skb, pkt_len);
1671 typhoon_recycle_rx_skb(tp, idx);
1672 } else {
1673 new_skb = skb;
1674 skb_put(new_skb, pkt_len);
1675 dma_unmap_single(&tp->pdev->dev, dma_addr, PKT_BUF_SZ,
1676 DMA_FROM_DEVICE);
1677 typhoon_alloc_rx_skb(tp, idx);
1678 }
1679 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1680 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1681 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1682 if (csum_bits ==
1683 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1684 csum_bits ==
1685 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1686 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1687 } else
1688 skb_checksum_none_assert(new_skb);
1689
1690 if (rx->rxStatus & TYPHOON_RX_VLAN)
1691 __vlan_hwaccel_put_tag(new_skb, htons(ETH_P_8021Q),
1692 ntohl(rx->vlanTag) & 0xffff);
1693 netif_receive_skb(new_skb);
1694
1695 received++;
1696 budget--;
1697 }
1698 *cleared = cpu_to_le32(rxaddr);
1699
1700 return received;
1701}
1702
1703static void
1704typhoon_fill_free_ring(struct typhoon *tp)
1705{
1706 u32 i;
1707
1708 for (i = 0; i < RXENT_ENTRIES; i++) {
1709 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1710 if (rxb->skb)
1711 continue;
1712 if (typhoon_alloc_rx_skb(tp, i) < 0)
1713 break;
1714 }
1715}
1716
1717static int
1718typhoon_poll(struct napi_struct *napi, int budget)
1719{
1720 struct typhoon *tp = container_of(napi, struct typhoon, napi);
1721 struct typhoon_indexes *indexes = tp->indexes;
1722 int work_done;
1723
1724 rmb();
1725 if (!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1726 typhoon_process_response(tp, 0, NULL);
1727
1728 if (le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1729 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1730
1731 work_done = 0;
1732
1733 if (indexes->rxHiCleared != indexes->rxHiReady) {
1734 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1735 &indexes->rxHiCleared, budget);
1736 }
1737
1738 if (indexes->rxLoCleared != indexes->rxLoReady) {
1739 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1740 &indexes->rxLoCleared, budget - work_done);
1741 }
1742
1743 if (le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1744 /* rxBuff ring is empty, try to fill it. */
1745 typhoon_fill_free_ring(tp);
1746 }
1747
1748 if (work_done < budget) {
1749 napi_complete_done(napi, work_done);
1750 iowrite32(TYPHOON_INTR_NONE,
1751 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1752 typhoon_post_pci_writes(tp->ioaddr);
1753 }
1754
1755 return work_done;
1756}
1757
1758static irqreturn_t
1759typhoon_interrupt(int irq, void *dev_instance)
1760{
1761 struct net_device *dev = dev_instance;
1762 struct typhoon *tp = netdev_priv(dev);
1763 void __iomem *ioaddr = tp->ioaddr;
1764 u32 intr_status;
1765
1766 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1767 if (!(intr_status & TYPHOON_INTR_HOST_INT))
1768 return IRQ_NONE;
1769
1770 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1771
1772 if (napi_schedule_prep(&tp->napi)) {
1773 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1774 typhoon_post_pci_writes(ioaddr);
1775 __napi_schedule(&tp->napi);
1776 } else {
1777 netdev_err(dev, "Error, poll already scheduled\n");
1778 }
1779 return IRQ_HANDLED;
1780}
1781
1782static void
1783typhoon_free_rx_rings(struct typhoon *tp)
1784{
1785 u32 i;
1786
1787 for (i = 0; i < RXENT_ENTRIES; i++) {
1788 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1789 if (rxb->skb) {
1790 dma_unmap_single(&tp->pdev->dev, rxb->dma_addr,
1791 PKT_BUF_SZ, DMA_FROM_DEVICE);
1792 dev_kfree_skb(rxb->skb);
1793 rxb->skb = NULL;
1794 }
1795 }
1796}
1797
1798static int
1799typhoon_sleep_early(struct typhoon *tp, __le16 events)
1800{
1801 void __iomem *ioaddr = tp->ioaddr;
1802 struct cmd_desc xp_cmd;
1803 int err;
1804
1805 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1806 xp_cmd.parm1 = events;
1807 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1808 if (err < 0) {
1809 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1810 err);
1811 return err;
1812 }
1813
1814 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1815 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1816 if (err < 0) {
1817 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1818 return err;
1819 }
1820
1821 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1822 return -ETIMEDOUT;
1823
1824 /* Since we cannot monitor the status of the link while sleeping,
1825 * tell the world it went away.
1826 */
1827 netif_carrier_off(tp->dev);
1828
1829 return 0;
1830}
1831
1832static int
1833typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1834{
1835 int err;
1836
1837 err = typhoon_sleep_early(tp, events);
1838
1839 if (err)
1840 return err;
1841
1842 pci_enable_wake(tp->pdev, state, 1);
1843 pci_disable_device(tp->pdev);
1844 return pci_set_power_state(tp->pdev, state);
1845}
1846
1847static int
1848typhoon_wakeup(struct typhoon *tp, int wait_type)
1849{
1850 void __iomem *ioaddr = tp->ioaddr;
1851
1852 /* Post 2.x.x versions of the Sleep Image require a reset before
1853 * we can download the Runtime Image. But let's not make users of
1854 * the old firmware pay for the reset.
1855 */
1856 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1857 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1858 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1859 return typhoon_reset(ioaddr, wait_type);
1860
1861 return 0;
1862}
1863
1864static int
1865typhoon_start_runtime(struct typhoon *tp)
1866{
1867 struct net_device *dev = tp->dev;
1868 void __iomem *ioaddr = tp->ioaddr;
1869 struct cmd_desc xp_cmd;
1870 int err;
1871
1872 typhoon_init_rings(tp);
1873 typhoon_fill_free_ring(tp);
1874
1875 err = typhoon_download_firmware(tp);
1876 if (err < 0) {
1877 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1878 goto error_out;
1879 }
1880
1881 if (typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1882 netdev_err(tp->dev, "cannot boot 3XP\n");
1883 err = -EIO;
1884 goto error_out;
1885 }
1886
1887 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1888 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1889 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1890 if (err < 0)
1891 goto error_out;
1892
1893 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1894 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1895 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1896 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1897 if (err < 0)
1898 goto error_out;
1899
1900 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1901 * us some more information on how to control it.
1902 */
1903 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1904 xp_cmd.parm1 = 0;
1905 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1906 if (err < 0)
1907 goto error_out;
1908
1909 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1910 xp_cmd.parm1 = tp->xcvr_select;
1911 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1912 if (err < 0)
1913 goto error_out;
1914
1915 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1916 xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1917 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1918 if (err < 0)
1919 goto error_out;
1920
1921 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1922 xp_cmd.parm2 = tp->offload;
1923 xp_cmd.parm3 = tp->offload;
1924 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1925 if (err < 0)
1926 goto error_out;
1927
1928 typhoon_set_rx_mode(dev);
1929
1930 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1931 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1932 if (err < 0)
1933 goto error_out;
1934
1935 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1936 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1937 if (err < 0)
1938 goto error_out;
1939
1940 tp->card_state = Running;
1941 smp_wmb();
1942
1943 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1944 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1945 typhoon_post_pci_writes(ioaddr);
1946
1947 return 0;
1948
1949error_out:
1950 typhoon_reset(ioaddr, WaitNoSleep);
1951 typhoon_free_rx_rings(tp);
1952 typhoon_init_rings(tp);
1953 return err;
1954}
1955
1956static int
1957typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1958{
1959 struct typhoon_indexes *indexes = tp->indexes;
1960 struct transmit_ring *txLo = &tp->txLoRing;
1961 void __iomem *ioaddr = tp->ioaddr;
1962 struct cmd_desc xp_cmd;
1963 int i;
1964
1965 /* Disable interrupts early, since we can't schedule a poll
1966 * when called with !netif_running(). This will be posted
1967 * when we force the posting of the command.
1968 */
1969 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
1970
1971 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
1972 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1973
1974 /* Wait 1/2 sec for any outstanding transmits to occur
1975 * We'll cleanup after the reset if this times out.
1976 */
1977 for (i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1978 if (indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
1979 break;
1980 udelay(TYPHOON_UDELAY);
1981 }
1982
1983 if (i == TYPHOON_WAIT_TIMEOUT)
1984 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
1985
1986 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
1987 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1988
1989 /* save the statistics so when we bring the interface up again,
1990 * the values reported to userspace are correct.
1991 */
1992 tp->card_state = Sleeping;
1993 smp_wmb();
1994 typhoon_do_get_stats(tp);
1995 memcpy(&tp->stats_saved, &tp->dev->stats, sizeof(struct net_device_stats));
1996
1997 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
1998 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1999
2000 if (typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2001 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
2002
2003 if (typhoon_reset(ioaddr, wait_type) < 0) {
2004 netdev_err(tp->dev, "unable to reset 3XP\n");
2005 return -ETIMEDOUT;
2006 }
2007
2008 /* cleanup any outstanding Tx packets */
2009 if (indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2010 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2011 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2012 }
2013
2014 return 0;
2015}
2016
2017static void
2018typhoon_tx_timeout(struct net_device *dev, unsigned int txqueue)
2019{
2020 struct typhoon *tp = netdev_priv(dev);
2021
2022 if (typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2023 netdev_warn(dev, "could not reset in tx timeout\n");
2024 goto truly_dead;
2025 }
2026
2027 /* If we ever start using the Hi ring, it will need cleaning too */
2028 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2029 typhoon_free_rx_rings(tp);
2030
2031 if (typhoon_start_runtime(tp) < 0) {
2032 netdev_err(dev, "could not start runtime in tx timeout\n");
2033 goto truly_dead;
2034 }
2035
2036 netif_wake_queue(dev);
2037 return;
2038
2039truly_dead:
2040 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2041 typhoon_reset(tp->ioaddr, NoWait);
2042 netif_carrier_off(dev);
2043}
2044
2045static int
2046typhoon_open(struct net_device *dev)
2047{
2048 struct typhoon *tp = netdev_priv(dev);
2049 int err;
2050
2051 err = typhoon_request_firmware(tp);
2052 if (err)
2053 goto out;
2054
2055 pci_set_power_state(tp->pdev, PCI_D0);
2056 pci_restore_state(tp->pdev);
2057
2058 err = typhoon_wakeup(tp, WaitSleep);
2059 if (err < 0) {
2060 netdev_err(dev, "unable to wakeup device\n");
2061 goto out_sleep;
2062 }
2063
2064 err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2065 dev->name, dev);
2066 if (err < 0)
2067 goto out_sleep;
2068
2069 napi_enable(&tp->napi);
2070
2071 err = typhoon_start_runtime(tp);
2072 if (err < 0) {
2073 napi_disable(&tp->napi);
2074 goto out_irq;
2075 }
2076
2077 netif_start_queue(dev);
2078 return 0;
2079
2080out_irq:
2081 free_irq(dev->irq, dev);
2082
2083out_sleep:
2084 if (typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2085 netdev_err(dev, "unable to reboot into sleep img\n");
2086 typhoon_reset(tp->ioaddr, NoWait);
2087 goto out;
2088 }
2089
2090 if (typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2091 netdev_err(dev, "unable to go back to sleep\n");
2092
2093out:
2094 return err;
2095}
2096
2097static int
2098typhoon_close(struct net_device *dev)
2099{
2100 struct typhoon *tp = netdev_priv(dev);
2101
2102 netif_stop_queue(dev);
2103 napi_disable(&tp->napi);
2104
2105 if (typhoon_stop_runtime(tp, WaitSleep) < 0)
2106 netdev_err(dev, "unable to stop runtime\n");
2107
2108 /* Make sure there is no irq handler running on a different CPU. */
2109 free_irq(dev->irq, dev);
2110
2111 typhoon_free_rx_rings(tp);
2112 typhoon_init_rings(tp);
2113
2114 if (typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2115 netdev_err(dev, "unable to boot sleep image\n");
2116
2117 if (typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2118 netdev_err(dev, "unable to put card to sleep\n");
2119
2120 return 0;
2121}
2122
2123static int __maybe_unused
2124typhoon_resume(struct device *dev_d)
2125{
2126 struct net_device *dev = dev_get_drvdata(dev_d);
2127 struct typhoon *tp = netdev_priv(dev);
2128
2129 /* If we're down, resume when we are upped.
2130 */
2131 if (!netif_running(dev))
2132 return 0;
2133
2134 if (typhoon_wakeup(tp, WaitNoSleep) < 0) {
2135 netdev_err(dev, "critical: could not wake up in resume\n");
2136 goto reset;
2137 }
2138
2139 if (typhoon_start_runtime(tp) < 0) {
2140 netdev_err(dev, "critical: could not start runtime in resume\n");
2141 goto reset;
2142 }
2143
2144 netif_device_attach(dev);
2145 return 0;
2146
2147reset:
2148 typhoon_reset(tp->ioaddr, NoWait);
2149 return -EBUSY;
2150}
2151
2152static int __maybe_unused
2153typhoon_suspend(struct device *dev_d)
2154{
2155 struct pci_dev *pdev = to_pci_dev(dev_d);
2156 struct net_device *dev = pci_get_drvdata(pdev);
2157 struct typhoon *tp = netdev_priv(dev);
2158 struct cmd_desc xp_cmd;
2159
2160 /* If we're down, we're already suspended.
2161 */
2162 if (!netif_running(dev))
2163 return 0;
2164
2165 /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2166 if (tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2167 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2168
2169 netif_device_detach(dev);
2170
2171 if (typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2172 netdev_err(dev, "unable to stop runtime\n");
2173 goto need_resume;
2174 }
2175
2176 typhoon_free_rx_rings(tp);
2177 typhoon_init_rings(tp);
2178
2179 if (typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2180 netdev_err(dev, "unable to boot sleep image\n");
2181 goto need_resume;
2182 }
2183
2184 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2185 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2186 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2187 if (typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2188 netdev_err(dev, "unable to set mac address in suspend\n");
2189 goto need_resume;
2190 }
2191
2192 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2193 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2194 if (typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2195 netdev_err(dev, "unable to set rx filter in suspend\n");
2196 goto need_resume;
2197 }
2198
2199 if (typhoon_sleep_early(tp, tp->wol_events) < 0) {
2200 netdev_err(dev, "unable to put card to sleep\n");
2201 goto need_resume;
2202 }
2203
2204 device_wakeup_enable(dev_d);
2205
2206 return 0;
2207
2208need_resume:
2209 typhoon_resume(dev_d);
2210 return -EBUSY;
2211}
2212
2213static int
2214typhoon_test_mmio(struct pci_dev *pdev)
2215{
2216 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2217 int mode = 0;
2218 u32 val;
2219
2220 if (!ioaddr)
2221 goto out;
2222
2223 if (ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2224 TYPHOON_STATUS_WAITING_FOR_HOST)
2225 goto out_unmap;
2226
2227 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2228 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2229 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2230
2231 /* Ok, see if we can change our interrupt status register by
2232 * sending ourselves an interrupt. If so, then MMIO works.
2233 * The 50usec delay is arbitrary -- it could probably be smaller.
2234 */
2235 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2236 if ((val & TYPHOON_INTR_SELF) == 0) {
2237 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2238 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2239 udelay(50);
2240 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2241 if (val & TYPHOON_INTR_SELF)
2242 mode = 1;
2243 }
2244
2245 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2246 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2247 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2248 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2249
2250out_unmap:
2251 pci_iounmap(pdev, ioaddr);
2252
2253out:
2254 if (!mode)
2255 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2256 return mode;
2257}
2258
2259#if MAX_SKB_FRAGS > 32
2260
2261#include <net/vxlan.h>
2262
2263static netdev_features_t typhoon_features_check(struct sk_buff *skb,
2264 struct net_device *dev,
2265 netdev_features_t features)
2266{
2267 if (skb_shinfo(skb)->nr_frags > 32 && skb_is_gso(skb))
2268 features &= ~NETIF_F_GSO_MASK;
2269
2270 features = vlan_features_check(skb, features);
2271 return vxlan_features_check(skb, features);
2272}
2273#endif
2274
2275static const struct net_device_ops typhoon_netdev_ops = {
2276 .ndo_open = typhoon_open,
2277 .ndo_stop = typhoon_close,
2278#if MAX_SKB_FRAGS > 32
2279 .ndo_features_check = typhoon_features_check,
2280#endif
2281 .ndo_start_xmit = typhoon_start_tx,
2282 .ndo_set_rx_mode = typhoon_set_rx_mode,
2283 .ndo_tx_timeout = typhoon_tx_timeout,
2284 .ndo_get_stats = typhoon_get_stats,
2285 .ndo_validate_addr = eth_validate_addr,
2286 .ndo_set_mac_address = eth_mac_addr,
2287};
2288
2289static int
2290typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2291{
2292 struct net_device *dev;
2293 struct typhoon *tp;
2294 int card_id = (int) ent->driver_data;
2295 u8 addr[ETH_ALEN] __aligned(4);
2296 void __iomem *ioaddr;
2297 void *shared;
2298 dma_addr_t shared_dma;
2299 struct cmd_desc xp_cmd;
2300 struct resp_desc xp_resp[3];
2301 int err = 0;
2302 const char *err_msg;
2303
2304 dev = alloc_etherdev(sizeof(*tp));
2305 if (dev == NULL) {
2306 err_msg = "unable to alloc new net device";
2307 err = -ENOMEM;
2308 goto error_out;
2309 }
2310 SET_NETDEV_DEV(dev, &pdev->dev);
2311
2312 err = pci_enable_device(pdev);
2313 if (err < 0) {
2314 err_msg = "unable to enable device";
2315 goto error_out_dev;
2316 }
2317
2318 err = pci_set_mwi(pdev);
2319 if (err < 0) {
2320 err_msg = "unable to set MWI";
2321 goto error_out_disable;
2322 }
2323
2324 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2325 if (err < 0) {
2326 err_msg = "No usable DMA configuration";
2327 goto error_out_mwi;
2328 }
2329
2330 /* sanity checks on IO and MMIO BARs
2331 */
2332 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2333 err_msg = "region #1 not a PCI IO resource, aborting";
2334 err = -ENODEV;
2335 goto error_out_mwi;
2336 }
2337 if (pci_resource_len(pdev, 0) < 128) {
2338 err_msg = "Invalid PCI IO region size, aborting";
2339 err = -ENODEV;
2340 goto error_out_mwi;
2341 }
2342 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2343 err_msg = "region #1 not a PCI MMIO resource, aborting";
2344 err = -ENODEV;
2345 goto error_out_mwi;
2346 }
2347 if (pci_resource_len(pdev, 1) < 128) {
2348 err_msg = "Invalid PCI MMIO region size, aborting";
2349 err = -ENODEV;
2350 goto error_out_mwi;
2351 }
2352
2353 err = pci_request_regions(pdev, KBUILD_MODNAME);
2354 if (err < 0) {
2355 err_msg = "could not request regions";
2356 goto error_out_mwi;
2357 }
2358
2359 /* map our registers
2360 */
2361 if (use_mmio != 0 && use_mmio != 1)
2362 use_mmio = typhoon_test_mmio(pdev);
2363
2364 ioaddr = pci_iomap(pdev, use_mmio, 128);
2365 if (!ioaddr) {
2366 err_msg = "cannot remap registers, aborting";
2367 err = -EIO;
2368 goto error_out_regions;
2369 }
2370
2371 /* allocate pci dma space for rx and tx descriptor rings
2372 */
2373 shared = dma_alloc_coherent(&pdev->dev, sizeof(struct typhoon_shared),
2374 &shared_dma, GFP_KERNEL);
2375 if (!shared) {
2376 err_msg = "could not allocate DMA memory";
2377 err = -ENOMEM;
2378 goto error_out_remap;
2379 }
2380
2381 dev->irq = pdev->irq;
2382 tp = netdev_priv(dev);
2383 tp->shared = shared;
2384 tp->shared_dma = shared_dma;
2385 tp->pdev = pdev;
2386 tp->tx_pdev = pdev;
2387 tp->ioaddr = ioaddr;
2388 tp->tx_ioaddr = ioaddr;
2389 tp->dev = dev;
2390
2391 /* Init sequence:
2392 * 1) Reset the adapter to clear any bad juju
2393 * 2) Reload the sleep image
2394 * 3) Boot the sleep image
2395 * 4) Get the hardware address.
2396 * 5) Put the card to sleep.
2397 */
2398 err = typhoon_reset(ioaddr, WaitSleep);
2399 if (err < 0) {
2400 err_msg = "could not reset 3XP";
2401 goto error_out_dma;
2402 }
2403
2404 /* Now that we've reset the 3XP and are sure it's not going to
2405 * write all over memory, enable bus mastering, and save our
2406 * state for resuming after a suspend.
2407 */
2408 pci_set_master(pdev);
2409 pci_save_state(pdev);
2410
2411 typhoon_init_interface(tp);
2412 typhoon_init_rings(tp);
2413
2414 err = typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST);
2415 if (err < 0) {
2416 err_msg = "cannot boot 3XP sleep image";
2417 goto error_out_reset;
2418 }
2419
2420 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2421 err = typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp);
2422 if (err < 0) {
2423 err_msg = "cannot read MAC address";
2424 goto error_out_reset;
2425 }
2426
2427 *(__be16 *)&addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2428 *(__be32 *)&addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2429 eth_hw_addr_set(dev, addr);
2430
2431 if (!is_valid_ether_addr(dev->dev_addr)) {
2432 err_msg = "Could not obtain valid ethernet address, aborting";
2433 err = -EIO;
2434 goto error_out_reset;
2435 }
2436
2437 /* Read the Sleep Image version last, so the response is valid
2438 * later when we print out the version reported.
2439 */
2440 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2441 err = typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp);
2442 if (err < 0) {
2443 err_msg = "Could not get Sleep Image version";
2444 goto error_out_reset;
2445 }
2446
2447 tp->capabilities = typhoon_card_info[card_id].capabilities;
2448 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2449
2450 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2451 * READ_VERSIONS command. Those versions are OK after waking up
2452 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2453 * seem to need a little extra help to get started. Since we don't
2454 * know how to nudge it along, just kick it.
2455 */
2456 if (xp_resp[0].numDesc != 0)
2457 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2458
2459 err = typhoon_sleep(tp, PCI_D3hot, 0);
2460 if (err < 0) {
2461 err_msg = "cannot put adapter to sleep";
2462 goto error_out_reset;
2463 }
2464
2465 /* The chip-specific entries in the device structure. */
2466 dev->netdev_ops = &typhoon_netdev_ops;
2467 netif_napi_add_weight(dev, &tp->napi, typhoon_poll, 16);
2468 dev->watchdog_timeo = TX_TIMEOUT;
2469
2470 dev->ethtool_ops = &typhoon_ethtool_ops;
2471
2472 /* We can handle scatter gather, up to 16 entries, and
2473 * we can do IP checksumming (only version 4, doh...)
2474 *
2475 * There's no way to turn off the RX VLAN offloading and stripping
2476 * on the current 3XP firmware -- it does not respect the offload
2477 * settings -- so we only allow the user to toggle the TX processing.
2478 */
2479 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2480 NETIF_F_HW_VLAN_CTAG_TX;
2481 dev->features = dev->hw_features |
2482 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_RXCSUM;
2483
2484 err = register_netdev(dev);
2485 if (err < 0) {
2486 err_msg = "unable to register netdev";
2487 goto error_out_reset;
2488 }
2489
2490 pci_set_drvdata(pdev, dev);
2491
2492 netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2493 typhoon_card_info[card_id].name,
2494 use_mmio ? "MMIO" : "IO",
2495 (unsigned long long)pci_resource_start(pdev, use_mmio),
2496 dev->dev_addr);
2497
2498 /* xp_resp still contains the response to the READ_VERSIONS command.
2499 * For debugging, let the user know what version he has.
2500 */
2501 if (xp_resp[0].numDesc == 0) {
2502 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2503 * of version is Month/Day of build.
2504 */
2505 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2506 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2507 monthday >> 8, monthday & 0xff);
2508 } else if (xp_resp[0].numDesc == 2) {
2509 /* This is the Typhoon 1.1+ type Sleep Image
2510 */
2511 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2512 u8 *ver_string = (u8 *) &xp_resp[1];
2513 ver_string[25] = 0;
2514 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2515 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2516 sleep_ver & 0xfff, ver_string);
2517 } else {
2518 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2519 xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2520 }
2521
2522 return 0;
2523
2524error_out_reset:
2525 typhoon_reset(ioaddr, NoWait);
2526
2527error_out_dma:
2528 dma_free_coherent(&pdev->dev, sizeof(struct typhoon_shared), shared,
2529 shared_dma);
2530error_out_remap:
2531 pci_iounmap(pdev, ioaddr);
2532error_out_regions:
2533 pci_release_regions(pdev);
2534error_out_mwi:
2535 pci_clear_mwi(pdev);
2536error_out_disable:
2537 pci_disable_device(pdev);
2538error_out_dev:
2539 free_netdev(dev);
2540error_out:
2541 pr_err("%s: %s\n", pci_name(pdev), err_msg);
2542 return err;
2543}
2544
2545static void
2546typhoon_remove_one(struct pci_dev *pdev)
2547{
2548 struct net_device *dev = pci_get_drvdata(pdev);
2549 struct typhoon *tp = netdev_priv(dev);
2550
2551 unregister_netdev(dev);
2552 pci_set_power_state(pdev, PCI_D0);
2553 pci_restore_state(pdev);
2554 typhoon_reset(tp->ioaddr, NoWait);
2555 pci_iounmap(pdev, tp->ioaddr);
2556 dma_free_coherent(&pdev->dev, sizeof(struct typhoon_shared),
2557 tp->shared, tp->shared_dma);
2558 pci_release_regions(pdev);
2559 pci_clear_mwi(pdev);
2560 pci_disable_device(pdev);
2561 free_netdev(dev);
2562}
2563
2564static SIMPLE_DEV_PM_OPS(typhoon_pm_ops, typhoon_suspend, typhoon_resume);
2565
2566static struct pci_driver typhoon_driver = {
2567 .name = KBUILD_MODNAME,
2568 .id_table = typhoon_pci_tbl,
2569 .probe = typhoon_init_one,
2570 .remove = typhoon_remove_one,
2571 .driver.pm = &typhoon_pm_ops,
2572};
2573
2574static int __init
2575typhoon_init(void)
2576{
2577 return pci_register_driver(&typhoon_driver);
2578}
2579
2580static void __exit
2581typhoon_cleanup(void)
2582{
2583 release_firmware(typhoon_fw);
2584 pci_unregister_driver(&typhoon_driver);
2585}
2586
2587module_init(typhoon_init);
2588module_exit(typhoon_cleanup);
1/* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
2/*
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
18
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
21 number Y1-LM-2015-01.
22
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
25
26 KNOWN ISSUES:
27 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
28 issue. Hopefully 3Com will fix it.
29 *) Waiting for a command response takes 8ms due to non-preemptable
30 polling. Only significant for getting stats and creating
31 SAs, but an ugly wart never the less.
32
33 TODO:
34 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
35 *) Add more support for ethtool (especially for NIC stats)
36 *) Allow disabling of RX checksum offloading
37 *) Fix MAC changing to work while the interface is up
38 (Need to put commands on the TX ring, which changes
39 the locking)
40 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
41 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
42*/
43
44/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
45 * Setting to > 1518 effectively disables this feature.
46 */
47static int rx_copybreak = 200;
48
49/* Should we use MMIO or Port IO?
50 * 0: Port IO
51 * 1: MMIO
52 * 2: Try MMIO, fallback to Port IO
53 */
54static unsigned int use_mmio = 2;
55
56/* end user-configurable values */
57
58/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
59 */
60static const int multicast_filter_limit = 32;
61
62/* Operational parameters that are set at compile time. */
63
64/* Keep the ring sizes a power of two for compile efficiency.
65 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
66 * Making the Tx ring too large decreases the effectiveness of channel
67 * bonding and packet priority.
68 * There are no ill effects from too-large receive rings.
69 *
70 * We don't currently use the Hi Tx ring so, don't make it very big.
71 *
72 * Beware that if we start using the Hi Tx ring, we will need to change
73 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
74 */
75#define TXHI_ENTRIES 2
76#define TXLO_ENTRIES 128
77#define RX_ENTRIES 32
78#define COMMAND_ENTRIES 16
79#define RESPONSE_ENTRIES 32
80
81#define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
82#define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
83
84/* The 3XP will preload and remove 64 entries from the free buffer
85 * list, and we need one entry to keep the ring from wrapping, so
86 * to keep this a power of two, we use 128 entries.
87 */
88#define RXFREE_ENTRIES 128
89#define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
90
91/* Operational parameters that usually are not changed. */
92
93/* Time in jiffies before concluding the transmitter is hung. */
94#define TX_TIMEOUT (2*HZ)
95
96#define PKT_BUF_SZ 1536
97#define FIRMWARE_NAME "3com/typhoon.bin"
98
99#define pr_fmt(fmt) KBUILD_MODNAME " " fmt
100
101#include <linux/module.h>
102#include <linux/kernel.h>
103#include <linux/sched.h>
104#include <linux/string.h>
105#include <linux/timer.h>
106#include <linux/errno.h>
107#include <linux/ioport.h>
108#include <linux/interrupt.h>
109#include <linux/pci.h>
110#include <linux/netdevice.h>
111#include <linux/etherdevice.h>
112#include <linux/skbuff.h>
113#include <linux/mm.h>
114#include <linux/init.h>
115#include <linux/delay.h>
116#include <linux/ethtool.h>
117#include <linux/if_vlan.h>
118#include <linux/crc32.h>
119#include <linux/bitops.h>
120#include <asm/processor.h>
121#include <asm/io.h>
122#include <asm/uaccess.h>
123#include <linux/in6.h>
124#include <linux/dma-mapping.h>
125#include <linux/firmware.h>
126
127#include "typhoon.h"
128
129MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
130MODULE_VERSION("1.0");
131MODULE_LICENSE("GPL");
132MODULE_FIRMWARE(FIRMWARE_NAME);
133MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
134MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
135 "the buffer given back to the NIC. Default "
136 "is 200.");
137MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
138 "Default is to try MMIO and fallback to PIO.");
139module_param(rx_copybreak, int, 0);
140module_param(use_mmio, int, 0);
141
142#if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
143#warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
144#undef NETIF_F_TSO
145#endif
146
147#if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
148#error TX ring too small!
149#endif
150
151struct typhoon_card_info {
152 const char *name;
153 const int capabilities;
154};
155
156#define TYPHOON_CRYPTO_NONE 0x00
157#define TYPHOON_CRYPTO_DES 0x01
158#define TYPHOON_CRYPTO_3DES 0x02
159#define TYPHOON_CRYPTO_VARIABLE 0x04
160#define TYPHOON_FIBER 0x08
161#define TYPHOON_WAKEUP_NEEDS_RESET 0x10
162
163enum typhoon_cards {
164 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
165 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
166 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
167 TYPHOON_FXM,
168};
169
170/* directly indexed by enum typhoon_cards, above */
171static struct typhoon_card_info typhoon_card_info[] = {
172 { "3Com Typhoon (3C990-TX)",
173 TYPHOON_CRYPTO_NONE},
174 { "3Com Typhoon (3CR990-TX-95)",
175 TYPHOON_CRYPTO_DES},
176 { "3Com Typhoon (3CR990-TX-97)",
177 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
178 { "3Com Typhoon (3C990SVR)",
179 TYPHOON_CRYPTO_NONE},
180 { "3Com Typhoon (3CR990SVR95)",
181 TYPHOON_CRYPTO_DES},
182 { "3Com Typhoon (3CR990SVR97)",
183 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
184 { "3Com Typhoon2 (3C990B-TX-M)",
185 TYPHOON_CRYPTO_VARIABLE},
186 { "3Com Typhoon2 (3C990BSVR)",
187 TYPHOON_CRYPTO_VARIABLE},
188 { "3Com Typhoon (3CR990-FX-95)",
189 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
190 { "3Com Typhoon (3CR990-FX-97)",
191 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
192 { "3Com Typhoon (3CR990-FX-95 Server)",
193 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
194 { "3Com Typhoon (3CR990-FX-97 Server)",
195 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
196 { "3Com Typhoon2 (3C990B-FX-97)",
197 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
198};
199
200/* Notes on the new subsystem numbering scheme:
201 * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
202 * bit 4 indicates if this card has secured firmware (we don't support it)
203 * bit 8 indicates if this is a (0) copper or (1) fiber card
204 * bits 12-16 indicate card type: (0) client and (1) server
205 */
206static const struct pci_device_id typhoon_pci_tbl[] = {
207 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
209 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
211 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
213 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
214 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
215 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
216 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
217 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
218 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
220 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
222 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
224 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
226 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
227 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
229 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
231 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
233 { 0, }
234};
235MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
236
237/* Define the shared memory area
238 * Align everything the 3XP will normally be using.
239 * We'll need to move/align txHi if we start using that ring.
240 */
241#define __3xp_aligned ____cacheline_aligned
242struct typhoon_shared {
243 struct typhoon_interface iface;
244 struct typhoon_indexes indexes __3xp_aligned;
245 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
246 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
247 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
248 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
249 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
250 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
251 u32 zeroWord;
252 struct tx_desc txHi[TXHI_ENTRIES];
253} __packed;
254
255struct rxbuff_ent {
256 struct sk_buff *skb;
257 dma_addr_t dma_addr;
258};
259
260struct typhoon {
261 /* Tx cache line section */
262 struct transmit_ring txLoRing ____cacheline_aligned;
263 struct pci_dev * tx_pdev;
264 void __iomem *tx_ioaddr;
265 u32 txlo_dma_addr;
266
267 /* Irq/Rx cache line section */
268 void __iomem *ioaddr ____cacheline_aligned;
269 struct typhoon_indexes *indexes;
270 u8 awaiting_resp;
271 u8 duplex;
272 u8 speed;
273 u8 card_state;
274 struct basic_ring rxLoRing;
275 struct pci_dev * pdev;
276 struct net_device * dev;
277 struct napi_struct napi;
278 struct basic_ring rxHiRing;
279 struct basic_ring rxBuffRing;
280 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
281
282 /* general section */
283 spinlock_t command_lock ____cacheline_aligned;
284 struct basic_ring cmdRing;
285 struct basic_ring respRing;
286 struct net_device_stats stats;
287 struct net_device_stats stats_saved;
288 struct typhoon_shared * shared;
289 dma_addr_t shared_dma;
290 __le16 xcvr_select;
291 __le16 wol_events;
292 __le32 offload;
293
294 /* unused stuff (future use) */
295 int capabilities;
296 struct transmit_ring txHiRing;
297};
298
299enum completion_wait_values {
300 NoWait = 0, WaitNoSleep, WaitSleep,
301};
302
303/* These are the values for the typhoon.card_state variable.
304 * These determine where the statistics will come from in get_stats().
305 * The sleep image does not support the statistics we need.
306 */
307enum state_values {
308 Sleeping = 0, Running,
309};
310
311/* PCI writes are not guaranteed to be posted in order, but outstanding writes
312 * cannot pass a read, so this forces current writes to post.
313 */
314#define typhoon_post_pci_writes(x) \
315 do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
316
317/* We'll wait up to six seconds for a reset, and half a second normally.
318 */
319#define TYPHOON_UDELAY 50
320#define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
321#define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
322#define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
323
324#if defined(NETIF_F_TSO)
325#define skb_tso_size(x) (skb_shinfo(x)->gso_size)
326#define TSO_NUM_DESCRIPTORS 2
327#define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
328#else
329#define NETIF_F_TSO 0
330#define skb_tso_size(x) 0
331#define TSO_NUM_DESCRIPTORS 0
332#define TSO_OFFLOAD_ON 0
333#endif
334
335static inline void
336typhoon_inc_index(u32 *index, const int count, const int num_entries)
337{
338 /* Increment a ring index -- we can use this for all rings execept
339 * the Rx rings, as they use different size descriptors
340 * otherwise, everything is the same size as a cmd_desc
341 */
342 *index += count * sizeof(struct cmd_desc);
343 *index %= num_entries * sizeof(struct cmd_desc);
344}
345
346static inline void
347typhoon_inc_cmd_index(u32 *index, const int count)
348{
349 typhoon_inc_index(index, count, COMMAND_ENTRIES);
350}
351
352static inline void
353typhoon_inc_resp_index(u32 *index, const int count)
354{
355 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
356}
357
358static inline void
359typhoon_inc_rxfree_index(u32 *index, const int count)
360{
361 typhoon_inc_index(index, count, RXFREE_ENTRIES);
362}
363
364static inline void
365typhoon_inc_tx_index(u32 *index, const int count)
366{
367 /* if we start using the Hi Tx ring, this needs updating */
368 typhoon_inc_index(index, count, TXLO_ENTRIES);
369}
370
371static inline void
372typhoon_inc_rx_index(u32 *index, const int count)
373{
374 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
375 *index += count * sizeof(struct rx_desc);
376 *index %= RX_ENTRIES * sizeof(struct rx_desc);
377}
378
379static int
380typhoon_reset(void __iomem *ioaddr, int wait_type)
381{
382 int i, err = 0;
383 int timeout;
384
385 if(wait_type == WaitNoSleep)
386 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
387 else
388 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
389
390 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
391 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
392
393 iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
394 typhoon_post_pci_writes(ioaddr);
395 udelay(1);
396 iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
397
398 if(wait_type != NoWait) {
399 for(i = 0; i < timeout; i++) {
400 if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
401 TYPHOON_STATUS_WAITING_FOR_HOST)
402 goto out;
403
404 if(wait_type == WaitSleep)
405 schedule_timeout_uninterruptible(1);
406 else
407 udelay(TYPHOON_UDELAY);
408 }
409
410 err = -ETIMEDOUT;
411 }
412
413out:
414 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
415 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
416
417 /* The 3XP seems to need a little extra time to complete the load
418 * of the sleep image before we can reliably boot it. Failure to
419 * do this occasionally results in a hung adapter after boot in
420 * typhoon_init_one() while trying to read the MAC address or
421 * putting the card to sleep. 3Com's driver waits 5ms, but
422 * that seems to be overkill. However, if we can sleep, we might
423 * as well give it that much time. Otherwise, we'll give it 500us,
424 * which should be enough (I've see it work well at 100us, but still
425 * saw occasional problems.)
426 */
427 if(wait_type == WaitSleep)
428 msleep(5);
429 else
430 udelay(500);
431 return err;
432}
433
434static int
435typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
436{
437 int i, err = 0;
438
439 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
440 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
441 goto out;
442 udelay(TYPHOON_UDELAY);
443 }
444
445 err = -ETIMEDOUT;
446
447out:
448 return err;
449}
450
451static inline void
452typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
453{
454 if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
455 netif_carrier_off(dev);
456 else
457 netif_carrier_on(dev);
458}
459
460static inline void
461typhoon_hello(struct typhoon *tp)
462{
463 struct basic_ring *ring = &tp->cmdRing;
464 struct cmd_desc *cmd;
465
466 /* We only get a hello request if we've not sent anything to the
467 * card in a long while. If the lock is held, then we're in the
468 * process of issuing a command, so we don't need to respond.
469 */
470 if(spin_trylock(&tp->command_lock)) {
471 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
472 typhoon_inc_cmd_index(&ring->lastWrite, 1);
473
474 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
475 wmb();
476 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
477 spin_unlock(&tp->command_lock);
478 }
479}
480
481static int
482typhoon_process_response(struct typhoon *tp, int resp_size,
483 struct resp_desc *resp_save)
484{
485 struct typhoon_indexes *indexes = tp->indexes;
486 struct resp_desc *resp;
487 u8 *base = tp->respRing.ringBase;
488 int count, len, wrap_len;
489 u32 cleared;
490 u32 ready;
491
492 cleared = le32_to_cpu(indexes->respCleared);
493 ready = le32_to_cpu(indexes->respReady);
494 while(cleared != ready) {
495 resp = (struct resp_desc *)(base + cleared);
496 count = resp->numDesc + 1;
497 if(resp_save && resp->seqNo) {
498 if(count > resp_size) {
499 resp_save->flags = TYPHOON_RESP_ERROR;
500 goto cleanup;
501 }
502
503 wrap_len = 0;
504 len = count * sizeof(*resp);
505 if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
506 wrap_len = cleared + len - RESPONSE_RING_SIZE;
507 len = RESPONSE_RING_SIZE - cleared;
508 }
509
510 memcpy(resp_save, resp, len);
511 if(unlikely(wrap_len)) {
512 resp_save += len / sizeof(*resp);
513 memcpy(resp_save, base, wrap_len);
514 }
515
516 resp_save = NULL;
517 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
518 typhoon_media_status(tp->dev, resp);
519 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
520 typhoon_hello(tp);
521 } else {
522 netdev_err(tp->dev,
523 "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
524 le16_to_cpu(resp->cmd),
525 resp->numDesc, resp->flags,
526 le16_to_cpu(resp->parm1),
527 le32_to_cpu(resp->parm2),
528 le32_to_cpu(resp->parm3));
529 }
530
531cleanup:
532 typhoon_inc_resp_index(&cleared, count);
533 }
534
535 indexes->respCleared = cpu_to_le32(cleared);
536 wmb();
537 return resp_save == NULL;
538}
539
540static inline int
541typhoon_num_free(int lastWrite, int lastRead, int ringSize)
542{
543 /* this works for all descriptors but rx_desc, as they are a
544 * different size than the cmd_desc -- everyone else is the same
545 */
546 lastWrite /= sizeof(struct cmd_desc);
547 lastRead /= sizeof(struct cmd_desc);
548 return (ringSize + lastRead - lastWrite - 1) % ringSize;
549}
550
551static inline int
552typhoon_num_free_cmd(struct typhoon *tp)
553{
554 int lastWrite = tp->cmdRing.lastWrite;
555 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
556
557 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
558}
559
560static inline int
561typhoon_num_free_resp(struct typhoon *tp)
562{
563 int respReady = le32_to_cpu(tp->indexes->respReady);
564 int respCleared = le32_to_cpu(tp->indexes->respCleared);
565
566 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
567}
568
569static inline int
570typhoon_num_free_tx(struct transmit_ring *ring)
571{
572 /* if we start using the Hi Tx ring, this needs updating */
573 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
574}
575
576static int
577typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
578 int num_resp, struct resp_desc *resp)
579{
580 struct typhoon_indexes *indexes = tp->indexes;
581 struct basic_ring *ring = &tp->cmdRing;
582 struct resp_desc local_resp;
583 int i, err = 0;
584 int got_resp;
585 int freeCmd, freeResp;
586 int len, wrap_len;
587
588 spin_lock(&tp->command_lock);
589
590 freeCmd = typhoon_num_free_cmd(tp);
591 freeResp = typhoon_num_free_resp(tp);
592
593 if(freeCmd < num_cmd || freeResp < num_resp) {
594 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
595 freeCmd, num_cmd, freeResp, num_resp);
596 err = -ENOMEM;
597 goto out;
598 }
599
600 if(cmd->flags & TYPHOON_CMD_RESPOND) {
601 /* If we're expecting a response, but the caller hasn't given
602 * us a place to put it, we'll provide one.
603 */
604 tp->awaiting_resp = 1;
605 if(resp == NULL) {
606 resp = &local_resp;
607 num_resp = 1;
608 }
609 }
610
611 wrap_len = 0;
612 len = num_cmd * sizeof(*cmd);
613 if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
614 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
615 len = COMMAND_RING_SIZE - ring->lastWrite;
616 }
617
618 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
619 if(unlikely(wrap_len)) {
620 struct cmd_desc *wrap_ptr = cmd;
621 wrap_ptr += len / sizeof(*cmd);
622 memcpy(ring->ringBase, wrap_ptr, wrap_len);
623 }
624
625 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
626
627 /* "I feel a presence... another warrior is on the mesa."
628 */
629 wmb();
630 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
631 typhoon_post_pci_writes(tp->ioaddr);
632
633 if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
634 goto out;
635
636 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
637 * preempt or do anything other than take interrupts. So, don't
638 * wait for a response unless you have to.
639 *
640 * I've thought about trying to sleep here, but we're called
641 * from many contexts that don't allow that. Also, given the way
642 * 3Com has implemented irq coalescing, we would likely timeout --
643 * this has been observed in real life!
644 *
645 * The big killer is we have to wait to get stats from the card,
646 * though we could go to a periodic refresh of those if we don't
647 * mind them getting somewhat stale. The rest of the waiting
648 * commands occur during open/close/suspend/resume, so they aren't
649 * time critical. Creating SAs in the future will also have to
650 * wait here.
651 */
652 got_resp = 0;
653 for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
654 if(indexes->respCleared != indexes->respReady)
655 got_resp = typhoon_process_response(tp, num_resp,
656 resp);
657 udelay(TYPHOON_UDELAY);
658 }
659
660 if(!got_resp) {
661 err = -ETIMEDOUT;
662 goto out;
663 }
664
665 /* Collect the error response even if we don't care about the
666 * rest of the response
667 */
668 if(resp->flags & TYPHOON_RESP_ERROR)
669 err = -EIO;
670
671out:
672 if(tp->awaiting_resp) {
673 tp->awaiting_resp = 0;
674 smp_wmb();
675
676 /* Ugh. If a response was added to the ring between
677 * the call to typhoon_process_response() and the clearing
678 * of tp->awaiting_resp, we could have missed the interrupt
679 * and it could hang in the ring an indeterminate amount of
680 * time. So, check for it, and interrupt ourselves if this
681 * is the case.
682 */
683 if(indexes->respCleared != indexes->respReady)
684 iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
685 }
686
687 spin_unlock(&tp->command_lock);
688 return err;
689}
690
691static inline void
692typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
693 u32 ring_dma)
694{
695 struct tcpopt_desc *tcpd;
696 u32 tcpd_offset = ring_dma;
697
698 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
699 tcpd_offset += txRing->lastWrite;
700 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
701 typhoon_inc_tx_index(&txRing->lastWrite, 1);
702
703 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
704 tcpd->numDesc = 1;
705 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
706 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
707 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
708 tcpd->bytesTx = cpu_to_le32(skb->len);
709 tcpd->status = 0;
710}
711
712static netdev_tx_t
713typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
714{
715 struct typhoon *tp = netdev_priv(dev);
716 struct transmit_ring *txRing;
717 struct tx_desc *txd, *first_txd;
718 dma_addr_t skb_dma;
719 int numDesc;
720
721 /* we have two rings to choose from, but we only use txLo for now
722 * If we start using the Hi ring as well, we'll need to update
723 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
724 * and TXHI_ENTRIES to match, as well as update the TSO code below
725 * to get the right DMA address
726 */
727 txRing = &tp->txLoRing;
728
729 /* We need one descriptor for each fragment of the sk_buff, plus the
730 * one for the ->data area of it.
731 *
732 * The docs say a maximum of 16 fragment descriptors per TCP option
733 * descriptor, then make a new packet descriptor and option descriptor
734 * for the next 16 fragments. The engineers say just an option
735 * descriptor is needed. I've tested up to 26 fragments with a single
736 * packet descriptor/option descriptor combo, so I use that for now.
737 *
738 * If problems develop with TSO, check this first.
739 */
740 numDesc = skb_shinfo(skb)->nr_frags + 1;
741 if (skb_is_gso(skb))
742 numDesc++;
743
744 /* When checking for free space in the ring, we need to also
745 * account for the initial Tx descriptor, and we always must leave
746 * at least one descriptor unused in the ring so that it doesn't
747 * wrap and look empty.
748 *
749 * The only time we should loop here is when we hit the race
750 * between marking the queue awake and updating the cleared index.
751 * Just loop and it will appear. This comes from the acenic driver.
752 */
753 while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
754 smp_rmb();
755
756 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
757 typhoon_inc_tx_index(&txRing->lastWrite, 1);
758
759 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
760 first_txd->numDesc = 0;
761 first_txd->len = 0;
762 first_txd->tx_addr = (u64)((unsigned long) skb);
763 first_txd->processFlags = 0;
764
765 if(skb->ip_summed == CHECKSUM_PARTIAL) {
766 /* The 3XP will figure out if this is UDP/TCP */
767 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
768 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
769 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
770 }
771
772 if (skb_vlan_tag_present(skb)) {
773 first_txd->processFlags |=
774 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
775 first_txd->processFlags |=
776 cpu_to_le32(htons(skb_vlan_tag_get(skb)) <<
777 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
778 }
779
780 if (skb_is_gso(skb)) {
781 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
782 first_txd->numDesc++;
783
784 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
785 }
786
787 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
788 typhoon_inc_tx_index(&txRing->lastWrite, 1);
789
790 /* No need to worry about padding packet -- the firmware pads
791 * it with zeros to ETH_ZLEN for us.
792 */
793 if(skb_shinfo(skb)->nr_frags == 0) {
794 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
795 PCI_DMA_TODEVICE);
796 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
797 txd->len = cpu_to_le16(skb->len);
798 txd->frag.addr = cpu_to_le32(skb_dma);
799 txd->frag.addrHi = 0;
800 first_txd->numDesc++;
801 } else {
802 int i, len;
803
804 len = skb_headlen(skb);
805 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
806 PCI_DMA_TODEVICE);
807 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
808 txd->len = cpu_to_le16(len);
809 txd->frag.addr = cpu_to_le32(skb_dma);
810 txd->frag.addrHi = 0;
811 first_txd->numDesc++;
812
813 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
814 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
815 void *frag_addr;
816
817 txd = (struct tx_desc *) (txRing->ringBase +
818 txRing->lastWrite);
819 typhoon_inc_tx_index(&txRing->lastWrite, 1);
820
821 len = skb_frag_size(frag);
822 frag_addr = skb_frag_address(frag);
823 skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
824 PCI_DMA_TODEVICE);
825 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
826 txd->len = cpu_to_le16(len);
827 txd->frag.addr = cpu_to_le32(skb_dma);
828 txd->frag.addrHi = 0;
829 first_txd->numDesc++;
830 }
831 }
832
833 /* Kick the 3XP
834 */
835 wmb();
836 iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
837
838 /* If we don't have room to put the worst case packet on the
839 * queue, then we must stop the queue. We need 2 extra
840 * descriptors -- one to prevent ring wrap, and one for the
841 * Tx header.
842 */
843 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
844
845 if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
846 netif_stop_queue(dev);
847
848 /* A Tx complete IRQ could have gotten between, making
849 * the ring free again. Only need to recheck here, since
850 * Tx is serialized.
851 */
852 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
853 netif_wake_queue(dev);
854 }
855
856 return NETDEV_TX_OK;
857}
858
859static void
860typhoon_set_rx_mode(struct net_device *dev)
861{
862 struct typhoon *tp = netdev_priv(dev);
863 struct cmd_desc xp_cmd;
864 u32 mc_filter[2];
865 __le16 filter;
866
867 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
868 if(dev->flags & IFF_PROMISC) {
869 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
870 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
871 (dev->flags & IFF_ALLMULTI)) {
872 /* Too many to match, or accept all multicasts. */
873 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
874 } else if (!netdev_mc_empty(dev)) {
875 struct netdev_hw_addr *ha;
876
877 memset(mc_filter, 0, sizeof(mc_filter));
878 netdev_for_each_mc_addr(ha, dev) {
879 int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
880 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
881 }
882
883 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
884 TYPHOON_CMD_SET_MULTICAST_HASH);
885 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
886 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
887 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
888 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
889
890 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
891 }
892
893 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
894 xp_cmd.parm1 = filter;
895 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
896}
897
898static int
899typhoon_do_get_stats(struct typhoon *tp)
900{
901 struct net_device_stats *stats = &tp->stats;
902 struct net_device_stats *saved = &tp->stats_saved;
903 struct cmd_desc xp_cmd;
904 struct resp_desc xp_resp[7];
905 struct stats_resp *s = (struct stats_resp *) xp_resp;
906 int err;
907
908 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
909 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
910 if(err < 0)
911 return err;
912
913 /* 3Com's Linux driver uses txMultipleCollisions as it's
914 * collisions value, but there is some other collision info as well...
915 *
916 * The extra status reported would be a good candidate for
917 * ethtool_ops->get_{strings,stats}()
918 */
919 stats->tx_packets = le32_to_cpu(s->txPackets) +
920 saved->tx_packets;
921 stats->tx_bytes = le64_to_cpu(s->txBytes) +
922 saved->tx_bytes;
923 stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
924 saved->tx_errors;
925 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
926 saved->tx_carrier_errors;
927 stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
928 saved->collisions;
929 stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
930 saved->rx_packets;
931 stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
932 saved->rx_bytes;
933 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
934 saved->rx_fifo_errors;
935 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
936 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
937 saved->rx_errors;
938 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
939 saved->rx_crc_errors;
940 stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
941 saved->rx_length_errors;
942 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
943 SPEED_100 : SPEED_10;
944 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
945 DUPLEX_FULL : DUPLEX_HALF;
946
947 return 0;
948}
949
950static struct net_device_stats *
951typhoon_get_stats(struct net_device *dev)
952{
953 struct typhoon *tp = netdev_priv(dev);
954 struct net_device_stats *stats = &tp->stats;
955 struct net_device_stats *saved = &tp->stats_saved;
956
957 smp_rmb();
958 if(tp->card_state == Sleeping)
959 return saved;
960
961 if(typhoon_do_get_stats(tp) < 0) {
962 netdev_err(dev, "error getting stats\n");
963 return saved;
964 }
965
966 return stats;
967}
968
969static void
970typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
971{
972 struct typhoon *tp = netdev_priv(dev);
973 struct pci_dev *pci_dev = tp->pdev;
974 struct cmd_desc xp_cmd;
975 struct resp_desc xp_resp[3];
976
977 smp_rmb();
978 if(tp->card_state == Sleeping) {
979 strlcpy(info->fw_version, "Sleep image",
980 sizeof(info->fw_version));
981 } else {
982 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
983 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
984 strlcpy(info->fw_version, "Unknown runtime",
985 sizeof(info->fw_version));
986 } else {
987 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
988 snprintf(info->fw_version, sizeof(info->fw_version),
989 "%02x.%03x.%03x", sleep_ver >> 24,
990 (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff);
991 }
992 }
993
994 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
995 strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
996}
997
998static int
999typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1000{
1001 struct typhoon *tp = netdev_priv(dev);
1002
1003 cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1004 SUPPORTED_Autoneg;
1005
1006 switch (tp->xcvr_select) {
1007 case TYPHOON_XCVR_10HALF:
1008 cmd->advertising = ADVERTISED_10baseT_Half;
1009 break;
1010 case TYPHOON_XCVR_10FULL:
1011 cmd->advertising = ADVERTISED_10baseT_Full;
1012 break;
1013 case TYPHOON_XCVR_100HALF:
1014 cmd->advertising = ADVERTISED_100baseT_Half;
1015 break;
1016 case TYPHOON_XCVR_100FULL:
1017 cmd->advertising = ADVERTISED_100baseT_Full;
1018 break;
1019 case TYPHOON_XCVR_AUTONEG:
1020 cmd->advertising = ADVERTISED_10baseT_Half |
1021 ADVERTISED_10baseT_Full |
1022 ADVERTISED_100baseT_Half |
1023 ADVERTISED_100baseT_Full |
1024 ADVERTISED_Autoneg;
1025 break;
1026 }
1027
1028 if(tp->capabilities & TYPHOON_FIBER) {
1029 cmd->supported |= SUPPORTED_FIBRE;
1030 cmd->advertising |= ADVERTISED_FIBRE;
1031 cmd->port = PORT_FIBRE;
1032 } else {
1033 cmd->supported |= SUPPORTED_10baseT_Half |
1034 SUPPORTED_10baseT_Full |
1035 SUPPORTED_TP;
1036 cmd->advertising |= ADVERTISED_TP;
1037 cmd->port = PORT_TP;
1038 }
1039
1040 /* need to get stats to make these link speed/duplex valid */
1041 typhoon_do_get_stats(tp);
1042 ethtool_cmd_speed_set(cmd, tp->speed);
1043 cmd->duplex = tp->duplex;
1044 cmd->phy_address = 0;
1045 cmd->transceiver = XCVR_INTERNAL;
1046 if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1047 cmd->autoneg = AUTONEG_ENABLE;
1048 else
1049 cmd->autoneg = AUTONEG_DISABLE;
1050 cmd->maxtxpkt = 1;
1051 cmd->maxrxpkt = 1;
1052
1053 return 0;
1054}
1055
1056static int
1057typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1058{
1059 struct typhoon *tp = netdev_priv(dev);
1060 u32 speed = ethtool_cmd_speed(cmd);
1061 struct cmd_desc xp_cmd;
1062 __le16 xcvr;
1063 int err;
1064
1065 err = -EINVAL;
1066 if (cmd->autoneg == AUTONEG_ENABLE) {
1067 xcvr = TYPHOON_XCVR_AUTONEG;
1068 } else {
1069 if (cmd->duplex == DUPLEX_HALF) {
1070 if (speed == SPEED_10)
1071 xcvr = TYPHOON_XCVR_10HALF;
1072 else if (speed == SPEED_100)
1073 xcvr = TYPHOON_XCVR_100HALF;
1074 else
1075 goto out;
1076 } else if (cmd->duplex == DUPLEX_FULL) {
1077 if (speed == SPEED_10)
1078 xcvr = TYPHOON_XCVR_10FULL;
1079 else if (speed == SPEED_100)
1080 xcvr = TYPHOON_XCVR_100FULL;
1081 else
1082 goto out;
1083 } else
1084 goto out;
1085 }
1086
1087 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1088 xp_cmd.parm1 = xcvr;
1089 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1090 if(err < 0)
1091 goto out;
1092
1093 tp->xcvr_select = xcvr;
1094 if(cmd->autoneg == AUTONEG_ENABLE) {
1095 tp->speed = 0xff; /* invalid */
1096 tp->duplex = 0xff; /* invalid */
1097 } else {
1098 tp->speed = speed;
1099 tp->duplex = cmd->duplex;
1100 }
1101
1102out:
1103 return err;
1104}
1105
1106static void
1107typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1108{
1109 struct typhoon *tp = netdev_priv(dev);
1110
1111 wol->supported = WAKE_PHY | WAKE_MAGIC;
1112 wol->wolopts = 0;
1113 if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1114 wol->wolopts |= WAKE_PHY;
1115 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1116 wol->wolopts |= WAKE_MAGIC;
1117 memset(&wol->sopass, 0, sizeof(wol->sopass));
1118}
1119
1120static int
1121typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1122{
1123 struct typhoon *tp = netdev_priv(dev);
1124
1125 if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1126 return -EINVAL;
1127
1128 tp->wol_events = 0;
1129 if(wol->wolopts & WAKE_PHY)
1130 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1131 if(wol->wolopts & WAKE_MAGIC)
1132 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1133
1134 return 0;
1135}
1136
1137static void
1138typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1139{
1140 ering->rx_max_pending = RXENT_ENTRIES;
1141 ering->tx_max_pending = TXLO_ENTRIES - 1;
1142
1143 ering->rx_pending = RXENT_ENTRIES;
1144 ering->tx_pending = TXLO_ENTRIES - 1;
1145}
1146
1147static const struct ethtool_ops typhoon_ethtool_ops = {
1148 .get_settings = typhoon_get_settings,
1149 .set_settings = typhoon_set_settings,
1150 .get_drvinfo = typhoon_get_drvinfo,
1151 .get_wol = typhoon_get_wol,
1152 .set_wol = typhoon_set_wol,
1153 .get_link = ethtool_op_get_link,
1154 .get_ringparam = typhoon_get_ringparam,
1155};
1156
1157static int
1158typhoon_wait_interrupt(void __iomem *ioaddr)
1159{
1160 int i, err = 0;
1161
1162 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1163 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1164 TYPHOON_INTR_BOOTCMD)
1165 goto out;
1166 udelay(TYPHOON_UDELAY);
1167 }
1168
1169 err = -ETIMEDOUT;
1170
1171out:
1172 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1173 return err;
1174}
1175
1176#define shared_offset(x) offsetof(struct typhoon_shared, x)
1177
1178static void
1179typhoon_init_interface(struct typhoon *tp)
1180{
1181 struct typhoon_interface *iface = &tp->shared->iface;
1182 dma_addr_t shared_dma;
1183
1184 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1185
1186 /* The *Hi members of iface are all init'd to zero by the memset().
1187 */
1188 shared_dma = tp->shared_dma + shared_offset(indexes);
1189 iface->ringIndex = cpu_to_le32(shared_dma);
1190
1191 shared_dma = tp->shared_dma + shared_offset(txLo);
1192 iface->txLoAddr = cpu_to_le32(shared_dma);
1193 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1194
1195 shared_dma = tp->shared_dma + shared_offset(txHi);
1196 iface->txHiAddr = cpu_to_le32(shared_dma);
1197 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1198
1199 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1200 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1201 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1202 sizeof(struct rx_free));
1203
1204 shared_dma = tp->shared_dma + shared_offset(rxLo);
1205 iface->rxLoAddr = cpu_to_le32(shared_dma);
1206 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1207
1208 shared_dma = tp->shared_dma + shared_offset(rxHi);
1209 iface->rxHiAddr = cpu_to_le32(shared_dma);
1210 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1211
1212 shared_dma = tp->shared_dma + shared_offset(cmd);
1213 iface->cmdAddr = cpu_to_le32(shared_dma);
1214 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1215
1216 shared_dma = tp->shared_dma + shared_offset(resp);
1217 iface->respAddr = cpu_to_le32(shared_dma);
1218 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1219
1220 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1221 iface->zeroAddr = cpu_to_le32(shared_dma);
1222
1223 tp->indexes = &tp->shared->indexes;
1224 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1225 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1226 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1227 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1228 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1229 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1230 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1231
1232 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1233 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1234
1235 tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1236 tp->card_state = Sleeping;
1237
1238 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1239 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1240 tp->offload |= TYPHOON_OFFLOAD_VLAN;
1241
1242 spin_lock_init(&tp->command_lock);
1243
1244 /* Force the writes to the shared memory area out before continuing. */
1245 wmb();
1246}
1247
1248static void
1249typhoon_init_rings(struct typhoon *tp)
1250{
1251 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1252
1253 tp->txLoRing.lastWrite = 0;
1254 tp->txHiRing.lastWrite = 0;
1255 tp->rxLoRing.lastWrite = 0;
1256 tp->rxHiRing.lastWrite = 0;
1257 tp->rxBuffRing.lastWrite = 0;
1258 tp->cmdRing.lastWrite = 0;
1259 tp->respRing.lastWrite = 0;
1260
1261 tp->txLoRing.lastRead = 0;
1262 tp->txHiRing.lastRead = 0;
1263}
1264
1265static const struct firmware *typhoon_fw;
1266
1267static int
1268typhoon_request_firmware(struct typhoon *tp)
1269{
1270 const struct typhoon_file_header *fHdr;
1271 const struct typhoon_section_header *sHdr;
1272 const u8 *image_data;
1273 u32 numSections;
1274 u32 section_len;
1275 u32 remaining;
1276 int err;
1277
1278 if (typhoon_fw)
1279 return 0;
1280
1281 err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1282 if (err) {
1283 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1284 FIRMWARE_NAME);
1285 return err;
1286 }
1287
1288 image_data = typhoon_fw->data;
1289 remaining = typhoon_fw->size;
1290 if (remaining < sizeof(struct typhoon_file_header))
1291 goto invalid_fw;
1292
1293 fHdr = (struct typhoon_file_header *) image_data;
1294 if (memcmp(fHdr->tag, "TYPHOON", 8))
1295 goto invalid_fw;
1296
1297 numSections = le32_to_cpu(fHdr->numSections);
1298 image_data += sizeof(struct typhoon_file_header);
1299 remaining -= sizeof(struct typhoon_file_header);
1300
1301 while (numSections--) {
1302 if (remaining < sizeof(struct typhoon_section_header))
1303 goto invalid_fw;
1304
1305 sHdr = (struct typhoon_section_header *) image_data;
1306 image_data += sizeof(struct typhoon_section_header);
1307 section_len = le32_to_cpu(sHdr->len);
1308
1309 if (remaining < section_len)
1310 goto invalid_fw;
1311
1312 image_data += section_len;
1313 remaining -= section_len;
1314 }
1315
1316 return 0;
1317
1318invalid_fw:
1319 netdev_err(tp->dev, "Invalid firmware image\n");
1320 release_firmware(typhoon_fw);
1321 typhoon_fw = NULL;
1322 return -EINVAL;
1323}
1324
1325static int
1326typhoon_download_firmware(struct typhoon *tp)
1327{
1328 void __iomem *ioaddr = tp->ioaddr;
1329 struct pci_dev *pdev = tp->pdev;
1330 const struct typhoon_file_header *fHdr;
1331 const struct typhoon_section_header *sHdr;
1332 const u8 *image_data;
1333 void *dpage;
1334 dma_addr_t dpage_dma;
1335 __sum16 csum;
1336 u32 irqEnabled;
1337 u32 irqMasked;
1338 u32 numSections;
1339 u32 section_len;
1340 u32 len;
1341 u32 load_addr;
1342 u32 hmac;
1343 int i;
1344 int err;
1345
1346 image_data = typhoon_fw->data;
1347 fHdr = (struct typhoon_file_header *) image_data;
1348
1349 /* Cannot just map the firmware image using pci_map_single() as
1350 * the firmware is vmalloc()'d and may not be physically contiguous,
1351 * so we allocate some consistent memory to copy the sections into.
1352 */
1353 err = -ENOMEM;
1354 dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1355 if(!dpage) {
1356 netdev_err(tp->dev, "no DMA mem for firmware\n");
1357 goto err_out;
1358 }
1359
1360 irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1361 iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1362 ioaddr + TYPHOON_REG_INTR_ENABLE);
1363 irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1364 iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1365 ioaddr + TYPHOON_REG_INTR_MASK);
1366
1367 err = -ETIMEDOUT;
1368 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1369 netdev_err(tp->dev, "card ready timeout\n");
1370 goto err_out_irq;
1371 }
1372
1373 numSections = le32_to_cpu(fHdr->numSections);
1374 load_addr = le32_to_cpu(fHdr->startAddr);
1375
1376 iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1377 iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1378 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1379 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1380 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1381 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1382 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1383 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1384 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1385 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1386 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1387 iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1388 typhoon_post_pci_writes(ioaddr);
1389 iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1390
1391 image_data += sizeof(struct typhoon_file_header);
1392
1393 /* The ioread32() in typhoon_wait_interrupt() will force the
1394 * last write to the command register to post, so
1395 * we don't need a typhoon_post_pci_writes() after it.
1396 */
1397 for(i = 0; i < numSections; i++) {
1398 sHdr = (struct typhoon_section_header *) image_data;
1399 image_data += sizeof(struct typhoon_section_header);
1400 load_addr = le32_to_cpu(sHdr->startAddr);
1401 section_len = le32_to_cpu(sHdr->len);
1402
1403 while(section_len) {
1404 len = min_t(u32, section_len, PAGE_SIZE);
1405
1406 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1407 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1408 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1409 netdev_err(tp->dev, "segment ready timeout\n");
1410 goto err_out_irq;
1411 }
1412
1413 /* Do an pseudo IPv4 checksum on the data -- first
1414 * need to convert each u16 to cpu order before
1415 * summing. Fortunately, due to the properties of
1416 * the checksum, we can do this once, at the end.
1417 */
1418 csum = csum_fold(csum_partial_copy_nocheck(image_data,
1419 dpage, len,
1420 0));
1421
1422 iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1423 iowrite32(le16_to_cpu((__force __le16)csum),
1424 ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1425 iowrite32(load_addr,
1426 ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1427 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1428 iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1429 typhoon_post_pci_writes(ioaddr);
1430 iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1431 ioaddr + TYPHOON_REG_COMMAND);
1432
1433 image_data += len;
1434 load_addr += len;
1435 section_len -= len;
1436 }
1437 }
1438
1439 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1440 ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1441 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1442 netdev_err(tp->dev, "final segment ready timeout\n");
1443 goto err_out_irq;
1444 }
1445
1446 iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1447
1448 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1449 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1450 ioread32(ioaddr + TYPHOON_REG_STATUS));
1451 goto err_out_irq;
1452 }
1453
1454 err = 0;
1455
1456err_out_irq:
1457 iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1458 iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1459
1460 pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1461
1462err_out:
1463 return err;
1464}
1465
1466static int
1467typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1468{
1469 void __iomem *ioaddr = tp->ioaddr;
1470
1471 if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1472 netdev_err(tp->dev, "boot ready timeout\n");
1473 goto out_timeout;
1474 }
1475
1476 iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1477 iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1478 typhoon_post_pci_writes(ioaddr);
1479 iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1480 ioaddr + TYPHOON_REG_COMMAND);
1481
1482 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1483 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1484 ioread32(ioaddr + TYPHOON_REG_STATUS));
1485 goto out_timeout;
1486 }
1487
1488 /* Clear the Transmit and Command ready registers
1489 */
1490 iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1491 iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1492 iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1493 typhoon_post_pci_writes(ioaddr);
1494 iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1495
1496 return 0;
1497
1498out_timeout:
1499 return -ETIMEDOUT;
1500}
1501
1502static u32
1503typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1504 volatile __le32 * index)
1505{
1506 u32 lastRead = txRing->lastRead;
1507 struct tx_desc *tx;
1508 dma_addr_t skb_dma;
1509 int dma_len;
1510 int type;
1511
1512 while(lastRead != le32_to_cpu(*index)) {
1513 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1514 type = tx->flags & TYPHOON_TYPE_MASK;
1515
1516 if(type == TYPHOON_TX_DESC) {
1517 /* This tx_desc describes a packet.
1518 */
1519 unsigned long ptr = tx->tx_addr;
1520 struct sk_buff *skb = (struct sk_buff *) ptr;
1521 dev_kfree_skb_irq(skb);
1522 } else if(type == TYPHOON_FRAG_DESC) {
1523 /* This tx_desc describes a memory mapping. Free it.
1524 */
1525 skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1526 dma_len = le16_to_cpu(tx->len);
1527 pci_unmap_single(tp->pdev, skb_dma, dma_len,
1528 PCI_DMA_TODEVICE);
1529 }
1530
1531 tx->flags = 0;
1532 typhoon_inc_tx_index(&lastRead, 1);
1533 }
1534
1535 return lastRead;
1536}
1537
1538static void
1539typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1540 volatile __le32 * index)
1541{
1542 u32 lastRead;
1543 int numDesc = MAX_SKB_FRAGS + 1;
1544
1545 /* This will need changing if we start to use the Hi Tx ring. */
1546 lastRead = typhoon_clean_tx(tp, txRing, index);
1547 if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1548 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1549 netif_wake_queue(tp->dev);
1550
1551 txRing->lastRead = lastRead;
1552 smp_wmb();
1553}
1554
1555static void
1556typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1557{
1558 struct typhoon_indexes *indexes = tp->indexes;
1559 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1560 struct basic_ring *ring = &tp->rxBuffRing;
1561 struct rx_free *r;
1562
1563 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1564 le32_to_cpu(indexes->rxBuffCleared)) {
1565 /* no room in ring, just drop the skb
1566 */
1567 dev_kfree_skb_any(rxb->skb);
1568 rxb->skb = NULL;
1569 return;
1570 }
1571
1572 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1573 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1574 r->virtAddr = idx;
1575 r->physAddr = cpu_to_le32(rxb->dma_addr);
1576
1577 /* Tell the card about it */
1578 wmb();
1579 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1580}
1581
1582static int
1583typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1584{
1585 struct typhoon_indexes *indexes = tp->indexes;
1586 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1587 struct basic_ring *ring = &tp->rxBuffRing;
1588 struct rx_free *r;
1589 struct sk_buff *skb;
1590 dma_addr_t dma_addr;
1591
1592 rxb->skb = NULL;
1593
1594 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1595 le32_to_cpu(indexes->rxBuffCleared))
1596 return -ENOMEM;
1597
1598 skb = netdev_alloc_skb(tp->dev, PKT_BUF_SZ);
1599 if(!skb)
1600 return -ENOMEM;
1601
1602#if 0
1603 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1604 * address! Pretty please?
1605 */
1606 skb_reserve(skb, 2);
1607#endif
1608
1609 dma_addr = pci_map_single(tp->pdev, skb->data,
1610 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1611
1612 /* Since no card does 64 bit DAC, the high bits will never
1613 * change from zero.
1614 */
1615 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1616 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1617 r->virtAddr = idx;
1618 r->physAddr = cpu_to_le32(dma_addr);
1619 rxb->skb = skb;
1620 rxb->dma_addr = dma_addr;
1621
1622 /* Tell the card about it */
1623 wmb();
1624 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1625 return 0;
1626}
1627
1628static int
1629typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1630 volatile __le32 * cleared, int budget)
1631{
1632 struct rx_desc *rx;
1633 struct sk_buff *skb, *new_skb;
1634 struct rxbuff_ent *rxb;
1635 dma_addr_t dma_addr;
1636 u32 local_ready;
1637 u32 rxaddr;
1638 int pkt_len;
1639 u32 idx;
1640 __le32 csum_bits;
1641 int received;
1642
1643 received = 0;
1644 local_ready = le32_to_cpu(*ready);
1645 rxaddr = le32_to_cpu(*cleared);
1646 while(rxaddr != local_ready && budget > 0) {
1647 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1648 idx = rx->addr;
1649 rxb = &tp->rxbuffers[idx];
1650 skb = rxb->skb;
1651 dma_addr = rxb->dma_addr;
1652
1653 typhoon_inc_rx_index(&rxaddr, 1);
1654
1655 if(rx->flags & TYPHOON_RX_ERROR) {
1656 typhoon_recycle_rx_skb(tp, idx);
1657 continue;
1658 }
1659
1660 pkt_len = le16_to_cpu(rx->frameLen);
1661
1662 if(pkt_len < rx_copybreak &&
1663 (new_skb = netdev_alloc_skb(tp->dev, pkt_len + 2)) != NULL) {
1664 skb_reserve(new_skb, 2);
1665 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1666 PKT_BUF_SZ,
1667 PCI_DMA_FROMDEVICE);
1668 skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1669 pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1670 PKT_BUF_SZ,
1671 PCI_DMA_FROMDEVICE);
1672 skb_put(new_skb, pkt_len);
1673 typhoon_recycle_rx_skb(tp, idx);
1674 } else {
1675 new_skb = skb;
1676 skb_put(new_skb, pkt_len);
1677 pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1678 PCI_DMA_FROMDEVICE);
1679 typhoon_alloc_rx_skb(tp, idx);
1680 }
1681 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1682 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1683 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1684 if(csum_bits ==
1685 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1686 csum_bits ==
1687 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1688 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1689 } else
1690 skb_checksum_none_assert(new_skb);
1691
1692 if (rx->rxStatus & TYPHOON_RX_VLAN)
1693 __vlan_hwaccel_put_tag(new_skb, htons(ETH_P_8021Q),
1694 ntohl(rx->vlanTag) & 0xffff);
1695 netif_receive_skb(new_skb);
1696
1697 received++;
1698 budget--;
1699 }
1700 *cleared = cpu_to_le32(rxaddr);
1701
1702 return received;
1703}
1704
1705static void
1706typhoon_fill_free_ring(struct typhoon *tp)
1707{
1708 u32 i;
1709
1710 for(i = 0; i < RXENT_ENTRIES; i++) {
1711 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1712 if(rxb->skb)
1713 continue;
1714 if(typhoon_alloc_rx_skb(tp, i) < 0)
1715 break;
1716 }
1717}
1718
1719static int
1720typhoon_poll(struct napi_struct *napi, int budget)
1721{
1722 struct typhoon *tp = container_of(napi, struct typhoon, napi);
1723 struct typhoon_indexes *indexes = tp->indexes;
1724 int work_done;
1725
1726 rmb();
1727 if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1728 typhoon_process_response(tp, 0, NULL);
1729
1730 if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1731 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1732
1733 work_done = 0;
1734
1735 if(indexes->rxHiCleared != indexes->rxHiReady) {
1736 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1737 &indexes->rxHiCleared, budget);
1738 }
1739
1740 if(indexes->rxLoCleared != indexes->rxLoReady) {
1741 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1742 &indexes->rxLoCleared, budget - work_done);
1743 }
1744
1745 if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1746 /* rxBuff ring is empty, try to fill it. */
1747 typhoon_fill_free_ring(tp);
1748 }
1749
1750 if (work_done < budget) {
1751 napi_complete(napi);
1752 iowrite32(TYPHOON_INTR_NONE,
1753 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1754 typhoon_post_pci_writes(tp->ioaddr);
1755 }
1756
1757 return work_done;
1758}
1759
1760static irqreturn_t
1761typhoon_interrupt(int irq, void *dev_instance)
1762{
1763 struct net_device *dev = dev_instance;
1764 struct typhoon *tp = netdev_priv(dev);
1765 void __iomem *ioaddr = tp->ioaddr;
1766 u32 intr_status;
1767
1768 intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1769 if(!(intr_status & TYPHOON_INTR_HOST_INT))
1770 return IRQ_NONE;
1771
1772 iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1773
1774 if (napi_schedule_prep(&tp->napi)) {
1775 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1776 typhoon_post_pci_writes(ioaddr);
1777 __napi_schedule(&tp->napi);
1778 } else {
1779 netdev_err(dev, "Error, poll already scheduled\n");
1780 }
1781 return IRQ_HANDLED;
1782}
1783
1784static void
1785typhoon_free_rx_rings(struct typhoon *tp)
1786{
1787 u32 i;
1788
1789 for(i = 0; i < RXENT_ENTRIES; i++) {
1790 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1791 if(rxb->skb) {
1792 pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1793 PCI_DMA_FROMDEVICE);
1794 dev_kfree_skb(rxb->skb);
1795 rxb->skb = NULL;
1796 }
1797 }
1798}
1799
1800static int
1801typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1802{
1803 struct pci_dev *pdev = tp->pdev;
1804 void __iomem *ioaddr = tp->ioaddr;
1805 struct cmd_desc xp_cmd;
1806 int err;
1807
1808 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1809 xp_cmd.parm1 = events;
1810 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1811 if(err < 0) {
1812 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1813 err);
1814 return err;
1815 }
1816
1817 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1818 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1819 if(err < 0) {
1820 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1821 return err;
1822 }
1823
1824 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1825 return -ETIMEDOUT;
1826
1827 /* Since we cannot monitor the status of the link while sleeping,
1828 * tell the world it went away.
1829 */
1830 netif_carrier_off(tp->dev);
1831
1832 pci_enable_wake(tp->pdev, state, 1);
1833 pci_disable_device(pdev);
1834 return pci_set_power_state(pdev, state);
1835}
1836
1837static int
1838typhoon_wakeup(struct typhoon *tp, int wait_type)
1839{
1840 struct pci_dev *pdev = tp->pdev;
1841 void __iomem *ioaddr = tp->ioaddr;
1842
1843 pci_set_power_state(pdev, PCI_D0);
1844 pci_restore_state(pdev);
1845
1846 /* Post 2.x.x versions of the Sleep Image require a reset before
1847 * we can download the Runtime Image. But let's not make users of
1848 * the old firmware pay for the reset.
1849 */
1850 iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1851 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1852 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1853 return typhoon_reset(ioaddr, wait_type);
1854
1855 return 0;
1856}
1857
1858static int
1859typhoon_start_runtime(struct typhoon *tp)
1860{
1861 struct net_device *dev = tp->dev;
1862 void __iomem *ioaddr = tp->ioaddr;
1863 struct cmd_desc xp_cmd;
1864 int err;
1865
1866 typhoon_init_rings(tp);
1867 typhoon_fill_free_ring(tp);
1868
1869 err = typhoon_download_firmware(tp);
1870 if(err < 0) {
1871 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1872 goto error_out;
1873 }
1874
1875 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1876 netdev_err(tp->dev, "cannot boot 3XP\n");
1877 err = -EIO;
1878 goto error_out;
1879 }
1880
1881 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1882 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1883 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1884 if(err < 0)
1885 goto error_out;
1886
1887 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1888 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1889 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1890 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1891 if(err < 0)
1892 goto error_out;
1893
1894 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1895 * us some more information on how to control it.
1896 */
1897 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1898 xp_cmd.parm1 = 0;
1899 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1900 if(err < 0)
1901 goto error_out;
1902
1903 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1904 xp_cmd.parm1 = tp->xcvr_select;
1905 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1906 if(err < 0)
1907 goto error_out;
1908
1909 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1910 xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1911 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1912 if(err < 0)
1913 goto error_out;
1914
1915 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1916 xp_cmd.parm2 = tp->offload;
1917 xp_cmd.parm3 = tp->offload;
1918 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1919 if(err < 0)
1920 goto error_out;
1921
1922 typhoon_set_rx_mode(dev);
1923
1924 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1925 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1926 if(err < 0)
1927 goto error_out;
1928
1929 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1930 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1931 if(err < 0)
1932 goto error_out;
1933
1934 tp->card_state = Running;
1935 smp_wmb();
1936
1937 iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1938 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1939 typhoon_post_pci_writes(ioaddr);
1940
1941 return 0;
1942
1943error_out:
1944 typhoon_reset(ioaddr, WaitNoSleep);
1945 typhoon_free_rx_rings(tp);
1946 typhoon_init_rings(tp);
1947 return err;
1948}
1949
1950static int
1951typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1952{
1953 struct typhoon_indexes *indexes = tp->indexes;
1954 struct transmit_ring *txLo = &tp->txLoRing;
1955 void __iomem *ioaddr = tp->ioaddr;
1956 struct cmd_desc xp_cmd;
1957 int i;
1958
1959 /* Disable interrupts early, since we can't schedule a poll
1960 * when called with !netif_running(). This will be posted
1961 * when we force the posting of the command.
1962 */
1963 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
1964
1965 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
1966 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1967
1968 /* Wait 1/2 sec for any outstanding transmits to occur
1969 * We'll cleanup after the reset if this times out.
1970 */
1971 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1972 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
1973 break;
1974 udelay(TYPHOON_UDELAY);
1975 }
1976
1977 if(i == TYPHOON_WAIT_TIMEOUT)
1978 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
1979
1980 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
1981 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1982
1983 /* save the statistics so when we bring the interface up again,
1984 * the values reported to userspace are correct.
1985 */
1986 tp->card_state = Sleeping;
1987 smp_wmb();
1988 typhoon_do_get_stats(tp);
1989 memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
1990
1991 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
1992 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1993
1994 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
1995 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
1996
1997 if(typhoon_reset(ioaddr, wait_type) < 0) {
1998 netdev_err(tp->dev, "unable to reset 3XP\n");
1999 return -ETIMEDOUT;
2000 }
2001
2002 /* cleanup any outstanding Tx packets */
2003 if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2004 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2005 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2006 }
2007
2008 return 0;
2009}
2010
2011static void
2012typhoon_tx_timeout(struct net_device *dev)
2013{
2014 struct typhoon *tp = netdev_priv(dev);
2015
2016 if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2017 netdev_warn(dev, "could not reset in tx timeout\n");
2018 goto truly_dead;
2019 }
2020
2021 /* If we ever start using the Hi ring, it will need cleaning too */
2022 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2023 typhoon_free_rx_rings(tp);
2024
2025 if(typhoon_start_runtime(tp) < 0) {
2026 netdev_err(dev, "could not start runtime in tx timeout\n");
2027 goto truly_dead;
2028 }
2029
2030 netif_wake_queue(dev);
2031 return;
2032
2033truly_dead:
2034 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2035 typhoon_reset(tp->ioaddr, NoWait);
2036 netif_carrier_off(dev);
2037}
2038
2039static int
2040typhoon_open(struct net_device *dev)
2041{
2042 struct typhoon *tp = netdev_priv(dev);
2043 int err;
2044
2045 err = typhoon_request_firmware(tp);
2046 if (err)
2047 goto out;
2048
2049 err = typhoon_wakeup(tp, WaitSleep);
2050 if(err < 0) {
2051 netdev_err(dev, "unable to wakeup device\n");
2052 goto out_sleep;
2053 }
2054
2055 err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2056 dev->name, dev);
2057 if(err < 0)
2058 goto out_sleep;
2059
2060 napi_enable(&tp->napi);
2061
2062 err = typhoon_start_runtime(tp);
2063 if(err < 0) {
2064 napi_disable(&tp->napi);
2065 goto out_irq;
2066 }
2067
2068 netif_start_queue(dev);
2069 return 0;
2070
2071out_irq:
2072 free_irq(dev->irq, dev);
2073
2074out_sleep:
2075 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2076 netdev_err(dev, "unable to reboot into sleep img\n");
2077 typhoon_reset(tp->ioaddr, NoWait);
2078 goto out;
2079 }
2080
2081 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2082 netdev_err(dev, "unable to go back to sleep\n");
2083
2084out:
2085 return err;
2086}
2087
2088static int
2089typhoon_close(struct net_device *dev)
2090{
2091 struct typhoon *tp = netdev_priv(dev);
2092
2093 netif_stop_queue(dev);
2094 napi_disable(&tp->napi);
2095
2096 if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2097 netdev_err(dev, "unable to stop runtime\n");
2098
2099 /* Make sure there is no irq handler running on a different CPU. */
2100 free_irq(dev->irq, dev);
2101
2102 typhoon_free_rx_rings(tp);
2103 typhoon_init_rings(tp);
2104
2105 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2106 netdev_err(dev, "unable to boot sleep image\n");
2107
2108 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2109 netdev_err(dev, "unable to put card to sleep\n");
2110
2111 return 0;
2112}
2113
2114#ifdef CONFIG_PM
2115static int
2116typhoon_resume(struct pci_dev *pdev)
2117{
2118 struct net_device *dev = pci_get_drvdata(pdev);
2119 struct typhoon *tp = netdev_priv(dev);
2120
2121 /* If we're down, resume when we are upped.
2122 */
2123 if(!netif_running(dev))
2124 return 0;
2125
2126 if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2127 netdev_err(dev, "critical: could not wake up in resume\n");
2128 goto reset;
2129 }
2130
2131 if(typhoon_start_runtime(tp) < 0) {
2132 netdev_err(dev, "critical: could not start runtime in resume\n");
2133 goto reset;
2134 }
2135
2136 netif_device_attach(dev);
2137 return 0;
2138
2139reset:
2140 typhoon_reset(tp->ioaddr, NoWait);
2141 return -EBUSY;
2142}
2143
2144static int
2145typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2146{
2147 struct net_device *dev = pci_get_drvdata(pdev);
2148 struct typhoon *tp = netdev_priv(dev);
2149 struct cmd_desc xp_cmd;
2150
2151 /* If we're down, we're already suspended.
2152 */
2153 if(!netif_running(dev))
2154 return 0;
2155
2156 /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2157 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2158 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2159
2160 netif_device_detach(dev);
2161
2162 if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2163 netdev_err(dev, "unable to stop runtime\n");
2164 goto need_resume;
2165 }
2166
2167 typhoon_free_rx_rings(tp);
2168 typhoon_init_rings(tp);
2169
2170 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2171 netdev_err(dev, "unable to boot sleep image\n");
2172 goto need_resume;
2173 }
2174
2175 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2176 xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2177 xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2178 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2179 netdev_err(dev, "unable to set mac address in suspend\n");
2180 goto need_resume;
2181 }
2182
2183 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2184 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2185 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2186 netdev_err(dev, "unable to set rx filter in suspend\n");
2187 goto need_resume;
2188 }
2189
2190 if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2191 netdev_err(dev, "unable to put card to sleep\n");
2192 goto need_resume;
2193 }
2194
2195 return 0;
2196
2197need_resume:
2198 typhoon_resume(pdev);
2199 return -EBUSY;
2200}
2201#endif
2202
2203static int
2204typhoon_test_mmio(struct pci_dev *pdev)
2205{
2206 void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2207 int mode = 0;
2208 u32 val;
2209
2210 if(!ioaddr)
2211 goto out;
2212
2213 if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2214 TYPHOON_STATUS_WAITING_FOR_HOST)
2215 goto out_unmap;
2216
2217 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2218 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2219 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2220
2221 /* Ok, see if we can change our interrupt status register by
2222 * sending ourselves an interrupt. If so, then MMIO works.
2223 * The 50usec delay is arbitrary -- it could probably be smaller.
2224 */
2225 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2226 if((val & TYPHOON_INTR_SELF) == 0) {
2227 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2228 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2229 udelay(50);
2230 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2231 if(val & TYPHOON_INTR_SELF)
2232 mode = 1;
2233 }
2234
2235 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2236 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2237 iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2238 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2239
2240out_unmap:
2241 pci_iounmap(pdev, ioaddr);
2242
2243out:
2244 if(!mode)
2245 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2246 return mode;
2247}
2248
2249static const struct net_device_ops typhoon_netdev_ops = {
2250 .ndo_open = typhoon_open,
2251 .ndo_stop = typhoon_close,
2252 .ndo_start_xmit = typhoon_start_tx,
2253 .ndo_set_rx_mode = typhoon_set_rx_mode,
2254 .ndo_tx_timeout = typhoon_tx_timeout,
2255 .ndo_get_stats = typhoon_get_stats,
2256 .ndo_validate_addr = eth_validate_addr,
2257 .ndo_set_mac_address = eth_mac_addr,
2258 .ndo_change_mtu = eth_change_mtu,
2259};
2260
2261static int
2262typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2263{
2264 struct net_device *dev;
2265 struct typhoon *tp;
2266 int card_id = (int) ent->driver_data;
2267 void __iomem *ioaddr;
2268 void *shared;
2269 dma_addr_t shared_dma;
2270 struct cmd_desc xp_cmd;
2271 struct resp_desc xp_resp[3];
2272 int err = 0;
2273 const char *err_msg;
2274
2275 dev = alloc_etherdev(sizeof(*tp));
2276 if(dev == NULL) {
2277 err_msg = "unable to alloc new net device";
2278 err = -ENOMEM;
2279 goto error_out;
2280 }
2281 SET_NETDEV_DEV(dev, &pdev->dev);
2282
2283 err = pci_enable_device(pdev);
2284 if(err < 0) {
2285 err_msg = "unable to enable device";
2286 goto error_out_dev;
2287 }
2288
2289 err = pci_set_mwi(pdev);
2290 if(err < 0) {
2291 err_msg = "unable to set MWI";
2292 goto error_out_disable;
2293 }
2294
2295 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2296 if(err < 0) {
2297 err_msg = "No usable DMA configuration";
2298 goto error_out_mwi;
2299 }
2300
2301 /* sanity checks on IO and MMIO BARs
2302 */
2303 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2304 err_msg = "region #1 not a PCI IO resource, aborting";
2305 err = -ENODEV;
2306 goto error_out_mwi;
2307 }
2308 if(pci_resource_len(pdev, 0) < 128) {
2309 err_msg = "Invalid PCI IO region size, aborting";
2310 err = -ENODEV;
2311 goto error_out_mwi;
2312 }
2313 if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2314 err_msg = "region #1 not a PCI MMIO resource, aborting";
2315 err = -ENODEV;
2316 goto error_out_mwi;
2317 }
2318 if(pci_resource_len(pdev, 1) < 128) {
2319 err_msg = "Invalid PCI MMIO region size, aborting";
2320 err = -ENODEV;
2321 goto error_out_mwi;
2322 }
2323
2324 err = pci_request_regions(pdev, KBUILD_MODNAME);
2325 if(err < 0) {
2326 err_msg = "could not request regions";
2327 goto error_out_mwi;
2328 }
2329
2330 /* map our registers
2331 */
2332 if(use_mmio != 0 && use_mmio != 1)
2333 use_mmio = typhoon_test_mmio(pdev);
2334
2335 ioaddr = pci_iomap(pdev, use_mmio, 128);
2336 if (!ioaddr) {
2337 err_msg = "cannot remap registers, aborting";
2338 err = -EIO;
2339 goto error_out_regions;
2340 }
2341
2342 /* allocate pci dma space for rx and tx descriptor rings
2343 */
2344 shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2345 &shared_dma);
2346 if(!shared) {
2347 err_msg = "could not allocate DMA memory";
2348 err = -ENOMEM;
2349 goto error_out_remap;
2350 }
2351
2352 dev->irq = pdev->irq;
2353 tp = netdev_priv(dev);
2354 tp->shared = shared;
2355 tp->shared_dma = shared_dma;
2356 tp->pdev = pdev;
2357 tp->tx_pdev = pdev;
2358 tp->ioaddr = ioaddr;
2359 tp->tx_ioaddr = ioaddr;
2360 tp->dev = dev;
2361
2362 /* Init sequence:
2363 * 1) Reset the adapter to clear any bad juju
2364 * 2) Reload the sleep image
2365 * 3) Boot the sleep image
2366 * 4) Get the hardware address.
2367 * 5) Put the card to sleep.
2368 */
2369 if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2370 err_msg = "could not reset 3XP";
2371 err = -EIO;
2372 goto error_out_dma;
2373 }
2374
2375 /* Now that we've reset the 3XP and are sure it's not going to
2376 * write all over memory, enable bus mastering, and save our
2377 * state for resuming after a suspend.
2378 */
2379 pci_set_master(pdev);
2380 pci_save_state(pdev);
2381
2382 typhoon_init_interface(tp);
2383 typhoon_init_rings(tp);
2384
2385 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2386 err_msg = "cannot boot 3XP sleep image";
2387 err = -EIO;
2388 goto error_out_reset;
2389 }
2390
2391 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2392 if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2393 err_msg = "cannot read MAC address";
2394 err = -EIO;
2395 goto error_out_reset;
2396 }
2397
2398 *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2399 *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2400
2401 if(!is_valid_ether_addr(dev->dev_addr)) {
2402 err_msg = "Could not obtain valid ethernet address, aborting";
2403 goto error_out_reset;
2404 }
2405
2406 /* Read the Sleep Image version last, so the response is valid
2407 * later when we print out the version reported.
2408 */
2409 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2410 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2411 err_msg = "Could not get Sleep Image version";
2412 goto error_out_reset;
2413 }
2414
2415 tp->capabilities = typhoon_card_info[card_id].capabilities;
2416 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2417
2418 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2419 * READ_VERSIONS command. Those versions are OK after waking up
2420 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2421 * seem to need a little extra help to get started. Since we don't
2422 * know how to nudge it along, just kick it.
2423 */
2424 if(xp_resp[0].numDesc != 0)
2425 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2426
2427 if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2428 err_msg = "cannot put adapter to sleep";
2429 err = -EIO;
2430 goto error_out_reset;
2431 }
2432
2433 /* The chip-specific entries in the device structure. */
2434 dev->netdev_ops = &typhoon_netdev_ops;
2435 netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2436 dev->watchdog_timeo = TX_TIMEOUT;
2437
2438 dev->ethtool_ops = &typhoon_ethtool_ops;
2439
2440 /* We can handle scatter gather, up to 16 entries, and
2441 * we can do IP checksumming (only version 4, doh...)
2442 *
2443 * There's no way to turn off the RX VLAN offloading and stripping
2444 * on the current 3XP firmware -- it does not respect the offload
2445 * settings -- so we only allow the user to toggle the TX processing.
2446 */
2447 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2448 NETIF_F_HW_VLAN_CTAG_TX;
2449 dev->features = dev->hw_features |
2450 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_RXCSUM;
2451
2452 if(register_netdev(dev) < 0) {
2453 err_msg = "unable to register netdev";
2454 goto error_out_reset;
2455 }
2456
2457 pci_set_drvdata(pdev, dev);
2458
2459 netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2460 typhoon_card_info[card_id].name,
2461 use_mmio ? "MMIO" : "IO",
2462 (unsigned long long)pci_resource_start(pdev, use_mmio),
2463 dev->dev_addr);
2464
2465 /* xp_resp still contains the response to the READ_VERSIONS command.
2466 * For debugging, let the user know what version he has.
2467 */
2468 if(xp_resp[0].numDesc == 0) {
2469 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2470 * of version is Month/Day of build.
2471 */
2472 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2473 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2474 monthday >> 8, monthday & 0xff);
2475 } else if(xp_resp[0].numDesc == 2) {
2476 /* This is the Typhoon 1.1+ type Sleep Image
2477 */
2478 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2479 u8 *ver_string = (u8 *) &xp_resp[1];
2480 ver_string[25] = 0;
2481 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2482 sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2483 sleep_ver & 0xfff, ver_string);
2484 } else {
2485 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2486 xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2487 }
2488
2489 return 0;
2490
2491error_out_reset:
2492 typhoon_reset(ioaddr, NoWait);
2493
2494error_out_dma:
2495 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2496 shared, shared_dma);
2497error_out_remap:
2498 pci_iounmap(pdev, ioaddr);
2499error_out_regions:
2500 pci_release_regions(pdev);
2501error_out_mwi:
2502 pci_clear_mwi(pdev);
2503error_out_disable:
2504 pci_disable_device(pdev);
2505error_out_dev:
2506 free_netdev(dev);
2507error_out:
2508 pr_err("%s: %s\n", pci_name(pdev), err_msg);
2509 return err;
2510}
2511
2512static void
2513typhoon_remove_one(struct pci_dev *pdev)
2514{
2515 struct net_device *dev = pci_get_drvdata(pdev);
2516 struct typhoon *tp = netdev_priv(dev);
2517
2518 unregister_netdev(dev);
2519 pci_set_power_state(pdev, PCI_D0);
2520 pci_restore_state(pdev);
2521 typhoon_reset(tp->ioaddr, NoWait);
2522 pci_iounmap(pdev, tp->ioaddr);
2523 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2524 tp->shared, tp->shared_dma);
2525 pci_release_regions(pdev);
2526 pci_clear_mwi(pdev);
2527 pci_disable_device(pdev);
2528 free_netdev(dev);
2529}
2530
2531static struct pci_driver typhoon_driver = {
2532 .name = KBUILD_MODNAME,
2533 .id_table = typhoon_pci_tbl,
2534 .probe = typhoon_init_one,
2535 .remove = typhoon_remove_one,
2536#ifdef CONFIG_PM
2537 .suspend = typhoon_suspend,
2538 .resume = typhoon_resume,
2539#endif
2540};
2541
2542static int __init
2543typhoon_init(void)
2544{
2545 return pci_register_driver(&typhoon_driver);
2546}
2547
2548static void __exit
2549typhoon_cleanup(void)
2550{
2551 release_firmware(typhoon_fw);
2552 pci_unregister_driver(&typhoon_driver);
2553}
2554
2555module_init(typhoon_init);
2556module_exit(typhoon_cleanup);