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1/* SPDX-License-Identifier: GPL-2.0 */
2
3/* Register Base Addresses */
4#define XRS_DEVICE_ID_BASE 0x0
5#define XRS_GPIO_BASE 0x10000
6#define XRS_PORT_OFFSET 0x10000
7#define XRS_PORT_BASE(x) (0x200000 + XRS_PORT_OFFSET * (x))
8#define XRS_RTC_BASE 0x280000
9#define XRS_TS_OFFSET 0x8000
10#define XRS_TS_BASE(x) (0x290000 + XRS_TS_OFFSET * (x))
11#define XRS_SWITCH_CONF_BASE 0x300000
12
13/* Device Identification Registers */
14#define XRS_DEV_ID0 (XRS_DEVICE_ID_BASE + 0)
15#define XRS_DEV_ID1 (XRS_DEVICE_ID_BASE + 2)
16#define XRS_INT_ID0 (XRS_DEVICE_ID_BASE + 4)
17#define XRS_INT_ID1 (XRS_DEVICE_ID_BASE + 6)
18#define XRS_REV_ID (XRS_DEVICE_ID_BASE + 8)
19
20/* GPIO Registers */
21#define XRS_CONFIG0 (XRS_GPIO_BASE + 0x1000)
22#define XRS_INPUT_STATUS0 (XRS_GPIO_BASE + 0x1002)
23#define XRS_CONFIG1 (XRS_GPIO_BASE + 0x1004)
24#define XRS_INPUT_STATUS1 (XRS_GPIO_BASE + 0x1006)
25#define XRS_CONFIG2 (XRS_GPIO_BASE + 0x1008)
26#define XRS_INPUT_STATUS2 (XRS_GPIO_BASE + 0x100a)
27
28/* Port Configuration Registers */
29#define XRS_PORT_GEN_BASE(x) (XRS_PORT_BASE(x) + 0x0)
30#define XRS_PORT_HSR_BASE(x) (XRS_PORT_BASE(x) + 0x2000)
31#define XRS_PORT_PTP_BASE(x) (XRS_PORT_BASE(x) + 0x4000)
32#define XRS_PORT_CNT_BASE(x) (XRS_PORT_BASE(x) + 0x6000)
33#define XRS_PORT_IPO_BASE(x) (XRS_PORT_BASE(x) + 0x8000)
34
35/* Port Configuration Registers - General and State */
36#define XRS_PORT_STATE(x) (XRS_PORT_GEN_BASE(x) + 0x0)
37#define XRS_PORT_FORWARDING 0
38#define XRS_PORT_LEARNING 1
39#define XRS_PORT_DISABLED 2
40#define XRS_PORT_MODE_NORMAL 0
41#define XRS_PORT_MODE_MANAGEMENT 1
42#define XRS_PORT_SPEED_1000 0x12
43#define XRS_PORT_SPEED_100 0x20
44#define XRS_PORT_SPEED_10 0x30
45#define XRS_PORT_VLAN(x) (XRS_PORT_GEN_BASE(x) + 0x10)
46#define XRS_PORT_VLAN0_MAPPING(x) (XRS_PORT_GEN_BASE(x) + 0x12)
47#define XRS_PORT_FWD_MASK(x) (XRS_PORT_GEN_BASE(x) + 0x14)
48#define XRS_PORT_VLAN_PRIO(x) (XRS_PORT_GEN_BASE(x) + 0x16)
49
50/* Port Configuration Registers - HSR/PRP */
51#define XRS_HSR_CFG(x) (XRS_PORT_HSR_BASE(x) + 0x0)
52#define XRS_HSR_CFG_HSR_PRP BIT(0)
53#define XRS_HSR_CFG_HSR 0
54#define XRS_HSR_CFG_PRP BIT(8)
55#define XRS_HSR_CFG_LANID_A 0
56#define XRS_HSR_CFG_LANID_B BIT(10)
57
58/* Port Configuration Registers - PTP */
59#define XRS_PTP_RX_SYNC_DELAY_NS_LO(x) (XRS_PORT_PTP_BASE(x) + 0x2)
60#define XRS_PTP_RX_SYNC_DELAY_NS_HI(x) (XRS_PORT_PTP_BASE(x) + 0x4)
61#define XRS_PTP_RX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0xa)
62#define XRS_PTP_TX_EVENT_DELAY_NS(x) (XRS_PORT_PTP_BASE(x) + 0x12)
63
64/* Port Configuration Registers - Counter */
65#define XRS_CNT_CTRL(x) (XRS_PORT_CNT_BASE(x) + 0x0)
66#define XRS_RX_GOOD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x200)
67#define XRS_RX_GOOD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x202)
68#define XRS_RX_BAD_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x204)
69#define XRS_RX_BAD_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x206)
70#define XRS_RX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x208)
71#define XRS_RX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x20a)
72#define XRS_RX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x20c)
73#define XRS_RX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x20e)
74#define XRS_RX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x210)
75#define XRS_RX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x212)
76#define XRS_RX_UNDERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x214)
77#define XRS_RX_UNDERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x216)
78#define XRS_RX_FRAGMENTS_L (XRS_PORT_CNT_BASE(0) + 0x218)
79#define XRS_RX_FRAGMENTS_H (XRS_PORT_CNT_BASE(0) + 0x21a)
80#define XRS_RX_OVERSIZE_L (XRS_PORT_CNT_BASE(0) + 0x21c)
81#define XRS_RX_OVERSIZE_H (XRS_PORT_CNT_BASE(0) + 0x21e)
82#define XRS_RX_JABBER_L (XRS_PORT_CNT_BASE(0) + 0x220)
83#define XRS_RX_JABBER_H (XRS_PORT_CNT_BASE(0) + 0x222)
84#define XRS_RX_ERR_L (XRS_PORT_CNT_BASE(0) + 0x224)
85#define XRS_RX_ERR_H (XRS_PORT_CNT_BASE(0) + 0x226)
86#define XRS_RX_CRC_L (XRS_PORT_CNT_BASE(0) + 0x228)
87#define XRS_RX_CRC_H (XRS_PORT_CNT_BASE(0) + 0x22a)
88#define XRS_RX_64_L (XRS_PORT_CNT_BASE(0) + 0x22c)
89#define XRS_RX_64_H (XRS_PORT_CNT_BASE(0) + 0x22e)
90#define XRS_RX_65_127_L (XRS_PORT_CNT_BASE(0) + 0x230)
91#define XRS_RX_65_127_H (XRS_PORT_CNT_BASE(0) + 0x232)
92#define XRS_RX_128_255_L (XRS_PORT_CNT_BASE(0) + 0x234)
93#define XRS_RX_128_255_H (XRS_PORT_CNT_BASE(0) + 0x236)
94#define XRS_RX_256_511_L (XRS_PORT_CNT_BASE(0) + 0x238)
95#define XRS_RX_256_511_H (XRS_PORT_CNT_BASE(0) + 0x23a)
96#define XRS_RX_512_1023_L (XRS_PORT_CNT_BASE(0) + 0x23c)
97#define XRS_RX_512_1023_H (XRS_PORT_CNT_BASE(0) + 0x23e)
98#define XRS_RX_1024_1536_L (XRS_PORT_CNT_BASE(0) + 0x240)
99#define XRS_RX_1024_1536_H (XRS_PORT_CNT_BASE(0) + 0x242)
100#define XRS_RX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x244)
101#define XRS_RX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x246)
102#define XRS_RX_WRONGLAN_L (XRS_PORT_CNT_BASE(0) + 0x248)
103#define XRS_RX_WRONGLAN_H (XRS_PORT_CNT_BASE(0) + 0x24a)
104#define XRS_RX_DUPLICATE_L (XRS_PORT_CNT_BASE(0) + 0x24c)
105#define XRS_RX_DUPLICATE_H (XRS_PORT_CNT_BASE(0) + 0x24e)
106#define XRS_TX_OCTETS_L (XRS_PORT_CNT_BASE(0) + 0x280)
107#define XRS_TX_OCTETS_H (XRS_PORT_CNT_BASE(0) + 0x282)
108#define XRS_TX_UNICAST_L (XRS_PORT_CNT_BASE(0) + 0x284)
109#define XRS_TX_UNICAST_H (XRS_PORT_CNT_BASE(0) + 0x286)
110#define XRS_TX_BROADCAST_L (XRS_PORT_CNT_BASE(0) + 0x288)
111#define XRS_TX_BROADCAST_H (XRS_PORT_CNT_BASE(0) + 0x28a)
112#define XRS_TX_MULTICAST_L (XRS_PORT_CNT_BASE(0) + 0x28c)
113#define XRS_TX_MULTICAST_H (XRS_PORT_CNT_BASE(0) + 0x28e)
114#define XRS_TX_HSR_PRP_L (XRS_PORT_CNT_BASE(0) + 0x290)
115#define XRS_TX_HSR_PRP_H (XRS_PORT_CNT_BASE(0) + 0x292)
116#define XRS_PRIQ_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c0)
117#define XRS_PRIQ_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c2)
118#define XRS_EARLY_DROP_L (XRS_PORT_CNT_BASE(0) + 0x2c4)
119#define XRS_EARLY_DROP_H (XRS_PORT_CNT_BASE(0) + 0x2c6)
120
121/* Port Configuration Registers - Inbound Policy 0 - 15 */
122#define XRS_ETH_ADDR_CFG(x, p) (XRS_PORT_IPO_BASE(x) + \
123 (p) * 0x20 + 0x0)
124#define XRS_ETH_ADDR_FWD_ALLOW(x, p) (XRS_PORT_IPO_BASE(x) + \
125 (p) * 0x20 + 0x2)
126#define XRS_ETH_ADDR_FWD_MIRROR(x, p) (XRS_PORT_IPO_BASE(x) + \
127 (p) * 0x20 + 0x4)
128#define XRS_ETH_ADDR_0(x, p) (XRS_PORT_IPO_BASE(x) + \
129 (p) * 0x20 + 0x8)
130#define XRS_ETH_ADDR_1(x, p) (XRS_PORT_IPO_BASE(x) + \
131 (p) * 0x20 + 0xa)
132#define XRS_ETH_ADDR_2(x, p) (XRS_PORT_IPO_BASE(x) + \
133 (p) * 0x20 + 0xc)
134
135/* RTC Registers */
136#define XRS_CUR_NSEC0 (XRS_RTC_BASE + 0x1004)
137#define XRS_CUR_NSEC1 (XRS_RTC_BASE + 0x1006)
138#define XRS_CUR_SEC0 (XRS_RTC_BASE + 0x1008)
139#define XRS_CUR_SEC1 (XRS_RTC_BASE + 0x100a)
140#define XRS_CUR_SEC2 (XRS_RTC_BASE + 0x100c)
141#define XRS_TIME_CC0 (XRS_RTC_BASE + 0x1010)
142#define XRS_TIME_CC1 (XRS_RTC_BASE + 0x1012)
143#define XRS_TIME_CC2 (XRS_RTC_BASE + 0x1014)
144#define XRS_STEP_SIZE0 (XRS_RTC_BASE + 0x1020)
145#define XRS_STEP_SIZE1 (XRS_RTC_BASE + 0x1022)
146#define XRS_STEP_SIZE2 (XRS_RTC_BASE + 0x1024)
147#define XRS_ADJUST_NSEC0 (XRS_RTC_BASE + 0x1034)
148#define XRS_ADJUST_NSEC1 (XRS_RTC_BASE + 0x1036)
149#define XRS_ADJUST_SEC0 (XRS_RTC_BASE + 0x1038)
150#define XRS_ADJUST_SEC1 (XRS_RTC_BASE + 0x103a)
151#define XRS_ADJUST_SEC2 (XRS_RTC_BASE + 0x103c)
152#define XRS_TIME_CMD (XRS_RTC_BASE + 0x1040)
153
154/* Time Stamper Registers */
155#define XRS_TS_CTRL(x) (XRS_TS_BASE(x) + 0x1000)
156#define XRS_TS_INT_MASK(x) (XRS_TS_BASE(x) + 0x1008)
157#define XRS_TS_INT_STATUS(x) (XRS_TS_BASE(x) + 0x1010)
158#define XRS_TS_NSEC0(x) (XRS_TS_BASE(x) + 0x1104)
159#define XRS_TS_NSEC1(x) (XRS_TS_BASE(x) + 0x1106)
160#define XRS_TS_SEC0(x) (XRS_TS_BASE(x) + 0x1108)
161#define XRS_TS_SEC1(x) (XRS_TS_BASE(x) + 0x110a)
162#define XRS_TS_SEC2(x) (XRS_TS_BASE(x) + 0x110c)
163#define XRS_PNCT0(x) (XRS_TS_BASE(x) + 0x1110)
164#define XRS_PNCT1(x) (XRS_TS_BASE(x) + 0x1112)
165
166/* Switch Configuration Registers */
167#define XRS_SWITCH_GEN_BASE (XRS_SWITCH_CONF_BASE + 0x0)
168#define XRS_SWITCH_TS_BASE (XRS_SWITCH_CONF_BASE + 0x2000)
169#define XRS_SWITCH_VLAN_BASE (XRS_SWITCH_CONF_BASE + 0x4000)
170
171/* Switch Configuration Registers - General */
172#define XRS_GENERAL (XRS_SWITCH_GEN_BASE + 0x10)
173#define XRS_GENERAL_TIME_TRAILER BIT(9)
174#define XRS_GENERAL_MOD_SYNC BIT(10)
175#define XRS_GENERAL_CUT_THRU BIT(13)
176#define XRS_GENERAL_CLR_MAC_TBL BIT(14)
177#define XRS_GENERAL_RESET BIT(15)
178#define XRS_MT_CLEAR_MASK (XRS_SWITCH_GEN_BASE + 0x12)
179#define XRS_ADDRESS_AGING (XRS_SWITCH_GEN_BASE + 0x20)
180#define XRS_TS_CTRL_TX (XRS_SWITCH_GEN_BASE + 0x28)
181#define XRS_TS_CTRL_RX (XRS_SWITCH_GEN_BASE + 0x2a)
182#define XRS_INT_MASK (XRS_SWITCH_GEN_BASE + 0x2c)
183#define XRS_INT_STATUS (XRS_SWITCH_GEN_BASE + 0x2e)
184#define XRS_MAC_TABLE0 (XRS_SWITCH_GEN_BASE + 0x200)
185#define XRS_MAC_TABLE1 (XRS_SWITCH_GEN_BASE + 0x202)
186#define XRS_MAC_TABLE2 (XRS_SWITCH_GEN_BASE + 0x204)
187#define XRS_MAC_TABLE3 (XRS_SWITCH_GEN_BASE + 0x206)
188
189/* Switch Configuration Registers - Frame Timestamp */
190#define XRS_TX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x0)
191#define XRS_TX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x2)
192#define XRS_TX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x4)
193#define XRS_TX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + 0x6)
194#define XRS_TX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
195 0x2 * (h) + 0xe)
196#define XRS_RX_TS_NS_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
197 0x200)
198#define XRS_RX_TS_NS_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
199 0x202)
200#define XRS_RX_TS_S_LO(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
201 0x204)
202#define XRS_RX_TS_S_HI(t) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
203 0x206)
204#define XRS_RX_TS_HDR(t, h) (XRS_SWITCH_TS_BASE + 0x80 * (t) + \
205 0x2 * (h) + 0xe)
206
207/* Switch Configuration Registers - VLAN */
208#define XRS_VLAN(v) (XRS_SWITCH_VLAN_BASE + 0x2 * (v))