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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Marvell 88E6xxx Switch Port Registers support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 */
10
11#ifndef _MV88E6XXX_PORT_H
12#define _MV88E6XXX_PORT_H
13
14#include "chip.h"
15
16/* Offset 0x00: Port Status Register */
17#define MV88E6XXX_PORT_STS 0x00
18#define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19#define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20#define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21#define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22#define MV88E6250_PORT_STS_LINK 0x1000
23#define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24#define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
26#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00
27#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00
28#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF 0x0c00
29#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF 0x0d00
30#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL 0x0e00
31#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL 0x0f00
32#define MV88E6XXX_PORT_STS_LINK 0x0800
33#define MV88E6XXX_PORT_STS_DUPLEX 0x0400
34#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300
35#define MV88E6XXX_PORT_STS_SPEED_10 0x0000
36#define MV88E6XXX_PORT_STS_SPEED_100 0x0100
37#define MV88E6XXX_PORT_STS_SPEED_1000 0x0200
38#define MV88E6XXX_PORT_STS_SPEED_10000 0x0300
39#define MV88E6352_PORT_STS_EEE 0x0040
40#define MV88E6165_PORT_STS_AM_DIS 0x0040
41#define MV88E6185_PORT_STS_MGMII 0x0040
42#define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020
43#define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010
44#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f
45#define MV88E6XXX_PORT_STS_CMODE_MII_PHY 0x0001
46#define MV88E6XXX_PORT_STS_CMODE_MII 0x0002
47#define MV88E6XXX_PORT_STS_CMODE_GMII 0x0003
48#define MV88E6XXX_PORT_STS_CMODE_RMII_PHY 0x0004
49#define MV88E6XXX_PORT_STS_CMODE_RMII 0x0005
50#define MV88E6XXX_PORT_STS_CMODE_RGMII 0x0007
51#define MV88E6XXX_PORT_STS_CMODE_100BASEX 0x0008
52#define MV88E6XXX_PORT_STS_CMODE_1000BASEX 0x0009
53#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a
54#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b
55#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c
56#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d
57#define MV88E6393X_PORT_STS_CMODE_5GBASER 0x000c
58#define MV88E6393X_PORT_STS_CMODE_10GBASER 0x000d
59#define MV88E6393X_PORT_STS_CMODE_USXGMII 0x000e
60#define MV88E6185_PORT_STS_CDUPLEX 0x0008
61#define MV88E6185_PORT_STS_CMODE_MASK 0x0007
62#define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000
63#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001
64#define MV88E6185_PORT_STS_CMODE_MII_100 0x0002
65#define MV88E6185_PORT_STS_CMODE_MII_10 0x0003
66#define MV88E6185_PORT_STS_CMODE_SERDES 0x0004
67#define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005
68#define MV88E6185_PORT_STS_CMODE_PHY 0x0006
69#define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007
70
71/* Offset 0x01: MAC (or PCS or Physical) Control Register */
72#define MV88E6XXX_PORT_MAC_CTL 0x01
73#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000
74#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000
75#define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000
76#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000
77#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000
78#define MV88E6352_PORT_MAC_CTL_200BASE 0x1000
79#define MV88E6XXX_PORT_MAC_CTL_EEE 0x0200
80#define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE 0x0100
81#define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400
82#define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200
83#define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100
84#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080
85#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040
86#define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020
87#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010
88#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008
89#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004
90#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003
91#define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000
92#define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001
93#define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002
94#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002
95#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003
96#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003
97
98/* Offset 0x02: Jamming Control Register */
99#define MV88E6097_PORT_JAM_CTL 0x02
100#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00
101#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff
102
103/* Offset 0x02: Flow Control Register */
104#define MV88E6390_PORT_FLOW_CTL 0x02
105#define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000
106#define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00
107#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000
108#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100
109#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff
110
111/* Offset 0x03: Switch Identifier Register */
112#define MV88E6XXX_PORT_SWITCH_ID 0x03
113#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0
114#define MV88E6XXX_PORT_SWITCH_ID_PROD_6020 0x0200
115#define MV88E6XXX_PORT_SWITCH_ID_PROD_6071 0x0710
116#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0
117#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950
118#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990
119#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00
120#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10
121#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060
122#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150
123#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210
124#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610
125#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650
126#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710
127#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720
128#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750
129#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760
130#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900
131#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910
132#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920
133#define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930
134#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70
135#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200
136#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
137#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500
138#define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610
139#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
140#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
141#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400
142#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410
143#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520
144#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710
145#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750
146#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900
147#define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930
148#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f
149
150/* Offset 0x04: Port Control Register */
151#define MV88E6XXX_PORT_CTL0 0x04
152#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000
153#define MV88E6XXX_PORT_CTL0_SA_FILT_MASK 0xc000
154#define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED 0x0000
155#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK 0x4000
156#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK 0x8000
157#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU 0xc000
158#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000
159#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000
160#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000
161#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000
162#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000
163#define MV88E6XXX_PORT_CTL0_HEADER 0x0800
164#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400
165#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200
166#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300
167#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000
168#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100
169#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200
170#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300
171#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100
172#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080
173#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040
174#define MV88E6185_PORT_CTL0_USE_IP 0x0020
175#define MV88E6185_PORT_CTL0_USE_TAG 0x0010
176#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004
177#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC 0x0004
178#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC 0x0008
179#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003
180#define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000
181#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001
182#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002
183#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003
184
185/* Offset 0x05: Port Control 1 */
186#define MV88E6XXX_PORT_CTL1 0x05
187#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000
188#define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000
189#define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00
190#define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8
191#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff
192
193/* Offset 0x06: Port Based VLAN Map */
194#define MV88E6XXX_PORT_BASE_VLAN 0x06
195#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000
196
197/* Offset 0x07: Default Port VLAN ID & Priority */
198#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07
199#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff
200
201/* Offset 0x08: Port Control 2 Register */
202#define MV88E6XXX_PORT_CTL2 0x08
203#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000
204#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000
205#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000
206#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000
207#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000
208#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000
209#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000
210#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000
211#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00
212#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000
213#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400
214#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800
215#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00
216#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200
217#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100
218#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080
219#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040
220#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020
221#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010
222#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f
223
224/* Offset 0x09: Egress Rate Control */
225#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09
226
227/* Offset 0x0A: Egress Rate Control 2 */
228#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a
229
230/* Offset 0x0B: Port Association Vector */
231#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b
232#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000
233#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000
234#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000
235#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000
236#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800
237
238/* Offset 0x0C: Port ATU Control */
239#define MV88E6XXX_PORT_ATU_CTL 0x0c
240
241/* Offset 0x0D: Priority Override Register */
242#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d
243
244/* Offset 0x0E: Policy Control Register */
245#define MV88E6XXX_PORT_POLICY_CTL 0x0e
246#define MV88E6XXX_PORT_POLICY_CTL_DA_MASK 0xc000
247#define MV88E6XXX_PORT_POLICY_CTL_SA_MASK 0x3000
248#define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK 0x0c00
249#define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK 0x0300
250#define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK 0x00c0
251#define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030
252#define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK 0x000c
253#define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK 0x0003
254#define MV88E6XXX_PORT_POLICY_CTL_NORMAL 0x0000
255#define MV88E6XXX_PORT_POLICY_CTL_MIRROR 0x0001
256#define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002
257#define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003
258
259/* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */
260#define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e
261#define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000
262#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00
263#define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff
264#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000
265#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100
266#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400
267#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500
268#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000
269#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800
270#define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0
271
272/* Offset 0x0F: Port Special Ether Type */
273#define MV88E6XXX_PORT_ETH_TYPE 0x0f
274#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100
275
276/* Offset 0x10: InDiscards Low Counter */
277#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10
278
279/* Offset 0x10: Extended Port Control Command */
280#define MV88E6393X_PORT_EPC_CMD 0x10
281#define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000
282#define MV88E6393X_PORT_EPC_CMD_WRITE 0x3000
283#define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02
284
285/* Offset 0x11: Extended Port Control Data */
286#define MV88E6393X_PORT_EPC_DATA 0x11
287
288/* Offset 0x11: InDiscards High Counter */
289#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11
290
291/* Offset 0x12: InFiltered Counter */
292#define MV88E6XXX_PORT_IN_FILTERED 0x12
293
294/* Offset 0x13: OutFiltered Counter */
295#define MV88E6XXX_PORT_OUT_FILTERED 0x13
296
297/* Offset 0x18: IEEE Priority Mapping Table */
298#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18
299#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000
300#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000
301#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000
302#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000
303#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000
304#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000
305#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000
306#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000
307#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000
308#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00
309#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff
310
311/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
312#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18
313
314/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
315#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19
316
317/* Offset 0x1a: Magic undocumented errata register */
318#define MV88E6XXX_PORT_RESERVED_1A 0x1a
319#define MV88E6XXX_PORT_RESERVED_1A_BUSY 0x8000
320#define MV88E6XXX_PORT_RESERVED_1A_WRITE 0x4000
321#define MV88E6XXX_PORT_RESERVED_1A_READ 0x0000
322#define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT 5
323#define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT 10
324#define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT 0x04
325#define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT 0x05
326#define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE 0x8000
327#define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000
328
329int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
330 u16 *val);
331int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
332 u16 val);
333int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,
334 int bit, int val);
335
336int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
337 int pause);
338int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
339 phy_interface_t mode);
340int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
341 phy_interface_t mode);
342int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
343 phy_interface_t mode);
344
345int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
346
347int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
348int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
349
350int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
351 int speed, int duplex);
352int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
353 int speed, int duplex);
354int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
355 int speed, int duplex);
356int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
357 int speed, int duplex);
358int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
359 int speed, int duplex);
360int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
361 int speed, int duplex);
362int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,
363 int speed, int duplex);
364
365phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,
366 int port);
367phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,
368 int port);
369phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
370 int port);
371phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,
372 int port);
373
374int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
375
376int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
377
378int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
379int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
380
381int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
382int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
383
384int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,
385 bool locked);
386
387int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
388 u16 mode);
389int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
390int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
391int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
392 enum mv88e6xxx_egress_mode mode);
393int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
394 enum mv88e6xxx_frame_mode mode);
395int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
396 enum mv88e6xxx_frame_mode mode);
397int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
398 int port, bool unicast);
399int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
400 int port, bool multicast);
401int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,
402 bool unicast);
403int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,
404 bool multicast);
405int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,
406 enum mv88e6xxx_policy_mapping mapping,
407 enum mv88e6xxx_policy_action action);
408int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,
409 enum mv88e6xxx_policy_mapping mapping,
410 enum mv88e6xxx_policy_action action);
411int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
412 u16 etype);
413int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,
414 enum mv88e6xxx_egress_direction direction,
415 int port);
416int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
417 int upstream_port);
418int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
419int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
420 u16 etype);
421int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
422 bool message_port);
423int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,
424 bool trunk, u8 id);
425int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
426 size_t size);
427int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
428int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
429int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,
430 u16 pav);
431int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
432 u8 out);
433int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
434 u8 out);
435int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
436 phy_interface_t mode);
437int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
438 phy_interface_t mode);
439int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
440 phy_interface_t mode);
441int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
442 phy_interface_t mode);
443int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
444int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
445int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,
446 bool drop_untagged);
447int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map);
448int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
449 int upstream_port);
450int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,
451 enum mv88e6xxx_egress_direction direction,
452 bool mirror);
453
454int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
455int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
456
457int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block,
458 int port, int reg, u16 val);
459int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip);
460int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,
461 int reg, u16 *val);
462
463#endif /* _MV88E6XXX_PORT_H */