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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 */
5
6#ifndef __MT7530_H
7#define __MT7530_H
8
9#define MT7530_NUM_PORTS 7
10#define MT7530_NUM_PHYS 5
11#define MT7530_NUM_FDB_RECORDS 2048
12#define MT7530_ALL_MEMBERS 0xff
13
14#define MTK_HDR_LEN 4
15#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
16
17enum mt753x_id {
18 ID_MT7530 = 0,
19 ID_MT7621 = 1,
20 ID_MT7531 = 2,
21 ID_MT7988 = 3,
22};
23
24#define NUM_TRGMII_CTRL 5
25
26#define TRGMII_BASE(x) (0x10000 + (x))
27
28/* Registers to ethsys access */
29#define ETHSYS_CLKCFG0 0x2c
30#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
31
32#define SYSC_REG_RSTCTRL 0x34
33#define RESET_MCM BIT(2)
34
35/* Registers to mac forward control for unknown frames */
36#define MT7530_MFC 0x10
37#define BC_FFP(x) (((x) & 0xff) << 24)
38#define BC_FFP_MASK BC_FFP(~0)
39#define UNM_FFP(x) (((x) & 0xff) << 16)
40#define UNM_FFP_MASK UNM_FFP(~0)
41#define UNU_FFP(x) (((x) & 0xff) << 8)
42#define UNU_FFP_MASK UNU_FFP(~0)
43#define CPU_EN BIT(7)
44#define CPU_PORT(x) ((x) << 4)
45#define CPU_MASK (0xf << 4)
46#define MIRROR_EN BIT(3)
47#define MIRROR_PORT(x) ((x) & 0x7)
48#define MIRROR_MASK 0x7
49
50/* Registers for CPU forward control */
51#define MT7531_CFC 0x4
52#define MT7531_MIRROR_EN BIT(19)
53#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
54#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
55#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
56#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
57#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
58
59#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
60 MT7531_CFC : MT7530_MFC)
61#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
62 MT7531_MIRROR_EN : MIRROR_EN)
63#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
64 MT7531_MIRROR_MASK : MIRROR_MASK)
65
66/* Registers for BPDU and PAE frame control*/
67#define MT753X_BPC 0x24
68#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
69#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
70#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
71
72/* Register for :03 and :0E MAC DA frame control */
73#define MT753X_RGAC2 0x2c
74#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
75#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
76
77enum mt753x_bpdu_port_fw {
78 MT753X_BPDU_FOLLOW_MFC,
79 MT753X_BPDU_CPU_EXCLUDE = 4,
80 MT753X_BPDU_CPU_INCLUDE = 5,
81 MT753X_BPDU_CPU_ONLY = 6,
82 MT753X_BPDU_DROP = 7,
83};
84
85/* Registers for address table access */
86#define MT7530_ATA1 0x74
87#define STATIC_EMP 0
88#define STATIC_ENT 3
89#define MT7530_ATA2 0x78
90#define ATA2_IVL BIT(15)
91#define ATA2_FID(x) (((x) & 0x7) << 12)
92
93/* Register for address table write data */
94#define MT7530_ATWD 0x7c
95
96/* Register for address table control */
97#define MT7530_ATC 0x80
98#define ATC_HASH (((x) & 0xfff) << 16)
99#define ATC_BUSY BIT(15)
100#define ATC_SRCH_END BIT(14)
101#define ATC_SRCH_HIT BIT(13)
102#define ATC_INVALID BIT(12)
103#define ATC_MAT(x) (((x) & 0xf) << 8)
104#define ATC_MAT_MACTAB ATC_MAT(0)
105
106enum mt7530_fdb_cmd {
107 MT7530_FDB_READ = 0,
108 MT7530_FDB_WRITE = 1,
109 MT7530_FDB_FLUSH = 2,
110 MT7530_FDB_START = 4,
111 MT7530_FDB_NEXT = 5,
112};
113
114/* Registers for table search read address */
115#define MT7530_TSRA1 0x84
116#define MAC_BYTE_0 24
117#define MAC_BYTE_1 16
118#define MAC_BYTE_2 8
119#define MAC_BYTE_3 0
120#define MAC_BYTE_MASK 0xff
121
122#define MT7530_TSRA2 0x88
123#define MAC_BYTE_4 24
124#define MAC_BYTE_5 16
125#define CVID 0
126#define CVID_MASK 0xfff
127
128#define MT7530_ATRD 0x8C
129#define AGE_TIMER 24
130#define AGE_TIMER_MASK 0xff
131#define PORT_MAP 4
132#define PORT_MAP_MASK 0xff
133#define ENT_STATUS 2
134#define ENT_STATUS_MASK 0x3
135
136/* Register for vlan table control */
137#define MT7530_VTCR 0x90
138#define VTCR_BUSY BIT(31)
139#define VTCR_INVALID BIT(16)
140#define VTCR_FUNC(x) (((x) & 0xf) << 12)
141#define VTCR_VID ((x) & 0xfff)
142
143enum mt7530_vlan_cmd {
144 /* Read/Write the specified VID entry from VAWD register based
145 * on VID.
146 */
147 MT7530_VTCR_RD_VID = 0,
148 MT7530_VTCR_WR_VID = 1,
149};
150
151/* Register for setup vlan and acl write data */
152#define MT7530_VAWD1 0x94
153#define PORT_STAG BIT(31)
154/* Independent VLAN Learning */
155#define IVL_MAC BIT(30)
156/* Egress Tag Consistent */
157#define EG_CON BIT(29)
158/* Per VLAN Egress Tag Control */
159#define VTAG_EN BIT(28)
160/* VLAN Member Control */
161#define PORT_MEM(x) (((x) & 0xff) << 16)
162/* Filter ID */
163#define FID(x) (((x) & 0x7) << 1)
164/* VLAN Entry Valid */
165#define VLAN_VALID BIT(0)
166#define PORT_MEM_SHFT 16
167#define PORT_MEM_MASK 0xff
168
169enum mt7530_fid {
170 FID_STANDALONE = 0,
171 FID_BRIDGED = 1,
172};
173
174#define MT7530_VAWD2 0x98
175/* Egress Tag Control */
176#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
177#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
178
179enum mt7530_vlan_egress_attr {
180 MT7530_VLAN_EGRESS_UNTAG = 0,
181 MT7530_VLAN_EGRESS_TAG = 2,
182 MT7530_VLAN_EGRESS_STACK = 3,
183};
184
185/* Register for address age control */
186#define MT7530_AAC 0xa0
187/* Disable ageing */
188#define AGE_DIS BIT(20)
189/* Age count */
190#define AGE_CNT_MASK GENMASK(19, 12)
191#define AGE_CNT_MAX 0xff
192#define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12))
193/* Age unit */
194#define AGE_UNIT_MASK GENMASK(11, 0)
195#define AGE_UNIT_MAX 0xfff
196#define AGE_UNIT(x) (AGE_UNIT_MASK & (x))
197
198/* Register for port STP state control */
199#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
200#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
201#define FID_PST_MASK(fid) FID_PST(fid, 0x3)
202
203enum mt7530_stp_state {
204 MT7530_STP_DISABLED = 0,
205 MT7530_STP_BLOCKING = 1,
206 MT7530_STP_LISTENING = 1,
207 MT7530_STP_LEARNING = 2,
208 MT7530_STP_FORWARDING = 3
209};
210
211/* Register for port control */
212#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
213#define PORT_TX_MIR BIT(9)
214#define PORT_RX_MIR BIT(8)
215#define PORT_VLAN(x) ((x) & 0x3)
216
217enum mt7530_port_mode {
218 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
219 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
220
221 /* Fallback Mode: Forward received frames with ingress ports that do
222 * not belong to the VLAN member. Frames whose VID is not listed on
223 * the VLAN table are forwarded by the PCR_MATRIX members.
224 */
225 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
226
227 /* Security Mode: Discard any frame due to ingress membership
228 * violation or VID missed on the VLAN table.
229 */
230 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
231};
232
233#define PCR_MATRIX(x) (((x) & 0xff) << 16)
234#define PORT_PRI(x) (((x) & 0x7) << 24)
235#define EG_TAG(x) (((x) & 0x3) << 28)
236#define PCR_MATRIX_MASK PCR_MATRIX(0xff)
237#define PCR_MATRIX_CLR PCR_MATRIX(0)
238#define PCR_PORT_VLAN_MASK PORT_VLAN(3)
239
240/* Register for port security control */
241#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
242#define SA_DIS BIT(4)
243
244/* Register for port vlan control */
245#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
246#define PORT_SPEC_TAG BIT(5)
247#define PVC_EG_TAG(x) (((x) & 0x7) << 8)
248#define PVC_EG_TAG_MASK PVC_EG_TAG(7)
249#define VLAN_ATTR(x) (((x) & 0x3) << 6)
250#define VLAN_ATTR_MASK VLAN_ATTR(3)
251#define ACC_FRM_MASK GENMASK(1, 0)
252
253enum mt7530_vlan_port_eg_tag {
254 MT7530_VLAN_EG_DISABLED = 0,
255 MT7530_VLAN_EG_CONSISTENT = 1,
256};
257
258enum mt7530_vlan_port_attr {
259 MT7530_VLAN_USER = 0,
260 MT7530_VLAN_TRANSPARENT = 3,
261};
262
263enum mt7530_vlan_port_acc_frm {
264 MT7530_VLAN_ACC_ALL = 0,
265 MT7530_VLAN_ACC_TAGGED = 1,
266 MT7530_VLAN_ACC_UNTAGGED = 2,
267};
268
269#define STAG_VPID (((x) & 0xffff) << 16)
270
271/* Register for port port-and-protocol based vlan 1 control */
272#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
273#define G0_PORT_VID(x) (((x) & 0xfff) << 0)
274#define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
275#define G0_PORT_VID_DEF G0_PORT_VID(0)
276
277/* Register for port MAC control register */
278#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
279#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
280#define PMCR_EXT_PHY BIT(17)
281#define PMCR_MAC_MODE BIT(16)
282#define PMCR_FORCE_MODE BIT(15)
283#define PMCR_TX_EN BIT(14)
284#define PMCR_RX_EN BIT(13)
285#define PMCR_BACKOFF_EN BIT(9)
286#define PMCR_BACKPR_EN BIT(8)
287#define PMCR_FORCE_EEE1G BIT(7)
288#define PMCR_FORCE_EEE100 BIT(6)
289#define PMCR_TX_FC_EN BIT(5)
290#define PMCR_RX_FC_EN BIT(4)
291#define PMCR_FORCE_SPEED_1000 BIT(3)
292#define PMCR_FORCE_SPEED_100 BIT(2)
293#define PMCR_FORCE_FDX BIT(1)
294#define PMCR_FORCE_LNK BIT(0)
295#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
296 PMCR_FORCE_SPEED_1000)
297#define MT7531_FORCE_LNK BIT(31)
298#define MT7531_FORCE_SPD BIT(30)
299#define MT7531_FORCE_DPX BIT(29)
300#define MT7531_FORCE_RX_FC BIT(28)
301#define MT7531_FORCE_TX_FC BIT(27)
302#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
303 MT7531_FORCE_SPD | \
304 MT7531_FORCE_DPX | \
305 MT7531_FORCE_RX_FC | \
306 MT7531_FORCE_TX_FC)
307#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
308 MT7531_FORCE_MODE : PMCR_FORCE_MODE)
309#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
310 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
311 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
312 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
313 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
314#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
315 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
316 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
317 PMCR_TX_EN | PMCR_RX_EN | \
318 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
319 PMCR_FORCE_SPEED_1000 | \
320 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
321
322#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
323#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
324#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
325#define LPI_THRESH_MASK GENMASK(15, 4)
326#define LPI_THRESH_SHT 4
327#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
328#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
329#define LPI_MODE_EN BIT(0)
330
331#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
332#define PMSR_EEE1G BIT(7)
333#define PMSR_EEE100M BIT(6)
334#define PMSR_RX_FC BIT(5)
335#define PMSR_TX_FC BIT(4)
336#define PMSR_SPEED_1000 BIT(3)
337#define PMSR_SPEED_100 BIT(2)
338#define PMSR_SPEED_10 0x00
339#define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
340#define PMSR_DPX BIT(1)
341#define PMSR_LINK BIT(0)
342
343/* Register for port debug count */
344#define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
345#define MT7531_DIS_CLR BIT(31)
346
347#define MT7530_GMACCR 0x30e0
348#define MAX_RX_JUMBO(x) ((x) << 2)
349#define MAX_RX_JUMBO_MASK GENMASK(5, 2)
350#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
351#define MAX_RX_PKT_LEN_1522 0x0
352#define MAX_RX_PKT_LEN_1536 0x1
353#define MAX_RX_PKT_LEN_1552 0x2
354#define MAX_RX_PKT_LEN_JUMBO 0x3
355
356/* Register for MIB */
357#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
358#define MT7530_MIB_CCR 0x4fe0
359#define CCR_MIB_ENABLE BIT(31)
360#define CCR_RX_OCT_CNT_GOOD BIT(7)
361#define CCR_RX_OCT_CNT_BAD BIT(6)
362#define CCR_TX_OCT_CNT_GOOD BIT(5)
363#define CCR_TX_OCT_CNT_BAD BIT(4)
364#define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
365 CCR_RX_OCT_CNT_BAD | \
366 CCR_TX_OCT_CNT_GOOD | \
367 CCR_TX_OCT_CNT_BAD)
368#define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
369 CCR_RX_OCT_CNT_GOOD | \
370 CCR_RX_OCT_CNT_BAD | \
371 CCR_TX_OCT_CNT_GOOD | \
372 CCR_TX_OCT_CNT_BAD)
373
374/* MT7531 SGMII register group */
375#define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
376#define MT7531_PHYA_CTRL_SIGNAL3 0x128
377
378/* Register for system reset */
379#define MT7530_SYS_CTRL 0x7000
380#define SYS_CTRL_PHY_RST BIT(2)
381#define SYS_CTRL_SW_RST BIT(1)
382#define SYS_CTRL_REG_RST BIT(0)
383
384/* Register for system interrupt */
385#define MT7530_SYS_INT_EN 0x7008
386
387/* Register for system interrupt status */
388#define MT7530_SYS_INT_STS 0x700c
389
390/* Register for PHY Indirect Access Control */
391#define MT7531_PHY_IAC 0x701C
392#define MT7531_PHY_ACS_ST BIT(31)
393#define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
394#define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
395#define MT7531_MDIO_CMD_MASK (0x3 << 18)
396#define MT7531_MDIO_ST_MASK (0x3 << 16)
397#define MT7531_MDIO_RW_DATA_MASK (0xffff)
398#define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
399#define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
400#define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
401#define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
402#define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
403
404enum mt7531_phy_iac_cmd {
405 MT7531_MDIO_ADDR = 0,
406 MT7531_MDIO_WRITE = 1,
407 MT7531_MDIO_READ = 2,
408 MT7531_MDIO_READ_CL45 = 3,
409};
410
411/* MDIO_ST: MDIO start field */
412enum mt7531_mdio_st {
413 MT7531_MDIO_ST_CL45 = 0,
414 MT7531_MDIO_ST_CL22 = 1,
415};
416
417#define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
418 MT7531_MDIO_CMD(MT7531_MDIO_READ))
419#define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
420 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
421#define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
422 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
423#define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
424 MT7531_MDIO_CMD(MT7531_MDIO_READ))
425#define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
426 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
427
428/* Register for RGMII clock phase */
429#define MT7531_CLKGEN_CTRL 0x7500
430#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
431#define CLK_SKEW_OUT_MASK GENMASK(9, 8)
432#define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
433#define CLK_SKEW_IN_MASK GENMASK(7, 6)
434#define RXCLK_NO_DELAY BIT(5)
435#define TXCLK_NO_REVERSE BIT(4)
436#define GP_MODE(x) (((x) & 0x3) << 1)
437#define GP_MODE_MASK GENMASK(2, 1)
438#define GP_CLK_EN BIT(0)
439
440enum mt7531_gp_mode {
441 MT7531_GP_MODE_RGMII = 0,
442 MT7531_GP_MODE_MII = 1,
443 MT7531_GP_MODE_REV_MII = 2
444};
445
446enum mt7531_clk_skew {
447 MT7531_CLK_SKEW_NO_CHG = 0,
448 MT7531_CLK_SKEW_DLY_100PPS = 1,
449 MT7531_CLK_SKEW_DLY_200PPS = 2,
450 MT7531_CLK_SKEW_REVERSE = 3,
451};
452
453/* Register for hw trap status */
454#define MT7530_HWTRAP 0x7800
455#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
456#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
457#define HWTRAP_XTAL_40MHZ (BIT(10))
458#define HWTRAP_XTAL_20MHZ (BIT(9))
459
460#define MT7531_HWTRAP 0x7800
461#define HWTRAP_XTAL_FSEL_MASK BIT(7)
462#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
463#define HWTRAP_XTAL_FSEL_40MHZ 0
464/* Unique fields of (M)HWSTRAP for MT7531 */
465#define XTAL_FSEL_S 7
466#define XTAL_FSEL_M BIT(7)
467#define PHY_EN BIT(6)
468#define CHG_STRAP BIT(8)
469
470/* Register for hw trap modification */
471#define MT7530_MHWTRAP 0x7804
472#define MHWTRAP_PHY0_SEL BIT(20)
473#define MHWTRAP_MANUAL BIT(16)
474#define MHWTRAP_P5_MAC_SEL BIT(13)
475#define MHWTRAP_P6_DIS BIT(8)
476#define MHWTRAP_P5_RGMII_MODE BIT(7)
477#define MHWTRAP_P5_DIS BIT(6)
478#define MHWTRAP_PHY_ACCESS BIT(5)
479
480/* Register for TOP signal control */
481#define MT7530_TOP_SIG_CTRL 0x7808
482#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
483
484#define MT7531_TOP_SIG_SR 0x780c
485#define PAD_DUAL_SGMII_EN BIT(1)
486#define PAD_MCM_SMI_EN BIT(0)
487
488#define MT7530_IO_DRV_CR 0x7810
489#define P5_IO_CLK_DRV(x) ((x) & 0x3)
490#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
491
492#define MT7531_CHIP_REV 0x781C
493
494#define MT7531_PLLGP_EN 0x7820
495#define EN_COREPLL BIT(2)
496#define SW_CLKSW BIT(1)
497#define SW_PLLGP BIT(0)
498
499#define MT7530_P6ECR 0x7830
500#define P6_INTF_MODE_MASK 0x3
501#define P6_INTF_MODE(x) ((x) & 0x3)
502
503#define MT7531_PLLGP_CR0 0x78a8
504#define RG_COREPLL_EN BIT(22)
505#define RG_COREPLL_POSDIV_S 23
506#define RG_COREPLL_POSDIV_M 0x3800000
507#define RG_COREPLL_SDM_PCW_S 1
508#define RG_COREPLL_SDM_PCW_M 0x3ffffe
509#define RG_COREPLL_SDM_PCW_CHG BIT(0)
510
511/* Registers for RGMII and SGMII PLL clock */
512#define MT7531_ANA_PLLGP_CR2 0x78b0
513#define MT7531_ANA_PLLGP_CR5 0x78bc
514
515/* Registers for TRGMII on the both side */
516#define MT7530_TRGMII_RCK_CTRL 0x7a00
517#define RX_RST BIT(31)
518#define RXC_DQSISEL BIT(30)
519#define DQSI1_TAP_MASK (0x7f << 8)
520#define DQSI0_TAP_MASK 0x7f
521#define DQSI1_TAP(x) (((x) & 0x7f) << 8)
522#define DQSI0_TAP(x) ((x) & 0x7f)
523
524#define MT7530_TRGMII_RCK_RTT 0x7a04
525#define DQS1_GATE BIT(31)
526#define DQS0_GATE BIT(30)
527
528#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
529#define BSLIP_EN BIT(31)
530#define EDGE_CHK BIT(30)
531#define RD_TAP_MASK 0x7f
532#define RD_TAP(x) ((x) & 0x7f)
533
534#define MT7530_TRGMII_TXCTRL 0x7a40
535#define TRAIN_TXEN BIT(31)
536#define TXC_INV BIT(30)
537#define TX_RST BIT(28)
538
539#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
540#define TD_DM_DRVP(x) ((x) & 0xf)
541#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
542
543#define MT7530_TRGMII_TCK_CTRL 0x7a78
544#define TCK_TAP(x) (((x) & 0xf) << 8)
545
546#define MT7530_P5RGMIIRXCR 0x7b00
547#define CSR_RGMII_EDGE_ALIGN BIT(8)
548#define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
549
550#define MT7530_P5RGMIITXCR 0x7b04
551#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
552
553/* Registers for GPIO mode */
554#define MT7531_GPIO_MODE0 0x7c0c
555#define MT7531_GPIO0_MASK GENMASK(3, 0)
556#define MT7531_GPIO0_INTERRUPT 1
557
558#define MT7531_GPIO_MODE1 0x7c10
559#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
560#define MT7531_EXT_P_MDC_11 (2 << 12)
561#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
562#define MT7531_EXT_P_MDIO_12 (2 << 16)
563
564/* Registers for LED GPIO control (MT7530 only)
565 * All registers follow this pattern:
566 * [ 2: 0] port 0
567 * [ 6: 4] port 1
568 * [10: 8] port 2
569 * [14:12] port 3
570 * [18:16] port 4
571 */
572
573/* LED enable, 0: Disable, 1: Enable (Default) */
574#define MT7530_LED_EN 0x7d00
575/* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
576#define MT7530_LED_IO_MODE 0x7d04
577/* GPIO direction, 0: Input, 1: Output */
578#define MT7530_LED_GPIO_DIR 0x7d10
579/* GPIO output enable, 0: Disable, 1: Enable */
580#define MT7530_LED_GPIO_OE 0x7d14
581/* GPIO value, 0: Low, 1: High */
582#define MT7530_LED_GPIO_DATA 0x7d18
583
584#define MT7530_CREV 0x7ffc
585#define CHIP_NAME_SHIFT 16
586#define MT7530_ID 0x7530
587
588#define MT7531_CREV 0x781C
589#define CHIP_REV_M 0x0f
590#define MT7531_ID 0x7531
591
592/* Registers for core PLL access through mmd indirect */
593#define CORE_PLL_GROUP2 0x401
594#define RG_SYSPLL_EN_NORMAL BIT(15)
595#define RG_SYSPLL_VODEN BIT(14)
596#define RG_SYSPLL_LF BIT(13)
597#define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
598#define RG_SYSPLL_LVROD_EN BIT(10)
599#define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
600#define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
601#define RG_SYSPLL_FBKSEL BIT(4)
602#define RT_SYSPLL_EN_AFE_OLT BIT(0)
603
604#define CORE_PLL_GROUP4 0x403
605#define RG_SYSPLL_DDSFBK_EN BIT(12)
606#define RG_SYSPLL_BIAS_EN BIT(11)
607#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
608#define MT7531_PHY_PLL_OFF BIT(5)
609#define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
610
611#define MT753X_CTRL_PHY_ADDR 0
612
613#define CORE_PLL_GROUP5 0x404
614#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
615
616#define CORE_PLL_GROUP6 0x405
617#define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
618
619#define CORE_PLL_GROUP7 0x406
620#define RG_LCDDS_PWDB BIT(15)
621#define RG_LCDDS_ISO_EN BIT(13)
622#define RG_LCCDS_C(x) (((x) & 0x7) << 4)
623#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
624
625#define CORE_PLL_GROUP10 0x409
626#define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
627
628#define CORE_PLL_GROUP11 0x40a
629#define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
630
631#define CORE_GSWPLL_GRP1 0x40d
632#define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
633#define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
634#define RG_GSWPLL_EN_PRE BIT(11)
635#define RG_GSWPLL_FBKSEL BIT(10)
636#define RG_GSWPLL_BP BIT(9)
637#define RG_GSWPLL_BR BIT(8)
638#define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
639
640#define CORE_GSWPLL_GRP2 0x40e
641#define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
642#define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
643
644#define CORE_TRGMII_GSW_CLK_CG 0x410
645#define REG_GSWCK_EN BIT(0)
646#define REG_TRGMIICK_EN BIT(1)
647
648#define MIB_DESC(_s, _o, _n) \
649 { \
650 .size = (_s), \
651 .offset = (_o), \
652 .name = (_n), \
653 }
654
655struct mt7530_mib_desc {
656 unsigned int size;
657 unsigned int offset;
658 const char *name;
659};
660
661struct mt7530_fdb {
662 u16 vid;
663 u8 port_mask;
664 u8 aging;
665 u8 mac[6];
666 bool noarp;
667};
668
669/* struct mt7530_port - This is the main data structure for holding the state
670 * of the port.
671 * @enable: The status used for show port is enabled or not.
672 * @pm: The matrix used to show all connections with the port.
673 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
674 * untagged frames will be assigned to the related VLAN.
675 * @sgmii_pcs: Pointer to PCS instance for SerDes ports
676 */
677struct mt7530_port {
678 bool enable;
679 u32 pm;
680 u16 pvid;
681 struct phylink_pcs *sgmii_pcs;
682};
683
684/* Port 5 interface select definitions */
685enum p5_interface_select {
686 P5_DISABLED = 0,
687 P5_INTF_SEL_PHY_P0,
688 P5_INTF_SEL_PHY_P4,
689 P5_INTF_SEL_GMAC5,
690 P5_INTF_SEL_GMAC5_SGMII,
691};
692
693struct mt7530_priv;
694
695struct mt753x_pcs {
696 struct phylink_pcs pcs;
697 struct mt7530_priv *priv;
698 int port;
699};
700
701/* struct mt753x_info - This is the main data structure for holding the specific
702 * part for each supported device
703 * @sw_setup: Holding the handler to a device initialization
704 * @phy_read_c22: Holding the way reading PHY port using C22
705 * @phy_write_c22: Holding the way writing PHY port using C22
706 * @phy_read_c45: Holding the way reading PHY port using C45
707 * @phy_write_c45: Holding the way writing PHY port using C45
708 * @pad_setup: Holding the way setting up the bus pad for a certain
709 * MAC port
710 * @phy_mode_supported: Check if the PHY type is being supported on a certain
711 * port
712 * @mac_port_validate: Holding the way to set addition validate type for a
713 * certan MAC port
714 * @mac_port_config: Holding the way setting up the PHY attribute to a
715 * certain MAC port
716 */
717struct mt753x_info {
718 enum mt753x_id id;
719
720 const struct phylink_pcs_ops *pcs_ops;
721
722 int (*sw_setup)(struct dsa_switch *ds);
723 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum);
724 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum,
725 u16 val);
726 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad,
727 int regnum);
728 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
729 int regnum, u16 val);
730 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
731 int (*cpu_port_config)(struct dsa_switch *ds, int port);
732 void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
733 struct phylink_config *config);
734 void (*mac_port_validate)(struct dsa_switch *ds, int port,
735 phy_interface_t interface,
736 unsigned long *supported);
737 int (*mac_port_config)(struct dsa_switch *ds, int port,
738 unsigned int mode,
739 phy_interface_t interface);
740};
741
742/* struct mt7530_priv - This is the main data structure for holding the state
743 * of the driver
744 * @dev: The device pointer
745 * @ds: The pointer to the dsa core structure
746 * @bus: The bus used for the device and built-in PHY
747 * @regmap: The regmap instance representing all switch registers
748 * @rstc: The pointer to reset control used by MCM
749 * @core_pwr: The power supplied into the core
750 * @io_pwr: The power supplied into the I/O
751 * @reset: The descriptor for GPIO line tied to its reset pin
752 * @mcm: Flag for distinguishing if standalone IC or module
753 * coupling
754 * @ports: Holding the state among ports
755 * @reg_mutex: The lock for protecting among process accessing
756 * registers
757 * @p6_interface Holding the current port 6 interface
758 * @p5_intf_sel: Holding the current port 5 interface select
759 * @irq: IRQ number of the switch
760 * @irq_domain: IRQ domain of the switch irq_chip
761 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
762 * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
763 */
764struct mt7530_priv {
765 struct device *dev;
766 struct dsa_switch *ds;
767 struct mii_bus *bus;
768 struct regmap *regmap;
769 struct reset_control *rstc;
770 struct regulator *core_pwr;
771 struct regulator *io_pwr;
772 struct gpio_desc *reset;
773 const struct mt753x_info *info;
774 unsigned int id;
775 bool mcm;
776 phy_interface_t p6_interface;
777 phy_interface_t p5_interface;
778 unsigned int p5_intf_sel;
779 u8 mirror_rx;
780 u8 mirror_tx;
781 struct mt7530_port ports[MT7530_NUM_PORTS];
782 struct mt753x_pcs pcs[MT7530_NUM_PORTS];
783 /* protect among processes for registers access*/
784 struct mutex reg_mutex;
785 int irq;
786 struct irq_domain *irq_domain;
787 u32 irq_enable;
788 int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
789};
790
791struct mt7530_hw_vlan_entry {
792 int port;
793 u8 old_members;
794 bool untagged;
795};
796
797static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
798 int port, bool untagged)
799{
800 e->port = port;
801 e->untagged = untagged;
802}
803
804typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
805 struct mt7530_hw_vlan_entry *);
806
807struct mt7530_hw_stats {
808 const char *string;
809 u16 reg;
810 u8 sizeof_stat;
811};
812
813struct mt7530_dummy_poll {
814 struct mt7530_priv *priv;
815 u32 reg;
816};
817
818static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
819 struct mt7530_priv *priv, u32 reg)
820{
821 p->priv = priv;
822 p->reg = reg;
823}
824
825int mt7530_probe_common(struct mt7530_priv *priv);
826void mt7530_remove_common(struct mt7530_priv *priv);
827
828extern const struct dsa_switch_ops mt7530_switch_ops;
829extern const struct mt753x_info mt753x_table[];
830
831#endif /* __MT7530_H */