Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Flora Fu, MediaTek
5 */
6
7#include <linux/interrupt.h>
8#include <linux/ioport.h>
9#include <linux/irqdomain.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14#include <linux/mfd/core.h>
15#include <linux/mfd/mt6323/core.h>
16#include <linux/mfd/mt6331/core.h>
17#include <linux/mfd/mt6357/core.h>
18#include <linux/mfd/mt6358/core.h>
19#include <linux/mfd/mt6359/core.h>
20#include <linux/mfd/mt6397/core.h>
21#include <linux/mfd/mt6323/registers.h>
22#include <linux/mfd/mt6331/registers.h>
23#include <linux/mfd/mt6357/registers.h>
24#include <linux/mfd/mt6358/registers.h>
25#include <linux/mfd/mt6359/registers.h>
26#include <linux/mfd/mt6397/registers.h>
27
28#define MT6323_RTC_BASE 0x8000
29#define MT6323_RTC_SIZE 0x40
30
31#define MT6357_RTC_BASE 0x0588
32#define MT6357_RTC_SIZE 0x3c
33
34#define MT6331_RTC_BASE 0x4000
35#define MT6331_RTC_SIZE 0x40
36
37#define MT6358_RTC_BASE 0x0588
38#define MT6358_RTC_SIZE 0x3c
39
40#define MT6397_RTC_BASE 0xe000
41#define MT6397_RTC_SIZE 0x3e
42
43#define MT6323_PWRC_BASE 0x8000
44#define MT6323_PWRC_SIZE 0x40
45
46static const struct resource mt6323_rtc_resources[] = {
47 DEFINE_RES_MEM(MT6323_RTC_BASE, MT6323_RTC_SIZE),
48 DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),
49};
50
51static const struct resource mt6357_rtc_resources[] = {
52 DEFINE_RES_MEM(MT6357_RTC_BASE, MT6357_RTC_SIZE),
53 DEFINE_RES_IRQ(MT6357_IRQ_RTC),
54};
55
56static const struct resource mt6331_rtc_resources[] = {
57 DEFINE_RES_MEM(MT6331_RTC_BASE, MT6331_RTC_SIZE),
58 DEFINE_RES_IRQ(MT6331_IRQ_STATUS_RTC),
59};
60
61static const struct resource mt6358_rtc_resources[] = {
62 DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE),
63 DEFINE_RES_IRQ(MT6358_IRQ_RTC),
64};
65
66static const struct resource mt6397_rtc_resources[] = {
67 DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),
68 DEFINE_RES_IRQ(MT6397_IRQ_RTC),
69};
70
71static const struct resource mt6358_keys_resources[] = {
72 DEFINE_RES_IRQ_NAMED(MT6358_IRQ_PWRKEY, "powerkey"),
73 DEFINE_RES_IRQ_NAMED(MT6358_IRQ_HOMEKEY, "homekey"),
74 DEFINE_RES_IRQ_NAMED(MT6358_IRQ_PWRKEY_R, "powerkey_r"),
75 DEFINE_RES_IRQ_NAMED(MT6358_IRQ_HOMEKEY_R, "homekey_r"),
76};
77
78static const struct resource mt6359_keys_resources[] = {
79 DEFINE_RES_IRQ_NAMED(MT6359_IRQ_PWRKEY, "powerkey"),
80 DEFINE_RES_IRQ_NAMED(MT6359_IRQ_HOMEKEY, "homekey"),
81 DEFINE_RES_IRQ_NAMED(MT6359_IRQ_PWRKEY_R, "powerkey_r"),
82 DEFINE_RES_IRQ_NAMED(MT6359_IRQ_HOMEKEY_R, "homekey_r"),
83};
84
85static const struct resource mt6323_keys_resources[] = {
86 DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_PWRKEY, "powerkey"),
87 DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_FCHRKEY, "homekey"),
88};
89
90static const struct resource mt6357_keys_resources[] = {
91 DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY, "powerkey"),
92 DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY, "homekey"),
93 DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY_R, "powerkey_r"),
94 DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY_R, "homekey_r"),
95};
96
97static const struct resource mt6331_keys_resources[] = {
98 DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_PWRKEY, "powerkey"),
99 DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_HOMEKEY, "homekey"),
100};
101
102static const struct resource mt6397_keys_resources[] = {
103 DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"),
104 DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"),
105};
106
107static const struct resource mt6323_pwrc_resources[] = {
108 DEFINE_RES_MEM(MT6323_PWRC_BASE, MT6323_PWRC_SIZE),
109};
110
111static const struct mfd_cell mt6323_devs[] = {
112 {
113 .name = "mt6323-rtc",
114 .num_resources = ARRAY_SIZE(mt6323_rtc_resources),
115 .resources = mt6323_rtc_resources,
116 .of_compatible = "mediatek,mt6323-rtc",
117 }, {
118 .name = "mt6323-regulator",
119 .of_compatible = "mediatek,mt6323-regulator"
120 }, {
121 .name = "mt6323-led",
122 .of_compatible = "mediatek,mt6323-led"
123 }, {
124 .name = "mtk-pmic-keys",
125 .num_resources = ARRAY_SIZE(mt6323_keys_resources),
126 .resources = mt6323_keys_resources,
127 .of_compatible = "mediatek,mt6323-keys"
128 }, {
129 .name = "mt6323-pwrc",
130 .num_resources = ARRAY_SIZE(mt6323_pwrc_resources),
131 .resources = mt6323_pwrc_resources,
132 .of_compatible = "mediatek,mt6323-pwrc"
133 },
134};
135
136static const struct mfd_cell mt6357_devs[] = {
137 {
138 .name = "mt6357-regulator",
139 }, {
140 .name = "mt6357-rtc",
141 .num_resources = ARRAY_SIZE(mt6357_rtc_resources),
142 .resources = mt6357_rtc_resources,
143 .of_compatible = "mediatek,mt6357-rtc",
144 }, {
145 .name = "mtk-pmic-keys",
146 .num_resources = ARRAY_SIZE(mt6357_keys_resources),
147 .resources = mt6357_keys_resources,
148 .of_compatible = "mediatek,mt6357-keys"
149 },
150};
151
152/* MT6331 is always used in combination with MT6332 */
153static const struct mfd_cell mt6331_mt6332_devs[] = {
154 {
155 .name = "mt6331-rtc",
156 .num_resources = ARRAY_SIZE(mt6331_rtc_resources),
157 .resources = mt6331_rtc_resources,
158 .of_compatible = "mediatek,mt6331-rtc",
159 }, {
160 .name = "mt6331-regulator",
161 .of_compatible = "mediatek,mt6331-regulator"
162 }, {
163 .name = "mt6332-regulator",
164 .of_compatible = "mediatek,mt6332-regulator"
165 }, {
166 .name = "mtk-pmic-keys",
167 .num_resources = ARRAY_SIZE(mt6331_keys_resources),
168 .resources = mt6331_keys_resources,
169 .of_compatible = "mediatek,mt6331-keys"
170 },
171};
172
173static const struct mfd_cell mt6358_devs[] = {
174 {
175 .name = "mt6358-regulator",
176 .of_compatible = "mediatek,mt6358-regulator"
177 }, {
178 .name = "mt6358-rtc",
179 .num_resources = ARRAY_SIZE(mt6358_rtc_resources),
180 .resources = mt6358_rtc_resources,
181 .of_compatible = "mediatek,mt6358-rtc",
182 }, {
183 .name = "mt6358-sound",
184 .of_compatible = "mediatek,mt6358-sound"
185 }, {
186 .name = "mt6358-keys",
187 .num_resources = ARRAY_SIZE(mt6358_keys_resources),
188 .resources = mt6358_keys_resources,
189 .of_compatible = "mediatek,mt6358-keys"
190 },
191};
192
193static const struct mfd_cell mt6359_devs[] = {
194 { .name = "mt6359-regulator", },
195 {
196 .name = "mt6359-rtc",
197 .num_resources = ARRAY_SIZE(mt6358_rtc_resources),
198 .resources = mt6358_rtc_resources,
199 .of_compatible = "mediatek,mt6358-rtc",
200 },
201 { .name = "mt6359-sound", },
202 {
203 .name = "mtk-pmic-keys",
204 .num_resources = ARRAY_SIZE(mt6359_keys_resources),
205 .resources = mt6359_keys_resources,
206 .of_compatible = "mediatek,mt6359-keys"
207 },
208};
209
210static const struct mfd_cell mt6397_devs[] = {
211 {
212 .name = "mt6397-rtc",
213 .num_resources = ARRAY_SIZE(mt6397_rtc_resources),
214 .resources = mt6397_rtc_resources,
215 .of_compatible = "mediatek,mt6397-rtc",
216 }, {
217 .name = "mt6397-regulator",
218 .of_compatible = "mediatek,mt6397-regulator",
219 }, {
220 .name = "mt6397-codec",
221 .of_compatible = "mediatek,mt6397-codec",
222 }, {
223 .name = "mt6397-clk",
224 .of_compatible = "mediatek,mt6397-clk",
225 }, {
226 .name = "mt6397-pinctrl",
227 .of_compatible = "mediatek,mt6397-pinctrl",
228 }, {
229 .name = "mtk-pmic-keys",
230 .num_resources = ARRAY_SIZE(mt6397_keys_resources),
231 .resources = mt6397_keys_resources,
232 .of_compatible = "mediatek,mt6397-keys"
233 }
234};
235
236struct chip_data {
237 u32 cid_addr;
238 u32 cid_shift;
239 const struct mfd_cell *cells;
240 int cell_size;
241 int (*irq_init)(struct mt6397_chip *chip);
242};
243
244static const struct chip_data mt6323_core = {
245 .cid_addr = MT6323_CID,
246 .cid_shift = 0,
247 .cells = mt6323_devs,
248 .cell_size = ARRAY_SIZE(mt6323_devs),
249 .irq_init = mt6397_irq_init,
250};
251
252static const struct chip_data mt6357_core = {
253 .cid_addr = MT6357_SWCID,
254 .cid_shift = 8,
255 .cells = mt6357_devs,
256 .cell_size = ARRAY_SIZE(mt6357_devs),
257 .irq_init = mt6358_irq_init,
258};
259
260static const struct chip_data mt6331_mt6332_core = {
261 .cid_addr = MT6331_HWCID,
262 .cid_shift = 0,
263 .cells = mt6331_mt6332_devs,
264 .cell_size = ARRAY_SIZE(mt6331_mt6332_devs),
265 .irq_init = mt6397_irq_init,
266};
267
268static const struct chip_data mt6358_core = {
269 .cid_addr = MT6358_SWCID,
270 .cid_shift = 8,
271 .cells = mt6358_devs,
272 .cell_size = ARRAY_SIZE(mt6358_devs),
273 .irq_init = mt6358_irq_init,
274};
275
276static const struct chip_data mt6359_core = {
277 .cid_addr = MT6359_SWCID,
278 .cid_shift = 8,
279 .cells = mt6359_devs,
280 .cell_size = ARRAY_SIZE(mt6359_devs),
281 .irq_init = mt6358_irq_init,
282};
283
284static const struct chip_data mt6397_core = {
285 .cid_addr = MT6397_CID,
286 .cid_shift = 0,
287 .cells = mt6397_devs,
288 .cell_size = ARRAY_SIZE(mt6397_devs),
289 .irq_init = mt6397_irq_init,
290};
291
292static int mt6397_probe(struct platform_device *pdev)
293{
294 int ret;
295 unsigned int id = 0;
296 struct mt6397_chip *pmic;
297 const struct chip_data *pmic_core;
298
299 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
300 if (!pmic)
301 return -ENOMEM;
302
303 pmic->dev = &pdev->dev;
304
305 /*
306 * mt6397 MFD is child device of soc pmic wrapper.
307 * Regmap is set from its parent.
308 */
309 pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
310 if (!pmic->regmap)
311 return -ENODEV;
312
313 pmic_core = of_device_get_match_data(&pdev->dev);
314 if (!pmic_core)
315 return -ENODEV;
316
317 ret = regmap_read(pmic->regmap, pmic_core->cid_addr, &id);
318 if (ret) {
319 dev_err(&pdev->dev, "Failed to read chip id: %d\n", ret);
320 return ret;
321 }
322
323 pmic->chip_id = (id >> pmic_core->cid_shift) & 0xff;
324
325 platform_set_drvdata(pdev, pmic);
326
327 pmic->irq = platform_get_irq(pdev, 0);
328 if (pmic->irq <= 0)
329 return pmic->irq;
330
331 ret = pmic_core->irq_init(pmic);
332 if (ret)
333 return ret;
334
335 ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
336 pmic_core->cells, pmic_core->cell_size,
337 NULL, 0, pmic->irq_domain);
338 if (ret) {
339 irq_domain_remove(pmic->irq_domain);
340 dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
341 }
342
343 return ret;
344}
345
346static const struct of_device_id mt6397_of_match[] = {
347 {
348 .compatible = "mediatek,mt6323",
349 .data = &mt6323_core,
350 }, {
351 .compatible = "mediatek,mt6331",
352 .data = &mt6331_mt6332_core,
353 }, {
354 .compatible = "mediatek,mt6357",
355 .data = &mt6357_core,
356 }, {
357 .compatible = "mediatek,mt6358",
358 .data = &mt6358_core,
359 }, {
360 .compatible = "mediatek,mt6359",
361 .data = &mt6359_core,
362 }, {
363 .compatible = "mediatek,mt6397",
364 .data = &mt6397_core,
365 }, {
366 /* sentinel */
367 }
368};
369MODULE_DEVICE_TABLE(of, mt6397_of_match);
370
371static const struct platform_device_id mt6397_id[] = {
372 { "mt6397", 0 },
373 { },
374};
375MODULE_DEVICE_TABLE(platform, mt6397_id);
376
377static struct platform_driver mt6397_driver = {
378 .probe = mt6397_probe,
379 .driver = {
380 .name = "mt6397",
381 .of_match_table = mt6397_of_match,
382 },
383 .id_table = mt6397_id,
384};
385
386module_platform_driver(mt6397_driver);
387
388MODULE_AUTHOR("Flora Fu, MediaTek");
389MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
390MODULE_LICENSE("GPL");
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/of_irq.h>
19#include <linux/regmap.h>
20#include <linux/mfd/core.h>
21#include <linux/mfd/mt6397/core.h>
22#include <linux/mfd/mt6323/core.h>
23#include <linux/mfd/mt6397/registers.h>
24#include <linux/mfd/mt6323/registers.h>
25
26#define MT6397_RTC_BASE 0xe000
27#define MT6397_RTC_SIZE 0x3e
28
29#define MT6323_CID_CODE 0x23
30#define MT6391_CID_CODE 0x91
31#define MT6397_CID_CODE 0x97
32
33static const struct resource mt6397_rtc_resources[] = {
34 {
35 .start = MT6397_RTC_BASE,
36 .end = MT6397_RTC_BASE + MT6397_RTC_SIZE,
37 .flags = IORESOURCE_MEM,
38 },
39 {
40 .start = MT6397_IRQ_RTC,
41 .end = MT6397_IRQ_RTC,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static const struct mfd_cell mt6323_devs[] = {
47 {
48 .name = "mt6323-regulator",
49 .of_compatible = "mediatek,mt6323-regulator"
50 },
51};
52
53static const struct mfd_cell mt6397_devs[] = {
54 {
55 .name = "mt6397-rtc",
56 .num_resources = ARRAY_SIZE(mt6397_rtc_resources),
57 .resources = mt6397_rtc_resources,
58 .of_compatible = "mediatek,mt6397-rtc",
59 }, {
60 .name = "mt6397-regulator",
61 .of_compatible = "mediatek,mt6397-regulator",
62 }, {
63 .name = "mt6397-codec",
64 .of_compatible = "mediatek,mt6397-codec",
65 }, {
66 .name = "mt6397-clk",
67 .of_compatible = "mediatek,mt6397-clk",
68 }, {
69 .name = "mt6397-pinctrl",
70 .of_compatible = "mediatek,mt6397-pinctrl",
71 },
72};
73
74static void mt6397_irq_lock(struct irq_data *data)
75{
76 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
77
78 mutex_lock(&mt6397->irqlock);
79}
80
81static void mt6397_irq_sync_unlock(struct irq_data *data)
82{
83 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
84
85 regmap_write(mt6397->regmap, mt6397->int_con[0],
86 mt6397->irq_masks_cur[0]);
87 regmap_write(mt6397->regmap, mt6397->int_con[1],
88 mt6397->irq_masks_cur[1]);
89
90 mutex_unlock(&mt6397->irqlock);
91}
92
93static void mt6397_irq_disable(struct irq_data *data)
94{
95 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
96 int shift = data->hwirq & 0xf;
97 int reg = data->hwirq >> 4;
98
99 mt6397->irq_masks_cur[reg] &= ~BIT(shift);
100}
101
102static void mt6397_irq_enable(struct irq_data *data)
103{
104 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
105 int shift = data->hwirq & 0xf;
106 int reg = data->hwirq >> 4;
107
108 mt6397->irq_masks_cur[reg] |= BIT(shift);
109}
110
111#ifdef CONFIG_PM_SLEEP
112static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
113{
114 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
115 int shift = irq_data->hwirq & 0xf;
116 int reg = irq_data->hwirq >> 4;
117
118 if (on)
119 mt6397->wake_mask[reg] |= BIT(shift);
120 else
121 mt6397->wake_mask[reg] &= ~BIT(shift);
122
123 return 0;
124}
125#else
126#define mt6397_irq_set_wake NULL
127#endif
128
129static struct irq_chip mt6397_irq_chip = {
130 .name = "mt6397-irq",
131 .irq_bus_lock = mt6397_irq_lock,
132 .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
133 .irq_enable = mt6397_irq_enable,
134 .irq_disable = mt6397_irq_disable,
135 .irq_set_wake = mt6397_irq_set_wake,
136};
137
138static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
139 int irqbase)
140{
141 unsigned int status;
142 int i, irq, ret;
143
144 ret = regmap_read(mt6397->regmap, reg, &status);
145 if (ret) {
146 dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
147 return;
148 }
149
150 for (i = 0; i < 16; i++) {
151 if (status & BIT(i)) {
152 irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
153 if (irq)
154 handle_nested_irq(irq);
155 }
156 }
157
158 regmap_write(mt6397->regmap, reg, status);
159}
160
161static irqreturn_t mt6397_irq_thread(int irq, void *data)
162{
163 struct mt6397_chip *mt6397 = data;
164
165 mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
166 mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
167
168 return IRQ_HANDLED;
169}
170
171static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
172 irq_hw_number_t hw)
173{
174 struct mt6397_chip *mt6397 = d->host_data;
175
176 irq_set_chip_data(irq, mt6397);
177 irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
178 irq_set_nested_thread(irq, 1);
179 irq_set_noprobe(irq);
180
181 return 0;
182}
183
184static const struct irq_domain_ops mt6397_irq_domain_ops = {
185 .map = mt6397_irq_domain_map,
186};
187
188static int mt6397_irq_init(struct mt6397_chip *mt6397)
189{
190 int ret;
191
192 mutex_init(&mt6397->irqlock);
193
194 /* Mask all interrupt sources */
195 regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
196 regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
197
198 mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
199 MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
200 if (!mt6397->irq_domain) {
201 dev_err(mt6397->dev, "could not create irq domain\n");
202 return -ENOMEM;
203 }
204
205 ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
206 mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
207 if (ret) {
208 dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
209 mt6397->irq, ret);
210 return ret;
211 }
212
213 return 0;
214}
215
216#ifdef CONFIG_PM_SLEEP
217static int mt6397_irq_suspend(struct device *dev)
218{
219 struct mt6397_chip *chip = dev_get_drvdata(dev);
220
221 regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
222 regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
223
224 enable_irq_wake(chip->irq);
225
226 return 0;
227}
228
229static int mt6397_irq_resume(struct device *dev)
230{
231 struct mt6397_chip *chip = dev_get_drvdata(dev);
232
233 regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
234 regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
235
236 disable_irq_wake(chip->irq);
237
238 return 0;
239}
240#endif
241
242static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
243 mt6397_irq_resume);
244
245static int mt6397_probe(struct platform_device *pdev)
246{
247 int ret;
248 unsigned int id;
249 struct mt6397_chip *pmic;
250
251 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
252 if (!pmic)
253 return -ENOMEM;
254
255 pmic->dev = &pdev->dev;
256
257 /*
258 * mt6397 MFD is child device of soc pmic wrapper.
259 * Regmap is set from its parent.
260 */
261 pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
262 if (!pmic->regmap)
263 return -ENODEV;
264
265 platform_set_drvdata(pdev, pmic);
266
267 ret = regmap_read(pmic->regmap, MT6397_CID, &id);
268 if (ret) {
269 dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
270 goto fail_irq;
271 }
272
273 switch (id & 0xff) {
274 case MT6323_CID_CODE:
275 pmic->int_con[0] = MT6323_INT_CON0;
276 pmic->int_con[1] = MT6323_INT_CON1;
277 pmic->int_status[0] = MT6323_INT_STATUS0;
278 pmic->int_status[1] = MT6323_INT_STATUS1;
279 ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
280 ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
281 break;
282
283 case MT6397_CID_CODE:
284 case MT6391_CID_CODE:
285 pmic->int_con[0] = MT6397_INT_CON0;
286 pmic->int_con[1] = MT6397_INT_CON1;
287 pmic->int_status[0] = MT6397_INT_STATUS0;
288 pmic->int_status[1] = MT6397_INT_STATUS1;
289 ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
290 ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
291 break;
292
293 default:
294 dev_err(&pdev->dev, "unsupported chip: %d\n", id);
295 ret = -ENODEV;
296 break;
297 }
298
299 pmic->irq = platform_get_irq(pdev, 0);
300 if (pmic->irq > 0) {
301 ret = mt6397_irq_init(pmic);
302 if (ret)
303 return ret;
304 }
305
306fail_irq:
307 if (ret) {
308 irq_domain_remove(pmic->irq_domain);
309 dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
310 }
311
312 return ret;
313}
314
315static int mt6397_remove(struct platform_device *pdev)
316{
317 mfd_remove_devices(&pdev->dev);
318
319 return 0;
320}
321
322static const struct of_device_id mt6397_of_match[] = {
323 { .compatible = "mediatek,mt6397" },
324 { .compatible = "mediatek,mt6323" },
325 { }
326};
327MODULE_DEVICE_TABLE(of, mt6397_of_match);
328
329static const struct platform_device_id mt6397_id[] = {
330 { "mt6397", 0 },
331 { },
332};
333MODULE_DEVICE_TABLE(platform, mt6397_id);
334
335static struct platform_driver mt6397_driver = {
336 .probe = mt6397_probe,
337 .remove = mt6397_remove,
338 .driver = {
339 .name = "mt6397",
340 .of_match_table = of_match_ptr(mt6397_of_match),
341 .pm = &mt6397_pm_ops,
342 },
343 .id_table = mt6397_id,
344};
345
346module_platform_driver(mt6397_driver);
347
348MODULE_AUTHOR("Flora Fu, MediaTek");
349MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
350MODULE_LICENSE("GPL");