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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * IOMMU API for Renesas VMSA-compatible IPMMU
4 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 *
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
7 */
8
9#include <linux/bitmap.h>
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/err.h>
13#include <linux/export.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/iopoll.h>
18#include <linux/io-pgtable.h>
19#include <linux/iommu.h>
20#include <linux/of.h>
21#include <linux/of_platform.h>
22#include <linux/pci.h>
23#include <linux/platform_device.h>
24#include <linux/sizes.h>
25#include <linux/slab.h>
26#include <linux/sys_soc.h>
27
28#if defined(CONFIG_ARM) && !defined(CONFIG_IOMMU_DMA)
29#include <asm/dma-iommu.h>
30#else
31#define arm_iommu_create_mapping(...) NULL
32#define arm_iommu_attach_device(...) -ENODEV
33#define arm_iommu_release_mapping(...) do {} while (0)
34#endif
35
36#define IPMMU_CTX_MAX 16U
37#define IPMMU_CTX_INVALID -1
38
39#define IPMMU_UTLB_MAX 64U
40
41struct ipmmu_features {
42 bool use_ns_alias_offset;
43 bool has_cache_leaf_nodes;
44 unsigned int number_of_contexts;
45 unsigned int num_utlbs;
46 bool setup_imbuscr;
47 bool twobit_imttbcr_sl0;
48 bool reserved_context;
49 bool cache_snoop;
50 unsigned int ctx_offset_base;
51 unsigned int ctx_offset_stride;
52 unsigned int utlb_offset_base;
53};
54
55struct ipmmu_vmsa_device {
56 struct device *dev;
57 void __iomem *base;
58 struct iommu_device iommu;
59 struct ipmmu_vmsa_device *root;
60 const struct ipmmu_features *features;
61 unsigned int num_ctx;
62 spinlock_t lock; /* Protects ctx and domains[] */
63 DECLARE_BITMAP(ctx, IPMMU_CTX_MAX);
64 struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
65 s8 utlb_ctx[IPMMU_UTLB_MAX];
66
67 struct dma_iommu_mapping *mapping;
68};
69
70struct ipmmu_vmsa_domain {
71 struct ipmmu_vmsa_device *mmu;
72 struct iommu_domain io_domain;
73
74 struct io_pgtable_cfg cfg;
75 struct io_pgtable_ops *iop;
76
77 unsigned int context_id;
78 struct mutex mutex; /* Protects mappings */
79};
80
81static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
82{
83 return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
84}
85
86static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
87{
88 return dev_iommu_priv_get(dev);
89}
90
91#define TLB_LOOP_TIMEOUT 100 /* 100us */
92
93/* -----------------------------------------------------------------------------
94 * Registers Definition
95 */
96
97#define IM_NS_ALIAS_OFFSET 0x800
98
99/* MMU "context" registers */
100#define IMCTR 0x0000 /* R-Car Gen2/3 */
101#define IMCTR_INTEN (1 << 2) /* R-Car Gen2/3 */
102#define IMCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
103#define IMCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
104
105#define IMTTBCR 0x0008 /* R-Car Gen2/3 */
106#define IMTTBCR_EAE (1 << 31) /* R-Car Gen2/3 */
107#define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12) /* R-Car Gen2 only */
108#define IMTTBCR_ORGN0_WB_WA (1 << 10) /* R-Car Gen2 only */
109#define IMTTBCR_IRGN0_WB_WA (1 << 8) /* R-Car Gen2 only */
110#define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6) /* R-Car Gen3 only */
111#define IMTTBCR_SL0_LVL_1 (1 << 4) /* R-Car Gen2 only */
112
113#define IMBUSCR 0x000c /* R-Car Gen2 only */
114#define IMBUSCR_DVM (1 << 2) /* R-Car Gen2 only */
115#define IMBUSCR_BUSSEL_MASK (3 << 0) /* R-Car Gen2 only */
116
117#define IMTTLBR0 0x0010 /* R-Car Gen2/3 */
118#define IMTTUBR0 0x0014 /* R-Car Gen2/3 */
119
120#define IMSTR 0x0020 /* R-Car Gen2/3 */
121#define IMSTR_MHIT (1 << 4) /* R-Car Gen2/3 */
122#define IMSTR_ABORT (1 << 2) /* R-Car Gen2/3 */
123#define IMSTR_PF (1 << 1) /* R-Car Gen2/3 */
124#define IMSTR_TF (1 << 0) /* R-Car Gen2/3 */
125
126#define IMMAIR0 0x0028 /* R-Car Gen2/3 */
127
128#define IMELAR 0x0030 /* R-Car Gen2/3, IMEAR on R-Car Gen2 */
129#define IMEUAR 0x0034 /* R-Car Gen3 only */
130
131/* uTLB registers */
132#define IMUCTR(n) ((n) < 32 ? IMUCTR0(n) : IMUCTR32(n))
133#define IMUCTR0(n) (0x0300 + ((n) * 16)) /* R-Car Gen2/3 */
134#define IMUCTR32(n) (0x0600 + (((n) - 32) * 16)) /* R-Car Gen3 only */
135#define IMUCTR_TTSEL_MMU(n) ((n) << 4) /* R-Car Gen2/3 */
136#define IMUCTR_FLUSH (1 << 1) /* R-Car Gen2/3 */
137#define IMUCTR_MMUEN (1 << 0) /* R-Car Gen2/3 */
138
139#define IMUASID(n) ((n) < 32 ? IMUASID0(n) : IMUASID32(n))
140#define IMUASID0(n) (0x0308 + ((n) * 16)) /* R-Car Gen2/3 */
141#define IMUASID32(n) (0x0608 + (((n) - 32) * 16)) /* R-Car Gen3 only */
142
143/* -----------------------------------------------------------------------------
144 * Root device handling
145 */
146
147static struct platform_driver ipmmu_driver;
148
149static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu)
150{
151 return mmu->root == mmu;
152}
153
154static int __ipmmu_check_device(struct device *dev, void *data)
155{
156 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
157 struct ipmmu_vmsa_device **rootp = data;
158
159 if (ipmmu_is_root(mmu))
160 *rootp = mmu;
161
162 return 0;
163}
164
165static struct ipmmu_vmsa_device *ipmmu_find_root(void)
166{
167 struct ipmmu_vmsa_device *root = NULL;
168
169 return driver_for_each_device(&ipmmu_driver.driver, NULL, &root,
170 __ipmmu_check_device) == 0 ? root : NULL;
171}
172
173/* -----------------------------------------------------------------------------
174 * Read/Write Access
175 */
176
177static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
178{
179 return ioread32(mmu->base + offset);
180}
181
182static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
183 u32 data)
184{
185 iowrite32(data, mmu->base + offset);
186}
187
188static unsigned int ipmmu_ctx_reg(struct ipmmu_vmsa_device *mmu,
189 unsigned int context_id, unsigned int reg)
190{
191 unsigned int base = mmu->features->ctx_offset_base;
192
193 if (context_id > 7)
194 base += 0x800 - 8 * 0x40;
195
196 return base + context_id * mmu->features->ctx_offset_stride + reg;
197}
198
199static u32 ipmmu_ctx_read(struct ipmmu_vmsa_device *mmu,
200 unsigned int context_id, unsigned int reg)
201{
202 return ipmmu_read(mmu, ipmmu_ctx_reg(mmu, context_id, reg));
203}
204
205static void ipmmu_ctx_write(struct ipmmu_vmsa_device *mmu,
206 unsigned int context_id, unsigned int reg, u32 data)
207{
208 ipmmu_write(mmu, ipmmu_ctx_reg(mmu, context_id, reg), data);
209}
210
211static u32 ipmmu_ctx_read_root(struct ipmmu_vmsa_domain *domain,
212 unsigned int reg)
213{
214 return ipmmu_ctx_read(domain->mmu->root, domain->context_id, reg);
215}
216
217static void ipmmu_ctx_write_root(struct ipmmu_vmsa_domain *domain,
218 unsigned int reg, u32 data)
219{
220 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data);
221}
222
223static void ipmmu_ctx_write_all(struct ipmmu_vmsa_domain *domain,
224 unsigned int reg, u32 data)
225{
226 if (domain->mmu != domain->mmu->root)
227 ipmmu_ctx_write(domain->mmu, domain->context_id, reg, data);
228
229 ipmmu_ctx_write(domain->mmu->root, domain->context_id, reg, data);
230}
231
232static u32 ipmmu_utlb_reg(struct ipmmu_vmsa_device *mmu, unsigned int reg)
233{
234 return mmu->features->utlb_offset_base + reg;
235}
236
237static void ipmmu_imuasid_write(struct ipmmu_vmsa_device *mmu,
238 unsigned int utlb, u32 data)
239{
240 ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)), data);
241}
242
243static void ipmmu_imuctr_write(struct ipmmu_vmsa_device *mmu,
244 unsigned int utlb, u32 data)
245{
246 ipmmu_write(mmu, ipmmu_utlb_reg(mmu, IMUCTR(utlb)), data);
247}
248
249/* -----------------------------------------------------------------------------
250 * TLB and microTLB Management
251 */
252
253/* Wait for any pending TLB invalidations to complete */
254static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
255{
256 u32 val;
257
258 if (read_poll_timeout_atomic(ipmmu_ctx_read_root, val,
259 !(val & IMCTR_FLUSH), 1, TLB_LOOP_TIMEOUT,
260 false, domain, IMCTR))
261 dev_err_ratelimited(domain->mmu->dev,
262 "TLB sync timed out -- MMU may be deadlocked\n");
263}
264
265static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
266{
267 u32 reg;
268
269 reg = ipmmu_ctx_read_root(domain, IMCTR);
270 reg |= IMCTR_FLUSH;
271 ipmmu_ctx_write_all(domain, IMCTR, reg);
272
273 ipmmu_tlb_sync(domain);
274}
275
276/*
277 * Enable MMU translation for the microTLB.
278 */
279static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
280 unsigned int utlb)
281{
282 struct ipmmu_vmsa_device *mmu = domain->mmu;
283
284 /*
285 * TODO: Reference-count the microTLB as several bus masters can be
286 * connected to the same microTLB.
287 */
288
289 /* TODO: What should we set the ASID to ? */
290 ipmmu_imuasid_write(mmu, utlb, 0);
291 /* TODO: Do we need to flush the microTLB ? */
292 ipmmu_imuctr_write(mmu, utlb, IMUCTR_TTSEL_MMU(domain->context_id) |
293 IMUCTR_FLUSH | IMUCTR_MMUEN);
294 mmu->utlb_ctx[utlb] = domain->context_id;
295}
296
297/*
298 * Disable MMU translation for the microTLB.
299 */
300static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
301 unsigned int utlb)
302{
303 struct ipmmu_vmsa_device *mmu = domain->mmu;
304
305 ipmmu_imuctr_write(mmu, utlb, 0);
306 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID;
307}
308
309static void ipmmu_tlb_flush_all(void *cookie)
310{
311 struct ipmmu_vmsa_domain *domain = cookie;
312
313 ipmmu_tlb_invalidate(domain);
314}
315
316static void ipmmu_tlb_flush(unsigned long iova, size_t size,
317 size_t granule, void *cookie)
318{
319 ipmmu_tlb_flush_all(cookie);
320}
321
322static const struct iommu_flush_ops ipmmu_flush_ops = {
323 .tlb_flush_all = ipmmu_tlb_flush_all,
324 .tlb_flush_walk = ipmmu_tlb_flush,
325};
326
327/* -----------------------------------------------------------------------------
328 * Domain/Context Management
329 */
330
331static int ipmmu_domain_allocate_context(struct ipmmu_vmsa_device *mmu,
332 struct ipmmu_vmsa_domain *domain)
333{
334 unsigned long flags;
335 int ret;
336
337 spin_lock_irqsave(&mmu->lock, flags);
338
339 ret = find_first_zero_bit(mmu->ctx, mmu->num_ctx);
340 if (ret != mmu->num_ctx) {
341 mmu->domains[ret] = domain;
342 set_bit(ret, mmu->ctx);
343 } else
344 ret = -EBUSY;
345
346 spin_unlock_irqrestore(&mmu->lock, flags);
347
348 return ret;
349}
350
351static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
352 unsigned int context_id)
353{
354 unsigned long flags;
355
356 spin_lock_irqsave(&mmu->lock, flags);
357
358 clear_bit(context_id, mmu->ctx);
359 mmu->domains[context_id] = NULL;
360
361 spin_unlock_irqrestore(&mmu->lock, flags);
362}
363
364static void ipmmu_domain_setup_context(struct ipmmu_vmsa_domain *domain)
365{
366 u64 ttbr;
367 u32 tmp;
368
369 /* TTBR0 */
370 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr;
371 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr);
372 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32);
373
374 /*
375 * TTBCR
376 * We use long descriptors and allocate the whole 32-bit VA space to
377 * TTBR0.
378 */
379 if (domain->mmu->features->twobit_imttbcr_sl0)
380 tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
381 else
382 tmp = IMTTBCR_SL0_LVL_1;
383
384 if (domain->mmu->features->cache_snoop)
385 tmp |= IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
386 IMTTBCR_IRGN0_WB_WA;
387
388 ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE | tmp);
389
390 /* MAIR0 */
391 ipmmu_ctx_write_root(domain, IMMAIR0,
392 domain->cfg.arm_lpae_s1_cfg.mair);
393
394 /* IMBUSCR */
395 if (domain->mmu->features->setup_imbuscr)
396 ipmmu_ctx_write_root(domain, IMBUSCR,
397 ipmmu_ctx_read_root(domain, IMBUSCR) &
398 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
399
400 /*
401 * IMSTR
402 * Clear all interrupt flags.
403 */
404 ipmmu_ctx_write_root(domain, IMSTR, ipmmu_ctx_read_root(domain, IMSTR));
405
406 /*
407 * IMCTR
408 * Enable the MMU and interrupt generation. The long-descriptor
409 * translation table format doesn't use TEX remapping. Don't enable AF
410 * software management as we have no use for it. Flush the TLB as
411 * required when modifying the context registers.
412 */
413 ipmmu_ctx_write_all(domain, IMCTR,
414 IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
415}
416
417static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
418{
419 int ret;
420
421 /*
422 * Allocate the page table operations.
423 *
424 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
425 * access, Long-descriptor format" that the NStable bit being set in a
426 * table descriptor will result in the NStable and NS bits of all child
427 * entries being ignored and considered as being set. The IPMMU seems
428 * not to comply with this, as it generates a secure access page fault
429 * if any of the NStable and NS bits isn't set when running in
430 * non-secure mode.
431 */
432 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
433 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K;
434 domain->cfg.ias = 32;
435 domain->cfg.oas = 40;
436 domain->cfg.tlb = &ipmmu_flush_ops;
437 domain->io_domain.geometry.aperture_end = DMA_BIT_MASK(32);
438 domain->io_domain.geometry.force_aperture = true;
439 /*
440 * TODO: Add support for coherent walk through CCI with DVM and remove
441 * cache handling. For now, delegate it to the io-pgtable code.
442 */
443 domain->cfg.coherent_walk = false;
444 domain->cfg.iommu_dev = domain->mmu->root->dev;
445
446 /*
447 * Find an unused context.
448 */
449 ret = ipmmu_domain_allocate_context(domain->mmu->root, domain);
450 if (ret < 0)
451 return ret;
452
453 domain->context_id = ret;
454
455 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
456 domain);
457 if (!domain->iop) {
458 ipmmu_domain_free_context(domain->mmu->root,
459 domain->context_id);
460 return -EINVAL;
461 }
462
463 ipmmu_domain_setup_context(domain);
464 return 0;
465}
466
467static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
468{
469 if (!domain->mmu)
470 return;
471
472 /*
473 * Disable the context. Flush the TLB as required when modifying the
474 * context registers.
475 *
476 * TODO: Is TLB flush really needed ?
477 */
478 ipmmu_ctx_write_all(domain, IMCTR, IMCTR_FLUSH);
479 ipmmu_tlb_sync(domain);
480 ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
481}
482
483/* -----------------------------------------------------------------------------
484 * Fault Handling
485 */
486
487static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
488{
489 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
490 struct ipmmu_vmsa_device *mmu = domain->mmu;
491 unsigned long iova;
492 u32 status;
493
494 status = ipmmu_ctx_read_root(domain, IMSTR);
495 if (!(status & err_mask))
496 return IRQ_NONE;
497
498 iova = ipmmu_ctx_read_root(domain, IMELAR);
499 if (IS_ENABLED(CONFIG_64BIT))
500 iova |= (u64)ipmmu_ctx_read_root(domain, IMEUAR) << 32;
501
502 /*
503 * Clear the error status flags. Unlike traditional interrupt flag
504 * registers that must be cleared by writing 1, this status register
505 * seems to require 0. The error address register must be read before,
506 * otherwise its value will be 0.
507 */
508 ipmmu_ctx_write_root(domain, IMSTR, 0);
509
510 /* Log fatal errors. */
511 if (status & IMSTR_MHIT)
512 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%lx\n",
513 iova);
514 if (status & IMSTR_ABORT)
515 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%lx\n",
516 iova);
517
518 if (!(status & (IMSTR_PF | IMSTR_TF)))
519 return IRQ_NONE;
520
521 /*
522 * Try to handle page faults and translation faults.
523 *
524 * TODO: We need to look up the faulty device based on the I/O VA. Use
525 * the IOMMU device for now.
526 */
527 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
528 return IRQ_HANDLED;
529
530 dev_err_ratelimited(mmu->dev,
531 "Unhandled fault: status 0x%08x iova 0x%lx\n",
532 status, iova);
533
534 return IRQ_HANDLED;
535}
536
537static irqreturn_t ipmmu_irq(int irq, void *dev)
538{
539 struct ipmmu_vmsa_device *mmu = dev;
540 irqreturn_t status = IRQ_NONE;
541 unsigned int i;
542 unsigned long flags;
543
544 spin_lock_irqsave(&mmu->lock, flags);
545
546 /*
547 * Check interrupts for all active contexts.
548 */
549 for (i = 0; i < mmu->num_ctx; i++) {
550 if (!mmu->domains[i])
551 continue;
552 if (ipmmu_domain_irq(mmu->domains[i]) == IRQ_HANDLED)
553 status = IRQ_HANDLED;
554 }
555
556 spin_unlock_irqrestore(&mmu->lock, flags);
557
558 return status;
559}
560
561/* -----------------------------------------------------------------------------
562 * IOMMU Operations
563 */
564
565static struct iommu_domain *ipmmu_domain_alloc_paging(struct device *dev)
566{
567 struct ipmmu_vmsa_domain *domain;
568
569 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
570 if (!domain)
571 return NULL;
572
573 mutex_init(&domain->mutex);
574
575 return &domain->io_domain;
576}
577
578static void ipmmu_domain_free(struct iommu_domain *io_domain)
579{
580 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
581
582 /*
583 * Free the domain resources. We assume that all devices have already
584 * been detached.
585 */
586 ipmmu_domain_destroy_context(domain);
587 free_io_pgtable_ops(domain->iop);
588 kfree(domain);
589}
590
591static int ipmmu_attach_device(struct iommu_domain *io_domain,
592 struct device *dev)
593{
594 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
595 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
596 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
597 unsigned int i;
598 int ret = 0;
599
600 if (!mmu) {
601 dev_err(dev, "Cannot attach to IPMMU\n");
602 return -ENXIO;
603 }
604
605 mutex_lock(&domain->mutex);
606
607 if (!domain->mmu) {
608 /* The domain hasn't been used yet, initialize it. */
609 domain->mmu = mmu;
610 ret = ipmmu_domain_init_context(domain);
611 if (ret < 0) {
612 dev_err(dev, "Unable to initialize IPMMU context\n");
613 domain->mmu = NULL;
614 } else {
615 dev_info(dev, "Using IPMMU context %u\n",
616 domain->context_id);
617 }
618 } else if (domain->mmu != mmu) {
619 /*
620 * Something is wrong, we can't attach two devices using
621 * different IOMMUs to the same domain.
622 */
623 ret = -EINVAL;
624 } else
625 dev_info(dev, "Reusing IPMMU context %u\n", domain->context_id);
626
627 mutex_unlock(&domain->mutex);
628
629 if (ret < 0)
630 return ret;
631
632 for (i = 0; i < fwspec->num_ids; ++i)
633 ipmmu_utlb_enable(domain, fwspec->ids[i]);
634
635 return 0;
636}
637
638static int ipmmu_iommu_identity_attach(struct iommu_domain *identity_domain,
639 struct device *dev)
640{
641 struct iommu_domain *io_domain = iommu_get_domain_for_dev(dev);
642 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
643 struct ipmmu_vmsa_domain *domain;
644 unsigned int i;
645
646 if (io_domain == identity_domain || !io_domain)
647 return 0;
648
649 domain = to_vmsa_domain(io_domain);
650 for (i = 0; i < fwspec->num_ids; ++i)
651 ipmmu_utlb_disable(domain, fwspec->ids[i]);
652
653 /*
654 * TODO: Optimize by disabling the context when no device is attached.
655 */
656 return 0;
657}
658
659static struct iommu_domain_ops ipmmu_iommu_identity_ops = {
660 .attach_dev = ipmmu_iommu_identity_attach,
661};
662
663static struct iommu_domain ipmmu_iommu_identity_domain = {
664 .type = IOMMU_DOMAIN_IDENTITY,
665 .ops = &ipmmu_iommu_identity_ops,
666};
667
668static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
669 phys_addr_t paddr, size_t pgsize, size_t pgcount,
670 int prot, gfp_t gfp, size_t *mapped)
671{
672 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
673
674 return domain->iop->map_pages(domain->iop, iova, paddr, pgsize, pgcount,
675 prot, gfp, mapped);
676}
677
678static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
679 size_t pgsize, size_t pgcount,
680 struct iommu_iotlb_gather *gather)
681{
682 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
683
684 return domain->iop->unmap_pages(domain->iop, iova, pgsize, pgcount, gather);
685}
686
687static void ipmmu_flush_iotlb_all(struct iommu_domain *io_domain)
688{
689 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
690
691 if (domain->mmu)
692 ipmmu_tlb_flush_all(domain);
693}
694
695static void ipmmu_iotlb_sync(struct iommu_domain *io_domain,
696 struct iommu_iotlb_gather *gather)
697{
698 ipmmu_flush_iotlb_all(io_domain);
699}
700
701static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
702 dma_addr_t iova)
703{
704 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
705
706 /* TODO: Is locking needed ? */
707
708 return domain->iop->iova_to_phys(domain->iop, iova);
709}
710
711static int ipmmu_init_platform_device(struct device *dev,
712 struct of_phandle_args *args)
713{
714 struct platform_device *ipmmu_pdev;
715
716 ipmmu_pdev = of_find_device_by_node(args->np);
717 if (!ipmmu_pdev)
718 return -ENODEV;
719
720 dev_iommu_priv_set(dev, platform_get_drvdata(ipmmu_pdev));
721
722 return 0;
723}
724
725static const struct soc_device_attribute soc_needs_opt_in[] = {
726 { .family = "R-Car Gen3", },
727 { .family = "R-Car Gen4", },
728 { .family = "RZ/G2", },
729 { /* sentinel */ }
730};
731
732static const struct soc_device_attribute soc_denylist[] = {
733 { .soc_id = "r8a774a1", },
734 { .soc_id = "r8a7795", .revision = "ES2.*" },
735 { .soc_id = "r8a7796", },
736 { /* sentinel */ }
737};
738
739static const char * const devices_allowlist[] = {
740 "ee100000.mmc",
741 "ee120000.mmc",
742 "ee140000.mmc",
743 "ee160000.mmc"
744};
745
746static bool ipmmu_device_is_allowed(struct device *dev)
747{
748 unsigned int i;
749
750 /*
751 * R-Car Gen3/4 and RZ/G2 use the allow list to opt-in devices.
752 * For Other SoCs, this returns true anyway.
753 */
754 if (!soc_device_match(soc_needs_opt_in))
755 return true;
756
757 /* Check whether this SoC can use the IPMMU correctly or not */
758 if (soc_device_match(soc_denylist))
759 return false;
760
761 /* Check whether this device is a PCI device */
762 if (dev_is_pci(dev))
763 return true;
764
765 /* Check whether this device can work with the IPMMU */
766 for (i = 0; i < ARRAY_SIZE(devices_allowlist); i++) {
767 if (!strcmp(dev_name(dev), devices_allowlist[i]))
768 return true;
769 }
770
771 /* Otherwise, do not allow use of IPMMU */
772 return false;
773}
774
775static int ipmmu_of_xlate(struct device *dev,
776 struct of_phandle_args *spec)
777{
778 if (!ipmmu_device_is_allowed(dev))
779 return -ENODEV;
780
781 iommu_fwspec_add_ids(dev, spec->args, 1);
782
783 /* Initialize once - xlate() will call multiple times */
784 if (to_ipmmu(dev))
785 return 0;
786
787 return ipmmu_init_platform_device(dev, spec);
788}
789
790static int ipmmu_init_arm_mapping(struct device *dev)
791{
792 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
793 int ret;
794
795 /*
796 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
797 * VAs. This will allocate a corresponding IOMMU domain.
798 *
799 * TODO:
800 * - Create one mapping per context (TLB).
801 * - Make the mapping size configurable ? We currently use a 2GB mapping
802 * at a 1GB offset to ensure that NULL VAs will fault.
803 */
804 if (!mmu->mapping) {
805 struct dma_iommu_mapping *mapping;
806
807 mapping = arm_iommu_create_mapping(&platform_bus_type,
808 SZ_1G, SZ_2G);
809 if (IS_ERR(mapping)) {
810 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
811 ret = PTR_ERR(mapping);
812 goto error;
813 }
814
815 mmu->mapping = mapping;
816 }
817
818 /* Attach the ARM VA mapping to the device. */
819 ret = arm_iommu_attach_device(dev, mmu->mapping);
820 if (ret < 0) {
821 dev_err(dev, "Failed to attach device to VA mapping\n");
822 goto error;
823 }
824
825 return 0;
826
827error:
828 if (mmu->mapping)
829 arm_iommu_release_mapping(mmu->mapping);
830
831 return ret;
832}
833
834static struct iommu_device *ipmmu_probe_device(struct device *dev)
835{
836 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
837
838 /*
839 * Only let through devices that have been verified in xlate()
840 */
841 if (!mmu)
842 return ERR_PTR(-ENODEV);
843
844 return &mmu->iommu;
845}
846
847static void ipmmu_probe_finalize(struct device *dev)
848{
849 int ret = 0;
850
851 if (IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA))
852 ret = ipmmu_init_arm_mapping(dev);
853
854 if (ret)
855 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
856}
857
858static void ipmmu_release_device(struct device *dev)
859{
860 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
861 struct ipmmu_vmsa_device *mmu = to_ipmmu(dev);
862 unsigned int i;
863
864 for (i = 0; i < fwspec->num_ids; ++i) {
865 unsigned int utlb = fwspec->ids[i];
866
867 ipmmu_imuctr_write(mmu, utlb, 0);
868 mmu->utlb_ctx[utlb] = IPMMU_CTX_INVALID;
869 }
870
871 arm_iommu_release_mapping(mmu->mapping);
872}
873
874static const struct iommu_ops ipmmu_ops = {
875 .identity_domain = &ipmmu_iommu_identity_domain,
876 .domain_alloc_paging = ipmmu_domain_alloc_paging,
877 .probe_device = ipmmu_probe_device,
878 .release_device = ipmmu_release_device,
879 .probe_finalize = ipmmu_probe_finalize,
880 /*
881 * FIXME: The device grouping is a fixed property of the hardware's
882 * ability to isolate and control DMA, it should not depend on kconfig.
883 */
884 .device_group = IS_ENABLED(CONFIG_ARM) && !IS_ENABLED(CONFIG_IOMMU_DMA)
885 ? generic_device_group : generic_single_device_group,
886 .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
887 .of_xlate = ipmmu_of_xlate,
888 .default_domain_ops = &(const struct iommu_domain_ops) {
889 .attach_dev = ipmmu_attach_device,
890 .map_pages = ipmmu_map,
891 .unmap_pages = ipmmu_unmap,
892 .flush_iotlb_all = ipmmu_flush_iotlb_all,
893 .iotlb_sync = ipmmu_iotlb_sync,
894 .iova_to_phys = ipmmu_iova_to_phys,
895 .free = ipmmu_domain_free,
896 }
897};
898
899/* -----------------------------------------------------------------------------
900 * Probe/remove and init
901 */
902
903static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
904{
905 unsigned int i;
906
907 /* Disable all contexts. */
908 for (i = 0; i < mmu->num_ctx; ++i)
909 ipmmu_ctx_write(mmu, i, IMCTR, 0);
910}
911
912static const struct ipmmu_features ipmmu_features_default = {
913 .use_ns_alias_offset = true,
914 .has_cache_leaf_nodes = false,
915 .number_of_contexts = 1, /* software only tested with one context */
916 .num_utlbs = 32,
917 .setup_imbuscr = true,
918 .twobit_imttbcr_sl0 = false,
919 .reserved_context = false,
920 .cache_snoop = true,
921 .ctx_offset_base = 0,
922 .ctx_offset_stride = 0x40,
923 .utlb_offset_base = 0,
924};
925
926static const struct ipmmu_features ipmmu_features_rcar_gen3 = {
927 .use_ns_alias_offset = false,
928 .has_cache_leaf_nodes = true,
929 .number_of_contexts = 8,
930 .num_utlbs = 48,
931 .setup_imbuscr = false,
932 .twobit_imttbcr_sl0 = true,
933 .reserved_context = true,
934 .cache_snoop = false,
935 .ctx_offset_base = 0,
936 .ctx_offset_stride = 0x40,
937 .utlb_offset_base = 0,
938};
939
940static const struct ipmmu_features ipmmu_features_rcar_gen4 = {
941 .use_ns_alias_offset = false,
942 .has_cache_leaf_nodes = true,
943 .number_of_contexts = 16,
944 .num_utlbs = 64,
945 .setup_imbuscr = false,
946 .twobit_imttbcr_sl0 = true,
947 .reserved_context = true,
948 .cache_snoop = false,
949 .ctx_offset_base = 0x10000,
950 .ctx_offset_stride = 0x1040,
951 .utlb_offset_base = 0x3000,
952};
953
954static const struct of_device_id ipmmu_of_ids[] = {
955 {
956 .compatible = "renesas,ipmmu-vmsa",
957 .data = &ipmmu_features_default,
958 }, {
959 .compatible = "renesas,ipmmu-r8a774a1",
960 .data = &ipmmu_features_rcar_gen3,
961 }, {
962 .compatible = "renesas,ipmmu-r8a774b1",
963 .data = &ipmmu_features_rcar_gen3,
964 }, {
965 .compatible = "renesas,ipmmu-r8a774c0",
966 .data = &ipmmu_features_rcar_gen3,
967 }, {
968 .compatible = "renesas,ipmmu-r8a774e1",
969 .data = &ipmmu_features_rcar_gen3,
970 }, {
971 .compatible = "renesas,ipmmu-r8a7795",
972 .data = &ipmmu_features_rcar_gen3,
973 }, {
974 .compatible = "renesas,ipmmu-r8a7796",
975 .data = &ipmmu_features_rcar_gen3,
976 }, {
977 .compatible = "renesas,ipmmu-r8a77961",
978 .data = &ipmmu_features_rcar_gen3,
979 }, {
980 .compatible = "renesas,ipmmu-r8a77965",
981 .data = &ipmmu_features_rcar_gen3,
982 }, {
983 .compatible = "renesas,ipmmu-r8a77970",
984 .data = &ipmmu_features_rcar_gen3,
985 }, {
986 .compatible = "renesas,ipmmu-r8a77980",
987 .data = &ipmmu_features_rcar_gen3,
988 }, {
989 .compatible = "renesas,ipmmu-r8a77990",
990 .data = &ipmmu_features_rcar_gen3,
991 }, {
992 .compatible = "renesas,ipmmu-r8a77995",
993 .data = &ipmmu_features_rcar_gen3,
994 }, {
995 .compatible = "renesas,ipmmu-r8a779a0",
996 .data = &ipmmu_features_rcar_gen4,
997 }, {
998 .compatible = "renesas,rcar-gen4-ipmmu-vmsa",
999 .data = &ipmmu_features_rcar_gen4,
1000 }, {
1001 /* Terminator */
1002 },
1003};
1004
1005static int ipmmu_probe(struct platform_device *pdev)
1006{
1007 struct ipmmu_vmsa_device *mmu;
1008 struct resource *res;
1009 int irq;
1010 int ret;
1011
1012 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
1013 if (!mmu) {
1014 dev_err(&pdev->dev, "cannot allocate device data\n");
1015 return -ENOMEM;
1016 }
1017
1018 mmu->dev = &pdev->dev;
1019 spin_lock_init(&mmu->lock);
1020 bitmap_zero(mmu->ctx, IPMMU_CTX_MAX);
1021 mmu->features = of_device_get_match_data(&pdev->dev);
1022 memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs);
1023 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
1024 if (ret)
1025 return ret;
1026
1027 /* Map I/O memory and request IRQ. */
1028 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 mmu->base = devm_ioremap_resource(&pdev->dev, res);
1030 if (IS_ERR(mmu->base))
1031 return PTR_ERR(mmu->base);
1032
1033 /*
1034 * The IPMMU has two register banks, for secure and non-secure modes.
1035 * The bank mapped at the beginning of the IPMMU address space
1036 * corresponds to the running mode of the CPU. When running in secure
1037 * mode the non-secure register bank is also available at an offset.
1038 *
1039 * Secure mode operation isn't clearly documented and is thus currently
1040 * not implemented in the driver. Furthermore, preliminary tests of
1041 * non-secure operation with the main register bank were not successful.
1042 * Offset the registers base unconditionally to point to the non-secure
1043 * alias space for now.
1044 */
1045 if (mmu->features->use_ns_alias_offset)
1046 mmu->base += IM_NS_ALIAS_OFFSET;
1047
1048 mmu->num_ctx = min(IPMMU_CTX_MAX, mmu->features->number_of_contexts);
1049
1050 /*
1051 * Determine if this IPMMU instance is a root device by checking for
1052 * the lack of has_cache_leaf_nodes flag or renesas,ipmmu-main property.
1053 */
1054 if (!mmu->features->has_cache_leaf_nodes ||
1055 !of_property_present(pdev->dev.of_node, "renesas,ipmmu-main"))
1056 mmu->root = mmu;
1057 else
1058 mmu->root = ipmmu_find_root();
1059
1060 /*
1061 * Wait until the root device has been registered for sure.
1062 */
1063 if (!mmu->root)
1064 return -EPROBE_DEFER;
1065
1066 /* Root devices have mandatory IRQs */
1067 if (ipmmu_is_root(mmu)) {
1068 irq = platform_get_irq(pdev, 0);
1069 if (irq < 0)
1070 return irq;
1071
1072 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
1073 dev_name(&pdev->dev), mmu);
1074 if (ret < 0) {
1075 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
1076 return ret;
1077 }
1078
1079 ipmmu_device_reset(mmu);
1080
1081 if (mmu->features->reserved_context) {
1082 dev_info(&pdev->dev, "IPMMU context 0 is reserved\n");
1083 set_bit(0, mmu->ctx);
1084 }
1085 }
1086
1087 /*
1088 * Register the IPMMU to the IOMMU subsystem in the following cases:
1089 * - R-Car Gen2 IPMMU (all devices registered)
1090 * - R-Car Gen3 IPMMU (leaf devices only - skip root IPMMU-MM device)
1091 */
1092 if (!mmu->features->has_cache_leaf_nodes || !ipmmu_is_root(mmu)) {
1093 ret = iommu_device_sysfs_add(&mmu->iommu, &pdev->dev, NULL,
1094 dev_name(&pdev->dev));
1095 if (ret)
1096 return ret;
1097
1098 ret = iommu_device_register(&mmu->iommu, &ipmmu_ops, &pdev->dev);
1099 if (ret)
1100 return ret;
1101 }
1102
1103 /*
1104 * We can't create the ARM mapping here as it requires the bus to have
1105 * an IOMMU, which only happens when bus_set_iommu() is called in
1106 * ipmmu_init() after the probe function returns.
1107 */
1108
1109 platform_set_drvdata(pdev, mmu);
1110
1111 return 0;
1112}
1113
1114static void ipmmu_remove(struct platform_device *pdev)
1115{
1116 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
1117
1118 iommu_device_sysfs_remove(&mmu->iommu);
1119 iommu_device_unregister(&mmu->iommu);
1120
1121 arm_iommu_release_mapping(mmu->mapping);
1122
1123 ipmmu_device_reset(mmu);
1124}
1125
1126#ifdef CONFIG_PM_SLEEP
1127static int ipmmu_resume_noirq(struct device *dev)
1128{
1129 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev);
1130 unsigned int i;
1131
1132 /* Reset root MMU and restore contexts */
1133 if (ipmmu_is_root(mmu)) {
1134 ipmmu_device_reset(mmu);
1135
1136 for (i = 0; i < mmu->num_ctx; i++) {
1137 if (!mmu->domains[i])
1138 continue;
1139
1140 ipmmu_domain_setup_context(mmu->domains[i]);
1141 }
1142 }
1143
1144 /* Re-enable active micro-TLBs */
1145 for (i = 0; i < mmu->features->num_utlbs; i++) {
1146 if (mmu->utlb_ctx[i] == IPMMU_CTX_INVALID)
1147 continue;
1148
1149 ipmmu_utlb_enable(mmu->root->domains[mmu->utlb_ctx[i]], i);
1150 }
1151
1152 return 0;
1153}
1154
1155static const struct dev_pm_ops ipmmu_pm = {
1156 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, ipmmu_resume_noirq)
1157};
1158#define DEV_PM_OPS &ipmmu_pm
1159#else
1160#define DEV_PM_OPS NULL
1161#endif /* CONFIG_PM_SLEEP */
1162
1163static struct platform_driver ipmmu_driver = {
1164 .driver = {
1165 .name = "ipmmu-vmsa",
1166 .of_match_table = of_match_ptr(ipmmu_of_ids),
1167 .pm = DEV_PM_OPS,
1168 },
1169 .probe = ipmmu_probe,
1170 .remove_new = ipmmu_remove,
1171};
1172builtin_platform_driver(ipmmu_driver);
1/*
2 * IPMMU VMSA
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/delay.h>
12#include <linux/dma-mapping.h>
13#include <linux/err.h>
14#include <linux/export.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/iommu.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/sizes.h>
22#include <linux/slab.h>
23
24#include <asm/dma-iommu.h>
25#include <asm/pgalloc.h>
26
27#include "io-pgtable.h"
28
29struct ipmmu_vmsa_device {
30 struct device *dev;
31 void __iomem *base;
32 struct list_head list;
33
34 unsigned int num_utlbs;
35
36 struct dma_iommu_mapping *mapping;
37};
38
39struct ipmmu_vmsa_domain {
40 struct ipmmu_vmsa_device *mmu;
41 struct iommu_domain io_domain;
42
43 struct io_pgtable_cfg cfg;
44 struct io_pgtable_ops *iop;
45
46 unsigned int context_id;
47 spinlock_t lock; /* Protects mappings */
48};
49
50struct ipmmu_vmsa_archdata {
51 struct ipmmu_vmsa_device *mmu;
52 unsigned int *utlbs;
53 unsigned int num_utlbs;
54};
55
56static DEFINE_SPINLOCK(ipmmu_devices_lock);
57static LIST_HEAD(ipmmu_devices);
58
59static struct ipmmu_vmsa_domain *to_vmsa_domain(struct iommu_domain *dom)
60{
61 return container_of(dom, struct ipmmu_vmsa_domain, io_domain);
62}
63
64#define TLB_LOOP_TIMEOUT 100 /* 100us */
65
66/* -----------------------------------------------------------------------------
67 * Registers Definition
68 */
69
70#define IM_NS_ALIAS_OFFSET 0x800
71
72#define IM_CTX_SIZE 0x40
73
74#define IMCTR 0x0000
75#define IMCTR_TRE (1 << 17)
76#define IMCTR_AFE (1 << 16)
77#define IMCTR_RTSEL_MASK (3 << 4)
78#define IMCTR_RTSEL_SHIFT 4
79#define IMCTR_TREN (1 << 3)
80#define IMCTR_INTEN (1 << 2)
81#define IMCTR_FLUSH (1 << 1)
82#define IMCTR_MMUEN (1 << 0)
83
84#define IMCAAR 0x0004
85
86#define IMTTBCR 0x0008
87#define IMTTBCR_EAE (1 << 31)
88#define IMTTBCR_PMB (1 << 30)
89#define IMTTBCR_SH1_NON_SHAREABLE (0 << 28)
90#define IMTTBCR_SH1_OUTER_SHAREABLE (2 << 28)
91#define IMTTBCR_SH1_INNER_SHAREABLE (3 << 28)
92#define IMTTBCR_SH1_MASK (3 << 28)
93#define IMTTBCR_ORGN1_NC (0 << 26)
94#define IMTTBCR_ORGN1_WB_WA (1 << 26)
95#define IMTTBCR_ORGN1_WT (2 << 26)
96#define IMTTBCR_ORGN1_WB (3 << 26)
97#define IMTTBCR_ORGN1_MASK (3 << 26)
98#define IMTTBCR_IRGN1_NC (0 << 24)
99#define IMTTBCR_IRGN1_WB_WA (1 << 24)
100#define IMTTBCR_IRGN1_WT (2 << 24)
101#define IMTTBCR_IRGN1_WB (3 << 24)
102#define IMTTBCR_IRGN1_MASK (3 << 24)
103#define IMTTBCR_TSZ1_MASK (7 << 16)
104#define IMTTBCR_TSZ1_SHIFT 16
105#define IMTTBCR_SH0_NON_SHAREABLE (0 << 12)
106#define IMTTBCR_SH0_OUTER_SHAREABLE (2 << 12)
107#define IMTTBCR_SH0_INNER_SHAREABLE (3 << 12)
108#define IMTTBCR_SH0_MASK (3 << 12)
109#define IMTTBCR_ORGN0_NC (0 << 10)
110#define IMTTBCR_ORGN0_WB_WA (1 << 10)
111#define IMTTBCR_ORGN0_WT (2 << 10)
112#define IMTTBCR_ORGN0_WB (3 << 10)
113#define IMTTBCR_ORGN0_MASK (3 << 10)
114#define IMTTBCR_IRGN0_NC (0 << 8)
115#define IMTTBCR_IRGN0_WB_WA (1 << 8)
116#define IMTTBCR_IRGN0_WT (2 << 8)
117#define IMTTBCR_IRGN0_WB (3 << 8)
118#define IMTTBCR_IRGN0_MASK (3 << 8)
119#define IMTTBCR_SL0_LVL_2 (0 << 4)
120#define IMTTBCR_SL0_LVL_1 (1 << 4)
121#define IMTTBCR_TSZ0_MASK (7 << 0)
122#define IMTTBCR_TSZ0_SHIFT O
123
124#define IMBUSCR 0x000c
125#define IMBUSCR_DVM (1 << 2)
126#define IMBUSCR_BUSSEL_SYS (0 << 0)
127#define IMBUSCR_BUSSEL_CCI (1 << 0)
128#define IMBUSCR_BUSSEL_IMCAAR (2 << 0)
129#define IMBUSCR_BUSSEL_CCI_IMCAAR (3 << 0)
130#define IMBUSCR_BUSSEL_MASK (3 << 0)
131
132#define IMTTLBR0 0x0010
133#define IMTTUBR0 0x0014
134#define IMTTLBR1 0x0018
135#define IMTTUBR1 0x001c
136
137#define IMSTR 0x0020
138#define IMSTR_ERRLVL_MASK (3 << 12)
139#define IMSTR_ERRLVL_SHIFT 12
140#define IMSTR_ERRCODE_TLB_FORMAT (1 << 8)
141#define IMSTR_ERRCODE_ACCESS_PERM (4 << 8)
142#define IMSTR_ERRCODE_SECURE_ACCESS (5 << 8)
143#define IMSTR_ERRCODE_MASK (7 << 8)
144#define IMSTR_MHIT (1 << 4)
145#define IMSTR_ABORT (1 << 2)
146#define IMSTR_PF (1 << 1)
147#define IMSTR_TF (1 << 0)
148
149#define IMMAIR0 0x0028
150#define IMMAIR1 0x002c
151#define IMMAIR_ATTR_MASK 0xff
152#define IMMAIR_ATTR_DEVICE 0x04
153#define IMMAIR_ATTR_NC 0x44
154#define IMMAIR_ATTR_WBRWA 0xff
155#define IMMAIR_ATTR_SHIFT(n) ((n) << 3)
156#define IMMAIR_ATTR_IDX_NC 0
157#define IMMAIR_ATTR_IDX_WBRWA 1
158#define IMMAIR_ATTR_IDX_DEV 2
159
160#define IMEAR 0x0030
161
162#define IMPCTR 0x0200
163#define IMPSTR 0x0208
164#define IMPEAR 0x020c
165#define IMPMBA(n) (0x0280 + ((n) * 4))
166#define IMPMBD(n) (0x02c0 + ((n) * 4))
167
168#define IMUCTR(n) (0x0300 + ((n) * 16))
169#define IMUCTR_FIXADDEN (1 << 31)
170#define IMUCTR_FIXADD_MASK (0xff << 16)
171#define IMUCTR_FIXADD_SHIFT 16
172#define IMUCTR_TTSEL_MMU(n) ((n) << 4)
173#define IMUCTR_TTSEL_PMB (8 << 4)
174#define IMUCTR_TTSEL_MASK (15 << 4)
175#define IMUCTR_FLUSH (1 << 1)
176#define IMUCTR_MMUEN (1 << 0)
177
178#define IMUASID(n) (0x0308 + ((n) * 16))
179#define IMUASID_ASID8_MASK (0xff << 8)
180#define IMUASID_ASID8_SHIFT 8
181#define IMUASID_ASID0_MASK (0xff << 0)
182#define IMUASID_ASID0_SHIFT 0
183
184/* -----------------------------------------------------------------------------
185 * Read/Write Access
186 */
187
188static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset)
189{
190 return ioread32(mmu->base + offset);
191}
192
193static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset,
194 u32 data)
195{
196 iowrite32(data, mmu->base + offset);
197}
198
199static u32 ipmmu_ctx_read(struct ipmmu_vmsa_domain *domain, unsigned int reg)
200{
201 return ipmmu_read(domain->mmu, domain->context_id * IM_CTX_SIZE + reg);
202}
203
204static void ipmmu_ctx_write(struct ipmmu_vmsa_domain *domain, unsigned int reg,
205 u32 data)
206{
207 ipmmu_write(domain->mmu, domain->context_id * IM_CTX_SIZE + reg, data);
208}
209
210/* -----------------------------------------------------------------------------
211 * TLB and microTLB Management
212 */
213
214/* Wait for any pending TLB invalidations to complete */
215static void ipmmu_tlb_sync(struct ipmmu_vmsa_domain *domain)
216{
217 unsigned int count = 0;
218
219 while (ipmmu_ctx_read(domain, IMCTR) & IMCTR_FLUSH) {
220 cpu_relax();
221 if (++count == TLB_LOOP_TIMEOUT) {
222 dev_err_ratelimited(domain->mmu->dev,
223 "TLB sync timed out -- MMU may be deadlocked\n");
224 return;
225 }
226 udelay(1);
227 }
228}
229
230static void ipmmu_tlb_invalidate(struct ipmmu_vmsa_domain *domain)
231{
232 u32 reg;
233
234 reg = ipmmu_ctx_read(domain, IMCTR);
235 reg |= IMCTR_FLUSH;
236 ipmmu_ctx_write(domain, IMCTR, reg);
237
238 ipmmu_tlb_sync(domain);
239}
240
241/*
242 * Enable MMU translation for the microTLB.
243 */
244static void ipmmu_utlb_enable(struct ipmmu_vmsa_domain *domain,
245 unsigned int utlb)
246{
247 struct ipmmu_vmsa_device *mmu = domain->mmu;
248
249 /*
250 * TODO: Reference-count the microTLB as several bus masters can be
251 * connected to the same microTLB.
252 */
253
254 /* TODO: What should we set the ASID to ? */
255 ipmmu_write(mmu, IMUASID(utlb), 0);
256 /* TODO: Do we need to flush the microTLB ? */
257 ipmmu_write(mmu, IMUCTR(utlb),
258 IMUCTR_TTSEL_MMU(domain->context_id) | IMUCTR_FLUSH |
259 IMUCTR_MMUEN);
260}
261
262/*
263 * Disable MMU translation for the microTLB.
264 */
265static void ipmmu_utlb_disable(struct ipmmu_vmsa_domain *domain,
266 unsigned int utlb)
267{
268 struct ipmmu_vmsa_device *mmu = domain->mmu;
269
270 ipmmu_write(mmu, IMUCTR(utlb), 0);
271}
272
273static void ipmmu_tlb_flush_all(void *cookie)
274{
275 struct ipmmu_vmsa_domain *domain = cookie;
276
277 ipmmu_tlb_invalidate(domain);
278}
279
280static void ipmmu_tlb_add_flush(unsigned long iova, size_t size,
281 size_t granule, bool leaf, void *cookie)
282{
283 /* The hardware doesn't support selective TLB flush. */
284}
285
286static struct iommu_gather_ops ipmmu_gather_ops = {
287 .tlb_flush_all = ipmmu_tlb_flush_all,
288 .tlb_add_flush = ipmmu_tlb_add_flush,
289 .tlb_sync = ipmmu_tlb_flush_all,
290};
291
292/* -----------------------------------------------------------------------------
293 * Domain/Context Management
294 */
295
296static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
297{
298 u64 ttbr;
299
300 /*
301 * Allocate the page table operations.
302 *
303 * VMSA states in section B3.6.3 "Control of Secure or Non-secure memory
304 * access, Long-descriptor format" that the NStable bit being set in a
305 * table descriptor will result in the NStable and NS bits of all child
306 * entries being ignored and considered as being set. The IPMMU seems
307 * not to comply with this, as it generates a secure access page fault
308 * if any of the NStable and NS bits isn't set when running in
309 * non-secure mode.
310 */
311 domain->cfg.quirks = IO_PGTABLE_QUIRK_ARM_NS;
312 domain->cfg.pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
313 domain->cfg.ias = 32;
314 domain->cfg.oas = 40;
315 domain->cfg.tlb = &ipmmu_gather_ops;
316 /*
317 * TODO: Add support for coherent walk through CCI with DVM and remove
318 * cache handling. For now, delegate it to the io-pgtable code.
319 */
320 domain->cfg.iommu_dev = domain->mmu->dev;
321
322 domain->iop = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &domain->cfg,
323 domain);
324 if (!domain->iop)
325 return -EINVAL;
326
327 /*
328 * TODO: When adding support for multiple contexts, find an unused
329 * context.
330 */
331 domain->context_id = 0;
332
333 /* TTBR0 */
334 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr[0];
335 ipmmu_ctx_write(domain, IMTTLBR0, ttbr);
336 ipmmu_ctx_write(domain, IMTTUBR0, ttbr >> 32);
337
338 /*
339 * TTBCR
340 * We use long descriptors with inner-shareable WBWA tables and allocate
341 * the whole 32-bit VA space to TTBR0.
342 */
343 ipmmu_ctx_write(domain, IMTTBCR, IMTTBCR_EAE |
344 IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
345 IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
346
347 /* MAIR0 */
348 ipmmu_ctx_write(domain, IMMAIR0, domain->cfg.arm_lpae_s1_cfg.mair[0]);
349
350 /* IMBUSCR */
351 ipmmu_ctx_write(domain, IMBUSCR,
352 ipmmu_ctx_read(domain, IMBUSCR) &
353 ~(IMBUSCR_DVM | IMBUSCR_BUSSEL_MASK));
354
355 /*
356 * IMSTR
357 * Clear all interrupt flags.
358 */
359 ipmmu_ctx_write(domain, IMSTR, ipmmu_ctx_read(domain, IMSTR));
360
361 /*
362 * IMCTR
363 * Enable the MMU and interrupt generation. The long-descriptor
364 * translation table format doesn't use TEX remapping. Don't enable AF
365 * software management as we have no use for it. Flush the TLB as
366 * required when modifying the context registers.
367 */
368 ipmmu_ctx_write(domain, IMCTR, IMCTR_INTEN | IMCTR_FLUSH | IMCTR_MMUEN);
369
370 return 0;
371}
372
373static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
374{
375 /*
376 * Disable the context. Flush the TLB as required when modifying the
377 * context registers.
378 *
379 * TODO: Is TLB flush really needed ?
380 */
381 ipmmu_ctx_write(domain, IMCTR, IMCTR_FLUSH);
382 ipmmu_tlb_sync(domain);
383}
384
385/* -----------------------------------------------------------------------------
386 * Fault Handling
387 */
388
389static irqreturn_t ipmmu_domain_irq(struct ipmmu_vmsa_domain *domain)
390{
391 const u32 err_mask = IMSTR_MHIT | IMSTR_ABORT | IMSTR_PF | IMSTR_TF;
392 struct ipmmu_vmsa_device *mmu = domain->mmu;
393 u32 status;
394 u32 iova;
395
396 status = ipmmu_ctx_read(domain, IMSTR);
397 if (!(status & err_mask))
398 return IRQ_NONE;
399
400 iova = ipmmu_ctx_read(domain, IMEAR);
401
402 /*
403 * Clear the error status flags. Unlike traditional interrupt flag
404 * registers that must be cleared by writing 1, this status register
405 * seems to require 0. The error address register must be read before,
406 * otherwise its value will be 0.
407 */
408 ipmmu_ctx_write(domain, IMSTR, 0);
409
410 /* Log fatal errors. */
411 if (status & IMSTR_MHIT)
412 dev_err_ratelimited(mmu->dev, "Multiple TLB hits @0x%08x\n",
413 iova);
414 if (status & IMSTR_ABORT)
415 dev_err_ratelimited(mmu->dev, "Page Table Walk Abort @0x%08x\n",
416 iova);
417
418 if (!(status & (IMSTR_PF | IMSTR_TF)))
419 return IRQ_NONE;
420
421 /*
422 * Try to handle page faults and translation faults.
423 *
424 * TODO: We need to look up the faulty device based on the I/O VA. Use
425 * the IOMMU device for now.
426 */
427 if (!report_iommu_fault(&domain->io_domain, mmu->dev, iova, 0))
428 return IRQ_HANDLED;
429
430 dev_err_ratelimited(mmu->dev,
431 "Unhandled fault: status 0x%08x iova 0x%08x\n",
432 status, iova);
433
434 return IRQ_HANDLED;
435}
436
437static irqreturn_t ipmmu_irq(int irq, void *dev)
438{
439 struct ipmmu_vmsa_device *mmu = dev;
440 struct iommu_domain *io_domain;
441 struct ipmmu_vmsa_domain *domain;
442
443 if (!mmu->mapping)
444 return IRQ_NONE;
445
446 io_domain = mmu->mapping->domain;
447 domain = to_vmsa_domain(io_domain);
448
449 return ipmmu_domain_irq(domain);
450}
451
452/* -----------------------------------------------------------------------------
453 * IOMMU Operations
454 */
455
456static struct iommu_domain *ipmmu_domain_alloc(unsigned type)
457{
458 struct ipmmu_vmsa_domain *domain;
459
460 if (type != IOMMU_DOMAIN_UNMANAGED)
461 return NULL;
462
463 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
464 if (!domain)
465 return NULL;
466
467 spin_lock_init(&domain->lock);
468
469 return &domain->io_domain;
470}
471
472static void ipmmu_domain_free(struct iommu_domain *io_domain)
473{
474 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
475
476 /*
477 * Free the domain resources. We assume that all devices have already
478 * been detached.
479 */
480 ipmmu_domain_destroy_context(domain);
481 free_io_pgtable_ops(domain->iop);
482 kfree(domain);
483}
484
485static int ipmmu_attach_device(struct iommu_domain *io_domain,
486 struct device *dev)
487{
488 struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
489 struct ipmmu_vmsa_device *mmu = archdata->mmu;
490 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
491 unsigned long flags;
492 unsigned int i;
493 int ret = 0;
494
495 if (!mmu) {
496 dev_err(dev, "Cannot attach to IPMMU\n");
497 return -ENXIO;
498 }
499
500 spin_lock_irqsave(&domain->lock, flags);
501
502 if (!domain->mmu) {
503 /* The domain hasn't been used yet, initialize it. */
504 domain->mmu = mmu;
505 ret = ipmmu_domain_init_context(domain);
506 } else if (domain->mmu != mmu) {
507 /*
508 * Something is wrong, we can't attach two devices using
509 * different IOMMUs to the same domain.
510 */
511 dev_err(dev, "Can't attach IPMMU %s to domain on IPMMU %s\n",
512 dev_name(mmu->dev), dev_name(domain->mmu->dev));
513 ret = -EINVAL;
514 }
515
516 spin_unlock_irqrestore(&domain->lock, flags);
517
518 if (ret < 0)
519 return ret;
520
521 for (i = 0; i < archdata->num_utlbs; ++i)
522 ipmmu_utlb_enable(domain, archdata->utlbs[i]);
523
524 return 0;
525}
526
527static void ipmmu_detach_device(struct iommu_domain *io_domain,
528 struct device *dev)
529{
530 struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
531 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
532 unsigned int i;
533
534 for (i = 0; i < archdata->num_utlbs; ++i)
535 ipmmu_utlb_disable(domain, archdata->utlbs[i]);
536
537 /*
538 * TODO: Optimize by disabling the context when no device is attached.
539 */
540}
541
542static int ipmmu_map(struct iommu_domain *io_domain, unsigned long iova,
543 phys_addr_t paddr, size_t size, int prot)
544{
545 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
546
547 if (!domain)
548 return -ENODEV;
549
550 return domain->iop->map(domain->iop, iova, paddr, size, prot);
551}
552
553static size_t ipmmu_unmap(struct iommu_domain *io_domain, unsigned long iova,
554 size_t size)
555{
556 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
557
558 return domain->iop->unmap(domain->iop, iova, size);
559}
560
561static phys_addr_t ipmmu_iova_to_phys(struct iommu_domain *io_domain,
562 dma_addr_t iova)
563{
564 struct ipmmu_vmsa_domain *domain = to_vmsa_domain(io_domain);
565
566 /* TODO: Is locking needed ? */
567
568 return domain->iop->iova_to_phys(domain->iop, iova);
569}
570
571static int ipmmu_find_utlbs(struct ipmmu_vmsa_device *mmu, struct device *dev,
572 unsigned int *utlbs, unsigned int num_utlbs)
573{
574 unsigned int i;
575
576 for (i = 0; i < num_utlbs; ++i) {
577 struct of_phandle_args args;
578 int ret;
579
580 ret = of_parse_phandle_with_args(dev->of_node, "iommus",
581 "#iommu-cells", i, &args);
582 if (ret < 0)
583 return ret;
584
585 of_node_put(args.np);
586
587 if (args.np != mmu->dev->of_node || args.args_count != 1)
588 return -EINVAL;
589
590 utlbs[i] = args.args[0];
591 }
592
593 return 0;
594}
595
596static int ipmmu_add_device(struct device *dev)
597{
598 struct ipmmu_vmsa_archdata *archdata;
599 struct ipmmu_vmsa_device *mmu;
600 struct iommu_group *group = NULL;
601 unsigned int *utlbs;
602 unsigned int i;
603 int num_utlbs;
604 int ret = -ENODEV;
605
606 if (dev->archdata.iommu) {
607 dev_warn(dev, "IOMMU driver already assigned to device %s\n",
608 dev_name(dev));
609 return -EINVAL;
610 }
611
612 /* Find the master corresponding to the device. */
613
614 num_utlbs = of_count_phandle_with_args(dev->of_node, "iommus",
615 "#iommu-cells");
616 if (num_utlbs < 0)
617 return -ENODEV;
618
619 utlbs = kcalloc(num_utlbs, sizeof(*utlbs), GFP_KERNEL);
620 if (!utlbs)
621 return -ENOMEM;
622
623 spin_lock(&ipmmu_devices_lock);
624
625 list_for_each_entry(mmu, &ipmmu_devices, list) {
626 ret = ipmmu_find_utlbs(mmu, dev, utlbs, num_utlbs);
627 if (!ret) {
628 /*
629 * TODO Take a reference to the MMU to protect
630 * against device removal.
631 */
632 break;
633 }
634 }
635
636 spin_unlock(&ipmmu_devices_lock);
637
638 if (ret < 0)
639 return -ENODEV;
640
641 for (i = 0; i < num_utlbs; ++i) {
642 if (utlbs[i] >= mmu->num_utlbs) {
643 ret = -EINVAL;
644 goto error;
645 }
646 }
647
648 /* Create a device group and add the device to it. */
649 group = iommu_group_alloc();
650 if (IS_ERR(group)) {
651 dev_err(dev, "Failed to allocate IOMMU group\n");
652 ret = PTR_ERR(group);
653 goto error;
654 }
655
656 ret = iommu_group_add_device(group, dev);
657 iommu_group_put(group);
658
659 if (ret < 0) {
660 dev_err(dev, "Failed to add device to IPMMU group\n");
661 group = NULL;
662 goto error;
663 }
664
665 archdata = kzalloc(sizeof(*archdata), GFP_KERNEL);
666 if (!archdata) {
667 ret = -ENOMEM;
668 goto error;
669 }
670
671 archdata->mmu = mmu;
672 archdata->utlbs = utlbs;
673 archdata->num_utlbs = num_utlbs;
674 dev->archdata.iommu = archdata;
675
676 /*
677 * Create the ARM mapping, used by the ARM DMA mapping core to allocate
678 * VAs. This will allocate a corresponding IOMMU domain.
679 *
680 * TODO:
681 * - Create one mapping per context (TLB).
682 * - Make the mapping size configurable ? We currently use a 2GB mapping
683 * at a 1GB offset to ensure that NULL VAs will fault.
684 */
685 if (!mmu->mapping) {
686 struct dma_iommu_mapping *mapping;
687
688 mapping = arm_iommu_create_mapping(&platform_bus_type,
689 SZ_1G, SZ_2G);
690 if (IS_ERR(mapping)) {
691 dev_err(mmu->dev, "failed to create ARM IOMMU mapping\n");
692 ret = PTR_ERR(mapping);
693 goto error;
694 }
695
696 mmu->mapping = mapping;
697 }
698
699 /* Attach the ARM VA mapping to the device. */
700 ret = arm_iommu_attach_device(dev, mmu->mapping);
701 if (ret < 0) {
702 dev_err(dev, "Failed to attach device to VA mapping\n");
703 goto error;
704 }
705
706 return 0;
707
708error:
709 arm_iommu_release_mapping(mmu->mapping);
710
711 kfree(dev->archdata.iommu);
712 kfree(utlbs);
713
714 dev->archdata.iommu = NULL;
715
716 if (!IS_ERR_OR_NULL(group))
717 iommu_group_remove_device(dev);
718
719 return ret;
720}
721
722static void ipmmu_remove_device(struct device *dev)
723{
724 struct ipmmu_vmsa_archdata *archdata = dev->archdata.iommu;
725
726 arm_iommu_detach_device(dev);
727 iommu_group_remove_device(dev);
728
729 kfree(archdata->utlbs);
730 kfree(archdata);
731
732 dev->archdata.iommu = NULL;
733}
734
735static const struct iommu_ops ipmmu_ops = {
736 .domain_alloc = ipmmu_domain_alloc,
737 .domain_free = ipmmu_domain_free,
738 .attach_dev = ipmmu_attach_device,
739 .detach_dev = ipmmu_detach_device,
740 .map = ipmmu_map,
741 .unmap = ipmmu_unmap,
742 .map_sg = default_iommu_map_sg,
743 .iova_to_phys = ipmmu_iova_to_phys,
744 .add_device = ipmmu_add_device,
745 .remove_device = ipmmu_remove_device,
746 .pgsize_bitmap = SZ_1G | SZ_2M | SZ_4K,
747};
748
749/* -----------------------------------------------------------------------------
750 * Probe/remove and init
751 */
752
753static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu)
754{
755 unsigned int i;
756
757 /* Disable all contexts. */
758 for (i = 0; i < 4; ++i)
759 ipmmu_write(mmu, i * IM_CTX_SIZE + IMCTR, 0);
760}
761
762static int ipmmu_probe(struct platform_device *pdev)
763{
764 struct ipmmu_vmsa_device *mmu;
765 struct resource *res;
766 int irq;
767 int ret;
768
769 if (!IS_ENABLED(CONFIG_OF) && !pdev->dev.platform_data) {
770 dev_err(&pdev->dev, "missing platform data\n");
771 return -EINVAL;
772 }
773
774 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL);
775 if (!mmu) {
776 dev_err(&pdev->dev, "cannot allocate device data\n");
777 return -ENOMEM;
778 }
779
780 mmu->dev = &pdev->dev;
781 mmu->num_utlbs = 32;
782
783 /* Map I/O memory and request IRQ. */
784 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
785 mmu->base = devm_ioremap_resource(&pdev->dev, res);
786 if (IS_ERR(mmu->base))
787 return PTR_ERR(mmu->base);
788
789 /*
790 * The IPMMU has two register banks, for secure and non-secure modes.
791 * The bank mapped at the beginning of the IPMMU address space
792 * corresponds to the running mode of the CPU. When running in secure
793 * mode the non-secure register bank is also available at an offset.
794 *
795 * Secure mode operation isn't clearly documented and is thus currently
796 * not implemented in the driver. Furthermore, preliminary tests of
797 * non-secure operation with the main register bank were not successful.
798 * Offset the registers base unconditionally to point to the non-secure
799 * alias space for now.
800 */
801 mmu->base += IM_NS_ALIAS_OFFSET;
802
803 irq = platform_get_irq(pdev, 0);
804 if (irq < 0) {
805 dev_err(&pdev->dev, "no IRQ found\n");
806 return irq;
807 }
808
809 ret = devm_request_irq(&pdev->dev, irq, ipmmu_irq, 0,
810 dev_name(&pdev->dev), mmu);
811 if (ret < 0) {
812 dev_err(&pdev->dev, "failed to request IRQ %d\n", irq);
813 return ret;
814 }
815
816 ipmmu_device_reset(mmu);
817
818 /*
819 * We can't create the ARM mapping here as it requires the bus to have
820 * an IOMMU, which only happens when bus_set_iommu() is called in
821 * ipmmu_init() after the probe function returns.
822 */
823
824 spin_lock(&ipmmu_devices_lock);
825 list_add(&mmu->list, &ipmmu_devices);
826 spin_unlock(&ipmmu_devices_lock);
827
828 platform_set_drvdata(pdev, mmu);
829
830 return 0;
831}
832
833static int ipmmu_remove(struct platform_device *pdev)
834{
835 struct ipmmu_vmsa_device *mmu = platform_get_drvdata(pdev);
836
837 spin_lock(&ipmmu_devices_lock);
838 list_del(&mmu->list);
839 spin_unlock(&ipmmu_devices_lock);
840
841 arm_iommu_release_mapping(mmu->mapping);
842
843 ipmmu_device_reset(mmu);
844
845 return 0;
846}
847
848static const struct of_device_id ipmmu_of_ids[] = {
849 { .compatible = "renesas,ipmmu-vmsa", },
850 { }
851};
852
853static struct platform_driver ipmmu_driver = {
854 .driver = {
855 .name = "ipmmu-vmsa",
856 .of_match_table = of_match_ptr(ipmmu_of_ids),
857 },
858 .probe = ipmmu_probe,
859 .remove = ipmmu_remove,
860};
861
862static int __init ipmmu_init(void)
863{
864 int ret;
865
866 ret = platform_driver_register(&ipmmu_driver);
867 if (ret < 0)
868 return ret;
869
870 if (!iommu_present(&platform_bus_type))
871 bus_set_iommu(&platform_bus_type, &ipmmu_ops);
872
873 return 0;
874}
875
876static void __exit ipmmu_exit(void)
877{
878 return platform_driver_unregister(&ipmmu_driver);
879}
880
881subsys_initcall(ipmmu_init);
882module_exit(ipmmu_exit);
883
884MODULE_DESCRIPTION("IOMMU API for Renesas VMSA-compatible IPMMU");
885MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
886MODULE_LICENSE("GPL v2");