Loading...
Note: File does not exist in v6.8.
1/*
2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
7 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
13 *
14 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/USA_new/service_support.htm
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
19 *
20 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
55 * Alan Cox <alan@lxorguk.ukuu.org.uk>
56 *
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
120 */
121
122#include <linux/types.h>
123#include <linux/module.h>
124#include <linux/kernel.h>
125#include <linux/delay.h>
126#include <linux/blkdev.h>
127#include <linux/interrupt.h>
128#include <linux/pci.h>
129#include <linux/init.h>
130#include <linux/ide.h>
131#include <linux/slab.h>
132
133#include <asm/uaccess.h>
134#include <asm/io.h>
135
136#define DRV_NAME "hpt366"
137
138/* various tuning parameters */
139#undef HPT_RESET_STATE_ENGINE
140#undef HPT_DELAY_INTERRUPT
141
142static const char *bad_ata100_5[] = {
143 "IBM-DTLA-307075",
144 "IBM-DTLA-307060",
145 "IBM-DTLA-307045",
146 "IBM-DTLA-307030",
147 "IBM-DTLA-307020",
148 "IBM-DTLA-307015",
149 "IBM-DTLA-305040",
150 "IBM-DTLA-305030",
151 "IBM-DTLA-305020",
152 "IC35L010AVER07-0",
153 "IC35L020AVER07-0",
154 "IC35L030AVER07-0",
155 "IC35L040AVER07-0",
156 "IC35L060AVER07-0",
157 "WDC AC310200R",
158 NULL
159};
160
161static const char *bad_ata66_4[] = {
162 "IBM-DTLA-307075",
163 "IBM-DTLA-307060",
164 "IBM-DTLA-307045",
165 "IBM-DTLA-307030",
166 "IBM-DTLA-307020",
167 "IBM-DTLA-307015",
168 "IBM-DTLA-305040",
169 "IBM-DTLA-305030",
170 "IBM-DTLA-305020",
171 "IC35L010AVER07-0",
172 "IC35L020AVER07-0",
173 "IC35L030AVER07-0",
174 "IC35L040AVER07-0",
175 "IC35L060AVER07-0",
176 "WDC AC310200R",
177 "MAXTOR STM3320620A",
178 NULL
179};
180
181static const char *bad_ata66_3[] = {
182 "WDC AC310200R",
183 NULL
184};
185
186static const char *bad_ata33[] = {
187 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
188 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
189 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
190 "Maxtor 90510D4",
191 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
192 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
193 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
194 NULL
195};
196
197static u8 xfer_speeds[] = {
198 XFER_UDMA_6,
199 XFER_UDMA_5,
200 XFER_UDMA_4,
201 XFER_UDMA_3,
202 XFER_UDMA_2,
203 XFER_UDMA_1,
204 XFER_UDMA_0,
205
206 XFER_MW_DMA_2,
207 XFER_MW_DMA_1,
208 XFER_MW_DMA_0,
209
210 XFER_PIO_4,
211 XFER_PIO_3,
212 XFER_PIO_2,
213 XFER_PIO_1,
214 XFER_PIO_0
215};
216
217/* Key for bus clock timings
218 * 36x 37x
219 * bits bits
220 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
221 * cycles = value + 1
222 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
223 * cycles = value + 1
224 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
225 * register access.
226 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
227 * register access.
228 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
229 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
230 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
231 * MW DMA xfer.
232 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
233 * task file register access.
234 * 28 28 UDMA enable.
235 * 29 29 DMA enable.
236 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
237 * PIO xfer.
238 * 31 31 FIFO enable.
239 */
240
241static u32 forty_base_hpt36x[] = {
242 /* XFER_UDMA_6 */ 0x900fd943,
243 /* XFER_UDMA_5 */ 0x900fd943,
244 /* XFER_UDMA_4 */ 0x900fd943,
245 /* XFER_UDMA_3 */ 0x900ad943,
246 /* XFER_UDMA_2 */ 0x900bd943,
247 /* XFER_UDMA_1 */ 0x9008d943,
248 /* XFER_UDMA_0 */ 0x9008d943,
249
250 /* XFER_MW_DMA_2 */ 0xa008d943,
251 /* XFER_MW_DMA_1 */ 0xa010d955,
252 /* XFER_MW_DMA_0 */ 0xa010d9fc,
253
254 /* XFER_PIO_4 */ 0xc008d963,
255 /* XFER_PIO_3 */ 0xc010d974,
256 /* XFER_PIO_2 */ 0xc010d997,
257 /* XFER_PIO_1 */ 0xc010d9c7,
258 /* XFER_PIO_0 */ 0xc018d9d9
259};
260
261static u32 thirty_three_base_hpt36x[] = {
262 /* XFER_UDMA_6 */ 0x90c9a731,
263 /* XFER_UDMA_5 */ 0x90c9a731,
264 /* XFER_UDMA_4 */ 0x90c9a731,
265 /* XFER_UDMA_3 */ 0x90cfa731,
266 /* XFER_UDMA_2 */ 0x90caa731,
267 /* XFER_UDMA_1 */ 0x90cba731,
268 /* XFER_UDMA_0 */ 0x90c8a731,
269
270 /* XFER_MW_DMA_2 */ 0xa0c8a731,
271 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
272 /* XFER_MW_DMA_0 */ 0xa0c8a797,
273
274 /* XFER_PIO_4 */ 0xc0c8a731,
275 /* XFER_PIO_3 */ 0xc0c8a742,
276 /* XFER_PIO_2 */ 0xc0d0a753,
277 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
278 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
279};
280
281static u32 twenty_five_base_hpt36x[] = {
282 /* XFER_UDMA_6 */ 0x90c98521,
283 /* XFER_UDMA_5 */ 0x90c98521,
284 /* XFER_UDMA_4 */ 0x90c98521,
285 /* XFER_UDMA_3 */ 0x90cf8521,
286 /* XFER_UDMA_2 */ 0x90cf8521,
287 /* XFER_UDMA_1 */ 0x90cb8521,
288 /* XFER_UDMA_0 */ 0x90cb8521,
289
290 /* XFER_MW_DMA_2 */ 0xa0ca8521,
291 /* XFER_MW_DMA_1 */ 0xa0ca8532,
292 /* XFER_MW_DMA_0 */ 0xa0ca8575,
293
294 /* XFER_PIO_4 */ 0xc0ca8521,
295 /* XFER_PIO_3 */ 0xc0ca8532,
296 /* XFER_PIO_2 */ 0xc0ca8542,
297 /* XFER_PIO_1 */ 0xc0d08572,
298 /* XFER_PIO_0 */ 0xc0d08585
299};
300
301/*
302 * The following are the new timing tables with PIO mode data/taskfile transfer
303 * overclocking fixed...
304 */
305
306/* This table is taken from the HPT370 data manual rev. 1.02 */
307static u32 thirty_three_base_hpt37x[] = {
308 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
309 /* XFER_UDMA_5 */ 0x16455031,
310 /* XFER_UDMA_4 */ 0x16455031,
311 /* XFER_UDMA_3 */ 0x166d5031,
312 /* XFER_UDMA_2 */ 0x16495031,
313 /* XFER_UDMA_1 */ 0x164d5033,
314 /* XFER_UDMA_0 */ 0x16515097,
315
316 /* XFER_MW_DMA_2 */ 0x26515031,
317 /* XFER_MW_DMA_1 */ 0x26515033,
318 /* XFER_MW_DMA_0 */ 0x26515097,
319
320 /* XFER_PIO_4 */ 0x06515021,
321 /* XFER_PIO_3 */ 0x06515022,
322 /* XFER_PIO_2 */ 0x06515033,
323 /* XFER_PIO_1 */ 0x06915065,
324 /* XFER_PIO_0 */ 0x06d1508a
325};
326
327static u32 fifty_base_hpt37x[] = {
328 /* XFER_UDMA_6 */ 0x1a861842,
329 /* XFER_UDMA_5 */ 0x1a861842,
330 /* XFER_UDMA_4 */ 0x1aae1842,
331 /* XFER_UDMA_3 */ 0x1a8e1842,
332 /* XFER_UDMA_2 */ 0x1a0e1842,
333 /* XFER_UDMA_1 */ 0x1a161854,
334 /* XFER_UDMA_0 */ 0x1a1a18ea,
335
336 /* XFER_MW_DMA_2 */ 0x2a821842,
337 /* XFER_MW_DMA_1 */ 0x2a821854,
338 /* XFER_MW_DMA_0 */ 0x2a8218ea,
339
340 /* XFER_PIO_4 */ 0x0a821842,
341 /* XFER_PIO_3 */ 0x0a821843,
342 /* XFER_PIO_2 */ 0x0a821855,
343 /* XFER_PIO_1 */ 0x0ac218a8,
344 /* XFER_PIO_0 */ 0x0b02190c
345};
346
347static u32 sixty_six_base_hpt37x[] = {
348 /* XFER_UDMA_6 */ 0x1c86fe62,
349 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
350 /* XFER_UDMA_4 */ 0x1c8afe62,
351 /* XFER_UDMA_3 */ 0x1c8efe62,
352 /* XFER_UDMA_2 */ 0x1c92fe62,
353 /* XFER_UDMA_1 */ 0x1c9afe62,
354 /* XFER_UDMA_0 */ 0x1c82fe62,
355
356 /* XFER_MW_DMA_2 */ 0x2c82fe62,
357 /* XFER_MW_DMA_1 */ 0x2c82fe66,
358 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
359
360 /* XFER_PIO_4 */ 0x0c82fe62,
361 /* XFER_PIO_3 */ 0x0c82fe84,
362 /* XFER_PIO_2 */ 0x0c82fea6,
363 /* XFER_PIO_1 */ 0x0d02ff26,
364 /* XFER_PIO_0 */ 0x0d42ff7f
365};
366
367#define HPT371_ALLOW_ATA133_6 1
368#define HPT302_ALLOW_ATA133_6 1
369#define HPT372_ALLOW_ATA133_6 1
370#define HPT370_ALLOW_ATA100_5 0
371#define HPT366_ALLOW_ATA66_4 1
372#define HPT366_ALLOW_ATA66_3 1
373
374/* Supported ATA clock frequencies */
375enum ata_clock {
376 ATA_CLOCK_25MHZ,
377 ATA_CLOCK_33MHZ,
378 ATA_CLOCK_40MHZ,
379 ATA_CLOCK_50MHZ,
380 ATA_CLOCK_66MHZ,
381 NUM_ATA_CLOCKS
382};
383
384struct hpt_timings {
385 u32 pio_mask;
386 u32 dma_mask;
387 u32 ultra_mask;
388 u32 *clock_table[NUM_ATA_CLOCKS];
389};
390
391/*
392 * Hold all the HighPoint chip information in one place.
393 */
394
395struct hpt_info {
396 char *chip_name; /* Chip name */
397 u8 chip_type; /* Chip type */
398 u8 udma_mask; /* Allowed UltraDMA modes mask. */
399 u8 dpll_clk; /* DPLL clock in MHz */
400 u8 pci_clk; /* PCI clock in MHz */
401 struct hpt_timings *timings; /* Chipset timing data */
402 u8 clock; /* ATA clock selected */
403};
404
405/* Supported HighPoint chips */
406enum {
407 HPT36x,
408 HPT370,
409 HPT370A,
410 HPT374,
411 HPT372,
412 HPT372A,
413 HPT302,
414 HPT371,
415 HPT372N,
416 HPT302N,
417 HPT371N
418};
419
420static struct hpt_timings hpt36x_timings = {
421 .pio_mask = 0xc1f8ffff,
422 .dma_mask = 0x303800ff,
423 .ultra_mask = 0x30070000,
424 .clock_table = {
425 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
426 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
427 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
428 [ATA_CLOCK_50MHZ] = NULL,
429 [ATA_CLOCK_66MHZ] = NULL
430 }
431};
432
433static struct hpt_timings hpt37x_timings = {
434 .pio_mask = 0xcfc3ffff,
435 .dma_mask = 0x31c001ff,
436 .ultra_mask = 0x303c0000,
437 .clock_table = {
438 [ATA_CLOCK_25MHZ] = NULL,
439 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
440 [ATA_CLOCK_40MHZ] = NULL,
441 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
442 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
443 }
444};
445
446static const struct hpt_info hpt36x = {
447 .chip_name = "HPT36x",
448 .chip_type = HPT36x,
449 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
450 .dpll_clk = 0, /* no DPLL */
451 .timings = &hpt36x_timings
452};
453
454static const struct hpt_info hpt370 = {
455 .chip_name = "HPT370",
456 .chip_type = HPT370,
457 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
458 .dpll_clk = 48,
459 .timings = &hpt37x_timings
460};
461
462static const struct hpt_info hpt370a = {
463 .chip_name = "HPT370A",
464 .chip_type = HPT370A,
465 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
466 .dpll_clk = 48,
467 .timings = &hpt37x_timings
468};
469
470static const struct hpt_info hpt374 = {
471 .chip_name = "HPT374",
472 .chip_type = HPT374,
473 .udma_mask = ATA_UDMA5,
474 .dpll_clk = 48,
475 .timings = &hpt37x_timings
476};
477
478static const struct hpt_info hpt372 = {
479 .chip_name = "HPT372",
480 .chip_type = HPT372,
481 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
482 .dpll_clk = 55,
483 .timings = &hpt37x_timings
484};
485
486static const struct hpt_info hpt372a = {
487 .chip_name = "HPT372A",
488 .chip_type = HPT372A,
489 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
490 .dpll_clk = 66,
491 .timings = &hpt37x_timings
492};
493
494static const struct hpt_info hpt302 = {
495 .chip_name = "HPT302",
496 .chip_type = HPT302,
497 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
498 .dpll_clk = 66,
499 .timings = &hpt37x_timings
500};
501
502static const struct hpt_info hpt371 = {
503 .chip_name = "HPT371",
504 .chip_type = HPT371,
505 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
506 .dpll_clk = 66,
507 .timings = &hpt37x_timings
508};
509
510static const struct hpt_info hpt372n = {
511 .chip_name = "HPT372N",
512 .chip_type = HPT372N,
513 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
514 .dpll_clk = 77,
515 .timings = &hpt37x_timings
516};
517
518static const struct hpt_info hpt302n = {
519 .chip_name = "HPT302N",
520 .chip_type = HPT302N,
521 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
522 .dpll_clk = 77,
523 .timings = &hpt37x_timings
524};
525
526static const struct hpt_info hpt371n = {
527 .chip_name = "HPT371N",
528 .chip_type = HPT371N,
529 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
530 .dpll_clk = 77,
531 .timings = &hpt37x_timings
532};
533
534static bool check_in_drive_list(ide_drive_t *drive, const char **list)
535{
536 return match_string(list, -1, (char *)&drive->id[ATA_ID_PROD]) >= 0;
537}
538
539static struct hpt_info *hpt3xx_get_info(struct device *dev)
540{
541 struct ide_host *host = dev_get_drvdata(dev);
542 struct hpt_info *info = (struct hpt_info *)host->host_priv;
543
544 return dev == host->dev[1] ? info + 1 : info;
545}
546
547/*
548 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
549 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
550 */
551
552static u8 hpt3xx_udma_filter(ide_drive_t *drive)
553{
554 ide_hwif_t *hwif = drive->hwif;
555 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
556 u8 mask = hwif->ultra_mask;
557
558 switch (info->chip_type) {
559 case HPT36x:
560 if (!HPT366_ALLOW_ATA66_4 ||
561 check_in_drive_list(drive, bad_ata66_4))
562 mask = ATA_UDMA3;
563
564 if (!HPT366_ALLOW_ATA66_3 ||
565 check_in_drive_list(drive, bad_ata66_3))
566 mask = ATA_UDMA2;
567 break;
568 case HPT370:
569 if (!HPT370_ALLOW_ATA100_5 ||
570 check_in_drive_list(drive, bad_ata100_5))
571 mask = ATA_UDMA4;
572 break;
573 case HPT370A:
574 if (!HPT370_ALLOW_ATA100_5 ||
575 check_in_drive_list(drive, bad_ata100_5))
576 return ATA_UDMA4;
577 case HPT372 :
578 case HPT372A:
579 case HPT372N:
580 case HPT374 :
581 if (ata_id_is_sata(drive->id))
582 mask &= ~0x0e;
583 /* Fall thru */
584 default:
585 return mask;
586 }
587
588 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
589}
590
591static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
592{
593 ide_hwif_t *hwif = drive->hwif;
594 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
595
596 switch (info->chip_type) {
597 case HPT372 :
598 case HPT372A:
599 case HPT372N:
600 case HPT374 :
601 if (ata_id_is_sata(drive->id))
602 return 0x00;
603 /* Fall thru */
604 default:
605 return 0x07;
606 }
607}
608
609static u32 get_speed_setting(u8 speed, struct hpt_info *info)
610{
611 int i;
612
613 /*
614 * Lookup the transfer mode table to get the index into
615 * the timing table.
616 *
617 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
618 */
619 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
620 if (xfer_speeds[i] == speed)
621 break;
622
623 return info->timings->clock_table[info->clock][i];
624}
625
626static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
627{
628 struct pci_dev *dev = to_pci_dev(hwif->dev);
629 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
630 struct hpt_timings *t = info->timings;
631 u8 itr_addr = 0x40 + (drive->dn * 4);
632 u32 old_itr = 0;
633 const u8 speed = drive->dma_mode;
634 u32 new_itr = get_speed_setting(speed, info);
635 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
636 (speed < XFER_UDMA_0 ? t->dma_mask :
637 t->ultra_mask);
638
639 pci_read_config_dword(dev, itr_addr, &old_itr);
640 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
641 /*
642 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
643 * to avoid problems handling I/O errors later
644 */
645 new_itr &= ~0xc0000000;
646
647 pci_write_config_dword(dev, itr_addr, new_itr);
648}
649
650static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
651{
652 drive->dma_mode = drive->pio_mode;
653 hpt3xx_set_mode(hwif, drive);
654}
655
656static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
657{
658 ide_hwif_t *hwif = drive->hwif;
659 struct pci_dev *dev = to_pci_dev(hwif->dev);
660 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
661
662 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
663 return;
664
665 if (info->chip_type >= HPT370) {
666 u8 scr1 = 0;
667
668 pci_read_config_byte(dev, 0x5a, &scr1);
669 if (((scr1 & 0x10) >> 4) != mask) {
670 if (mask)
671 scr1 |= 0x10;
672 else
673 scr1 &= ~0x10;
674 pci_write_config_byte(dev, 0x5a, scr1);
675 }
676 } else if (mask)
677 disable_irq(hwif->irq);
678 else
679 enable_irq(hwif->irq);
680}
681
682/*
683 * This is specific to the HPT366 UDMA chipset
684 * by HighPoint|Triones Technologies, Inc.
685 */
686static void hpt366_dma_lost_irq(ide_drive_t *drive)
687{
688 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
689 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
690
691 pci_read_config_byte(dev, 0x50, &mcr1);
692 pci_read_config_byte(dev, 0x52, &mcr3);
693 pci_read_config_byte(dev, 0x5a, &scr1);
694 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
695 drive->name, __func__, mcr1, mcr3, scr1);
696 if (scr1 & 0x10)
697 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
698 ide_dma_lost_irq(drive);
699}
700
701static void hpt370_clear_engine(ide_drive_t *drive)
702{
703 ide_hwif_t *hwif = drive->hwif;
704 struct pci_dev *dev = to_pci_dev(hwif->dev);
705
706 pci_write_config_byte(dev, hwif->select_data, 0x37);
707 udelay(10);
708}
709
710static void hpt370_irq_timeout(ide_drive_t *drive)
711{
712 ide_hwif_t *hwif = drive->hwif;
713 struct pci_dev *dev = to_pci_dev(hwif->dev);
714 u16 bfifo = 0;
715 u8 dma_cmd;
716
717 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
718 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
719
720 /* get DMA command mode */
721 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
722 /* stop DMA */
723 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
724 hpt370_clear_engine(drive);
725}
726
727static void hpt370_dma_start(ide_drive_t *drive)
728{
729#ifdef HPT_RESET_STATE_ENGINE
730 hpt370_clear_engine(drive);
731#endif
732 ide_dma_start(drive);
733}
734
735static int hpt370_dma_end(ide_drive_t *drive)
736{
737 ide_hwif_t *hwif = drive->hwif;
738 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
739
740 if (dma_stat & ATA_DMA_ACTIVE) {
741 /* wait a little */
742 udelay(20);
743 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
744 if (dma_stat & ATA_DMA_ACTIVE)
745 hpt370_irq_timeout(drive);
746 }
747 return ide_dma_end(drive);
748}
749
750/* returns 1 if DMA IRQ issued, 0 otherwise */
751static int hpt374_dma_test_irq(ide_drive_t *drive)
752{
753 ide_hwif_t *hwif = drive->hwif;
754 struct pci_dev *dev = to_pci_dev(hwif->dev);
755 u16 bfifo = 0;
756 u8 dma_stat;
757
758 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
759 if (bfifo & 0x1FF) {
760// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
761 return 0;
762 }
763
764 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
765 /* return 1 if INTR asserted */
766 if (dma_stat & ATA_DMA_INTR)
767 return 1;
768
769 return 0;
770}
771
772static int hpt374_dma_end(ide_drive_t *drive)
773{
774 ide_hwif_t *hwif = drive->hwif;
775 struct pci_dev *dev = to_pci_dev(hwif->dev);
776 u8 mcr = 0, mcr_addr = hwif->select_data;
777 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
778
779 pci_read_config_byte(dev, 0x6a, &bwsr);
780 pci_read_config_byte(dev, mcr_addr, &mcr);
781 if (bwsr & mask)
782 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
783 return ide_dma_end(drive);
784}
785
786/**
787 * hpt3xxn_set_clock - perform clock switching dance
788 * @hwif: hwif to switch
789 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
790 *
791 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
792 */
793
794static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
795{
796 unsigned long base = hwif->extra_base;
797 u8 scr2 = inb(base + 0x6b);
798
799 if ((scr2 & 0x7f) == mode)
800 return;
801
802 /* Tristate the bus */
803 outb(0x80, base + 0x63);
804 outb(0x80, base + 0x67);
805
806 /* Switch clock and reset channels */
807 outb(mode, base + 0x6b);
808 outb(0xc0, base + 0x69);
809
810 /*
811 * Reset the state machines.
812 * NOTE: avoid accidentally enabling the disabled channels.
813 */
814 outb(inb(base + 0x60) | 0x32, base + 0x60);
815 outb(inb(base + 0x64) | 0x32, base + 0x64);
816
817 /* Complete reset */
818 outb(0x00, base + 0x69);
819
820 /* Reconnect channels to bus */
821 outb(0x00, base + 0x63);
822 outb(0x00, base + 0x67);
823}
824
825/**
826 * hpt3xxn_rw_disk - prepare for I/O
827 * @drive: drive for command
828 * @rq: block request structure
829 *
830 * This is called when a disk I/O is issued to HPT3xxN.
831 * We need it because of the clock switching.
832 */
833
834static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
835{
836 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
837}
838
839/**
840 * hpt37x_calibrate_dpll - calibrate the DPLL
841 * @dev: PCI device
842 *
843 * Perform a calibration cycle on the DPLL.
844 * Returns 1 if this succeeds
845 */
846static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
847{
848 u32 dpll = (f_high << 16) | f_low | 0x100;
849 u8 scr2;
850 int i;
851
852 pci_write_config_dword(dev, 0x5c, dpll);
853
854 /* Wait for oscillator ready */
855 for(i = 0; i < 0x5000; ++i) {
856 udelay(50);
857 pci_read_config_byte(dev, 0x5b, &scr2);
858 if (scr2 & 0x80)
859 break;
860 }
861 /* See if it stays ready (we'll just bail out if it's not yet) */
862 for(i = 0; i < 0x1000; ++i) {
863 pci_read_config_byte(dev, 0x5b, &scr2);
864 /* DPLL destabilized? */
865 if(!(scr2 & 0x80))
866 return 0;
867 }
868 /* Turn off tuning, we have the DPLL set */
869 pci_read_config_dword (dev, 0x5c, &dpll);
870 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
871 return 1;
872}
873
874static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
875{
876 struct ide_host *host = pci_get_drvdata(dev);
877 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
878 u8 chip_type = info->chip_type;
879 u8 new_mcr, old_mcr = 0;
880
881 /*
882 * Disable the "fast interrupt" prediction. Don't hold off
883 * on interrupts. (== 0x01 despite what the docs say)
884 */
885 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
886
887 if (chip_type >= HPT374)
888 new_mcr = old_mcr & ~0x07;
889 else if (chip_type >= HPT370) {
890 new_mcr = old_mcr;
891 new_mcr &= ~0x02;
892#ifdef HPT_DELAY_INTERRUPT
893 new_mcr &= ~0x01;
894#else
895 new_mcr |= 0x01;
896#endif
897 } else /* HPT366 and HPT368 */
898 new_mcr = old_mcr & ~0x80;
899
900 if (new_mcr != old_mcr)
901 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
902}
903
904static int init_chipset_hpt366(struct pci_dev *dev)
905{
906 unsigned long io_base = pci_resource_start(dev, 4);
907 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
908 const char *name = DRV_NAME;
909 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
910 u8 chip_type;
911 enum ata_clock clock;
912
913 chip_type = info->chip_type;
914
915 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
916 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
917 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
918 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
919
920 /*
921 * First, try to estimate the PCI clock frequency...
922 */
923 if (chip_type >= HPT370) {
924 u8 scr1 = 0;
925 u16 f_cnt = 0;
926 u32 temp = 0;
927
928 /* Interrupt force enable. */
929 pci_read_config_byte(dev, 0x5a, &scr1);
930 if (scr1 & 0x10)
931 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
932
933 /*
934 * HighPoint does this for HPT372A.
935 * NOTE: This register is only writeable via I/O space.
936 */
937 if (chip_type == HPT372A)
938 outb(0x0e, io_base + 0x9c);
939
940 /*
941 * Default to PCI clock. Make sure MA15/16 are set to output
942 * to prevent drives having problems with 40-pin cables.
943 */
944 pci_write_config_byte(dev, 0x5b, 0x23);
945
946 /*
947 * We'll have to read f_CNT value in order to determine
948 * the PCI clock frequency according to the following ratio:
949 *
950 * f_CNT = Fpci * 192 / Fdpll
951 *
952 * First try reading the register in which the HighPoint BIOS
953 * saves f_CNT value before reprogramming the DPLL from its
954 * default setting (which differs for the various chips).
955 *
956 * NOTE: This register is only accessible via I/O space;
957 * HPT374 BIOS only saves it for the function 0, so we have to
958 * always read it from there -- no need to check the result of
959 * pci_get_slot() for the function 0 as the whole device has
960 * been already "pinned" (via function 1) in init_setup_hpt374()
961 */
962 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
963 struct pci_dev *dev1 = pci_get_slot(dev->bus,
964 dev->devfn - 1);
965 unsigned long io_base = pci_resource_start(dev1, 4);
966
967 temp = inl(io_base + 0x90);
968 pci_dev_put(dev1);
969 } else
970 temp = inl(io_base + 0x90);
971
972 /*
973 * In case the signature check fails, we'll have to
974 * resort to reading the f_CNT register itself in hopes
975 * that nobody has touched the DPLL yet...
976 */
977 if ((temp & 0xFFFFF000) != 0xABCDE000) {
978 int i;
979
980 printk(KERN_WARNING "%s %s: no clock data saved by "
981 "BIOS\n", name, pci_name(dev));
982
983 /* Calculate the average value of f_CNT. */
984 for (temp = i = 0; i < 128; i++) {
985 pci_read_config_word(dev, 0x78, &f_cnt);
986 temp += f_cnt & 0x1ff;
987 mdelay(1);
988 }
989 f_cnt = temp / 128;
990 } else
991 f_cnt = temp & 0x1ff;
992
993 dpll_clk = info->dpll_clk;
994 pci_clk = (f_cnt * dpll_clk) / 192;
995
996 /* Clamp PCI clock to bands. */
997 if (pci_clk < 40)
998 pci_clk = 33;
999 else if(pci_clk < 45)
1000 pci_clk = 40;
1001 else if(pci_clk < 55)
1002 pci_clk = 50;
1003 else
1004 pci_clk = 66;
1005
1006 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1007 "assuming %d MHz PCI\n", name, pci_name(dev),
1008 dpll_clk, f_cnt, pci_clk);
1009 } else {
1010 u32 itr1 = 0;
1011
1012 pci_read_config_dword(dev, 0x40, &itr1);
1013
1014 /* Detect PCI clock by looking at cmd_high_time. */
1015 switch((itr1 >> 8) & 0x07) {
1016 case 0x09:
1017 pci_clk = 40;
1018 break;
1019 case 0x05:
1020 pci_clk = 25;
1021 break;
1022 case 0x07:
1023 default:
1024 pci_clk = 33;
1025 break;
1026 }
1027 }
1028
1029 /* Let's assume we'll use PCI clock for the ATA clock... */
1030 switch (pci_clk) {
1031 case 25:
1032 clock = ATA_CLOCK_25MHZ;
1033 break;
1034 case 33:
1035 default:
1036 clock = ATA_CLOCK_33MHZ;
1037 break;
1038 case 40:
1039 clock = ATA_CLOCK_40MHZ;
1040 break;
1041 case 50:
1042 clock = ATA_CLOCK_50MHZ;
1043 break;
1044 case 66:
1045 clock = ATA_CLOCK_66MHZ;
1046 break;
1047 }
1048
1049 /*
1050 * Only try the DPLL if we don't have a table for the PCI clock that
1051 * we are running at for HPT370/A, always use it for anything newer...
1052 *
1053 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1054 * We also don't like using the DPLL because this causes glitches
1055 * on PRST-/SRST- when the state engine gets reset...
1056 */
1057 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1058 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1059 int adjust;
1060
1061 /*
1062 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1063 * supported/enabled, use 50 MHz DPLL clock otherwise...
1064 */
1065 if (info->udma_mask == ATA_UDMA6) {
1066 dpll_clk = 66;
1067 clock = ATA_CLOCK_66MHZ;
1068 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1069 dpll_clk = 50;
1070 clock = ATA_CLOCK_50MHZ;
1071 }
1072
1073 if (info->timings->clock_table[clock] == NULL) {
1074 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1075 name, pci_name(dev));
1076 return -EIO;
1077 }
1078
1079 /* Select the DPLL clock. */
1080 pci_write_config_byte(dev, 0x5b, 0x21);
1081
1082 /*
1083 * Adjust the DPLL based upon PCI clock, enable it,
1084 * and wait for stabilization...
1085 */
1086 f_low = (pci_clk * 48) / dpll_clk;
1087
1088 for (adjust = 0; adjust < 8; adjust++) {
1089 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1090 break;
1091
1092 /*
1093 * See if it'll settle at a fractionally different clock
1094 */
1095 if (adjust & 1)
1096 f_low -= adjust >> 1;
1097 else
1098 f_low += adjust >> 1;
1099 }
1100 if (adjust == 8) {
1101 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1102 name, pci_name(dev));
1103 return -EIO;
1104 }
1105
1106 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1107 name, pci_name(dev), dpll_clk);
1108 } else {
1109 /* Mark the fact that we're not using the DPLL. */
1110 dpll_clk = 0;
1111
1112 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1113 name, pci_name(dev), pci_clk);
1114 }
1115
1116 /* Store the clock frequencies. */
1117 info->dpll_clk = dpll_clk;
1118 info->pci_clk = pci_clk;
1119 info->clock = clock;
1120
1121 if (chip_type >= HPT370) {
1122 u8 mcr1, mcr4;
1123
1124 /*
1125 * Reset the state engines.
1126 * NOTE: Avoid accidentally enabling the disabled channels.
1127 */
1128 pci_read_config_byte (dev, 0x50, &mcr1);
1129 pci_read_config_byte (dev, 0x54, &mcr4);
1130 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1131 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1132 udelay(100);
1133 }
1134
1135 /*
1136 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1137 * the MISC. register to stretch the UltraDMA Tss timing.
1138 * NOTE: This register is only writeable via I/O space.
1139 */
1140 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1141 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1142
1143 hpt3xx_disable_fast_irq(dev, 0x50);
1144 hpt3xx_disable_fast_irq(dev, 0x54);
1145
1146 return 0;
1147}
1148
1149static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
1150{
1151 struct pci_dev *dev = to_pci_dev(hwif->dev);
1152 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1153 u8 chip_type = info->chip_type;
1154 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1155
1156 /*
1157 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1158 * address lines to access an external EEPROM. To read valid
1159 * cable detect state the pins must be enabled as inputs.
1160 */
1161 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1162 /*
1163 * HPT374 PCI function 1
1164 * - set bit 15 of reg 0x52 to enable TCBLID as input
1165 * - set bit 15 of reg 0x56 to enable FCBLID as input
1166 */
1167 u8 mcr_addr = hwif->select_data + 2;
1168 u16 mcr;
1169
1170 pci_read_config_word(dev, mcr_addr, &mcr);
1171 pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
1172 /* Debounce, then read cable ID register */
1173 udelay(10);
1174 pci_read_config_byte(dev, 0x5a, &scr1);
1175 pci_write_config_word(dev, mcr_addr, mcr);
1176 } else if (chip_type >= HPT370) {
1177 /*
1178 * HPT370/372 and 374 pcifn 0
1179 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1180 */
1181 u8 scr2 = 0;
1182
1183 pci_read_config_byte(dev, 0x5b, &scr2);
1184 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1185 /* Debounce, then read cable ID register */
1186 udelay(10);
1187 pci_read_config_byte(dev, 0x5a, &scr1);
1188 pci_write_config_byte(dev, 0x5b, scr2);
1189 } else
1190 pci_read_config_byte(dev, 0x5a, &scr1);
1191
1192 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1193}
1194
1195static void init_hwif_hpt366(ide_hwif_t *hwif)
1196{
1197 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1198 u8 chip_type = info->chip_type;
1199
1200 /* Cache the channel's MISC. control registers' offset */
1201 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1202
1203 /*
1204 * HPT3xxN chips have some complications:
1205 *
1206 * - on 33 MHz PCI we must clock switch
1207 * - on 66 MHz PCI we must NOT use the PCI clock
1208 */
1209 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1210 /*
1211 * Clock is shared between the channels,
1212 * so we'll have to serialize them... :-(
1213 */
1214 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
1215 hwif->rw_disk = &hpt3xxn_rw_disk;
1216 }
1217}
1218
1219static int init_dma_hpt366(ide_hwif_t *hwif,
1220 const struct ide_port_info *d)
1221{
1222 struct pci_dev *dev = to_pci_dev(hwif->dev);
1223 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1224 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
1225
1226 if (base == 0)
1227 return -1;
1228
1229 hwif->dma_base = base;
1230
1231 if (ide_pci_check_simplex(hwif, d) < 0)
1232 return -1;
1233
1234 if (ide_pci_set_master(dev, d->name) < 0)
1235 return -1;
1236
1237 dma_old = inb(base + 2);
1238
1239 local_irq_save(flags);
1240
1241 dma_new = dma_old;
1242 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1243 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1244
1245 if (masterdma & 0x30) dma_new |= 0x20;
1246 if ( slavedma & 0x30) dma_new |= 0x40;
1247 if (dma_new != dma_old)
1248 outb(dma_new, base + 2);
1249
1250 local_irq_restore(flags);
1251
1252 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1253 hwif->name, base, base + 7);
1254
1255 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1256
1257 if (ide_allocate_dma_engine(hwif))
1258 return -1;
1259
1260 return 0;
1261}
1262
1263static void hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1264{
1265 if (dev2->irq != dev->irq) {
1266 /* FIXME: we need a core pci_set_interrupt() */
1267 dev2->irq = dev->irq;
1268 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
1269 "fixed\n", pci_name(dev2));
1270 }
1271}
1272
1273static void hpt371_init(struct pci_dev *dev)
1274{
1275 u8 mcr1 = 0;
1276
1277 /*
1278 * HPT371 chips physically have only one channel, the secondary one,
1279 * but the primary channel registers do exist! Go figure...
1280 * So, we manually disable the non-existing channel here
1281 * (if the BIOS hasn't done this already).
1282 */
1283 pci_read_config_byte(dev, 0x50, &mcr1);
1284 if (mcr1 & 0x04)
1285 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1286}
1287
1288static int hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1289{
1290 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1291
1292 /*
1293 * Now we'll have to force both channels enabled if
1294 * at least one of them has been enabled by BIOS...
1295 */
1296 pci_read_config_byte(dev, 0x50, &mcr1);
1297 if (mcr1 & 0x30)
1298 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1299
1300 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1301 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1302
1303 if (pin1 != pin2 && dev->irq == dev2->irq) {
1304 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
1305 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
1306 return 1;
1307 }
1308
1309 return 0;
1310}
1311
1312#define IDE_HFLAGS_HPT3XX \
1313 (IDE_HFLAG_NO_ATAPI_DMA | \
1314 IDE_HFLAG_OFF_BOARD)
1315
1316static const struct ide_port_ops hpt3xx_port_ops = {
1317 .set_pio_mode = hpt3xx_set_pio_mode,
1318 .set_dma_mode = hpt3xx_set_mode,
1319 .maskproc = hpt3xx_maskproc,
1320 .mdma_filter = hpt3xx_mdma_filter,
1321 .udma_filter = hpt3xx_udma_filter,
1322 .cable_detect = hpt3xx_cable_detect,
1323};
1324
1325static const struct ide_dma_ops hpt37x_dma_ops = {
1326 .dma_host_set = ide_dma_host_set,
1327 .dma_setup = ide_dma_setup,
1328 .dma_start = ide_dma_start,
1329 .dma_end = hpt374_dma_end,
1330 .dma_test_irq = hpt374_dma_test_irq,
1331 .dma_lost_irq = ide_dma_lost_irq,
1332 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1333 .dma_sff_read_status = ide_dma_sff_read_status,
1334};
1335
1336static const struct ide_dma_ops hpt370_dma_ops = {
1337 .dma_host_set = ide_dma_host_set,
1338 .dma_setup = ide_dma_setup,
1339 .dma_start = hpt370_dma_start,
1340 .dma_end = hpt370_dma_end,
1341 .dma_test_irq = ide_dma_test_irq,
1342 .dma_lost_irq = ide_dma_lost_irq,
1343 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1344 .dma_clear = hpt370_irq_timeout,
1345 .dma_sff_read_status = ide_dma_sff_read_status,
1346};
1347
1348static const struct ide_dma_ops hpt36x_dma_ops = {
1349 .dma_host_set = ide_dma_host_set,
1350 .dma_setup = ide_dma_setup,
1351 .dma_start = ide_dma_start,
1352 .dma_end = ide_dma_end,
1353 .dma_test_irq = ide_dma_test_irq,
1354 .dma_lost_irq = hpt366_dma_lost_irq,
1355 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1356 .dma_sff_read_status = ide_dma_sff_read_status,
1357};
1358
1359static const struct ide_port_info hpt366_chipsets[] = {
1360 { /* 0: HPT36x */
1361 .name = DRV_NAME,
1362 .init_chipset = init_chipset_hpt366,
1363 .init_hwif = init_hwif_hpt366,
1364 .init_dma = init_dma_hpt366,
1365 /*
1366 * HPT36x chips have one channel per function and have
1367 * both channel enable bits located differently and visible
1368 * to both functions -- really stupid design decision... :-(
1369 * Bit 4 is for the primary channel, bit 5 for the secondary.
1370 */
1371 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1372 .port_ops = &hpt3xx_port_ops,
1373 .dma_ops = &hpt36x_dma_ops,
1374 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1375 .pio_mask = ATA_PIO4,
1376 .mwdma_mask = ATA_MWDMA2,
1377 },
1378 { /* 1: HPT3xx */
1379 .name = DRV_NAME,
1380 .init_chipset = init_chipset_hpt366,
1381 .init_hwif = init_hwif_hpt366,
1382 .init_dma = init_dma_hpt366,
1383 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1384 .port_ops = &hpt3xx_port_ops,
1385 .dma_ops = &hpt37x_dma_ops,
1386 .host_flags = IDE_HFLAGS_HPT3XX,
1387 .pio_mask = ATA_PIO4,
1388 .mwdma_mask = ATA_MWDMA2,
1389 }
1390};
1391
1392/**
1393 * hpt366_init_one - called when an HPT366 is found
1394 * @dev: the hpt366 device
1395 * @id: the matching pci id
1396 *
1397 * Called when the PCI registration layer (or the IDE initialization)
1398 * finds a device matching our IDE device tables.
1399 */
1400static int hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1401{
1402 const struct hpt_info *info = NULL;
1403 struct hpt_info *dyn_info;
1404 struct pci_dev *dev2 = NULL;
1405 struct ide_port_info d;
1406 u8 idx = id->driver_data;
1407 u8 rev = dev->revision;
1408 int ret;
1409
1410 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1411 return -ENODEV;
1412
1413 switch (idx) {
1414 case 0:
1415 if (rev < 3)
1416 info = &hpt36x;
1417 else {
1418 switch (min_t(u8, rev, 6)) {
1419 case 3: info = &hpt370; break;
1420 case 4: info = &hpt370a; break;
1421 case 5: info = &hpt372; break;
1422 case 6: info = &hpt372n; break;
1423 }
1424 idx++;
1425 }
1426 break;
1427 case 1:
1428 info = (rev > 1) ? &hpt372n : &hpt372a;
1429 break;
1430 case 2:
1431 info = (rev > 1) ? &hpt302n : &hpt302;
1432 break;
1433 case 3:
1434 hpt371_init(dev);
1435 info = (rev > 1) ? &hpt371n : &hpt371;
1436 break;
1437 case 4:
1438 info = &hpt374;
1439 break;
1440 case 5:
1441 info = &hpt372n;
1442 break;
1443 }
1444
1445 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
1446
1447 d = hpt366_chipsets[min_t(u8, idx, 1)];
1448
1449 d.udma_mask = info->udma_mask;
1450
1451 /* fixup ->dma_ops for HPT370/HPT370A */
1452 if (info == &hpt370 || info == &hpt370a)
1453 d.dma_ops = &hpt370_dma_ops;
1454
1455 if (info == &hpt36x || info == &hpt374)
1456 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1457
1458 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1459 if (dyn_info == NULL) {
1460 printk(KERN_ERR "%s %s: out of memory!\n",
1461 d.name, pci_name(dev));
1462 pci_dev_put(dev2);
1463 return -ENOMEM;
1464 }
1465
1466 /*
1467 * Copy everything from a static "template" structure
1468 * to just allocated per-chip hpt_info structure.
1469 */
1470 memcpy(dyn_info, info, sizeof(*dyn_info));
1471
1472 if (dev2) {
1473 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
1474
1475 if (info == &hpt374)
1476 hpt374_init(dev, dev2);
1477 else {
1478 if (hpt36x_init(dev, dev2))
1479 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
1480 }
1481
1482 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1483 if (ret < 0) {
1484 pci_dev_put(dev2);
1485 kfree(dyn_info);
1486 }
1487 return ret;
1488 }
1489
1490 ret = ide_pci_init_one(dev, &d, dyn_info);
1491 if (ret < 0)
1492 kfree(dyn_info);
1493
1494 return ret;
1495}
1496
1497static void hpt366_remove(struct pci_dev *dev)
1498{
1499 struct ide_host *host = pci_get_drvdata(dev);
1500 struct ide_info *info = host->host_priv;
1501 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1502
1503 ide_pci_remove(dev);
1504 pci_dev_put(dev2);
1505 kfree(info);
1506}
1507
1508static const struct pci_device_id hpt366_pci_tbl[] = {
1509 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1510 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1511 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1512 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1513 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1514 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1515 { 0, },
1516};
1517MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1518
1519static struct pci_driver hpt366_pci_driver = {
1520 .name = "HPT366_IDE",
1521 .id_table = hpt366_pci_tbl,
1522 .probe = hpt366_init_one,
1523 .remove = hpt366_remove,
1524 .suspend = ide_pci_suspend,
1525 .resume = ide_pci_resume,
1526};
1527
1528static int __init hpt366_ide_init(void)
1529{
1530 return ide_pci_register_driver(&hpt366_pci_driver);
1531}
1532
1533static void __exit hpt366_ide_exit(void)
1534{
1535 pci_unregister_driver(&hpt366_pci_driver);
1536}
1537
1538module_init(hpt366_ide_init);
1539module_exit(hpt366_ide_exit);
1540
1541MODULE_AUTHOR("Andre Hedrick");
1542MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1543MODULE_LICENSE("GPL");