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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight Trace Port Interface Unit driver
6 */
7
8#include <linux/atomic.h>
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/device.h>
12#include <linux/io.h>
13#include <linux/err.h>
14#include <linux/slab.h>
15#include <linux/pm_runtime.h>
16#include <linux/coresight.h>
17#include <linux/amba/bus.h>
18#include <linux/clk.h>
19
20#include "coresight-priv.h"
21
22#define TPIU_SUPP_PORTSZ 0x000
23#define TPIU_CURR_PORTSZ 0x004
24#define TPIU_SUPP_TRIGMODES 0x100
25#define TPIU_TRIG_CNTRVAL 0x104
26#define TPIU_TRIG_MULT 0x108
27#define TPIU_SUPP_TESTPATM 0x200
28#define TPIU_CURR_TESTPATM 0x204
29#define TPIU_TEST_PATREPCNTR 0x208
30#define TPIU_FFSR 0x300
31#define TPIU_FFCR 0x304
32#define TPIU_FSYNC_CNTR 0x308
33#define TPIU_EXTCTL_INPORT 0x400
34#define TPIU_EXTCTL_OUTPORT 0x404
35#define TPIU_ITTRFLINACK 0xee4
36#define TPIU_ITTRFLIN 0xee8
37#define TPIU_ITATBDATA0 0xeec
38#define TPIU_ITATBCTR2 0xef0
39#define TPIU_ITATBCTR1 0xef4
40#define TPIU_ITATBCTR0 0xef8
41
42/** register definition **/
43/* FFSR - 0x300 */
44#define FFSR_FT_STOPPED_BIT 1
45/* FFCR - 0x304 */
46#define FFCR_FON_MAN_BIT 6
47#define FFCR_FON_MAN BIT(6)
48#define FFCR_STOP_FI BIT(12)
49
50DEFINE_CORESIGHT_DEVLIST(tpiu_devs, "tpiu");
51
52/*
53 * @base: memory mapped base address for this component.
54 * @atclk: optional clock for the core parts of the TPIU.
55 * @csdev: component vitals needed by the framework.
56 */
57struct tpiu_drvdata {
58 void __iomem *base;
59 struct clk *atclk;
60 struct coresight_device *csdev;
61};
62
63static void tpiu_enable_hw(struct csdev_access *csa)
64{
65 CS_UNLOCK(csa->base);
66
67 /* TODO: fill this up */
68
69 CS_LOCK(csa->base);
70}
71
72static int tpiu_enable(struct coresight_device *csdev, enum cs_mode mode,
73 void *__unused)
74{
75 tpiu_enable_hw(&csdev->access);
76 atomic_inc(&csdev->refcnt);
77 dev_dbg(&csdev->dev, "TPIU enabled\n");
78 return 0;
79}
80
81static void tpiu_disable_hw(struct csdev_access *csa)
82{
83 CS_UNLOCK(csa->base);
84
85 /* Clear formatter and stop on flush */
86 csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR);
87 /* Generate manual flush */
88 csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR);
89 /* Wait for flush to complete */
90 coresight_timeout(csa, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
91 /* Wait for formatter to stop */
92 coresight_timeout(csa, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
93
94 CS_LOCK(csa->base);
95}
96
97static int tpiu_disable(struct coresight_device *csdev)
98{
99 if (atomic_dec_return(&csdev->refcnt))
100 return -EBUSY;
101
102 tpiu_disable_hw(&csdev->access);
103
104 dev_dbg(&csdev->dev, "TPIU disabled\n");
105 return 0;
106}
107
108static const struct coresight_ops_sink tpiu_sink_ops = {
109 .enable = tpiu_enable,
110 .disable = tpiu_disable,
111};
112
113static const struct coresight_ops tpiu_cs_ops = {
114 .sink_ops = &tpiu_sink_ops,
115};
116
117static int tpiu_probe(struct amba_device *adev, const struct amba_id *id)
118{
119 int ret;
120 void __iomem *base;
121 struct device *dev = &adev->dev;
122 struct coresight_platform_data *pdata = NULL;
123 struct tpiu_drvdata *drvdata;
124 struct resource *res = &adev->res;
125 struct coresight_desc desc = { 0 };
126
127 desc.name = coresight_alloc_device_name(&tpiu_devs, dev);
128 if (!desc.name)
129 return -ENOMEM;
130
131 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
132 if (!drvdata)
133 return -ENOMEM;
134
135 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
136 if (!IS_ERR(drvdata->atclk)) {
137 ret = clk_prepare_enable(drvdata->atclk);
138 if (ret)
139 return ret;
140 }
141 dev_set_drvdata(dev, drvdata);
142
143 /* Validity for the resource is already checked by the AMBA core */
144 base = devm_ioremap_resource(dev, res);
145 if (IS_ERR(base))
146 return PTR_ERR(base);
147
148 drvdata->base = base;
149 desc.access = CSDEV_ACCESS_IOMEM(base);
150
151 /* Disable tpiu to support older devices */
152 tpiu_disable_hw(&desc.access);
153
154 pdata = coresight_get_platform_data(dev);
155 if (IS_ERR(pdata))
156 return PTR_ERR(pdata);
157 dev->platform_data = pdata;
158
159 desc.type = CORESIGHT_DEV_TYPE_SINK;
160 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT;
161 desc.ops = &tpiu_cs_ops;
162 desc.pdata = pdata;
163 desc.dev = dev;
164 drvdata->csdev = coresight_register(&desc);
165
166 if (!IS_ERR(drvdata->csdev)) {
167 pm_runtime_put(&adev->dev);
168 return 0;
169 }
170
171 return PTR_ERR(drvdata->csdev);
172}
173
174static void tpiu_remove(struct amba_device *adev)
175{
176 struct tpiu_drvdata *drvdata = dev_get_drvdata(&adev->dev);
177
178 coresight_unregister(drvdata->csdev);
179}
180
181#ifdef CONFIG_PM
182static int tpiu_runtime_suspend(struct device *dev)
183{
184 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
185
186 if (drvdata && !IS_ERR(drvdata->atclk))
187 clk_disable_unprepare(drvdata->atclk);
188
189 return 0;
190}
191
192static int tpiu_runtime_resume(struct device *dev)
193{
194 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
195
196 if (drvdata && !IS_ERR(drvdata->atclk))
197 clk_prepare_enable(drvdata->atclk);
198
199 return 0;
200}
201#endif
202
203static const struct dev_pm_ops tpiu_dev_pm_ops = {
204 SET_RUNTIME_PM_OPS(tpiu_runtime_suspend, tpiu_runtime_resume, NULL)
205};
206
207static const struct amba_id tpiu_ids[] = {
208 {
209 .id = 0x000bb912,
210 .mask = 0x000fffff,
211 },
212 {
213 .id = 0x0004b912,
214 .mask = 0x0007ffff,
215 },
216 {
217 /* Coresight SoC-600 */
218 .id = 0x000bb9e7,
219 .mask = 0x000fffff,
220 },
221 { 0, 0},
222};
223
224MODULE_DEVICE_TABLE(amba, tpiu_ids);
225
226static struct amba_driver tpiu_driver = {
227 .drv = {
228 .name = "coresight-tpiu",
229 .owner = THIS_MODULE,
230 .pm = &tpiu_dev_pm_ops,
231 .suppress_bind_attrs = true,
232 },
233 .probe = tpiu_probe,
234 .remove = tpiu_remove,
235 .id_table = tpiu_ids,
236};
237
238module_amba_driver(tpiu_driver);
239
240MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
241MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
242MODULE_DESCRIPTION("Arm CoreSight TPIU (Trace Port Interface Unit) driver");
243MODULE_LICENSE("GPL v2");
1/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
2 *
3 * Description: CoreSight Trace Port Interface Unit driver
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/device.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/slab.h>
21#include <linux/pm_runtime.h>
22#include <linux/coresight.h>
23#include <linux/amba/bus.h>
24#include <linux/clk.h>
25
26#include "coresight-priv.h"
27
28#define TPIU_SUPP_PORTSZ 0x000
29#define TPIU_CURR_PORTSZ 0x004
30#define TPIU_SUPP_TRIGMODES 0x100
31#define TPIU_TRIG_CNTRVAL 0x104
32#define TPIU_TRIG_MULT 0x108
33#define TPIU_SUPP_TESTPATM 0x200
34#define TPIU_CURR_TESTPATM 0x204
35#define TPIU_TEST_PATREPCNTR 0x208
36#define TPIU_FFSR 0x300
37#define TPIU_FFCR 0x304
38#define TPIU_FSYNC_CNTR 0x308
39#define TPIU_EXTCTL_INPORT 0x400
40#define TPIU_EXTCTL_OUTPORT 0x404
41#define TPIU_ITTRFLINACK 0xee4
42#define TPIU_ITTRFLIN 0xee8
43#define TPIU_ITATBDATA0 0xeec
44#define TPIU_ITATBCTR2 0xef0
45#define TPIU_ITATBCTR1 0xef4
46#define TPIU_ITATBCTR0 0xef8
47
48/** register definition **/
49/* FFCR - 0x304 */
50#define FFCR_FON_MAN BIT(6)
51
52/**
53 * @base: memory mapped base address for this component.
54 * @dev: the device entity associated to this component.
55 * @atclk: optional clock for the core parts of the TPIU.
56 * @csdev: component vitals needed by the framework.
57 */
58struct tpiu_drvdata {
59 void __iomem *base;
60 struct device *dev;
61 struct clk *atclk;
62 struct coresight_device *csdev;
63};
64
65static void tpiu_enable_hw(struct tpiu_drvdata *drvdata)
66{
67 CS_UNLOCK(drvdata->base);
68
69 /* TODO: fill this up */
70
71 CS_LOCK(drvdata->base);
72}
73
74static int tpiu_enable(struct coresight_device *csdev, u32 mode)
75{
76 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
77
78 tpiu_enable_hw(drvdata);
79
80 dev_info(drvdata->dev, "TPIU enabled\n");
81 return 0;
82}
83
84static void tpiu_disable_hw(struct tpiu_drvdata *drvdata)
85{
86 CS_UNLOCK(drvdata->base);
87
88 /* Clear formatter controle reg. */
89 writel_relaxed(0x0, drvdata->base + TPIU_FFCR);
90 /* Generate manual flush */
91 writel_relaxed(FFCR_FON_MAN, drvdata->base + TPIU_FFCR);
92
93 CS_LOCK(drvdata->base);
94}
95
96static void tpiu_disable(struct coresight_device *csdev)
97{
98 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
99
100 tpiu_disable_hw(drvdata);
101
102 dev_info(drvdata->dev, "TPIU disabled\n");
103}
104
105static const struct coresight_ops_sink tpiu_sink_ops = {
106 .enable = tpiu_enable,
107 .disable = tpiu_disable,
108};
109
110static const struct coresight_ops tpiu_cs_ops = {
111 .sink_ops = &tpiu_sink_ops,
112};
113
114static int tpiu_probe(struct amba_device *adev, const struct amba_id *id)
115{
116 int ret;
117 void __iomem *base;
118 struct device *dev = &adev->dev;
119 struct coresight_platform_data *pdata = NULL;
120 struct tpiu_drvdata *drvdata;
121 struct resource *res = &adev->res;
122 struct coresight_desc *desc;
123 struct device_node *np = adev->dev.of_node;
124
125 if (np) {
126 pdata = of_get_coresight_platform_data(dev, np);
127 if (IS_ERR(pdata))
128 return PTR_ERR(pdata);
129 adev->dev.platform_data = pdata;
130 }
131
132 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
133 if (!drvdata)
134 return -ENOMEM;
135
136 drvdata->dev = &adev->dev;
137 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
138 if (!IS_ERR(drvdata->atclk)) {
139 ret = clk_prepare_enable(drvdata->atclk);
140 if (ret)
141 return ret;
142 }
143 dev_set_drvdata(dev, drvdata);
144
145 /* Validity for the resource is already checked by the AMBA core */
146 base = devm_ioremap_resource(dev, res);
147 if (IS_ERR(base))
148 return PTR_ERR(base);
149
150 drvdata->base = base;
151
152 /* Disable tpiu to support older devices */
153 tpiu_disable_hw(drvdata);
154
155 pm_runtime_put(&adev->dev);
156
157 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
158 if (!desc)
159 return -ENOMEM;
160
161 desc->type = CORESIGHT_DEV_TYPE_SINK;
162 desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT;
163 desc->ops = &tpiu_cs_ops;
164 desc->pdata = pdata;
165 desc->dev = dev;
166 drvdata->csdev = coresight_register(desc);
167 if (IS_ERR(drvdata->csdev))
168 return PTR_ERR(drvdata->csdev);
169
170 dev_info(dev, "TPIU initialized\n");
171 return 0;
172}
173
174#ifdef CONFIG_PM
175static int tpiu_runtime_suspend(struct device *dev)
176{
177 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
178
179 if (drvdata && !IS_ERR(drvdata->atclk))
180 clk_disable_unprepare(drvdata->atclk);
181
182 return 0;
183}
184
185static int tpiu_runtime_resume(struct device *dev)
186{
187 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
188
189 if (drvdata && !IS_ERR(drvdata->atclk))
190 clk_prepare_enable(drvdata->atclk);
191
192 return 0;
193}
194#endif
195
196static const struct dev_pm_ops tpiu_dev_pm_ops = {
197 SET_RUNTIME_PM_OPS(tpiu_runtime_suspend, tpiu_runtime_resume, NULL)
198};
199
200static struct amba_id tpiu_ids[] = {
201 {
202 .id = 0x0003b912,
203 .mask = 0x0003ffff,
204 },
205 {
206 .id = 0x0004b912,
207 .mask = 0x0007ffff,
208 },
209 { 0, 0},
210};
211
212static struct amba_driver tpiu_driver = {
213 .drv = {
214 .name = "coresight-tpiu",
215 .owner = THIS_MODULE,
216 .pm = &tpiu_dev_pm_ops,
217 .suppress_bind_attrs = true,
218 },
219 .probe = tpiu_probe,
220 .id_table = tpiu_ids,
221};
222builtin_amba_driver(tpiu_driver);