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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022 Intel Corporation
4 */
5
6#ifndef _XE_GUC_FWIF_H
7#define _XE_GUC_FWIF_H
8
9#include <linux/bits.h>
10
11#include "abi/guc_klvs_abi.h"
12
13#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 4
14#define G2H_LEN_DW_DEREGISTER_CONTEXT 3
15#define G2H_LEN_DW_TLB_INVALIDATE 3
16
17#define GUC_CONTEXT_DISABLE 0
18#define GUC_CONTEXT_ENABLE 1
19
20#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
21#define GUC_CLIENT_PRIORITY_HIGH 1
22#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
23#define GUC_CLIENT_PRIORITY_NORMAL 3
24#define GUC_CLIENT_PRIORITY_NUM 4
25
26#define GUC_RENDER_ENGINE 0
27#define GUC_VIDEO_ENGINE 1
28#define GUC_BLITTER_ENGINE 2
29#define GUC_VIDEOENHANCE_ENGINE 3
30#define GUC_VIDEO_ENGINE2 4
31#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
32
33#define GUC_RENDER_CLASS 0
34#define GUC_VIDEO_CLASS 1
35#define GUC_VIDEOENHANCE_CLASS 2
36#define GUC_BLITTER_CLASS 3
37#define GUC_COMPUTE_CLASS 4
38#define GUC_GSC_OTHER_CLASS 5
39#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
40#define GUC_MAX_ENGINE_CLASSES 16
41#define GUC_MAX_INSTANCES_PER_CLASS 32
42
43/* Helper for context registration H2G */
44struct guc_ctxt_registration_info {
45 u32 flags;
46 u32 context_idx;
47 u32 engine_class;
48 u32 engine_submit_mask;
49 u32 wq_desc_lo;
50 u32 wq_desc_hi;
51 u32 wq_base_lo;
52 u32 wq_base_hi;
53 u32 wq_size;
54 u32 hwlrca_lo;
55 u32 hwlrca_hi;
56};
57#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
58
59/* 32-bit KLV structure as used by policy updates and others */
60struct guc_klv_generic_dw_t {
61 u32 kl;
62 u32 value;
63} __packed;
64
65/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
66struct guc_update_exec_queue_policy_header {
67 u32 action;
68 u32 guc_id;
69} __packed;
70
71struct guc_update_exec_queue_policy {
72 struct guc_update_exec_queue_policy_header header;
73 struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
74} __packed;
75
76/* GUC_CTL_* - Parameters for loading the GuC */
77#define GUC_CTL_LOG_PARAMS 0
78#define GUC_LOG_VALID BIT(0)
79#define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1)
80#define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2)
81#define GUC_LOG_LOG_ALLOC_UNITS BIT(3)
82#define GUC_LOG_CRASH_SHIFT 4
83#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
84#define GUC_LOG_DEBUG_SHIFT 6
85#define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT)
86#define GUC_LOG_CAPTURE_SHIFT 10
87#define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT)
88#define GUC_LOG_BUF_ADDR_SHIFT 12
89
90#define GUC_CTL_WA 1
91#define GUC_WA_GAM_CREDITS BIT(10)
92#define GUC_WA_DUAL_QUEUE BIT(11)
93#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
94#define GUC_WA_CONTEXT_ISOLATION BIT(15)
95#define GUC_WA_PRE_PARSER BIT(14)
96#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
97#define GUC_WA_POLLCS BIT(18)
98#define GUC_WA_RENDER_RST_RC6_EXIT BIT(19)
99#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
100
101#define GUC_CTL_FEATURE 2
102#define GUC_CTL_ENABLE_SLPC BIT(2)
103#define GUC_CTL_DISABLE_SCHEDULER BIT(14)
104
105#define GUC_CTL_DEBUG 3
106#define GUC_LOG_VERBOSITY_SHIFT 0
107#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
108#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
109#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
110#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
111#define GUC_LOG_VERBOSITY_MIN 0
112#define GUC_LOG_VERBOSITY_MAX 3
113#define GUC_LOG_VERBOSITY_MASK 0x0000000f
114#define GUC_LOG_DESTINATION_MASK (3 << 4)
115#define GUC_LOG_DISABLED (1 << 6)
116#define GUC_PROFILE_ENABLED (1 << 7)
117
118#define GUC_CTL_ADS 4
119#define GUC_ADS_ADDR_SHIFT 1
120#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
121
122#define GUC_CTL_DEVID 5
123
124#define GUC_CTL_MAX_DWORDS 14
125
126/* Scheduling policy settings */
127
128#define GLOBAL_POLICY_MAX_NUM_WI 15
129
130/* Don't reset an engine upon preemption failure */
131#define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
132
133#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
134
135struct guc_policies {
136 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
137 /*
138 * In micro seconds. How much time to allow before DPC processing is
139 * called back via interrupt (to prevent DPC queue drain starving).
140 * Typically 1000s of micro seconds (example only, not granularity).
141 */
142 u32 dpc_promote_time;
143
144 /* Must be set to take these new values. */
145 u32 is_valid;
146
147 /*
148 * Max number of WIs to process per call. A large value may keep CS
149 * idle.
150 */
151 u32 max_num_work_items;
152
153 u32 global_flags;
154 u32 reserved[4];
155} __packed;
156
157/* GuC MMIO reg state struct */
158struct guc_mmio_reg {
159 u32 offset;
160 u32 value;
161 u32 flags;
162 u32 mask;
163#define GUC_REGSET_MASKED BIT(0)
164#define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
165#define GUC_REGSET_RESTORE_ONLY BIT(3)
166} __packed;
167
168/* GuC register sets */
169struct guc_mmio_reg_set {
170 u32 address;
171 u16 count;
172 u16 reserved;
173} __packed;
174
175/* Generic GT SysInfo data types */
176#define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0
177#define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1
178#define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2
179#define GUC_GENERIC_GT_SYSINFO_MAX 16
180
181/* HW info */
182struct guc_gt_system_info {
183 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
184 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
185 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
186} __packed;
187
188enum {
189 GUC_CAPTURE_LIST_INDEX_PF = 0,
190 GUC_CAPTURE_LIST_INDEX_VF = 1,
191 GUC_CAPTURE_LIST_INDEX_MAX = 2,
192};
193
194/* GuC Additional Data Struct */
195struct guc_ads {
196 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
197 u32 reserved0;
198 u32 scheduler_policies;
199 u32 gt_system_info;
200 u32 reserved1;
201 u32 control_data;
202 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
203 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
204 u32 private_data;
205 u32 um_init_data;
206 u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
207 u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
208 u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
209 u32 reserved[14];
210} __packed;
211
212/* Engine usage stats */
213struct guc_engine_usage_record {
214 u32 current_context_index;
215 u32 last_switch_in_stamp;
216 u32 reserved0;
217 u32 total_runtime;
218 u32 reserved1[4];
219} __packed;
220
221struct guc_engine_usage {
222 struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
223} __packed;
224
225/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
226enum xe_guc_recv_message {
227 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
228 XE_GUC_RECV_MSG_EXCEPTION = BIT(30),
229};
230
231/* Page fault structures */
232struct access_counter_desc {
233 u32 dw0;
234#define ACCESS_COUNTER_TYPE BIT(0)
235#define ACCESS_COUNTER_SUBG_LO GENMASK(31, 1)
236
237 u32 dw1;
238#define ACCESS_COUNTER_SUBG_HI BIT(0)
239#define ACCESS_COUNTER_RSVD0 GENMASK(2, 1)
240#define ACCESS_COUNTER_ENG_INSTANCE GENMASK(8, 3)
241#define ACCESS_COUNTER_ENG_CLASS GENMASK(11, 9)
242#define ACCESS_COUNTER_ASID GENMASK(31, 12)
243
244 u32 dw2;
245#define ACCESS_COUNTER_VFID GENMASK(5, 0)
246#define ACCESS_COUNTER_RSVD1 GENMASK(7, 6)
247#define ACCESS_COUNTER_GRANULARITY GENMASK(10, 8)
248#define ACCESS_COUNTER_RSVD2 GENMASK(16, 11)
249#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)
250
251 u32 dw3;
252#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)
253} __packed;
254
255enum guc_um_queue_type {
256 GUC_UM_HW_QUEUE_PAGE_FAULT = 0,
257 GUC_UM_HW_QUEUE_PAGE_FAULT_RESPONSE,
258 GUC_UM_HW_QUEUE_ACCESS_COUNTER,
259 GUC_UM_HW_QUEUE_MAX
260};
261
262struct guc_um_queue_params {
263 u64 base_dpa;
264 u32 base_ggtt_address;
265 u32 size_in_bytes;
266 u32 rsvd[4];
267} __packed;
268
269struct guc_um_init_params {
270 u64 page_response_timeout_in_us;
271 u32 rsvd[6];
272 struct guc_um_queue_params queue_params[GUC_UM_HW_QUEUE_MAX];
273} __packed;
274
275enum xe_guc_fault_reply_type {
276 PFR_ACCESS = 0,
277 PFR_ENGINE,
278 PFR_VFID,
279 PFR_ALL,
280 PFR_INVALID
281};
282
283enum xe_guc_response_desc_type {
284 TLB_INVALIDATION_DESC = 0,
285 FAULT_RESPONSE_DESC
286};
287
288struct xe_guc_pagefault_desc {
289 u32 dw0;
290#define PFD_FAULT_LEVEL GENMASK(2, 0)
291#define PFD_SRC_ID GENMASK(10, 3)
292#define PFD_RSVD_0 GENMASK(17, 11)
293#define XE2_PFD_TRVA_FAULT BIT(18)
294#define PFD_ENG_INSTANCE GENMASK(24, 19)
295#define PFD_ENG_CLASS GENMASK(27, 25)
296#define PFD_PDATA_LO GENMASK(31, 28)
297
298 u32 dw1;
299#define PFD_PDATA_HI GENMASK(11, 0)
300#define PFD_PDATA_HI_SHIFT 4
301#define PFD_ASID GENMASK(31, 12)
302
303 u32 dw2;
304#define PFD_ACCESS_TYPE GENMASK(1, 0)
305#define PFD_FAULT_TYPE GENMASK(3, 2)
306#define PFD_VFID GENMASK(9, 4)
307#define PFD_RSVD_1 GENMASK(11, 10)
308#define PFD_VIRTUAL_ADDR_LO GENMASK(31, 12)
309#define PFD_VIRTUAL_ADDR_LO_SHIFT 12
310
311 u32 dw3;
312#define PFD_VIRTUAL_ADDR_HI GENMASK(31, 0)
313#define PFD_VIRTUAL_ADDR_HI_SHIFT 32
314} __packed;
315
316struct xe_guc_pagefault_reply {
317 u32 dw0;
318#define PFR_VALID BIT(0)
319#define PFR_SUCCESS BIT(1)
320#define PFR_REPLY GENMASK(4, 2)
321#define PFR_RSVD_0 GENMASK(9, 5)
322#define PFR_DESC_TYPE GENMASK(11, 10)
323#define PFR_ASID GENMASK(31, 12)
324
325 u32 dw1;
326#define PFR_VFID GENMASK(5, 0)
327#define PFR_RSVD_1 BIT(6)
328#define PFR_ENG_INSTANCE GENMASK(12, 7)
329#define PFR_ENG_CLASS GENMASK(15, 13)
330#define PFR_PDATA GENMASK(31, 16)
331
332 u32 dw2;
333#define PFR_RSVD_2 GENMASK(31, 0)
334} __packed;
335
336struct xe_guc_acc_desc {
337 u32 dw0;
338#define ACC_TYPE BIT(0)
339#define ACC_TRIGGER 0
340#define ACC_NOTIFY 1
341#define ACC_SUBG_LO GENMASK(31, 1)
342
343 u32 dw1;
344#define ACC_SUBG_HI BIT(0)
345#define ACC_RSVD0 GENMASK(2, 1)
346#define ACC_ENG_INSTANCE GENMASK(8, 3)
347#define ACC_ENG_CLASS GENMASK(11, 9)
348#define ACC_ASID GENMASK(31, 12)
349
350 u32 dw2;
351#define ACC_VFID GENMASK(5, 0)
352#define ACC_RSVD1 GENMASK(7, 6)
353#define ACC_GRANULARITY GENMASK(10, 8)
354#define ACC_RSVD2 GENMASK(16, 11)
355#define ACC_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)
356
357 u32 dw3;
358#define ACC_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)
359} __packed;
360
361#endif