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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nouveau_drv.h"
25#include "nouveau_dma.h"
26#include "nouveau_fence.h"
27#include "nouveau_vmm.h"
28
29#include "nv50_display.h"
30
31#include <nvif/push206e.h>
32
33#include <nvhw/class/cl826f.h>
34
35static int
36nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
37{
38 struct nvif_push *push = chan->chan.push;
39 int ret = PUSH_WAIT(push, 8);
40 if (ret == 0) {
41 PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
42
43 PUSH_MTHD(push, NV826F, SEMAPHOREA,
44 NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
45
46 SEMAPHOREB, lower_32_bits(virtual),
47 SEMAPHOREC, sequence,
48
49 SEMAPHORED,
50 NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE),
51
52 NON_STALLED_INTERRUPT, 0);
53 PUSH_KICK(push);
54 }
55 return ret;
56}
57
58static int
59nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
60{
61 struct nvif_push *push = chan->chan.push;
62 int ret = PUSH_WAIT(push, 7);
63 if (ret == 0) {
64 PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle);
65
66 PUSH_MTHD(push, NV826F, SEMAPHOREA,
67 NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)),
68
69 SEMAPHOREB, lower_32_bits(virtual),
70 SEMAPHOREC, sequence,
71
72 SEMAPHORED,
73 NVDEF(NV826F, SEMAPHORED, OPERATION, ACQ_GEQ));
74 PUSH_KICK(push);
75 }
76 return ret;
77}
78
79static inline u32
80nv84_fence_chid(struct nouveau_channel *chan)
81{
82 return chan->drm->runl[chan->runlist].chan_id_base + chan->chid;
83}
84
85static int
86nv84_fence_emit(struct nouveau_fence *fence)
87{
88 struct nouveau_channel *chan = fence->channel;
89 struct nv84_fence_chan *fctx = chan->fence;
90 u64 addr = fctx->vma->addr + nv84_fence_chid(chan) * 16;
91
92 return fctx->base.emit32(chan, addr, fence->base.seqno);
93}
94
95static int
96nv84_fence_sync(struct nouveau_fence *fence,
97 struct nouveau_channel *prev, struct nouveau_channel *chan)
98{
99 struct nv84_fence_chan *fctx = chan->fence;
100 u64 addr = fctx->vma->addr + nv84_fence_chid(prev) * 16;
101
102 return fctx->base.sync32(chan, addr, fence->base.seqno);
103}
104
105static u32
106nv84_fence_read(struct nouveau_channel *chan)
107{
108 struct nv84_fence_priv *priv = chan->drm->fence;
109 return nouveau_bo_rd32(priv->bo, nv84_fence_chid(chan) * 16/4);
110}
111
112static void
113nv84_fence_context_del(struct nouveau_channel *chan)
114{
115 struct nv84_fence_priv *priv = chan->drm->fence;
116 struct nv84_fence_chan *fctx = chan->fence;
117
118 nouveau_bo_wr32(priv->bo, nv84_fence_chid(chan) * 16 / 4, fctx->base.sequence);
119 mutex_lock(&priv->mutex);
120 nouveau_vma_del(&fctx->vma);
121 mutex_unlock(&priv->mutex);
122 nouveau_fence_context_del(&fctx->base);
123 chan->fence = NULL;
124 nouveau_fence_context_free(&fctx->base);
125}
126
127int
128nv84_fence_context_new(struct nouveau_channel *chan)
129{
130 struct nv84_fence_priv *priv = chan->drm->fence;
131 struct nv84_fence_chan *fctx;
132 int ret;
133
134 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
135 if (!fctx)
136 return -ENOMEM;
137
138 nouveau_fence_context_new(chan, &fctx->base);
139 fctx->base.emit = nv84_fence_emit;
140 fctx->base.sync = nv84_fence_sync;
141 fctx->base.read = nv84_fence_read;
142 fctx->base.emit32 = nv84_fence_emit32;
143 fctx->base.sync32 = nv84_fence_sync32;
144 fctx->base.sequence = nv84_fence_read(chan);
145
146 mutex_lock(&priv->mutex);
147 ret = nouveau_vma_new(priv->bo, chan->vmm, &fctx->vma);
148 mutex_unlock(&priv->mutex);
149
150 if (ret)
151 nv84_fence_context_del(chan);
152 return ret;
153}
154
155static bool
156nv84_fence_suspend(struct nouveau_drm *drm)
157{
158 struct nv84_fence_priv *priv = drm->fence;
159 int i;
160
161 priv->suspend = vmalloc(array_size(sizeof(u32), drm->chan_total));
162 if (priv->suspend) {
163 for (i = 0; i < drm->chan_total; i++)
164 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
165 }
166
167 return priv->suspend != NULL;
168}
169
170static void
171nv84_fence_resume(struct nouveau_drm *drm)
172{
173 struct nv84_fence_priv *priv = drm->fence;
174 int i;
175
176 if (priv->suspend) {
177 for (i = 0; i < drm->chan_total; i++)
178 nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
179 vfree(priv->suspend);
180 priv->suspend = NULL;
181 }
182}
183
184static void
185nv84_fence_destroy(struct nouveau_drm *drm)
186{
187 struct nv84_fence_priv *priv = drm->fence;
188 nouveau_bo_unmap(priv->bo);
189 if (priv->bo)
190 nouveau_bo_unpin(priv->bo);
191 nouveau_bo_ref(NULL, &priv->bo);
192 drm->fence = NULL;
193 kfree(priv);
194}
195
196int
197nv84_fence_create(struct nouveau_drm *drm)
198{
199 struct nv84_fence_priv *priv;
200 u32 domain;
201 int ret;
202
203 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
204 if (!priv)
205 return -ENOMEM;
206
207 priv->base.dtor = nv84_fence_destroy;
208 priv->base.suspend = nv84_fence_suspend;
209 priv->base.resume = nv84_fence_resume;
210 priv->base.context_new = nv84_fence_context_new;
211 priv->base.context_del = nv84_fence_context_del;
212
213 priv->base.uevent = true;
214
215 mutex_init(&priv->mutex);
216
217 /* Use VRAM if there is any ; otherwise fallback to system memory */
218 domain = drm->client.device.info.ram_size != 0 ?
219 NOUVEAU_GEM_DOMAIN_VRAM :
220 /*
221 * fences created in sysmem must be non-cached or we
222 * will lose CPU/GPU coherency!
223 */
224 NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT;
225 ret = nouveau_bo_new(&drm->client, 16 * drm->chan_total, 0,
226 domain, 0, 0, NULL, NULL, &priv->bo);
227 if (ret == 0) {
228 ret = nouveau_bo_pin(priv->bo, domain, false);
229 if (ret == 0) {
230 ret = nouveau_bo_map(priv->bo);
231 if (ret)
232 nouveau_bo_unpin(priv->bo);
233 }
234 if (ret)
235 nouveau_bo_ref(NULL, &priv->bo);
236 }
237
238 if (ret)
239 nv84_fence_destroy(drm);
240 return ret;
241}
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "nouveau_drm.h"
26#include "nouveau_dma.h"
27#include "nouveau_fence.h"
28
29#include "nv50_display.h"
30
31u64
32nv84_fence_crtc(struct nouveau_channel *chan, int crtc)
33{
34 struct nv84_fence_chan *fctx = chan->fence;
35 return fctx->dispc_vma[crtc].offset;
36}
37
38static int
39nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
40{
41 int ret = RING_SPACE(chan, 8);
42 if (ret == 0) {
43 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
44 OUT_RING (chan, chan->vram.handle);
45 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
46 OUT_RING (chan, upper_32_bits(virtual));
47 OUT_RING (chan, lower_32_bits(virtual));
48 OUT_RING (chan, sequence);
49 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
50 OUT_RING (chan, 0x00000000);
51 FIRE_RING (chan);
52 }
53 return ret;
54}
55
56static int
57nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
58{
59 int ret = RING_SPACE(chan, 7);
60 if (ret == 0) {
61 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
62 OUT_RING (chan, chan->vram.handle);
63 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
64 OUT_RING (chan, upper_32_bits(virtual));
65 OUT_RING (chan, lower_32_bits(virtual));
66 OUT_RING (chan, sequence);
67 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
68 FIRE_RING (chan);
69 }
70 return ret;
71}
72
73static int
74nv84_fence_emit(struct nouveau_fence *fence)
75{
76 struct nouveau_channel *chan = fence->channel;
77 struct nv84_fence_chan *fctx = chan->fence;
78 u64 addr = chan->chid * 16;
79
80 if (fence->sysmem)
81 addr += fctx->vma_gart.offset;
82 else
83 addr += fctx->vma.offset;
84
85 return fctx->base.emit32(chan, addr, fence->base.seqno);
86}
87
88static int
89nv84_fence_sync(struct nouveau_fence *fence,
90 struct nouveau_channel *prev, struct nouveau_channel *chan)
91{
92 struct nv84_fence_chan *fctx = chan->fence;
93 u64 addr = prev->chid * 16;
94
95 if (fence->sysmem)
96 addr += fctx->vma_gart.offset;
97 else
98 addr += fctx->vma.offset;
99
100 return fctx->base.sync32(chan, addr, fence->base.seqno);
101}
102
103static u32
104nv84_fence_read(struct nouveau_channel *chan)
105{
106 struct nv84_fence_priv *priv = chan->drm->fence;
107 return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
108}
109
110static void
111nv84_fence_context_del(struct nouveau_channel *chan)
112{
113 struct drm_device *dev = chan->drm->dev;
114 struct nv84_fence_priv *priv = chan->drm->fence;
115 struct nv84_fence_chan *fctx = chan->fence;
116 int i;
117
118 for (i = 0; i < dev->mode_config.num_crtc; i++) {
119 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
120 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
121 }
122
123 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
124 nouveau_bo_vma_del(priv->bo, &fctx->vma_gart);
125 nouveau_bo_vma_del(priv->bo, &fctx->vma);
126 nouveau_fence_context_del(&fctx->base);
127 chan->fence = NULL;
128 nouveau_fence_context_free(&fctx->base);
129}
130
131int
132nv84_fence_context_new(struct nouveau_channel *chan)
133{
134 struct nouveau_cli *cli = (void *)chan->user.client;
135 struct nv84_fence_priv *priv = chan->drm->fence;
136 struct nv84_fence_chan *fctx;
137 int ret, i;
138
139 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
140 if (!fctx)
141 return -ENOMEM;
142
143 nouveau_fence_context_new(chan, &fctx->base);
144 fctx->base.emit = nv84_fence_emit;
145 fctx->base.sync = nv84_fence_sync;
146 fctx->base.read = nv84_fence_read;
147 fctx->base.emit32 = nv84_fence_emit32;
148 fctx->base.sync32 = nv84_fence_sync32;
149 fctx->base.sequence = nv84_fence_read(chan);
150
151 ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma);
152 if (ret == 0) {
153 ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm,
154 &fctx->vma_gart);
155 }
156
157 /* map display semaphore buffers into channel's vm */
158 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
159 struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i);
160 ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]);
161 }
162
163 if (ret)
164 nv84_fence_context_del(chan);
165 return ret;
166}
167
168static bool
169nv84_fence_suspend(struct nouveau_drm *drm)
170{
171 struct nv84_fence_priv *priv = drm->fence;
172 int i;
173
174 priv->suspend = vmalloc(priv->base.contexts * sizeof(u32));
175 if (priv->suspend) {
176 for (i = 0; i < priv->base.contexts; i++)
177 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
178 }
179
180 return priv->suspend != NULL;
181}
182
183static void
184nv84_fence_resume(struct nouveau_drm *drm)
185{
186 struct nv84_fence_priv *priv = drm->fence;
187 int i;
188
189 if (priv->suspend) {
190 for (i = 0; i < priv->base.contexts; i++)
191 nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
192 vfree(priv->suspend);
193 priv->suspend = NULL;
194 }
195}
196
197static void
198nv84_fence_destroy(struct nouveau_drm *drm)
199{
200 struct nv84_fence_priv *priv = drm->fence;
201 nouveau_bo_unmap(priv->bo_gart);
202 if (priv->bo_gart)
203 nouveau_bo_unpin(priv->bo_gart);
204 nouveau_bo_ref(NULL, &priv->bo_gart);
205 nouveau_bo_unmap(priv->bo);
206 if (priv->bo)
207 nouveau_bo_unpin(priv->bo);
208 nouveau_bo_ref(NULL, &priv->bo);
209 drm->fence = NULL;
210 kfree(priv);
211}
212
213int
214nv84_fence_create(struct nouveau_drm *drm)
215{
216 struct nvkm_fifo *fifo = nvxx_fifo(&drm->device);
217 struct nv84_fence_priv *priv;
218 u32 domain;
219 int ret;
220
221 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
222 if (!priv)
223 return -ENOMEM;
224
225 priv->base.dtor = nv84_fence_destroy;
226 priv->base.suspend = nv84_fence_suspend;
227 priv->base.resume = nv84_fence_resume;
228 priv->base.context_new = nv84_fence_context_new;
229 priv->base.context_del = nv84_fence_context_del;
230
231 priv->base.contexts = fifo->nr;
232 priv->base.context_base = fence_context_alloc(priv->base.contexts);
233 priv->base.uevent = true;
234
235 /* Use VRAM if there is any ; otherwise fallback to system memory */
236 domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
237 /*
238 * fences created in sysmem must be non-cached or we
239 * will lose CPU/GPU coherency!
240 */
241 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
242 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0,
243 0, NULL, NULL, &priv->bo);
244 if (ret == 0) {
245 ret = nouveau_bo_pin(priv->bo, domain, false);
246 if (ret == 0) {
247 ret = nouveau_bo_map(priv->bo);
248 if (ret)
249 nouveau_bo_unpin(priv->bo);
250 }
251 if (ret)
252 nouveau_bo_ref(NULL, &priv->bo);
253 }
254
255 if (ret == 0)
256 ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0,
257 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED, 0,
258 0, NULL, NULL, &priv->bo_gart);
259 if (ret == 0) {
260 ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT, false);
261 if (ret == 0) {
262 ret = nouveau_bo_map(priv->bo_gart);
263 if (ret)
264 nouveau_bo_unpin(priv->bo_gart);
265 }
266 if (ret)
267 nouveau_bo_ref(NULL, &priv->bo_gart);
268 }
269
270 if (ret)
271 nv84_fence_destroy(drm);
272 return ret;
273}