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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * offload engine driver for the Marvell XOR engine
4 * Copyright (C) 2007, 2008, Marvell International Ltd.
5 */
6
7#include <linux/init.h>
8#include <linux/slab.h>
9#include <linux/delay.h>
10#include <linux/dma-mapping.h>
11#include <linux/spinlock.h>
12#include <linux/interrupt.h>
13#include <linux/platform_device.h>
14#include <linux/property.h>
15#include <linux/memory.h>
16#include <linux/clk.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/irqdomain.h>
20#include <linux/cpumask.h>
21#include <linux/platform_data/dma-mv_xor.h>
22
23#include "dmaengine.h"
24#include "mv_xor.h"
25
26enum mv_xor_type {
27 XOR_ORION,
28 XOR_ARMADA_38X,
29 XOR_ARMADA_37XX,
30};
31
32enum mv_xor_mode {
33 XOR_MODE_IN_REG,
34 XOR_MODE_IN_DESC,
35};
36
37static void mv_xor_issue_pending(struct dma_chan *chan);
38
39#define to_mv_xor_chan(chan) \
40 container_of(chan, struct mv_xor_chan, dmachan)
41
42#define to_mv_xor_slot(tx) \
43 container_of(tx, struct mv_xor_desc_slot, async_tx)
44
45#define mv_chan_to_devp(chan) \
46 ((chan)->dmadev.dev)
47
48static void mv_desc_init(struct mv_xor_desc_slot *desc,
49 dma_addr_t addr, u32 byte_count,
50 enum dma_ctrl_flags flags)
51{
52 struct mv_xor_desc *hw_desc = desc->hw_desc;
53
54 hw_desc->status = XOR_DESC_DMA_OWNED;
55 hw_desc->phy_next_desc = 0;
56 /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */
57 hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ?
58 XOR_DESC_EOD_INT_EN : 0;
59 hw_desc->phy_dest_addr = addr;
60 hw_desc->byte_count = byte_count;
61}
62
63static void mv_desc_set_mode(struct mv_xor_desc_slot *desc)
64{
65 struct mv_xor_desc *hw_desc = desc->hw_desc;
66
67 switch (desc->type) {
68 case DMA_XOR:
69 case DMA_INTERRUPT:
70 hw_desc->desc_command |= XOR_DESC_OPERATION_XOR;
71 break;
72 case DMA_MEMCPY:
73 hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY;
74 break;
75 default:
76 BUG();
77 return;
78 }
79}
80
81static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
82 u32 next_desc_addr)
83{
84 struct mv_xor_desc *hw_desc = desc->hw_desc;
85 BUG_ON(hw_desc->phy_next_desc);
86 hw_desc->phy_next_desc = next_desc_addr;
87}
88
89static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
90 int index, dma_addr_t addr)
91{
92 struct mv_xor_desc *hw_desc = desc->hw_desc;
93 hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
94 if (desc->type == DMA_XOR)
95 hw_desc->desc_command |= (1 << index);
96}
97
98static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
99{
100 return readl_relaxed(XOR_CURR_DESC(chan));
101}
102
103static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
104 u32 next_desc_addr)
105{
106 writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
107}
108
109static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
110{
111 u32 val = readl_relaxed(XOR_INTR_MASK(chan));
112 val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
113 writel_relaxed(val, XOR_INTR_MASK(chan));
114}
115
116static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
117{
118 u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
119 intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
120 return intr_cause;
121}
122
123static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan)
124{
125 u32 val;
126
127 val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED;
128 val = ~(val << (chan->idx * 16));
129 dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
130 writel_relaxed(val, XOR_INTR_CAUSE(chan));
131}
132
133static void mv_chan_clear_err_status(struct mv_xor_chan *chan)
134{
135 u32 val = 0xFFFF0000 >> (chan->idx * 16);
136 writel_relaxed(val, XOR_INTR_CAUSE(chan));
137}
138
139static void mv_chan_set_mode(struct mv_xor_chan *chan,
140 u32 op_mode)
141{
142 u32 config = readl_relaxed(XOR_CONFIG(chan));
143
144 config &= ~0x7;
145 config |= op_mode;
146
147#if defined(__BIG_ENDIAN)
148 config |= XOR_DESCRIPTOR_SWAP;
149#else
150 config &= ~XOR_DESCRIPTOR_SWAP;
151#endif
152
153 writel_relaxed(config, XOR_CONFIG(chan));
154}
155
156static void mv_chan_activate(struct mv_xor_chan *chan)
157{
158 dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
159
160 /* writel ensures all descriptors are flushed before activation */
161 writel(BIT(0), XOR_ACTIVATION(chan));
162}
163
164static char mv_chan_is_busy(struct mv_xor_chan *chan)
165{
166 u32 state = readl_relaxed(XOR_ACTIVATION(chan));
167
168 state = (state >> 4) & 0x3;
169
170 return (state == 1) ? 1 : 0;
171}
172
173/*
174 * mv_chan_start_new_chain - program the engine to operate on new
175 * chain headed by sw_desc
176 * Caller must hold &mv_chan->lock while calling this function
177 */
178static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan,
179 struct mv_xor_desc_slot *sw_desc)
180{
181 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
182 __func__, __LINE__, sw_desc);
183
184 /* set the hardware chain */
185 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
186
187 mv_chan->pending++;
188 mv_xor_issue_pending(&mv_chan->dmachan);
189}
190
191static dma_cookie_t
192mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
193 struct mv_xor_chan *mv_chan,
194 dma_cookie_t cookie)
195{
196 BUG_ON(desc->async_tx.cookie < 0);
197
198 if (desc->async_tx.cookie > 0) {
199 cookie = desc->async_tx.cookie;
200
201 dma_descriptor_unmap(&desc->async_tx);
202 /* call the callback (must not sleep or submit new
203 * operations to this channel)
204 */
205 dmaengine_desc_get_callback_invoke(&desc->async_tx, NULL);
206 }
207
208 /* run dependent operations */
209 dma_run_dependencies(&desc->async_tx);
210
211 return cookie;
212}
213
214static int
215mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan)
216{
217 struct mv_xor_desc_slot *iter, *_iter;
218
219 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
220 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
221 node) {
222
223 if (async_tx_test_ack(&iter->async_tx)) {
224 list_move_tail(&iter->node, &mv_chan->free_slots);
225 if (!list_empty(&iter->sg_tx_list)) {
226 list_splice_tail_init(&iter->sg_tx_list,
227 &mv_chan->free_slots);
228 }
229 }
230 }
231 return 0;
232}
233
234static int
235mv_desc_clean_slot(struct mv_xor_desc_slot *desc,
236 struct mv_xor_chan *mv_chan)
237{
238 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
239 __func__, __LINE__, desc, desc->async_tx.flags);
240
241 /* the client is allowed to attach dependent operations
242 * until 'ack' is set
243 */
244 if (!async_tx_test_ack(&desc->async_tx)) {
245 /* move this slot to the completed_slots */
246 list_move_tail(&desc->node, &mv_chan->completed_slots);
247 if (!list_empty(&desc->sg_tx_list)) {
248 list_splice_tail_init(&desc->sg_tx_list,
249 &mv_chan->completed_slots);
250 }
251 } else {
252 list_move_tail(&desc->node, &mv_chan->free_slots);
253 if (!list_empty(&desc->sg_tx_list)) {
254 list_splice_tail_init(&desc->sg_tx_list,
255 &mv_chan->free_slots);
256 }
257 }
258
259 return 0;
260}
261
262/* This function must be called with the mv_xor_chan spinlock held */
263static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan)
264{
265 struct mv_xor_desc_slot *iter, *_iter;
266 dma_cookie_t cookie = 0;
267 int busy = mv_chan_is_busy(mv_chan);
268 u32 current_desc = mv_chan_get_current_desc(mv_chan);
269 int current_cleaned = 0;
270 struct mv_xor_desc *hw_desc;
271
272 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
273 dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
274 mv_chan_clean_completed_slots(mv_chan);
275
276 /* free completed slots from the chain starting with
277 * the oldest descriptor
278 */
279
280 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
281 node) {
282
283 /* clean finished descriptors */
284 hw_desc = iter->hw_desc;
285 if (hw_desc->status & XOR_DESC_SUCCESS) {
286 cookie = mv_desc_run_tx_complete_actions(iter, mv_chan,
287 cookie);
288
289 /* done processing desc, clean slot */
290 mv_desc_clean_slot(iter, mv_chan);
291
292 /* break if we did cleaned the current */
293 if (iter->async_tx.phys == current_desc) {
294 current_cleaned = 1;
295 break;
296 }
297 } else {
298 if (iter->async_tx.phys == current_desc) {
299 current_cleaned = 0;
300 break;
301 }
302 }
303 }
304
305 if ((busy == 0) && !list_empty(&mv_chan->chain)) {
306 if (current_cleaned) {
307 /*
308 * current descriptor cleaned and removed, run
309 * from list head
310 */
311 iter = list_entry(mv_chan->chain.next,
312 struct mv_xor_desc_slot,
313 node);
314 mv_chan_start_new_chain(mv_chan, iter);
315 } else {
316 if (!list_is_last(&iter->node, &mv_chan->chain)) {
317 /*
318 * descriptors are still waiting after
319 * current, trigger them
320 */
321 iter = list_entry(iter->node.next,
322 struct mv_xor_desc_slot,
323 node);
324 mv_chan_start_new_chain(mv_chan, iter);
325 } else {
326 /*
327 * some descriptors are still waiting
328 * to be cleaned
329 */
330 tasklet_schedule(&mv_chan->irq_tasklet);
331 }
332 }
333 }
334
335 if (cookie > 0)
336 mv_chan->dmachan.completed_cookie = cookie;
337}
338
339static void mv_xor_tasklet(struct tasklet_struct *t)
340{
341 struct mv_xor_chan *chan = from_tasklet(chan, t, irq_tasklet);
342
343 spin_lock(&chan->lock);
344 mv_chan_slot_cleanup(chan);
345 spin_unlock(&chan->lock);
346}
347
348static struct mv_xor_desc_slot *
349mv_chan_alloc_slot(struct mv_xor_chan *mv_chan)
350{
351 struct mv_xor_desc_slot *iter;
352
353 spin_lock_bh(&mv_chan->lock);
354
355 if (!list_empty(&mv_chan->free_slots)) {
356 iter = list_first_entry(&mv_chan->free_slots,
357 struct mv_xor_desc_slot,
358 node);
359
360 list_move_tail(&iter->node, &mv_chan->allocated_slots);
361
362 spin_unlock_bh(&mv_chan->lock);
363
364 /* pre-ack descriptor */
365 async_tx_ack(&iter->async_tx);
366 iter->async_tx.cookie = -EBUSY;
367
368 return iter;
369
370 }
371
372 spin_unlock_bh(&mv_chan->lock);
373
374 /* try to free some slots if the allocation fails */
375 tasklet_schedule(&mv_chan->irq_tasklet);
376
377 return NULL;
378}
379
380/************************ DMA engine API functions ****************************/
381static dma_cookie_t
382mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
383{
384 struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
385 struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
386 struct mv_xor_desc_slot *old_chain_tail;
387 dma_cookie_t cookie;
388 int new_hw_chain = 1;
389
390 dev_dbg(mv_chan_to_devp(mv_chan),
391 "%s sw_desc %p: async_tx %p\n",
392 __func__, sw_desc, &sw_desc->async_tx);
393
394 spin_lock_bh(&mv_chan->lock);
395 cookie = dma_cookie_assign(tx);
396
397 if (list_empty(&mv_chan->chain))
398 list_move_tail(&sw_desc->node, &mv_chan->chain);
399 else {
400 new_hw_chain = 0;
401
402 old_chain_tail = list_entry(mv_chan->chain.prev,
403 struct mv_xor_desc_slot,
404 node);
405 list_move_tail(&sw_desc->node, &mv_chan->chain);
406
407 dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
408 &old_chain_tail->async_tx.phys);
409
410 /* fix up the hardware chain */
411 mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys);
412
413 /* if the channel is not busy */
414 if (!mv_chan_is_busy(mv_chan)) {
415 u32 current_desc = mv_chan_get_current_desc(mv_chan);
416 /*
417 * and the curren desc is the end of the chain before
418 * the append, then we need to start the channel
419 */
420 if (current_desc == old_chain_tail->async_tx.phys)
421 new_hw_chain = 1;
422 }
423 }
424
425 if (new_hw_chain)
426 mv_chan_start_new_chain(mv_chan, sw_desc);
427
428 spin_unlock_bh(&mv_chan->lock);
429
430 return cookie;
431}
432
433/* returns the number of allocated descriptors */
434static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
435{
436 void *virt_desc;
437 dma_addr_t dma_desc;
438 int idx;
439 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
440 struct mv_xor_desc_slot *slot = NULL;
441 int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
442
443 /* Allocate descriptor slots */
444 idx = mv_chan->slots_allocated;
445 while (idx < num_descs_in_pool) {
446 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
447 if (!slot) {
448 dev_info(mv_chan_to_devp(mv_chan),
449 "channel only initialized %d descriptor slots",
450 idx);
451 break;
452 }
453 virt_desc = mv_chan->dma_desc_pool_virt;
454 slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE;
455
456 dma_async_tx_descriptor_init(&slot->async_tx, chan);
457 slot->async_tx.tx_submit = mv_xor_tx_submit;
458 INIT_LIST_HEAD(&slot->node);
459 INIT_LIST_HEAD(&slot->sg_tx_list);
460 dma_desc = mv_chan->dma_desc_pool;
461 slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE;
462 slot->idx = idx++;
463
464 spin_lock_bh(&mv_chan->lock);
465 mv_chan->slots_allocated = idx;
466 list_add_tail(&slot->node, &mv_chan->free_slots);
467 spin_unlock_bh(&mv_chan->lock);
468 }
469
470 dev_dbg(mv_chan_to_devp(mv_chan),
471 "allocated %d descriptor slots\n",
472 mv_chan->slots_allocated);
473
474 return mv_chan->slots_allocated ? : -ENOMEM;
475}
476
477/*
478 * Check if source or destination is an PCIe/IO address (non-SDRAM) and add
479 * a new MBus window if necessary. Use a cache for these check so that
480 * the MMIO mapped registers don't have to be accessed for this check
481 * to speed up this process.
482 */
483static int mv_xor_add_io_win(struct mv_xor_chan *mv_chan, u32 addr)
484{
485 struct mv_xor_device *xordev = mv_chan->xordev;
486 void __iomem *base = mv_chan->mmr_high_base;
487 u32 win_enable;
488 u32 size;
489 u8 target, attr;
490 int ret;
491 int i;
492
493 /* Nothing needs to get done for the Armada 3700 */
494 if (xordev->xor_type == XOR_ARMADA_37XX)
495 return 0;
496
497 /*
498 * Loop over the cached windows to check, if the requested area
499 * is already mapped. If this the case, nothing needs to be done
500 * and we can return.
501 */
502 for (i = 0; i < WINDOW_COUNT; i++) {
503 if (addr >= xordev->win_start[i] &&
504 addr <= xordev->win_end[i]) {
505 /* Window is already mapped */
506 return 0;
507 }
508 }
509
510 /*
511 * The window is not mapped, so we need to create the new mapping
512 */
513
514 /* If no IO window is found that addr has to be located in SDRAM */
515 ret = mvebu_mbus_get_io_win_info(addr, &size, &target, &attr);
516 if (ret < 0)
517 return 0;
518
519 /*
520 * Mask the base addr 'addr' according to 'size' read back from the
521 * MBus window. Otherwise we might end up with an address located
522 * somewhere in the middle of this area here.
523 */
524 size -= 1;
525 addr &= ~size;
526
527 /*
528 * Reading one of both enabled register is enough, as they are always
529 * programmed to the identical values
530 */
531 win_enable = readl(base + WINDOW_BAR_ENABLE(0));
532
533 /* Set 'i' to the first free window to write the new values to */
534 i = ffs(~win_enable) - 1;
535 if (i >= WINDOW_COUNT)
536 return -ENOMEM;
537
538 writel((addr & 0xffff0000) | (attr << 8) | target,
539 base + WINDOW_BASE(i));
540 writel(size & 0xffff0000, base + WINDOW_SIZE(i));
541
542 /* Fill the caching variables for later use */
543 xordev->win_start[i] = addr;
544 xordev->win_end[i] = addr + size;
545
546 win_enable |= (1 << i);
547 win_enable |= 3 << (16 + (2 * i));
548 writel(win_enable, base + WINDOW_BAR_ENABLE(0));
549 writel(win_enable, base + WINDOW_BAR_ENABLE(1));
550
551 return 0;
552}
553
554static struct dma_async_tx_descriptor *
555mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
556 unsigned int src_cnt, size_t len, unsigned long flags)
557{
558 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
559 struct mv_xor_desc_slot *sw_desc;
560 int ret;
561
562 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
563 return NULL;
564
565 BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
566
567 dev_dbg(mv_chan_to_devp(mv_chan),
568 "%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
569 __func__, src_cnt, len, &dest, flags);
570
571 /* Check if a new window needs to get added for 'dest' */
572 ret = mv_xor_add_io_win(mv_chan, dest);
573 if (ret)
574 return NULL;
575
576 sw_desc = mv_chan_alloc_slot(mv_chan);
577 if (sw_desc) {
578 sw_desc->type = DMA_XOR;
579 sw_desc->async_tx.flags = flags;
580 mv_desc_init(sw_desc, dest, len, flags);
581 if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
582 mv_desc_set_mode(sw_desc);
583 while (src_cnt--) {
584 /* Check if a new window needs to get added for 'src' */
585 ret = mv_xor_add_io_win(mv_chan, src[src_cnt]);
586 if (ret)
587 return NULL;
588 mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]);
589 }
590 }
591
592 dev_dbg(mv_chan_to_devp(mv_chan),
593 "%s sw_desc %p async_tx %p \n",
594 __func__, sw_desc, &sw_desc->async_tx);
595 return sw_desc ? &sw_desc->async_tx : NULL;
596}
597
598static struct dma_async_tx_descriptor *
599mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
600 size_t len, unsigned long flags)
601{
602 /*
603 * A MEMCPY operation is identical to an XOR operation with only
604 * a single source address.
605 */
606 return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
607}
608
609static struct dma_async_tx_descriptor *
610mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
611{
612 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
613 dma_addr_t src, dest;
614 size_t len;
615
616 src = mv_chan->dummy_src_addr;
617 dest = mv_chan->dummy_dst_addr;
618 len = MV_XOR_MIN_BYTE_COUNT;
619
620 /*
621 * We implement the DMA_INTERRUPT operation as a minimum sized
622 * XOR operation with a single dummy source address.
623 */
624 return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
625}
626
627static void mv_xor_free_chan_resources(struct dma_chan *chan)
628{
629 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
630 struct mv_xor_desc_slot *iter, *_iter;
631 int in_use_descs = 0;
632
633 spin_lock_bh(&mv_chan->lock);
634
635 mv_chan_slot_cleanup(mv_chan);
636
637 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
638 node) {
639 in_use_descs++;
640 list_move_tail(&iter->node, &mv_chan->free_slots);
641 }
642 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
643 node) {
644 in_use_descs++;
645 list_move_tail(&iter->node, &mv_chan->free_slots);
646 }
647 list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots,
648 node) {
649 in_use_descs++;
650 list_move_tail(&iter->node, &mv_chan->free_slots);
651 }
652 list_for_each_entry_safe_reverse(
653 iter, _iter, &mv_chan->free_slots, node) {
654 list_del(&iter->node);
655 kfree(iter);
656 mv_chan->slots_allocated--;
657 }
658
659 dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
660 __func__, mv_chan->slots_allocated);
661 spin_unlock_bh(&mv_chan->lock);
662
663 if (in_use_descs)
664 dev_err(mv_chan_to_devp(mv_chan),
665 "freeing %d in use descriptors!\n", in_use_descs);
666}
667
668/**
669 * mv_xor_status - poll the status of an XOR transaction
670 * @chan: XOR channel handle
671 * @cookie: XOR transaction identifier
672 * @txstate: XOR transactions state holder (or NULL)
673 */
674static enum dma_status mv_xor_status(struct dma_chan *chan,
675 dma_cookie_t cookie,
676 struct dma_tx_state *txstate)
677{
678 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
679 enum dma_status ret;
680
681 ret = dma_cookie_status(chan, cookie, txstate);
682 if (ret == DMA_COMPLETE)
683 return ret;
684
685 spin_lock_bh(&mv_chan->lock);
686 mv_chan_slot_cleanup(mv_chan);
687 spin_unlock_bh(&mv_chan->lock);
688
689 return dma_cookie_status(chan, cookie, txstate);
690}
691
692static void mv_chan_dump_regs(struct mv_xor_chan *chan)
693{
694 u32 val;
695
696 val = readl_relaxed(XOR_CONFIG(chan));
697 dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val);
698
699 val = readl_relaxed(XOR_ACTIVATION(chan));
700 dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val);
701
702 val = readl_relaxed(XOR_INTR_CAUSE(chan));
703 dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val);
704
705 val = readl_relaxed(XOR_INTR_MASK(chan));
706 dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val);
707
708 val = readl_relaxed(XOR_ERROR_CAUSE(chan));
709 dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val);
710
711 val = readl_relaxed(XOR_ERROR_ADDR(chan));
712 dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val);
713}
714
715static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan,
716 u32 intr_cause)
717{
718 if (intr_cause & XOR_INT_ERR_DECODE) {
719 dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n");
720 return;
721 }
722
723 dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n",
724 chan->idx, intr_cause);
725
726 mv_chan_dump_regs(chan);
727 WARN_ON(1);
728}
729
730static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
731{
732 struct mv_xor_chan *chan = data;
733 u32 intr_cause = mv_chan_get_intr_cause(chan);
734
735 dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
736
737 if (intr_cause & XOR_INTR_ERRORS)
738 mv_chan_err_interrupt_handler(chan, intr_cause);
739
740 tasklet_schedule(&chan->irq_tasklet);
741
742 mv_chan_clear_eoc_cause(chan);
743
744 return IRQ_HANDLED;
745}
746
747static void mv_xor_issue_pending(struct dma_chan *chan)
748{
749 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
750
751 if (mv_chan->pending >= MV_XOR_THRESHOLD) {
752 mv_chan->pending = 0;
753 mv_chan_activate(mv_chan);
754 }
755}
756
757/*
758 * Perform a transaction to verify the HW works.
759 */
760
761static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan)
762{
763 int i, ret;
764 void *src, *dest;
765 dma_addr_t src_dma, dest_dma;
766 struct dma_chan *dma_chan;
767 dma_cookie_t cookie;
768 struct dma_async_tx_descriptor *tx;
769 struct dmaengine_unmap_data *unmap;
770 int err = 0;
771
772 src = kmalloc(PAGE_SIZE, GFP_KERNEL);
773 if (!src)
774 return -ENOMEM;
775
776 dest = kzalloc(PAGE_SIZE, GFP_KERNEL);
777 if (!dest) {
778 kfree(src);
779 return -ENOMEM;
780 }
781
782 /* Fill in src buffer */
783 for (i = 0; i < PAGE_SIZE; i++)
784 ((u8 *) src)[i] = (u8)i;
785
786 dma_chan = &mv_chan->dmachan;
787 if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
788 err = -ENODEV;
789 goto out;
790 }
791
792 unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
793 if (!unmap) {
794 err = -ENOMEM;
795 goto free_resources;
796 }
797
798 src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src),
799 offset_in_page(src), PAGE_SIZE,
800 DMA_TO_DEVICE);
801 unmap->addr[0] = src_dma;
802
803 ret = dma_mapping_error(dma_chan->device->dev, src_dma);
804 if (ret) {
805 err = -ENOMEM;
806 goto free_resources;
807 }
808 unmap->to_cnt = 1;
809
810 dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest),
811 offset_in_page(dest), PAGE_SIZE,
812 DMA_FROM_DEVICE);
813 unmap->addr[1] = dest_dma;
814
815 ret = dma_mapping_error(dma_chan->device->dev, dest_dma);
816 if (ret) {
817 err = -ENOMEM;
818 goto free_resources;
819 }
820 unmap->from_cnt = 1;
821 unmap->len = PAGE_SIZE;
822
823 tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
824 PAGE_SIZE, 0);
825 if (!tx) {
826 dev_err(dma_chan->device->dev,
827 "Self-test cannot prepare operation, disabling\n");
828 err = -ENODEV;
829 goto free_resources;
830 }
831
832 cookie = mv_xor_tx_submit(tx);
833 if (dma_submit_error(cookie)) {
834 dev_err(dma_chan->device->dev,
835 "Self-test submit error, disabling\n");
836 err = -ENODEV;
837 goto free_resources;
838 }
839
840 mv_xor_issue_pending(dma_chan);
841 async_tx_ack(tx);
842 msleep(1);
843
844 if (mv_xor_status(dma_chan, cookie, NULL) !=
845 DMA_COMPLETE) {
846 dev_err(dma_chan->device->dev,
847 "Self-test copy timed out, disabling\n");
848 err = -ENODEV;
849 goto free_resources;
850 }
851
852 dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
853 PAGE_SIZE, DMA_FROM_DEVICE);
854 if (memcmp(src, dest, PAGE_SIZE)) {
855 dev_err(dma_chan->device->dev,
856 "Self-test copy failed compare, disabling\n");
857 err = -ENODEV;
858 goto free_resources;
859 }
860
861free_resources:
862 dmaengine_unmap_put(unmap);
863 mv_xor_free_chan_resources(dma_chan);
864out:
865 kfree(src);
866 kfree(dest);
867 return err;
868}
869
870#define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
871static int
872mv_chan_xor_self_test(struct mv_xor_chan *mv_chan)
873{
874 int i, src_idx, ret;
875 struct page *dest;
876 struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
877 dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
878 dma_addr_t dest_dma;
879 struct dma_async_tx_descriptor *tx;
880 struct dmaengine_unmap_data *unmap;
881 struct dma_chan *dma_chan;
882 dma_cookie_t cookie;
883 u8 cmp_byte = 0;
884 u32 cmp_word;
885 int err = 0;
886 int src_count = MV_XOR_NUM_SRC_TEST;
887
888 for (src_idx = 0; src_idx < src_count; src_idx++) {
889 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
890 if (!xor_srcs[src_idx]) {
891 while (src_idx--)
892 __free_page(xor_srcs[src_idx]);
893 return -ENOMEM;
894 }
895 }
896
897 dest = alloc_page(GFP_KERNEL);
898 if (!dest) {
899 while (src_idx--)
900 __free_page(xor_srcs[src_idx]);
901 return -ENOMEM;
902 }
903
904 /* Fill in src buffers */
905 for (src_idx = 0; src_idx < src_count; src_idx++) {
906 u8 *ptr = page_address(xor_srcs[src_idx]);
907 for (i = 0; i < PAGE_SIZE; i++)
908 ptr[i] = (1 << src_idx);
909 }
910
911 for (src_idx = 0; src_idx < src_count; src_idx++)
912 cmp_byte ^= (u8) (1 << src_idx);
913
914 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
915 (cmp_byte << 8) | cmp_byte;
916
917 memset(page_address(dest), 0, PAGE_SIZE);
918
919 dma_chan = &mv_chan->dmachan;
920 if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
921 err = -ENODEV;
922 goto out;
923 }
924
925 unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
926 GFP_KERNEL);
927 if (!unmap) {
928 err = -ENOMEM;
929 goto free_resources;
930 }
931
932 /* test xor */
933 for (i = 0; i < src_count; i++) {
934 unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
935 0, PAGE_SIZE, DMA_TO_DEVICE);
936 dma_srcs[i] = unmap->addr[i];
937 ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]);
938 if (ret) {
939 err = -ENOMEM;
940 goto free_resources;
941 }
942 unmap->to_cnt++;
943 }
944
945 unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
946 DMA_FROM_DEVICE);
947 dest_dma = unmap->addr[src_count];
948 ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]);
949 if (ret) {
950 err = -ENOMEM;
951 goto free_resources;
952 }
953 unmap->from_cnt = 1;
954 unmap->len = PAGE_SIZE;
955
956 tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
957 src_count, PAGE_SIZE, 0);
958 if (!tx) {
959 dev_err(dma_chan->device->dev,
960 "Self-test cannot prepare operation, disabling\n");
961 err = -ENODEV;
962 goto free_resources;
963 }
964
965 cookie = mv_xor_tx_submit(tx);
966 if (dma_submit_error(cookie)) {
967 dev_err(dma_chan->device->dev,
968 "Self-test submit error, disabling\n");
969 err = -ENODEV;
970 goto free_resources;
971 }
972
973 mv_xor_issue_pending(dma_chan);
974 async_tx_ack(tx);
975 msleep(8);
976
977 if (mv_xor_status(dma_chan, cookie, NULL) !=
978 DMA_COMPLETE) {
979 dev_err(dma_chan->device->dev,
980 "Self-test xor timed out, disabling\n");
981 err = -ENODEV;
982 goto free_resources;
983 }
984
985 dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
986 PAGE_SIZE, DMA_FROM_DEVICE);
987 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
988 u32 *ptr = page_address(dest);
989 if (ptr[i] != cmp_word) {
990 dev_err(dma_chan->device->dev,
991 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
992 i, ptr[i], cmp_word);
993 err = -ENODEV;
994 goto free_resources;
995 }
996 }
997
998free_resources:
999 dmaengine_unmap_put(unmap);
1000 mv_xor_free_chan_resources(dma_chan);
1001out:
1002 src_idx = src_count;
1003 while (src_idx--)
1004 __free_page(xor_srcs[src_idx]);
1005 __free_page(dest);
1006 return err;
1007}
1008
1009static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
1010{
1011 struct dma_chan *chan, *_chan;
1012 struct device *dev = mv_chan->dmadev.dev;
1013
1014 dma_async_device_unregister(&mv_chan->dmadev);
1015
1016 dma_free_coherent(dev, MV_XOR_POOL_SIZE,
1017 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1018 dma_unmap_single(dev, mv_chan->dummy_src_addr,
1019 MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
1020 dma_unmap_single(dev, mv_chan->dummy_dst_addr,
1021 MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
1022
1023 list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
1024 device_node) {
1025 list_del(&chan->device_node);
1026 }
1027
1028 free_irq(mv_chan->irq, mv_chan);
1029
1030 return 0;
1031}
1032
1033static struct mv_xor_chan *
1034mv_xor_channel_add(struct mv_xor_device *xordev,
1035 struct platform_device *pdev,
1036 int idx, dma_cap_mask_t cap_mask, int irq)
1037{
1038 int ret = 0;
1039 struct mv_xor_chan *mv_chan;
1040 struct dma_device *dma_dev;
1041
1042 mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
1043 if (!mv_chan)
1044 return ERR_PTR(-ENOMEM);
1045
1046 mv_chan->idx = idx;
1047 mv_chan->irq = irq;
1048 if (xordev->xor_type == XOR_ORION)
1049 mv_chan->op_in_desc = XOR_MODE_IN_REG;
1050 else
1051 mv_chan->op_in_desc = XOR_MODE_IN_DESC;
1052
1053 dma_dev = &mv_chan->dmadev;
1054 dma_dev->dev = &pdev->dev;
1055 mv_chan->xordev = xordev;
1056
1057 /*
1058 * These source and destination dummy buffers are used to implement
1059 * a DMA_INTERRUPT operation as a minimum-sized XOR operation.
1060 * Hence, we only need to map the buffers at initialization-time.
1061 */
1062 mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev,
1063 mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
1064 mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev,
1065 mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
1066
1067 /* allocate coherent memory for hardware descriptors
1068 * note: writecombine gives slightly better performance, but
1069 * requires that we explicitly flush the writes
1070 */
1071 mv_chan->dma_desc_pool_virt =
1072 dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool,
1073 GFP_KERNEL);
1074 if (!mv_chan->dma_desc_pool_virt)
1075 return ERR_PTR(-ENOMEM);
1076
1077 /* discover transaction capabilites from the platform data */
1078 dma_dev->cap_mask = cap_mask;
1079
1080 INIT_LIST_HEAD(&dma_dev->channels);
1081
1082 /* set base routines */
1083 dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
1084 dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
1085 dma_dev->device_tx_status = mv_xor_status;
1086 dma_dev->device_issue_pending = mv_xor_issue_pending;
1087
1088 /* set prep routines based on capability */
1089 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1090 dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt;
1091 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1092 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
1093 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1094 dma_dev->max_xor = 8;
1095 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
1096 }
1097
1098 mv_chan->mmr_base = xordev->xor_base;
1099 mv_chan->mmr_high_base = xordev->xor_high_base;
1100 tasklet_setup(&mv_chan->irq_tasklet, mv_xor_tasklet);
1101
1102 /* clear errors before enabling interrupts */
1103 mv_chan_clear_err_status(mv_chan);
1104
1105 ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
1106 0, dev_name(&pdev->dev), mv_chan);
1107 if (ret)
1108 goto err_free_dma;
1109
1110 mv_chan_unmask_interrupts(mv_chan);
1111
1112 if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
1113 mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC);
1114 else
1115 mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR);
1116
1117 spin_lock_init(&mv_chan->lock);
1118 INIT_LIST_HEAD(&mv_chan->chain);
1119 INIT_LIST_HEAD(&mv_chan->completed_slots);
1120 INIT_LIST_HEAD(&mv_chan->free_slots);
1121 INIT_LIST_HEAD(&mv_chan->allocated_slots);
1122 mv_chan->dmachan.device = dma_dev;
1123 dma_cookie_init(&mv_chan->dmachan);
1124
1125 list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
1126
1127 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1128 ret = mv_chan_memcpy_self_test(mv_chan);
1129 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1130 if (ret)
1131 goto err_free_irq;
1132 }
1133
1134 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1135 ret = mv_chan_xor_self_test(mv_chan);
1136 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1137 if (ret)
1138 goto err_free_irq;
1139 }
1140
1141 dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n",
1142 mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode",
1143 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1144 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1145 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1146
1147 ret = dma_async_device_register(dma_dev);
1148 if (ret)
1149 goto err_free_irq;
1150
1151 return mv_chan;
1152
1153err_free_irq:
1154 free_irq(mv_chan->irq, mv_chan);
1155err_free_dma:
1156 dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
1157 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1158 return ERR_PTR(ret);
1159}
1160
1161static void
1162mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
1163 const struct mbus_dram_target_info *dram)
1164{
1165 void __iomem *base = xordev->xor_high_base;
1166 u32 win_enable = 0;
1167 int i;
1168
1169 for (i = 0; i < 8; i++) {
1170 writel(0, base + WINDOW_BASE(i));
1171 writel(0, base + WINDOW_SIZE(i));
1172 if (i < 4)
1173 writel(0, base + WINDOW_REMAP_HIGH(i));
1174 }
1175
1176 for (i = 0; i < dram->num_cs; i++) {
1177 const struct mbus_dram_window *cs = dram->cs + i;
1178
1179 writel((cs->base & 0xffff0000) |
1180 (cs->mbus_attr << 8) |
1181 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1182 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1183
1184 /* Fill the caching variables for later use */
1185 xordev->win_start[i] = cs->base;
1186 xordev->win_end[i] = cs->base + cs->size - 1;
1187
1188 win_enable |= (1 << i);
1189 win_enable |= 3 << (16 + (2 * i));
1190 }
1191
1192 writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1193 writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1194 writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1195 writel(0, base + WINDOW_OVERRIDE_CTRL(1));
1196}
1197
1198static void
1199mv_xor_conf_mbus_windows_a3700(struct mv_xor_device *xordev)
1200{
1201 void __iomem *base = xordev->xor_high_base;
1202 u32 win_enable = 0;
1203 int i;
1204
1205 for (i = 0; i < 8; i++) {
1206 writel(0, base + WINDOW_BASE(i));
1207 writel(0, base + WINDOW_SIZE(i));
1208 if (i < 4)
1209 writel(0, base + WINDOW_REMAP_HIGH(i));
1210 }
1211 /*
1212 * For Armada3700 open default 4GB Mbus window. The dram
1213 * related configuration are done at AXIS level.
1214 */
1215 writel(0xffff0000, base + WINDOW_SIZE(0));
1216 win_enable |= 1;
1217 win_enable |= 3 << 16;
1218
1219 writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1220 writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1221 writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1222 writel(0, base + WINDOW_OVERRIDE_CTRL(1));
1223}
1224
1225/*
1226 * Since this XOR driver is basically used only for RAID5, we don't
1227 * need to care about synchronizing ->suspend with DMA activity,
1228 * because the DMA engine will naturally be quiet due to the block
1229 * devices being suspended.
1230 */
1231static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
1232{
1233 struct mv_xor_device *xordev = platform_get_drvdata(pdev);
1234 int i;
1235
1236 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1237 struct mv_xor_chan *mv_chan = xordev->channels[i];
1238
1239 if (!mv_chan)
1240 continue;
1241
1242 mv_chan->saved_config_reg =
1243 readl_relaxed(XOR_CONFIG(mv_chan));
1244 mv_chan->saved_int_mask_reg =
1245 readl_relaxed(XOR_INTR_MASK(mv_chan));
1246 }
1247
1248 return 0;
1249}
1250
1251static int mv_xor_resume(struct platform_device *dev)
1252{
1253 struct mv_xor_device *xordev = platform_get_drvdata(dev);
1254 const struct mbus_dram_target_info *dram;
1255 int i;
1256
1257 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1258 struct mv_xor_chan *mv_chan = xordev->channels[i];
1259
1260 if (!mv_chan)
1261 continue;
1262
1263 writel_relaxed(mv_chan->saved_config_reg,
1264 XOR_CONFIG(mv_chan));
1265 writel_relaxed(mv_chan->saved_int_mask_reg,
1266 XOR_INTR_MASK(mv_chan));
1267 }
1268
1269 if (xordev->xor_type == XOR_ARMADA_37XX) {
1270 mv_xor_conf_mbus_windows_a3700(xordev);
1271 return 0;
1272 }
1273
1274 dram = mv_mbus_dram_info();
1275 if (dram)
1276 mv_xor_conf_mbus_windows(xordev, dram);
1277
1278 return 0;
1279}
1280
1281static const struct of_device_id mv_xor_dt_ids[] = {
1282 { .compatible = "marvell,orion-xor", .data = (void *)XOR_ORION },
1283 { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_ARMADA_38X },
1284 { .compatible = "marvell,armada-3700-xor", .data = (void *)XOR_ARMADA_37XX },
1285 {},
1286};
1287
1288static unsigned int mv_xor_engine_count;
1289
1290static int mv_xor_probe(struct platform_device *pdev)
1291{
1292 const struct mbus_dram_target_info *dram;
1293 struct mv_xor_device *xordev;
1294 struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
1295 struct resource *res;
1296 unsigned int max_engines, max_channels;
1297 int i, ret;
1298
1299 dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
1300
1301 xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
1302 if (!xordev)
1303 return -ENOMEM;
1304
1305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1306 if (!res)
1307 return -ENODEV;
1308
1309 xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
1310 resource_size(res));
1311 if (!xordev->xor_base)
1312 return -EBUSY;
1313
1314 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1315 if (!res)
1316 return -ENODEV;
1317
1318 xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1319 resource_size(res));
1320 if (!xordev->xor_high_base)
1321 return -EBUSY;
1322
1323 platform_set_drvdata(pdev, xordev);
1324
1325
1326 /*
1327 * We need to know which type of XOR device we use before
1328 * setting up. In non-dt case it can only be the legacy one.
1329 */
1330 xordev->xor_type = XOR_ORION;
1331 if (pdev->dev.of_node)
1332 xordev->xor_type = (uintptr_t)device_get_match_data(&pdev->dev);
1333
1334 /*
1335 * (Re-)program MBUS remapping windows if we are asked to.
1336 */
1337 if (xordev->xor_type == XOR_ARMADA_37XX) {
1338 mv_xor_conf_mbus_windows_a3700(xordev);
1339 } else {
1340 dram = mv_mbus_dram_info();
1341 if (dram)
1342 mv_xor_conf_mbus_windows(xordev, dram);
1343 }
1344
1345 /* Not all platforms can gate the clock, so it is not
1346 * an error if the clock does not exists.
1347 */
1348 xordev->clk = clk_get(&pdev->dev, NULL);
1349 if (!IS_ERR(xordev->clk))
1350 clk_prepare_enable(xordev->clk);
1351
1352 /*
1353 * We don't want to have more than one channel per CPU in
1354 * order for async_tx to perform well. So we limit the number
1355 * of engines and channels so that we take into account this
1356 * constraint. Note that we also want to use channels from
1357 * separate engines when possible. For dual-CPU Armada 3700
1358 * SoC with single XOR engine allow using its both channels.
1359 */
1360 max_engines = num_present_cpus();
1361 if (xordev->xor_type == XOR_ARMADA_37XX)
1362 max_channels = num_present_cpus();
1363 else
1364 max_channels = min_t(unsigned int,
1365 MV_XOR_MAX_CHANNELS,
1366 DIV_ROUND_UP(num_present_cpus(), 2));
1367
1368 if (mv_xor_engine_count >= max_engines)
1369 return 0;
1370
1371 if (pdev->dev.of_node) {
1372 struct device_node *np;
1373 int i = 0;
1374
1375 for_each_child_of_node(pdev->dev.of_node, np) {
1376 struct mv_xor_chan *chan;
1377 dma_cap_mask_t cap_mask;
1378 int irq;
1379
1380 if (i >= max_channels)
1381 continue;
1382
1383 dma_cap_zero(cap_mask);
1384 dma_cap_set(DMA_MEMCPY, cap_mask);
1385 dma_cap_set(DMA_XOR, cap_mask);
1386 dma_cap_set(DMA_INTERRUPT, cap_mask);
1387
1388 irq = irq_of_parse_and_map(np, 0);
1389 if (!irq) {
1390 ret = -ENODEV;
1391 goto err_channel_add;
1392 }
1393
1394 chan = mv_xor_channel_add(xordev, pdev, i,
1395 cap_mask, irq);
1396 if (IS_ERR(chan)) {
1397 ret = PTR_ERR(chan);
1398 irq_dispose_mapping(irq);
1399 goto err_channel_add;
1400 }
1401
1402 xordev->channels[i] = chan;
1403 i++;
1404 }
1405 } else if (pdata && pdata->channels) {
1406 for (i = 0; i < max_channels; i++) {
1407 struct mv_xor_channel_data *cd;
1408 struct mv_xor_chan *chan;
1409 int irq;
1410
1411 cd = &pdata->channels[i];
1412 irq = platform_get_irq(pdev, i);
1413 if (irq < 0) {
1414 ret = irq;
1415 goto err_channel_add;
1416 }
1417
1418 chan = mv_xor_channel_add(xordev, pdev, i,
1419 cd->cap_mask, irq);
1420 if (IS_ERR(chan)) {
1421 ret = PTR_ERR(chan);
1422 goto err_channel_add;
1423 }
1424
1425 xordev->channels[i] = chan;
1426 }
1427 }
1428
1429 return 0;
1430
1431err_channel_add:
1432 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
1433 if (xordev->channels[i]) {
1434 mv_xor_channel_remove(xordev->channels[i]);
1435 if (pdev->dev.of_node)
1436 irq_dispose_mapping(xordev->channels[i]->irq);
1437 }
1438
1439 if (!IS_ERR(xordev->clk)) {
1440 clk_disable_unprepare(xordev->clk);
1441 clk_put(xordev->clk);
1442 }
1443
1444 return ret;
1445}
1446
1447static struct platform_driver mv_xor_driver = {
1448 .probe = mv_xor_probe,
1449 .suspend = mv_xor_suspend,
1450 .resume = mv_xor_resume,
1451 .driver = {
1452 .name = MV_XOR_NAME,
1453 .of_match_table = mv_xor_dt_ids,
1454 },
1455};
1456
1457builtin_platform_driver(mv_xor_driver);
1458
1459/*
1460MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1461MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1462MODULE_LICENSE("GPL");
1463*/
1/*
2 * offload engine driver for the Marvell XOR engine
3 * Copyright (C) 2007, 2008, Marvell International Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/init.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
18#include <linux/dma-mapping.h>
19#include <linux/spinlock.h>
20#include <linux/interrupt.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
23#include <linux/memory.h>
24#include <linux/clk.h>
25#include <linux/of.h>
26#include <linux/of_irq.h>
27#include <linux/irqdomain.h>
28#include <linux/cpumask.h>
29#include <linux/platform_data/dma-mv_xor.h>
30
31#include "dmaengine.h"
32#include "mv_xor.h"
33
34enum mv_xor_mode {
35 XOR_MODE_IN_REG,
36 XOR_MODE_IN_DESC,
37};
38
39static void mv_xor_issue_pending(struct dma_chan *chan);
40
41#define to_mv_xor_chan(chan) \
42 container_of(chan, struct mv_xor_chan, dmachan)
43
44#define to_mv_xor_slot(tx) \
45 container_of(tx, struct mv_xor_desc_slot, async_tx)
46
47#define mv_chan_to_devp(chan) \
48 ((chan)->dmadev.dev)
49
50static void mv_desc_init(struct mv_xor_desc_slot *desc,
51 dma_addr_t addr, u32 byte_count,
52 enum dma_ctrl_flags flags)
53{
54 struct mv_xor_desc *hw_desc = desc->hw_desc;
55
56 hw_desc->status = XOR_DESC_DMA_OWNED;
57 hw_desc->phy_next_desc = 0;
58 /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */
59 hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ?
60 XOR_DESC_EOD_INT_EN : 0;
61 hw_desc->phy_dest_addr = addr;
62 hw_desc->byte_count = byte_count;
63}
64
65static void mv_desc_set_mode(struct mv_xor_desc_slot *desc)
66{
67 struct mv_xor_desc *hw_desc = desc->hw_desc;
68
69 switch (desc->type) {
70 case DMA_XOR:
71 case DMA_INTERRUPT:
72 hw_desc->desc_command |= XOR_DESC_OPERATION_XOR;
73 break;
74 case DMA_MEMCPY:
75 hw_desc->desc_command |= XOR_DESC_OPERATION_MEMCPY;
76 break;
77 default:
78 BUG();
79 return;
80 }
81}
82
83static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc,
84 u32 next_desc_addr)
85{
86 struct mv_xor_desc *hw_desc = desc->hw_desc;
87 BUG_ON(hw_desc->phy_next_desc);
88 hw_desc->phy_next_desc = next_desc_addr;
89}
90
91static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc,
92 int index, dma_addr_t addr)
93{
94 struct mv_xor_desc *hw_desc = desc->hw_desc;
95 hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr;
96 if (desc->type == DMA_XOR)
97 hw_desc->desc_command |= (1 << index);
98}
99
100static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan)
101{
102 return readl_relaxed(XOR_CURR_DESC(chan));
103}
104
105static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan,
106 u32 next_desc_addr)
107{
108 writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan));
109}
110
111static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan)
112{
113 u32 val = readl_relaxed(XOR_INTR_MASK(chan));
114 val |= XOR_INTR_MASK_VALUE << (chan->idx * 16);
115 writel_relaxed(val, XOR_INTR_MASK(chan));
116}
117
118static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan)
119{
120 u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan));
121 intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF;
122 return intr_cause;
123}
124
125static void mv_chan_clear_eoc_cause(struct mv_xor_chan *chan)
126{
127 u32 val;
128
129 val = XOR_INT_END_OF_DESC | XOR_INT_END_OF_CHAIN | XOR_INT_STOPPED;
130 val = ~(val << (chan->idx * 16));
131 dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val);
132 writel_relaxed(val, XOR_INTR_CAUSE(chan));
133}
134
135static void mv_chan_clear_err_status(struct mv_xor_chan *chan)
136{
137 u32 val = 0xFFFF0000 >> (chan->idx * 16);
138 writel_relaxed(val, XOR_INTR_CAUSE(chan));
139}
140
141static void mv_chan_set_mode(struct mv_xor_chan *chan,
142 u32 op_mode)
143{
144 u32 config = readl_relaxed(XOR_CONFIG(chan));
145
146 config &= ~0x7;
147 config |= op_mode;
148
149#if defined(__BIG_ENDIAN)
150 config |= XOR_DESCRIPTOR_SWAP;
151#else
152 config &= ~XOR_DESCRIPTOR_SWAP;
153#endif
154
155 writel_relaxed(config, XOR_CONFIG(chan));
156}
157
158static void mv_chan_activate(struct mv_xor_chan *chan)
159{
160 dev_dbg(mv_chan_to_devp(chan), " activate chan.\n");
161
162 /* writel ensures all descriptors are flushed before activation */
163 writel(BIT(0), XOR_ACTIVATION(chan));
164}
165
166static char mv_chan_is_busy(struct mv_xor_chan *chan)
167{
168 u32 state = readl_relaxed(XOR_ACTIVATION(chan));
169
170 state = (state >> 4) & 0x3;
171
172 return (state == 1) ? 1 : 0;
173}
174
175/*
176 * mv_chan_start_new_chain - program the engine to operate on new
177 * chain headed by sw_desc
178 * Caller must hold &mv_chan->lock while calling this function
179 */
180static void mv_chan_start_new_chain(struct mv_xor_chan *mv_chan,
181 struct mv_xor_desc_slot *sw_desc)
182{
183 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n",
184 __func__, __LINE__, sw_desc);
185
186 /* set the hardware chain */
187 mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys);
188
189 mv_chan->pending++;
190 mv_xor_issue_pending(&mv_chan->dmachan);
191}
192
193static dma_cookie_t
194mv_desc_run_tx_complete_actions(struct mv_xor_desc_slot *desc,
195 struct mv_xor_chan *mv_chan,
196 dma_cookie_t cookie)
197{
198 BUG_ON(desc->async_tx.cookie < 0);
199
200 if (desc->async_tx.cookie > 0) {
201 cookie = desc->async_tx.cookie;
202
203 /* call the callback (must not sleep or submit new
204 * operations to this channel)
205 */
206 if (desc->async_tx.callback)
207 desc->async_tx.callback(
208 desc->async_tx.callback_param);
209
210 dma_descriptor_unmap(&desc->async_tx);
211 }
212
213 /* run dependent operations */
214 dma_run_dependencies(&desc->async_tx);
215
216 return cookie;
217}
218
219static int
220mv_chan_clean_completed_slots(struct mv_xor_chan *mv_chan)
221{
222 struct mv_xor_desc_slot *iter, *_iter;
223
224 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
225 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
226 node) {
227
228 if (async_tx_test_ack(&iter->async_tx))
229 list_move_tail(&iter->node, &mv_chan->free_slots);
230 }
231 return 0;
232}
233
234static int
235mv_desc_clean_slot(struct mv_xor_desc_slot *desc,
236 struct mv_xor_chan *mv_chan)
237{
238 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n",
239 __func__, __LINE__, desc, desc->async_tx.flags);
240
241 /* the client is allowed to attach dependent operations
242 * until 'ack' is set
243 */
244 if (!async_tx_test_ack(&desc->async_tx))
245 /* move this slot to the completed_slots */
246 list_move_tail(&desc->node, &mv_chan->completed_slots);
247 else
248 list_move_tail(&desc->node, &mv_chan->free_slots);
249
250 return 0;
251}
252
253/* This function must be called with the mv_xor_chan spinlock held */
254static void mv_chan_slot_cleanup(struct mv_xor_chan *mv_chan)
255{
256 struct mv_xor_desc_slot *iter, *_iter;
257 dma_cookie_t cookie = 0;
258 int busy = mv_chan_is_busy(mv_chan);
259 u32 current_desc = mv_chan_get_current_desc(mv_chan);
260 int current_cleaned = 0;
261 struct mv_xor_desc *hw_desc;
262
263 dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__);
264 dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc);
265 mv_chan_clean_completed_slots(mv_chan);
266
267 /* free completed slots from the chain starting with
268 * the oldest descriptor
269 */
270
271 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
272 node) {
273
274 /* clean finished descriptors */
275 hw_desc = iter->hw_desc;
276 if (hw_desc->status & XOR_DESC_SUCCESS) {
277 cookie = mv_desc_run_tx_complete_actions(iter, mv_chan,
278 cookie);
279
280 /* done processing desc, clean slot */
281 mv_desc_clean_slot(iter, mv_chan);
282
283 /* break if we did cleaned the current */
284 if (iter->async_tx.phys == current_desc) {
285 current_cleaned = 1;
286 break;
287 }
288 } else {
289 if (iter->async_tx.phys == current_desc) {
290 current_cleaned = 0;
291 break;
292 }
293 }
294 }
295
296 if ((busy == 0) && !list_empty(&mv_chan->chain)) {
297 if (current_cleaned) {
298 /*
299 * current descriptor cleaned and removed, run
300 * from list head
301 */
302 iter = list_entry(mv_chan->chain.next,
303 struct mv_xor_desc_slot,
304 node);
305 mv_chan_start_new_chain(mv_chan, iter);
306 } else {
307 if (!list_is_last(&iter->node, &mv_chan->chain)) {
308 /*
309 * descriptors are still waiting after
310 * current, trigger them
311 */
312 iter = list_entry(iter->node.next,
313 struct mv_xor_desc_slot,
314 node);
315 mv_chan_start_new_chain(mv_chan, iter);
316 } else {
317 /*
318 * some descriptors are still waiting
319 * to be cleaned
320 */
321 tasklet_schedule(&mv_chan->irq_tasklet);
322 }
323 }
324 }
325
326 if (cookie > 0)
327 mv_chan->dmachan.completed_cookie = cookie;
328}
329
330static void mv_xor_tasklet(unsigned long data)
331{
332 struct mv_xor_chan *chan = (struct mv_xor_chan *) data;
333
334 spin_lock_bh(&chan->lock);
335 mv_chan_slot_cleanup(chan);
336 spin_unlock_bh(&chan->lock);
337}
338
339static struct mv_xor_desc_slot *
340mv_chan_alloc_slot(struct mv_xor_chan *mv_chan)
341{
342 struct mv_xor_desc_slot *iter;
343
344 spin_lock_bh(&mv_chan->lock);
345
346 if (!list_empty(&mv_chan->free_slots)) {
347 iter = list_first_entry(&mv_chan->free_slots,
348 struct mv_xor_desc_slot,
349 node);
350
351 list_move_tail(&iter->node, &mv_chan->allocated_slots);
352
353 spin_unlock_bh(&mv_chan->lock);
354
355 /* pre-ack descriptor */
356 async_tx_ack(&iter->async_tx);
357 iter->async_tx.cookie = -EBUSY;
358
359 return iter;
360
361 }
362
363 spin_unlock_bh(&mv_chan->lock);
364
365 /* try to free some slots if the allocation fails */
366 tasklet_schedule(&mv_chan->irq_tasklet);
367
368 return NULL;
369}
370
371/************************ DMA engine API functions ****************************/
372static dma_cookie_t
373mv_xor_tx_submit(struct dma_async_tx_descriptor *tx)
374{
375 struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx);
376 struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan);
377 struct mv_xor_desc_slot *old_chain_tail;
378 dma_cookie_t cookie;
379 int new_hw_chain = 1;
380
381 dev_dbg(mv_chan_to_devp(mv_chan),
382 "%s sw_desc %p: async_tx %p\n",
383 __func__, sw_desc, &sw_desc->async_tx);
384
385 spin_lock_bh(&mv_chan->lock);
386 cookie = dma_cookie_assign(tx);
387
388 if (list_empty(&mv_chan->chain))
389 list_move_tail(&sw_desc->node, &mv_chan->chain);
390 else {
391 new_hw_chain = 0;
392
393 old_chain_tail = list_entry(mv_chan->chain.prev,
394 struct mv_xor_desc_slot,
395 node);
396 list_move_tail(&sw_desc->node, &mv_chan->chain);
397
398 dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %pa\n",
399 &old_chain_tail->async_tx.phys);
400
401 /* fix up the hardware chain */
402 mv_desc_set_next_desc(old_chain_tail, sw_desc->async_tx.phys);
403
404 /* if the channel is not busy */
405 if (!mv_chan_is_busy(mv_chan)) {
406 u32 current_desc = mv_chan_get_current_desc(mv_chan);
407 /*
408 * and the curren desc is the end of the chain before
409 * the append, then we need to start the channel
410 */
411 if (current_desc == old_chain_tail->async_tx.phys)
412 new_hw_chain = 1;
413 }
414 }
415
416 if (new_hw_chain)
417 mv_chan_start_new_chain(mv_chan, sw_desc);
418
419 spin_unlock_bh(&mv_chan->lock);
420
421 return cookie;
422}
423
424/* returns the number of allocated descriptors */
425static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
426{
427 void *virt_desc;
428 dma_addr_t dma_desc;
429 int idx;
430 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
431 struct mv_xor_desc_slot *slot = NULL;
432 int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE;
433
434 /* Allocate descriptor slots */
435 idx = mv_chan->slots_allocated;
436 while (idx < num_descs_in_pool) {
437 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
438 if (!slot) {
439 dev_info(mv_chan_to_devp(mv_chan),
440 "channel only initialized %d descriptor slots",
441 idx);
442 break;
443 }
444 virt_desc = mv_chan->dma_desc_pool_virt;
445 slot->hw_desc = virt_desc + idx * MV_XOR_SLOT_SIZE;
446
447 dma_async_tx_descriptor_init(&slot->async_tx, chan);
448 slot->async_tx.tx_submit = mv_xor_tx_submit;
449 INIT_LIST_HEAD(&slot->node);
450 dma_desc = mv_chan->dma_desc_pool;
451 slot->async_tx.phys = dma_desc + idx * MV_XOR_SLOT_SIZE;
452 slot->idx = idx++;
453
454 spin_lock_bh(&mv_chan->lock);
455 mv_chan->slots_allocated = idx;
456 list_add_tail(&slot->node, &mv_chan->free_slots);
457 spin_unlock_bh(&mv_chan->lock);
458 }
459
460 dev_dbg(mv_chan_to_devp(mv_chan),
461 "allocated %d descriptor slots\n",
462 mv_chan->slots_allocated);
463
464 return mv_chan->slots_allocated ? : -ENOMEM;
465}
466
467static struct dma_async_tx_descriptor *
468mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
469 unsigned int src_cnt, size_t len, unsigned long flags)
470{
471 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
472 struct mv_xor_desc_slot *sw_desc;
473
474 if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
475 return NULL;
476
477 BUG_ON(len > MV_XOR_MAX_BYTE_COUNT);
478
479 dev_dbg(mv_chan_to_devp(mv_chan),
480 "%s src_cnt: %d len: %u dest %pad flags: %ld\n",
481 __func__, src_cnt, len, &dest, flags);
482
483 sw_desc = mv_chan_alloc_slot(mv_chan);
484 if (sw_desc) {
485 sw_desc->type = DMA_XOR;
486 sw_desc->async_tx.flags = flags;
487 mv_desc_init(sw_desc, dest, len, flags);
488 if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
489 mv_desc_set_mode(sw_desc);
490 while (src_cnt--)
491 mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]);
492 }
493
494 dev_dbg(mv_chan_to_devp(mv_chan),
495 "%s sw_desc %p async_tx %p \n",
496 __func__, sw_desc, &sw_desc->async_tx);
497 return sw_desc ? &sw_desc->async_tx : NULL;
498}
499
500static struct dma_async_tx_descriptor *
501mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
502 size_t len, unsigned long flags)
503{
504 /*
505 * A MEMCPY operation is identical to an XOR operation with only
506 * a single source address.
507 */
508 return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
509}
510
511static struct dma_async_tx_descriptor *
512mv_xor_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
513{
514 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
515 dma_addr_t src, dest;
516 size_t len;
517
518 src = mv_chan->dummy_src_addr;
519 dest = mv_chan->dummy_dst_addr;
520 len = MV_XOR_MIN_BYTE_COUNT;
521
522 /*
523 * We implement the DMA_INTERRUPT operation as a minimum sized
524 * XOR operation with a single dummy source address.
525 */
526 return mv_xor_prep_dma_xor(chan, dest, &src, 1, len, flags);
527}
528
529static void mv_xor_free_chan_resources(struct dma_chan *chan)
530{
531 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
532 struct mv_xor_desc_slot *iter, *_iter;
533 int in_use_descs = 0;
534
535 spin_lock_bh(&mv_chan->lock);
536
537 mv_chan_slot_cleanup(mv_chan);
538
539 list_for_each_entry_safe(iter, _iter, &mv_chan->chain,
540 node) {
541 in_use_descs++;
542 list_move_tail(&iter->node, &mv_chan->free_slots);
543 }
544 list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots,
545 node) {
546 in_use_descs++;
547 list_move_tail(&iter->node, &mv_chan->free_slots);
548 }
549 list_for_each_entry_safe(iter, _iter, &mv_chan->allocated_slots,
550 node) {
551 in_use_descs++;
552 list_move_tail(&iter->node, &mv_chan->free_slots);
553 }
554 list_for_each_entry_safe_reverse(
555 iter, _iter, &mv_chan->free_slots, node) {
556 list_del(&iter->node);
557 kfree(iter);
558 mv_chan->slots_allocated--;
559 }
560
561 dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n",
562 __func__, mv_chan->slots_allocated);
563 spin_unlock_bh(&mv_chan->lock);
564
565 if (in_use_descs)
566 dev_err(mv_chan_to_devp(mv_chan),
567 "freeing %d in use descriptors!\n", in_use_descs);
568}
569
570/**
571 * mv_xor_status - poll the status of an XOR transaction
572 * @chan: XOR channel handle
573 * @cookie: XOR transaction identifier
574 * @txstate: XOR transactions state holder (or NULL)
575 */
576static enum dma_status mv_xor_status(struct dma_chan *chan,
577 dma_cookie_t cookie,
578 struct dma_tx_state *txstate)
579{
580 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
581 enum dma_status ret;
582
583 ret = dma_cookie_status(chan, cookie, txstate);
584 if (ret == DMA_COMPLETE)
585 return ret;
586
587 spin_lock_bh(&mv_chan->lock);
588 mv_chan_slot_cleanup(mv_chan);
589 spin_unlock_bh(&mv_chan->lock);
590
591 return dma_cookie_status(chan, cookie, txstate);
592}
593
594static void mv_chan_dump_regs(struct mv_xor_chan *chan)
595{
596 u32 val;
597
598 val = readl_relaxed(XOR_CONFIG(chan));
599 dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val);
600
601 val = readl_relaxed(XOR_ACTIVATION(chan));
602 dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val);
603
604 val = readl_relaxed(XOR_INTR_CAUSE(chan));
605 dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val);
606
607 val = readl_relaxed(XOR_INTR_MASK(chan));
608 dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val);
609
610 val = readl_relaxed(XOR_ERROR_CAUSE(chan));
611 dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val);
612
613 val = readl_relaxed(XOR_ERROR_ADDR(chan));
614 dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val);
615}
616
617static void mv_chan_err_interrupt_handler(struct mv_xor_chan *chan,
618 u32 intr_cause)
619{
620 if (intr_cause & XOR_INT_ERR_DECODE) {
621 dev_dbg(mv_chan_to_devp(chan), "ignoring address decode error\n");
622 return;
623 }
624
625 dev_err(mv_chan_to_devp(chan), "error on chan %d. intr cause 0x%08x\n",
626 chan->idx, intr_cause);
627
628 mv_chan_dump_regs(chan);
629 WARN_ON(1);
630}
631
632static irqreturn_t mv_xor_interrupt_handler(int irq, void *data)
633{
634 struct mv_xor_chan *chan = data;
635 u32 intr_cause = mv_chan_get_intr_cause(chan);
636
637 dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause);
638
639 if (intr_cause & XOR_INTR_ERRORS)
640 mv_chan_err_interrupt_handler(chan, intr_cause);
641
642 tasklet_schedule(&chan->irq_tasklet);
643
644 mv_chan_clear_eoc_cause(chan);
645
646 return IRQ_HANDLED;
647}
648
649static void mv_xor_issue_pending(struct dma_chan *chan)
650{
651 struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
652
653 if (mv_chan->pending >= MV_XOR_THRESHOLD) {
654 mv_chan->pending = 0;
655 mv_chan_activate(mv_chan);
656 }
657}
658
659/*
660 * Perform a transaction to verify the HW works.
661 */
662
663static int mv_chan_memcpy_self_test(struct mv_xor_chan *mv_chan)
664{
665 int i, ret;
666 void *src, *dest;
667 dma_addr_t src_dma, dest_dma;
668 struct dma_chan *dma_chan;
669 dma_cookie_t cookie;
670 struct dma_async_tx_descriptor *tx;
671 struct dmaengine_unmap_data *unmap;
672 int err = 0;
673
674 src = kmalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
675 if (!src)
676 return -ENOMEM;
677
678 dest = kzalloc(sizeof(u8) * PAGE_SIZE, GFP_KERNEL);
679 if (!dest) {
680 kfree(src);
681 return -ENOMEM;
682 }
683
684 /* Fill in src buffer */
685 for (i = 0; i < PAGE_SIZE; i++)
686 ((u8 *) src)[i] = (u8)i;
687
688 dma_chan = &mv_chan->dmachan;
689 if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
690 err = -ENODEV;
691 goto out;
692 }
693
694 unmap = dmaengine_get_unmap_data(dma_chan->device->dev, 2, GFP_KERNEL);
695 if (!unmap) {
696 err = -ENOMEM;
697 goto free_resources;
698 }
699
700 src_dma = dma_map_page(dma_chan->device->dev, virt_to_page(src), 0,
701 PAGE_SIZE, DMA_TO_DEVICE);
702 unmap->addr[0] = src_dma;
703
704 ret = dma_mapping_error(dma_chan->device->dev, src_dma);
705 if (ret) {
706 err = -ENOMEM;
707 goto free_resources;
708 }
709 unmap->to_cnt = 1;
710
711 dest_dma = dma_map_page(dma_chan->device->dev, virt_to_page(dest), 0,
712 PAGE_SIZE, DMA_FROM_DEVICE);
713 unmap->addr[1] = dest_dma;
714
715 ret = dma_mapping_error(dma_chan->device->dev, dest_dma);
716 if (ret) {
717 err = -ENOMEM;
718 goto free_resources;
719 }
720 unmap->from_cnt = 1;
721 unmap->len = PAGE_SIZE;
722
723 tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
724 PAGE_SIZE, 0);
725 if (!tx) {
726 dev_err(dma_chan->device->dev,
727 "Self-test cannot prepare operation, disabling\n");
728 err = -ENODEV;
729 goto free_resources;
730 }
731
732 cookie = mv_xor_tx_submit(tx);
733 if (dma_submit_error(cookie)) {
734 dev_err(dma_chan->device->dev,
735 "Self-test submit error, disabling\n");
736 err = -ENODEV;
737 goto free_resources;
738 }
739
740 mv_xor_issue_pending(dma_chan);
741 async_tx_ack(tx);
742 msleep(1);
743
744 if (mv_xor_status(dma_chan, cookie, NULL) !=
745 DMA_COMPLETE) {
746 dev_err(dma_chan->device->dev,
747 "Self-test copy timed out, disabling\n");
748 err = -ENODEV;
749 goto free_resources;
750 }
751
752 dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
753 PAGE_SIZE, DMA_FROM_DEVICE);
754 if (memcmp(src, dest, PAGE_SIZE)) {
755 dev_err(dma_chan->device->dev,
756 "Self-test copy failed compare, disabling\n");
757 err = -ENODEV;
758 goto free_resources;
759 }
760
761free_resources:
762 dmaengine_unmap_put(unmap);
763 mv_xor_free_chan_resources(dma_chan);
764out:
765 kfree(src);
766 kfree(dest);
767 return err;
768}
769
770#define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */
771static int
772mv_chan_xor_self_test(struct mv_xor_chan *mv_chan)
773{
774 int i, src_idx, ret;
775 struct page *dest;
776 struct page *xor_srcs[MV_XOR_NUM_SRC_TEST];
777 dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST];
778 dma_addr_t dest_dma;
779 struct dma_async_tx_descriptor *tx;
780 struct dmaengine_unmap_data *unmap;
781 struct dma_chan *dma_chan;
782 dma_cookie_t cookie;
783 u8 cmp_byte = 0;
784 u32 cmp_word;
785 int err = 0;
786 int src_count = MV_XOR_NUM_SRC_TEST;
787
788 for (src_idx = 0; src_idx < src_count; src_idx++) {
789 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
790 if (!xor_srcs[src_idx]) {
791 while (src_idx--)
792 __free_page(xor_srcs[src_idx]);
793 return -ENOMEM;
794 }
795 }
796
797 dest = alloc_page(GFP_KERNEL);
798 if (!dest) {
799 while (src_idx--)
800 __free_page(xor_srcs[src_idx]);
801 return -ENOMEM;
802 }
803
804 /* Fill in src buffers */
805 for (src_idx = 0; src_idx < src_count; src_idx++) {
806 u8 *ptr = page_address(xor_srcs[src_idx]);
807 for (i = 0; i < PAGE_SIZE; i++)
808 ptr[i] = (1 << src_idx);
809 }
810
811 for (src_idx = 0; src_idx < src_count; src_idx++)
812 cmp_byte ^= (u8) (1 << src_idx);
813
814 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
815 (cmp_byte << 8) | cmp_byte;
816
817 memset(page_address(dest), 0, PAGE_SIZE);
818
819 dma_chan = &mv_chan->dmachan;
820 if (mv_xor_alloc_chan_resources(dma_chan) < 1) {
821 err = -ENODEV;
822 goto out;
823 }
824
825 unmap = dmaengine_get_unmap_data(dma_chan->device->dev, src_count + 1,
826 GFP_KERNEL);
827 if (!unmap) {
828 err = -ENOMEM;
829 goto free_resources;
830 }
831
832 /* test xor */
833 for (i = 0; i < src_count; i++) {
834 unmap->addr[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
835 0, PAGE_SIZE, DMA_TO_DEVICE);
836 dma_srcs[i] = unmap->addr[i];
837 ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[i]);
838 if (ret) {
839 err = -ENOMEM;
840 goto free_resources;
841 }
842 unmap->to_cnt++;
843 }
844
845 unmap->addr[src_count] = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE,
846 DMA_FROM_DEVICE);
847 dest_dma = unmap->addr[src_count];
848 ret = dma_mapping_error(dma_chan->device->dev, unmap->addr[src_count]);
849 if (ret) {
850 err = -ENOMEM;
851 goto free_resources;
852 }
853 unmap->from_cnt = 1;
854 unmap->len = PAGE_SIZE;
855
856 tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
857 src_count, PAGE_SIZE, 0);
858 if (!tx) {
859 dev_err(dma_chan->device->dev,
860 "Self-test cannot prepare operation, disabling\n");
861 err = -ENODEV;
862 goto free_resources;
863 }
864
865 cookie = mv_xor_tx_submit(tx);
866 if (dma_submit_error(cookie)) {
867 dev_err(dma_chan->device->dev,
868 "Self-test submit error, disabling\n");
869 err = -ENODEV;
870 goto free_resources;
871 }
872
873 mv_xor_issue_pending(dma_chan);
874 async_tx_ack(tx);
875 msleep(8);
876
877 if (mv_xor_status(dma_chan, cookie, NULL) !=
878 DMA_COMPLETE) {
879 dev_err(dma_chan->device->dev,
880 "Self-test xor timed out, disabling\n");
881 err = -ENODEV;
882 goto free_resources;
883 }
884
885 dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma,
886 PAGE_SIZE, DMA_FROM_DEVICE);
887 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
888 u32 *ptr = page_address(dest);
889 if (ptr[i] != cmp_word) {
890 dev_err(dma_chan->device->dev,
891 "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n",
892 i, ptr[i], cmp_word);
893 err = -ENODEV;
894 goto free_resources;
895 }
896 }
897
898free_resources:
899 dmaengine_unmap_put(unmap);
900 mv_xor_free_chan_resources(dma_chan);
901out:
902 src_idx = src_count;
903 while (src_idx--)
904 __free_page(xor_srcs[src_idx]);
905 __free_page(dest);
906 return err;
907}
908
909static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan)
910{
911 struct dma_chan *chan, *_chan;
912 struct device *dev = mv_chan->dmadev.dev;
913
914 dma_async_device_unregister(&mv_chan->dmadev);
915
916 dma_free_coherent(dev, MV_XOR_POOL_SIZE,
917 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
918 dma_unmap_single(dev, mv_chan->dummy_src_addr,
919 MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
920 dma_unmap_single(dev, mv_chan->dummy_dst_addr,
921 MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
922
923 list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels,
924 device_node) {
925 list_del(&chan->device_node);
926 }
927
928 free_irq(mv_chan->irq, mv_chan);
929
930 return 0;
931}
932
933static struct mv_xor_chan *
934mv_xor_channel_add(struct mv_xor_device *xordev,
935 struct platform_device *pdev,
936 int idx, dma_cap_mask_t cap_mask, int irq, int op_in_desc)
937{
938 int ret = 0;
939 struct mv_xor_chan *mv_chan;
940 struct dma_device *dma_dev;
941
942 mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL);
943 if (!mv_chan)
944 return ERR_PTR(-ENOMEM);
945
946 mv_chan->idx = idx;
947 mv_chan->irq = irq;
948 mv_chan->op_in_desc = op_in_desc;
949
950 dma_dev = &mv_chan->dmadev;
951
952 /*
953 * These source and destination dummy buffers are used to implement
954 * a DMA_INTERRUPT operation as a minimum-sized XOR operation.
955 * Hence, we only need to map the buffers at initialization-time.
956 */
957 mv_chan->dummy_src_addr = dma_map_single(dma_dev->dev,
958 mv_chan->dummy_src, MV_XOR_MIN_BYTE_COUNT, DMA_FROM_DEVICE);
959 mv_chan->dummy_dst_addr = dma_map_single(dma_dev->dev,
960 mv_chan->dummy_dst, MV_XOR_MIN_BYTE_COUNT, DMA_TO_DEVICE);
961
962 /* allocate coherent memory for hardware descriptors
963 * note: writecombine gives slightly better performance, but
964 * requires that we explicitly flush the writes
965 */
966 mv_chan->dma_desc_pool_virt =
967 dma_alloc_wc(&pdev->dev, MV_XOR_POOL_SIZE, &mv_chan->dma_desc_pool,
968 GFP_KERNEL);
969 if (!mv_chan->dma_desc_pool_virt)
970 return ERR_PTR(-ENOMEM);
971
972 /* discover transaction capabilites from the platform data */
973 dma_dev->cap_mask = cap_mask;
974
975 INIT_LIST_HEAD(&dma_dev->channels);
976
977 /* set base routines */
978 dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources;
979 dma_dev->device_free_chan_resources = mv_xor_free_chan_resources;
980 dma_dev->device_tx_status = mv_xor_status;
981 dma_dev->device_issue_pending = mv_xor_issue_pending;
982 dma_dev->dev = &pdev->dev;
983
984 /* set prep routines based on capability */
985 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
986 dma_dev->device_prep_dma_interrupt = mv_xor_prep_dma_interrupt;
987 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
988 dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy;
989 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
990 dma_dev->max_xor = 8;
991 dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor;
992 }
993
994 mv_chan->mmr_base = xordev->xor_base;
995 mv_chan->mmr_high_base = xordev->xor_high_base;
996 tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long)
997 mv_chan);
998
999 /* clear errors before enabling interrupts */
1000 mv_chan_clear_err_status(mv_chan);
1001
1002 ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler,
1003 0, dev_name(&pdev->dev), mv_chan);
1004 if (ret)
1005 goto err_free_dma;
1006
1007 mv_chan_unmask_interrupts(mv_chan);
1008
1009 if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
1010 mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_IN_DESC);
1011 else
1012 mv_chan_set_mode(mv_chan, XOR_OPERATION_MODE_XOR);
1013
1014 spin_lock_init(&mv_chan->lock);
1015 INIT_LIST_HEAD(&mv_chan->chain);
1016 INIT_LIST_HEAD(&mv_chan->completed_slots);
1017 INIT_LIST_HEAD(&mv_chan->free_slots);
1018 INIT_LIST_HEAD(&mv_chan->allocated_slots);
1019 mv_chan->dmachan.device = dma_dev;
1020 dma_cookie_init(&mv_chan->dmachan);
1021
1022 list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels);
1023
1024 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1025 ret = mv_chan_memcpy_self_test(mv_chan);
1026 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1027 if (ret)
1028 goto err_free_irq;
1029 }
1030
1031 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1032 ret = mv_chan_xor_self_test(mv_chan);
1033 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1034 if (ret)
1035 goto err_free_irq;
1036 }
1037
1038 dev_info(&pdev->dev, "Marvell XOR (%s): ( %s%s%s)\n",
1039 mv_chan->op_in_desc ? "Descriptor Mode" : "Registers Mode",
1040 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1041 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1042 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1043
1044 dma_async_device_register(dma_dev);
1045 return mv_chan;
1046
1047err_free_irq:
1048 free_irq(mv_chan->irq, mv_chan);
1049 err_free_dma:
1050 dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE,
1051 mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool);
1052 return ERR_PTR(ret);
1053}
1054
1055static void
1056mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
1057 const struct mbus_dram_target_info *dram)
1058{
1059 void __iomem *base = xordev->xor_high_base;
1060 u32 win_enable = 0;
1061 int i;
1062
1063 for (i = 0; i < 8; i++) {
1064 writel(0, base + WINDOW_BASE(i));
1065 writel(0, base + WINDOW_SIZE(i));
1066 if (i < 4)
1067 writel(0, base + WINDOW_REMAP_HIGH(i));
1068 }
1069
1070 for (i = 0; i < dram->num_cs; i++) {
1071 const struct mbus_dram_window *cs = dram->cs + i;
1072
1073 writel((cs->base & 0xffff0000) |
1074 (cs->mbus_attr << 8) |
1075 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1076 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1077
1078 win_enable |= (1 << i);
1079 win_enable |= 3 << (16 + (2 * i));
1080 }
1081
1082 writel(win_enable, base + WINDOW_BAR_ENABLE(0));
1083 writel(win_enable, base + WINDOW_BAR_ENABLE(1));
1084 writel(0, base + WINDOW_OVERRIDE_CTRL(0));
1085 writel(0, base + WINDOW_OVERRIDE_CTRL(1));
1086}
1087
1088/*
1089 * Since this XOR driver is basically used only for RAID5, we don't
1090 * need to care about synchronizing ->suspend with DMA activity,
1091 * because the DMA engine will naturally be quiet due to the block
1092 * devices being suspended.
1093 */
1094static int mv_xor_suspend(struct platform_device *pdev, pm_message_t state)
1095{
1096 struct mv_xor_device *xordev = platform_get_drvdata(pdev);
1097 int i;
1098
1099 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1100 struct mv_xor_chan *mv_chan = xordev->channels[i];
1101
1102 if (!mv_chan)
1103 continue;
1104
1105 mv_chan->saved_config_reg =
1106 readl_relaxed(XOR_CONFIG(mv_chan));
1107 mv_chan->saved_int_mask_reg =
1108 readl_relaxed(XOR_INTR_MASK(mv_chan));
1109 }
1110
1111 return 0;
1112}
1113
1114static int mv_xor_resume(struct platform_device *dev)
1115{
1116 struct mv_xor_device *xordev = platform_get_drvdata(dev);
1117 const struct mbus_dram_target_info *dram;
1118 int i;
1119
1120 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) {
1121 struct mv_xor_chan *mv_chan = xordev->channels[i];
1122
1123 if (!mv_chan)
1124 continue;
1125
1126 writel_relaxed(mv_chan->saved_config_reg,
1127 XOR_CONFIG(mv_chan));
1128 writel_relaxed(mv_chan->saved_int_mask_reg,
1129 XOR_INTR_MASK(mv_chan));
1130 }
1131
1132 dram = mv_mbus_dram_info();
1133 if (dram)
1134 mv_xor_conf_mbus_windows(xordev, dram);
1135
1136 return 0;
1137}
1138
1139static const struct of_device_id mv_xor_dt_ids[] = {
1140 { .compatible = "marvell,orion-xor", .data = (void *)XOR_MODE_IN_REG },
1141 { .compatible = "marvell,armada-380-xor", .data = (void *)XOR_MODE_IN_DESC },
1142 {},
1143};
1144
1145static unsigned int mv_xor_engine_count;
1146
1147static int mv_xor_probe(struct platform_device *pdev)
1148{
1149 const struct mbus_dram_target_info *dram;
1150 struct mv_xor_device *xordev;
1151 struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev);
1152 struct resource *res;
1153 unsigned int max_engines, max_channels;
1154 int i, ret;
1155 int op_in_desc;
1156
1157 dev_notice(&pdev->dev, "Marvell shared XOR driver\n");
1158
1159 xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL);
1160 if (!xordev)
1161 return -ENOMEM;
1162
1163 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1164 if (!res)
1165 return -ENODEV;
1166
1167 xordev->xor_base = devm_ioremap(&pdev->dev, res->start,
1168 resource_size(res));
1169 if (!xordev->xor_base)
1170 return -EBUSY;
1171
1172 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1173 if (!res)
1174 return -ENODEV;
1175
1176 xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start,
1177 resource_size(res));
1178 if (!xordev->xor_high_base)
1179 return -EBUSY;
1180
1181 platform_set_drvdata(pdev, xordev);
1182
1183 /*
1184 * (Re-)program MBUS remapping windows if we are asked to.
1185 */
1186 dram = mv_mbus_dram_info();
1187 if (dram)
1188 mv_xor_conf_mbus_windows(xordev, dram);
1189
1190 /* Not all platforms can gate the clock, so it is not
1191 * an error if the clock does not exists.
1192 */
1193 xordev->clk = clk_get(&pdev->dev, NULL);
1194 if (!IS_ERR(xordev->clk))
1195 clk_prepare_enable(xordev->clk);
1196
1197 /*
1198 * We don't want to have more than one channel per CPU in
1199 * order for async_tx to perform well. So we limit the number
1200 * of engines and channels so that we take into account this
1201 * constraint. Note that we also want to use channels from
1202 * separate engines when possible.
1203 */
1204 max_engines = num_present_cpus();
1205 max_channels = min_t(unsigned int,
1206 MV_XOR_MAX_CHANNELS,
1207 DIV_ROUND_UP(num_present_cpus(), 2));
1208
1209 if (mv_xor_engine_count >= max_engines)
1210 return 0;
1211
1212 if (pdev->dev.of_node) {
1213 struct device_node *np;
1214 int i = 0;
1215 const struct of_device_id *of_id =
1216 of_match_device(mv_xor_dt_ids,
1217 &pdev->dev);
1218
1219 for_each_child_of_node(pdev->dev.of_node, np) {
1220 struct mv_xor_chan *chan;
1221 dma_cap_mask_t cap_mask;
1222 int irq;
1223 op_in_desc = (int)of_id->data;
1224
1225 if (i >= max_channels)
1226 continue;
1227
1228 dma_cap_zero(cap_mask);
1229 dma_cap_set(DMA_MEMCPY, cap_mask);
1230 dma_cap_set(DMA_XOR, cap_mask);
1231 dma_cap_set(DMA_INTERRUPT, cap_mask);
1232
1233 irq = irq_of_parse_and_map(np, 0);
1234 if (!irq) {
1235 ret = -ENODEV;
1236 goto err_channel_add;
1237 }
1238
1239 chan = mv_xor_channel_add(xordev, pdev, i,
1240 cap_mask, irq, op_in_desc);
1241 if (IS_ERR(chan)) {
1242 ret = PTR_ERR(chan);
1243 irq_dispose_mapping(irq);
1244 goto err_channel_add;
1245 }
1246
1247 xordev->channels[i] = chan;
1248 i++;
1249 }
1250 } else if (pdata && pdata->channels) {
1251 for (i = 0; i < max_channels; i++) {
1252 struct mv_xor_channel_data *cd;
1253 struct mv_xor_chan *chan;
1254 int irq;
1255
1256 cd = &pdata->channels[i];
1257 if (!cd) {
1258 ret = -ENODEV;
1259 goto err_channel_add;
1260 }
1261
1262 irq = platform_get_irq(pdev, i);
1263 if (irq < 0) {
1264 ret = irq;
1265 goto err_channel_add;
1266 }
1267
1268 chan = mv_xor_channel_add(xordev, pdev, i,
1269 cd->cap_mask, irq,
1270 XOR_MODE_IN_REG);
1271 if (IS_ERR(chan)) {
1272 ret = PTR_ERR(chan);
1273 goto err_channel_add;
1274 }
1275
1276 xordev->channels[i] = chan;
1277 }
1278 }
1279
1280 return 0;
1281
1282err_channel_add:
1283 for (i = 0; i < MV_XOR_MAX_CHANNELS; i++)
1284 if (xordev->channels[i]) {
1285 mv_xor_channel_remove(xordev->channels[i]);
1286 if (pdev->dev.of_node)
1287 irq_dispose_mapping(xordev->channels[i]->irq);
1288 }
1289
1290 if (!IS_ERR(xordev->clk)) {
1291 clk_disable_unprepare(xordev->clk);
1292 clk_put(xordev->clk);
1293 }
1294
1295 return ret;
1296}
1297
1298static struct platform_driver mv_xor_driver = {
1299 .probe = mv_xor_probe,
1300 .suspend = mv_xor_suspend,
1301 .resume = mv_xor_resume,
1302 .driver = {
1303 .name = MV_XOR_NAME,
1304 .of_match_table = of_match_ptr(mv_xor_dt_ids),
1305 },
1306};
1307
1308
1309static int __init mv_xor_init(void)
1310{
1311 return platform_driver_register(&mv_xor_driver);
1312}
1313device_initcall(mv_xor_init);
1314
1315/*
1316MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>");
1317MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine");
1318MODULE_LICENSE("GPL");
1319*/