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1# SPDX-License-Identifier: GPL-2.0-only
2menuconfig PM_DEVFREQ
3 bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
4 select PM_OPP
5 help
6 A device may have a list of frequencies and voltages available.
7 devfreq, a generic DVFS framework can be registered for a device
8 in order to let the governor provided to devfreq choose an
9 operating frequency based on the device driver's policy.
10
11 Each device may have its own governor and policy. Devfreq can
12 reevaluate the device state periodically and/or based on the
13 notification to "nb", a notifier block, of devfreq.
14
15 Like some CPUs with CPUfreq, a device may have multiple clocks.
16 However, because the clock frequencies of a single device are
17 determined by the single device's state, an instance of devfreq
18 is attached to a single device and returns a "representative"
19 clock frequency of the device, which is also attached
20 to a device by 1-to-1. The device registering devfreq takes the
21 responsibility to "interpret" the representative frequency and
22 to set its every clock accordingly with the "target" callback
23 given to devfreq.
24
25 When OPP is used with the devfreq device, it is recommended to
26 register devfreq's nb to the OPP's notifier head. If OPP is
27 used with the devfreq device, you may use OPP helper
28 functions defined in devfreq.h.
29
30if PM_DEVFREQ
31
32comment "DEVFREQ Governors"
33
34config DEVFREQ_GOV_SIMPLE_ONDEMAND
35 tristate "Simple Ondemand"
36 help
37 Chooses frequency based on the recent load on the device. Works
38 similar as ONDEMAND governor of CPUFREQ does. A device with
39 Simple-Ondemand should be able to provide busy/total counter
40 values that imply the usage rate. A device may provide tuned
41 values to the governor with data field at devfreq_add_device().
42
43config DEVFREQ_GOV_PERFORMANCE
44 tristate "Performance"
45 help
46 Sets the frequency at the maximum available frequency.
47 This governor always returns UINT_MAX as frequency so that
48 the DEVFREQ framework returns the highest frequency available
49 at any time.
50
51config DEVFREQ_GOV_POWERSAVE
52 tristate "Powersave"
53 help
54 Sets the frequency at the minimum available frequency.
55 This governor always returns 0 as frequency so that
56 the DEVFREQ framework returns the lowest frequency available
57 at any time.
58
59config DEVFREQ_GOV_USERSPACE
60 tristate "Userspace"
61 help
62 Sets the frequency at the user specified one.
63 This governor returns the user configured frequency if there
64 has been an input to /sys/devices/.../userspace/set_freq.
65 Otherwise, the governor does not change the frequency
66 given at the initialization.
67
68config DEVFREQ_GOV_PASSIVE
69 tristate "Passive"
70 help
71 Sets the frequency based on the frequency of its parent devfreq
72 device. This governor does not change the frequency by itself
73 through sysfs entries. The passive governor recommends that
74 devfreq device uses the OPP table to get the frequency/voltage.
75
76comment "DEVFREQ Drivers"
77
78config ARM_EXYNOS_BUS_DEVFREQ
79 tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
80 depends on ARCH_EXYNOS || COMPILE_TEST
81 select DEVFREQ_GOV_SIMPLE_ONDEMAND
82 select DEVFREQ_GOV_PASSIVE
83 select DEVFREQ_EVENT_EXYNOS_PPMU
84 select PM_DEVFREQ_EVENT
85 help
86 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
87 Memory bus has one more group of memory bus (e.g, MIF and INT block).
88 Each memory bus group could contain many memoby bus block. It reads
89 PPMU counters of memory controllers by using DEVFREQ-event device
90 and adjusts the operating frequencies and voltages with OPP support.
91 This does not yet operate with optimal voltages.
92
93config ARM_IMX_BUS_DEVFREQ
94 tristate "i.MX Generic Bus DEVFREQ Driver"
95 depends on ARCH_MXC || COMPILE_TEST
96 select DEVFREQ_GOV_USERSPACE
97 help
98 This adds the generic DEVFREQ driver for i.MX interconnects. It
99 allows adjusting NIC/NOC frequency.
100
101config ARM_IMX8M_DDRC_DEVFREQ
102 tristate "i.MX8M DDRC DEVFREQ Driver"
103 depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \
104 (COMPILE_TEST && HAVE_ARM_SMCCC)
105 select DEVFREQ_GOV_USERSPACE
106 help
107 This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
108 adjusting DRAM frequency.
109
110config ARM_TEGRA_DEVFREQ
111 tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
112 depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
113 ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
114 ARCH_TEGRA_210_SOC || \
115 COMPILE_TEST
116 depends on COMMON_CLK
117 help
118 This adds the DEVFREQ driver for the Tegra family of SoCs.
119 It reads ACTMON counters of memory controllers and adjusts the
120 operating frequencies and voltages with OPP support.
121
122config ARM_MEDIATEK_CCI_DEVFREQ
123 tristate "MEDIATEK CCI DEVFREQ Driver"
124 depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
125 select DEVFREQ_GOV_PASSIVE
126 help
127 This adds a devfreq driver for MediaTek Cache Coherent Interconnect
128 which is shared the same regulators with the cpu cluster. It can track
129 buck voltages and update a proper CCI frequency. Use the notification
130 to get the regulator status.
131
132config ARM_RK3399_DMC_DEVFREQ
133 tristate "ARM RK3399 DMC DEVFREQ Driver"
134 depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
135 (COMPILE_TEST && HAVE_ARM_SMCCC)
136 select DEVFREQ_EVENT_ROCKCHIP_DFI
137 select DEVFREQ_GOV_SIMPLE_ONDEMAND
138 select PM_DEVFREQ_EVENT
139 help
140 This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
141 It sets the frequency for the memory controller and reads the usage counts
142 from hardware.
143
144config ARM_SUN8I_A33_MBUS_DEVFREQ
145 tristate "sun8i/sun50i MBUS DEVFREQ Driver"
146 depends on ARCH_SUNXI || COMPILE_TEST
147 depends on COMMON_CLK
148 select DEVFREQ_GOV_SIMPLE_ONDEMAND
149 help
150 This adds the DEVFREQ driver for the MBUS controller in some
151 Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
152
153source "drivers/devfreq/event/Kconfig"
154
155endif # PM_DEVFREQ
1menuconfig PM_DEVFREQ
2 bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
3 select SRCU
4 help
5 A device may have a list of frequencies and voltages available.
6 devfreq, a generic DVFS framework can be registered for a device
7 in order to let the governor provided to devfreq choose an
8 operating frequency based on the device driver's policy.
9
10 Each device may have its own governor and policy. Devfreq can
11 reevaluate the device state periodically and/or based on the
12 notification to "nb", a notifier block, of devfreq.
13
14 Like some CPUs with CPUfreq, a device may have multiple clocks.
15 However, because the clock frequencies of a single device are
16 determined by the single device's state, an instance of devfreq
17 is attached to a single device and returns a "representative"
18 clock frequency of the device, which is also attached
19 to a device by 1-to-1. The device registering devfreq takes the
20 responsibility to "interpret" the representative frequency and
21 to set its every clock accordingly with the "target" callback
22 given to devfreq.
23
24 When OPP is used with the devfreq device, it is recommended to
25 register devfreq's nb to the OPP's notifier head. If OPP is
26 used with the devfreq device, you may use OPP helper
27 functions defined in devfreq.h.
28
29if PM_DEVFREQ
30
31comment "DEVFREQ Governors"
32
33config DEVFREQ_GOV_SIMPLE_ONDEMAND
34 tristate "Simple Ondemand"
35 help
36 Chooses frequency based on the recent load on the device. Works
37 similar as ONDEMAND governor of CPUFREQ does. A device with
38 Simple-Ondemand should be able to provide busy/total counter
39 values that imply the usage rate. A device may provide tuned
40 values to the governor with data field at devfreq_add_device().
41
42config DEVFREQ_GOV_PERFORMANCE
43 tristate "Performance"
44 help
45 Sets the frequency at the maximum available frequency.
46 This governor always returns UINT_MAX as frequency so that
47 the DEVFREQ framework returns the highest frequency available
48 at any time.
49
50config DEVFREQ_GOV_POWERSAVE
51 tristate "Powersave"
52 help
53 Sets the frequency at the minimum available frequency.
54 This governor always returns 0 as frequency so that
55 the DEVFREQ framework returns the lowest frequency available
56 at any time.
57
58config DEVFREQ_GOV_USERSPACE
59 tristate "Userspace"
60 help
61 Sets the frequency at the user specified one.
62 This governor returns the user configured frequency if there
63 has been an input to /sys/devices/.../power/devfreq_set_freq.
64 Otherwise, the governor does not change the frequency
65 given at the initialization.
66
67comment "DEVFREQ Drivers"
68
69config ARM_EXYNOS4_BUS_DEVFREQ
70 bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
71 depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM
72 select DEVFREQ_GOV_SIMPLE_ONDEMAND
73 select PM_OPP
74 help
75 This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
76 and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
77 It reads PPMU counters of memory controllers and adjusts
78 the operating frequencies and voltages with OPP support.
79 This does not yet operate with optimal voltages.
80
81config ARM_EXYNOS5_BUS_DEVFREQ
82 tristate "ARM Exynos5250 Bus DEVFREQ Driver"
83 depends on SOC_EXYNOS5250
84 select DEVFREQ_GOV_SIMPLE_ONDEMAND
85 select PM_OPP
86 help
87 This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int).
88 It reads PPMU counters of memory controllers and adjusts the
89 operating frequencies and voltages with OPP support.
90
91config ARM_TEGRA_DEVFREQ
92 tristate "Tegra DEVFREQ Driver"
93 depends on ARCH_TEGRA_124_SOC
94 select DEVFREQ_GOV_SIMPLE_ONDEMAND
95 select PM_OPP
96 help
97 This adds the DEVFREQ driver for the Tegra family of SoCs.
98 It reads ACTMON counters of memory controllers and adjusts the
99 operating frequencies and voltages with OPP support.
100
101source "drivers/devfreq/event/Kconfig"
102
103endif # PM_DEVFREQ