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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * AMCC SoC PPC4xx Crypto Driver
4 *
5 * Copyright (c) 2008 Applied Micro Circuits Corporation.
6 * All rights reserved. James Hsiao <jhsiao@amcc.com>
7 *
8 * This is the header file for AMCC Crypto offload Linux device driver for
9 * use with Linux CryptoAPI.
10
11 */
12
13#ifndef __CRYPTO4XX_CORE_H__
14#define __CRYPTO4XX_CORE_H__
15
16#include <linux/ratelimit.h>
17#include <linux/mutex.h>
18#include <linux/scatterlist.h>
19#include <crypto/internal/hash.h>
20#include <crypto/internal/aead.h>
21#include <crypto/internal/rng.h>
22#include <crypto/internal/skcipher.h>
23#include "crypto4xx_reg_def.h"
24#include "crypto4xx_sa.h"
25
26#define PPC460SX_SDR0_SRST 0x201
27#define PPC405EX_SDR0_SRST 0x200
28#define PPC460EX_SDR0_SRST 0x201
29#define PPC460EX_CE_RESET 0x08000000
30#define PPC460SX_CE_RESET 0x20000000
31#define PPC405EX_CE_RESET 0x00000008
32
33#define CRYPTO4XX_CRYPTO_PRIORITY 300
34#define PPC4XX_NUM_PD 256
35#define PPC4XX_LAST_PD (PPC4XX_NUM_PD - 1)
36#define PPC4XX_NUM_GD 1024
37#define PPC4XX_LAST_GD (PPC4XX_NUM_GD - 1)
38#define PPC4XX_NUM_SD 256
39#define PPC4XX_LAST_SD (PPC4XX_NUM_SD - 1)
40#define PPC4XX_SD_BUFFER_SIZE 2048
41
42#define PD_ENTRY_BUSY BIT(1)
43#define PD_ENTRY_INUSE BIT(0)
44#define PD_ENTRY_FREE 0
45#define ERING_WAS_FULL 0xffffffff
46
47struct crypto4xx_device;
48
49union shadow_sa_buf {
50 struct dynamic_sa_ctl sa;
51
52 /* alloc 256 bytes which is enough for any kind of dynamic sa */
53 u8 buf[256];
54} __packed;
55
56struct pd_uinfo {
57 struct crypto4xx_device *dev;
58 u32 state;
59 u32 first_gd; /* first gather discriptor
60 used by this packet */
61 u32 num_gd; /* number of gather discriptor
62 used by this packet */
63 u32 first_sd; /* first scatter discriptor
64 used by this packet */
65 u32 num_sd; /* number of scatter discriptors
66 used by this packet */
67 struct dynamic_sa_ctl *sa_va; /* shadow sa */
68 struct sa_state_record *sr_va; /* state record for shadow sa */
69 u32 sr_pa;
70 struct scatterlist *dest_va;
71 struct crypto_async_request *async_req; /* base crypto request
72 for this packet */
73};
74
75struct crypto4xx_device {
76 struct crypto4xx_core_device *core_dev;
77 void __iomem *ce_base;
78 void __iomem *trng_base;
79
80 struct ce_pd *pdr; /* base address of packet descriptor ring */
81 dma_addr_t pdr_pa; /* physical address of pdr_base_register */
82 struct ce_gd *gdr; /* gather descriptor ring */
83 dma_addr_t gdr_pa; /* physical address of gdr_base_register */
84 struct ce_sd *sdr; /* scatter descriptor ring */
85 dma_addr_t sdr_pa; /* physical address of sdr_base_register */
86 void *scatter_buffer_va;
87 dma_addr_t scatter_buffer_pa;
88
89 union shadow_sa_buf *shadow_sa_pool;
90 dma_addr_t shadow_sa_pool_pa;
91 struct sa_state_record *shadow_sr_pool;
92 dma_addr_t shadow_sr_pool_pa;
93 u32 pdr_tail;
94 u32 pdr_head;
95 u32 gdr_tail;
96 u32 gdr_head;
97 u32 sdr_tail;
98 u32 sdr_head;
99 struct pd_uinfo *pdr_uinfo;
100 struct list_head alg_list; /* List of algorithm supported
101 by this device */
102 struct ratelimit_state aead_ratelimit;
103 bool is_revb;
104};
105
106struct crypto4xx_core_device {
107 struct device *device;
108 struct platform_device *ofdev;
109 struct crypto4xx_device *dev;
110 struct hwrng *trng;
111 u32 int_status;
112 u32 irq;
113 struct tasklet_struct tasklet;
114 spinlock_t lock;
115 struct mutex rng_lock;
116};
117
118struct crypto4xx_ctx {
119 struct crypto4xx_device *dev;
120 struct dynamic_sa_ctl *sa_in;
121 struct dynamic_sa_ctl *sa_out;
122 __le32 iv_nonce;
123 u32 sa_len;
124 union {
125 struct crypto_sync_skcipher *cipher;
126 struct crypto_aead *aead;
127 } sw_cipher;
128};
129
130struct crypto4xx_aead_reqctx {
131 struct scatterlist dst[2];
132};
133
134struct crypto4xx_alg_common {
135 u32 type;
136 union {
137 struct skcipher_alg cipher;
138 struct ahash_alg hash;
139 struct aead_alg aead;
140 struct rng_alg rng;
141 } u;
142};
143
144struct crypto4xx_alg {
145 struct list_head entry;
146 struct crypto4xx_alg_common alg;
147 struct crypto4xx_device *dev;
148};
149
150int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size);
151void crypto4xx_free_sa(struct crypto4xx_ctx *ctx);
152void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
153int crypto4xx_build_pd(struct crypto_async_request *req,
154 struct crypto4xx_ctx *ctx,
155 struct scatterlist *src,
156 struct scatterlist *dst,
157 const unsigned int datalen,
158 const __le32 *iv, const u32 iv_len,
159 const struct dynamic_sa_ctl *sa,
160 const unsigned int sa_len,
161 const unsigned int assoclen,
162 struct scatterlist *dst_tmp);
163int crypto4xx_setkey_aes_cbc(struct crypto_skcipher *cipher,
164 const u8 *key, unsigned int keylen);
165int crypto4xx_setkey_aes_ctr(struct crypto_skcipher *cipher,
166 const u8 *key, unsigned int keylen);
167int crypto4xx_setkey_aes_ecb(struct crypto_skcipher *cipher,
168 const u8 *key, unsigned int keylen);
169int crypto4xx_setkey_rfc3686(struct crypto_skcipher *cipher,
170 const u8 *key, unsigned int keylen);
171int crypto4xx_encrypt_ctr(struct skcipher_request *req);
172int crypto4xx_decrypt_ctr(struct skcipher_request *req);
173int crypto4xx_encrypt_iv_stream(struct skcipher_request *req);
174int crypto4xx_decrypt_iv_stream(struct skcipher_request *req);
175int crypto4xx_encrypt_iv_block(struct skcipher_request *req);
176int crypto4xx_decrypt_iv_block(struct skcipher_request *req);
177int crypto4xx_encrypt_noiv_block(struct skcipher_request *req);
178int crypto4xx_decrypt_noiv_block(struct skcipher_request *req);
179int crypto4xx_rfc3686_encrypt(struct skcipher_request *req);
180int crypto4xx_rfc3686_decrypt(struct skcipher_request *req);
181int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
182int crypto4xx_hash_digest(struct ahash_request *req);
183int crypto4xx_hash_final(struct ahash_request *req);
184int crypto4xx_hash_update(struct ahash_request *req);
185int crypto4xx_hash_init(struct ahash_request *req);
186
187/*
188 * Note: Only use this function to copy items that is word aligned.
189 */
190static inline void crypto4xx_memcpy_swab32(u32 *dst, const void *buf,
191 size_t len)
192{
193 for (; len >= 4; buf += 4, len -= 4)
194 *dst++ = __swab32p((u32 *) buf);
195
196 if (len) {
197 const u8 *tmp = (u8 *)buf;
198
199 switch (len) {
200 case 3:
201 *dst = (tmp[2] << 16) |
202 (tmp[1] << 8) |
203 tmp[0];
204 break;
205 case 2:
206 *dst = (tmp[1] << 8) |
207 tmp[0];
208 break;
209 case 1:
210 *dst = tmp[0];
211 break;
212 default:
213 break;
214 }
215 }
216}
217
218static inline void crypto4xx_memcpy_from_le32(u32 *dst, const void *buf,
219 size_t len)
220{
221 crypto4xx_memcpy_swab32(dst, buf, len);
222}
223
224static inline void crypto4xx_memcpy_to_le32(__le32 *dst, const void *buf,
225 size_t len)
226{
227 crypto4xx_memcpy_swab32((u32 *)dst, buf, len);
228}
229
230int crypto4xx_setauthsize_aead(struct crypto_aead *ciper,
231 unsigned int authsize);
232int crypto4xx_setkey_aes_ccm(struct crypto_aead *cipher,
233 const u8 *key, unsigned int keylen);
234int crypto4xx_encrypt_aes_ccm(struct aead_request *req);
235int crypto4xx_decrypt_aes_ccm(struct aead_request *req);
236int crypto4xx_setkey_aes_gcm(struct crypto_aead *cipher,
237 const u8 *key, unsigned int keylen);
238int crypto4xx_encrypt_aes_gcm(struct aead_request *req);
239int crypto4xx_decrypt_aes_gcm(struct aead_request *req);
240
241#endif
1/**
2 * AMCC SoC PPC4xx Crypto Driver
3 *
4 * Copyright (c) 2008 Applied Micro Circuits Corporation.
5 * All rights reserved. James Hsiao <jhsiao@amcc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * This is the header file for AMCC Crypto offload Linux device driver for
18 * use with Linux CryptoAPI.
19
20 */
21
22#ifndef __CRYPTO4XX_CORE_H__
23#define __CRYPTO4XX_CORE_H__
24
25#include <crypto/internal/hash.h>
26
27#define PPC460SX_SDR0_SRST 0x201
28#define PPC405EX_SDR0_SRST 0x200
29#define PPC460EX_SDR0_SRST 0x201
30#define PPC460EX_CE_RESET 0x08000000
31#define PPC460SX_CE_RESET 0x20000000
32#define PPC405EX_CE_RESET 0x00000008
33
34#define CRYPTO4XX_CRYPTO_PRIORITY 300
35#define PPC4XX_LAST_PD 63
36#define PPC4XX_NUM_PD 64
37#define PPC4XX_LAST_GD 1023
38#define PPC4XX_NUM_GD 1024
39#define PPC4XX_LAST_SD 63
40#define PPC4XX_NUM_SD 64
41#define PPC4XX_SD_BUFFER_SIZE 2048
42
43#define PD_ENTRY_INUSE 1
44#define PD_ENTRY_FREE 0
45#define ERING_WAS_FULL 0xffffffff
46
47struct crypto4xx_device;
48
49struct pd_uinfo {
50 struct crypto4xx_device *dev;
51 u32 state;
52 u32 using_sd;
53 u32 first_gd; /* first gather discriptor
54 used by this packet */
55 u32 num_gd; /* number of gather discriptor
56 used by this packet */
57 u32 first_sd; /* first scatter discriptor
58 used by this packet */
59 u32 num_sd; /* number of scatter discriptors
60 used by this packet */
61 void *sa_va; /* shadow sa, when using cp from ctx->sa */
62 u32 sa_pa;
63 void *sr_va; /* state record for shadow sa */
64 u32 sr_pa;
65 struct scatterlist *dest_va;
66 struct crypto_async_request *async_req; /* base crypto request
67 for this packet */
68};
69
70struct crypto4xx_device {
71 struct crypto4xx_core_device *core_dev;
72 char *name;
73 u64 ce_phy_address;
74 void __iomem *ce_base;
75
76 void *pdr; /* base address of packet
77 descriptor ring */
78 dma_addr_t pdr_pa; /* physical address used to
79 program ce pdr_base_register */
80 void *gdr; /* gather descriptor ring */
81 dma_addr_t gdr_pa; /* physical address used to
82 program ce gdr_base_register */
83 void *sdr; /* scatter descriptor ring */
84 dma_addr_t sdr_pa; /* physical address used to
85 program ce sdr_base_register */
86 void *scatter_buffer_va;
87 dma_addr_t scatter_buffer_pa;
88 u32 scatter_buffer_size;
89
90 void *shadow_sa_pool; /* pool of memory for sa in pd_uinfo */
91 dma_addr_t shadow_sa_pool_pa;
92 void *shadow_sr_pool; /* pool of memory for sr in pd_uinfo */
93 dma_addr_t shadow_sr_pool_pa;
94 u32 pdr_tail;
95 u32 pdr_head;
96 u32 gdr_tail;
97 u32 gdr_head;
98 u32 sdr_tail;
99 u32 sdr_head;
100 void *pdr_uinfo;
101 struct list_head alg_list; /* List of algorithm supported
102 by this device */
103};
104
105struct crypto4xx_core_device {
106 struct device *device;
107 struct platform_device *ofdev;
108 struct crypto4xx_device *dev;
109 u32 int_status;
110 u32 irq;
111 struct tasklet_struct tasklet;
112 spinlock_t lock;
113};
114
115struct crypto4xx_ctx {
116 struct crypto4xx_device *dev;
117 void *sa_in;
118 dma_addr_t sa_in_dma_addr;
119 void *sa_out;
120 dma_addr_t sa_out_dma_addr;
121 void *state_record;
122 dma_addr_t state_record_dma_addr;
123 u32 sa_len;
124 u32 offset_to_sr_ptr; /* offset to state ptr, in dynamic sa */
125 u32 direction;
126 u32 next_hdr;
127 u32 save_iv;
128 u32 pd_ctl_len;
129 u32 pd_ctl;
130 u32 bypass;
131 u32 is_hash;
132 u32 hash_final;
133};
134
135struct crypto4xx_req_ctx {
136 struct crypto4xx_device *dev; /* Device in which
137 operation to send to */
138 void *sa;
139 u32 sa_dma_addr;
140 u16 sa_len;
141};
142
143struct crypto4xx_alg_common {
144 u32 type;
145 union {
146 struct crypto_alg cipher;
147 struct ahash_alg hash;
148 } u;
149};
150
151struct crypto4xx_alg {
152 struct list_head entry;
153 struct crypto4xx_alg_common alg;
154 struct crypto4xx_device *dev;
155};
156
157static inline struct crypto4xx_alg *crypto_alg_to_crypto4xx_alg(
158 struct crypto_alg *x)
159{
160 switch (x->cra_flags & CRYPTO_ALG_TYPE_MASK) {
161 case CRYPTO_ALG_TYPE_AHASH:
162 return container_of(__crypto_ahash_alg(x),
163 struct crypto4xx_alg, alg.u.hash);
164 }
165
166 return container_of(x, struct crypto4xx_alg, alg.u.cipher);
167}
168
169extern int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size);
170extern void crypto4xx_free_sa(struct crypto4xx_ctx *ctx);
171extern u32 crypto4xx_alloc_sa_rctx(struct crypto4xx_ctx *ctx,
172 struct crypto4xx_ctx *rctx);
173extern void crypto4xx_free_sa_rctx(struct crypto4xx_ctx *rctx);
174extern void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
175extern u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx);
176extern u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx *ctx);
177extern u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx);
178extern u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx);
179extern void crypto4xx_memcpy_le(unsigned int *dst,
180 const unsigned char *buf, int len);
181extern u32 crypto4xx_build_pd(struct crypto_async_request *req,
182 struct crypto4xx_ctx *ctx,
183 struct scatterlist *src,
184 struct scatterlist *dst,
185 unsigned int datalen,
186 void *iv, u32 iv_len);
187extern int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
188 const u8 *key, unsigned int keylen);
189extern int crypto4xx_encrypt(struct ablkcipher_request *req);
190extern int crypto4xx_decrypt(struct ablkcipher_request *req);
191extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
192extern int crypto4xx_hash_digest(struct ahash_request *req);
193extern int crypto4xx_hash_final(struct ahash_request *req);
194extern int crypto4xx_hash_update(struct ahash_request *req);
195extern int crypto4xx_hash_init(struct ahash_request *req);
196#endif