1#include <linux/init.h>
  2#include <linux/clocksource.h>
  3#include <linux/clockchips.h>
  4#include <linux/interrupt.h>
  5#include <linux/irq.h>
  6
  7#include <linux/clk.h>
  8#include <linux/err.h>
  9#include <linux/ioport.h>
 10#include <linux/io.h>
 11#include <linux/platform_device.h>
 12#include <linux/atmel_tc.h>
 13
 14
 15/*
 16 * We're configured to use a specific TC block, one that's not hooked
 17 * up to external hardware, to provide a time solution:
 18 *
 19 *   - Two channels combine to create a free-running 32 bit counter
 20 *     with a base rate of 5+ MHz, packaged as a clocksource (with
 21 *     resolution better than 200 nsec).
 22 *   - Some chips support 32 bit counter. A single channel is used for
 23 *     this 32 bit free-running counter. the second channel is not used.
 24 *
 25 *   - The third channel may be used to provide a 16-bit clockevent
 26 *     source, used in either periodic or oneshot mode.  This runs
 27 *     at 32 KiHZ, and can handle delays of up to two seconds.
 28 *
 29 * A boot clocksource and clockevent source are also currently needed,
 30 * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
 31 * this code can be used when init_timers() is called, well before most
 32 * devices are set up.  (Some low end AT91 parts, which can run uClinux,
 33 * have only the timers in one TC block... they currently don't support
 34 * the tclib code, because of that initialization issue.)
 35 *
 36 * REVISIT behavior during system suspend states... we should disable
 37 * all clocks and save the power.  Easily done for clockevent devices,
 38 * but clocksources won't necessarily get the needed notifications.
 39 * For deeper system sleep states, this will be mandatory...
 40 */
 41
 42static void __iomem *tcaddr;
 43
 44static cycle_t tc_get_cycles(struct clocksource *cs)
 45{
 46	unsigned long	flags;
 47	u32		lower, upper;
 48
 49	raw_local_irq_save(flags);
 50	do {
 51		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
 52		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
 53	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
 54
 55	raw_local_irq_restore(flags);
 56	return (upper << 16) | lower;
 57}
 58
 59static cycle_t tc_get_cycles32(struct clocksource *cs)
 60{
 61	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
 62}
 63
 64static struct clocksource clksrc = {
 65	.name           = "tcb_clksrc",
 66	.rating         = 200,
 67	.read           = tc_get_cycles,
 68	.mask           = CLOCKSOURCE_MASK(32),
 69	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 70};
 71
 72#ifdef CONFIG_GENERIC_CLOCKEVENTS
 73
 74struct tc_clkevt_device {
 75	struct clock_event_device	clkevt;
 76	struct clk			*clk;
 77	void __iomem			*regs;
 78};
 79
 80static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
 81{
 82	return container_of(clkevt, struct tc_clkevt_device, clkevt);
 83}
 84
 85/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
 86 * because using one of the divided clocks would usually mean the
 87 * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
 88 *
 89 * A divided clock could be good for high resolution timers, since
 90 * 30.5 usec resolution can seem "low".
 91 */
 92static u32 timer_clock;
 93
 94static int tc_shutdown(struct clock_event_device *d)
 95{
 96	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
 97	void __iomem		*regs = tcd->regs;
 98
 99	__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
100	__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
101	if (!clockevent_state_detached(d))
102		clk_disable(tcd->clk);
103
104	return 0;
105}
106
107static int tc_set_oneshot(struct clock_event_device *d)
108{
109	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
110	void __iomem		*regs = tcd->regs;
111
112	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
113		tc_shutdown(d);
114
115	clk_enable(tcd->clk);
116
117	/* slow clock, count up to RC, then irq and stop */
118	__raw_writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
119		     ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
120	__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
121
122	/* set_next_event() configures and starts the timer */
123	return 0;
124}
125
126static int tc_set_periodic(struct clock_event_device *d)
127{
128	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
129	void __iomem		*regs = tcd->regs;
130
131	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
132		tc_shutdown(d);
133
134	/* By not making the gentime core emulate periodic mode on top
135	 * of oneshot, we get lower overhead and improved accuracy.
136	 */
137	clk_enable(tcd->clk);
138
139	/* slow clock, count up to RC, then irq and restart */
140	__raw_writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
141		     regs + ATMEL_TC_REG(2, CMR));
142	__raw_writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
143
144	/* Enable clock and interrupts on RC compare */
145	__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
146
147	/* go go gadget! */
148	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs +
149		     ATMEL_TC_REG(2, CCR));
150	return 0;
151}
152
153static int tc_next_event(unsigned long delta, struct clock_event_device *d)
154{
155	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
156
157	/* go go gadget! */
158	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
159			tcaddr + ATMEL_TC_REG(2, CCR));
160	return 0;
161}
162
163static struct tc_clkevt_device clkevt = {
164	.clkevt	= {
165		.name			= "tc_clkevt",
166		.features		= CLOCK_EVT_FEAT_PERIODIC |
167					  CLOCK_EVT_FEAT_ONESHOT,
168		/* Should be lower than at91rm9200's system timer */
169		.rating			= 125,
170		.set_next_event		= tc_next_event,
171		.set_state_shutdown	= tc_shutdown,
172		.set_state_periodic	= tc_set_periodic,
173		.set_state_oneshot	= tc_set_oneshot,
174	},
175};
176
177static irqreturn_t ch2_irq(int irq, void *handle)
178{
179	struct tc_clkevt_device	*dev = handle;
180	unsigned int		sr;
181
182	sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
183	if (sr & ATMEL_TC_CPCS) {
184		dev->clkevt.event_handler(&dev->clkevt);
185		return IRQ_HANDLED;
186	}
187
188	return IRQ_NONE;
189}
190
191static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
192{
193	int ret;
194	struct clk *t2_clk = tc->clk[2];
195	int irq = tc->irq[2];
196
197	ret = clk_prepare_enable(tc->slow_clk);
198	if (ret)
199		return ret;
200
201	/* try to enable t2 clk to avoid future errors in mode change */
202	ret = clk_prepare_enable(t2_clk);
203	if (ret) {
204		clk_disable_unprepare(tc->slow_clk);
205		return ret;
206	}
207
208	clk_disable(t2_clk);
209
210	clkevt.regs = tc->regs;
211	clkevt.clk = t2_clk;
212
213	timer_clock = clk32k_divisor_idx;
214
215	clkevt.clkevt.cpumask = cpumask_of(0);
216
217	ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt);
218	if (ret) {
219		clk_unprepare(t2_clk);
220		clk_disable_unprepare(tc->slow_clk);
221		return ret;
222	}
223
224	clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
225
226	return ret;
227}
228
229#else /* !CONFIG_GENERIC_CLOCKEVENTS */
230
231static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
232{
233	/* NOTHING */
234	return 0;
235}
236
237#endif
238
239static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx)
240{
241	/* channel 0:  waveform mode, input mclk/8, clock TIOA0 on overflow */
242	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
243			| ATMEL_TC_WAVE
244			| ATMEL_TC_WAVESEL_UP		/* free-run */
245			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */
246			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */
247			tcaddr + ATMEL_TC_REG(0, CMR));
248	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
249	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
250	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
251	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
252
253	/* channel 1:  waveform mode, input TIOA0 */
254	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */
255			| ATMEL_TC_WAVE
256			| ATMEL_TC_WAVESEL_UP,		/* free-run */
257			tcaddr + ATMEL_TC_REG(1, CMR));
258	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */
259	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
260
261	/* chain channel 0 to channel 1*/
262	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
263	/* then reset all the timers */
264	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
265}
266
267static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx)
268{
269	/* channel 0:  waveform mode, input mclk/8 */
270	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */
271			| ATMEL_TC_WAVE
272			| ATMEL_TC_WAVESEL_UP,		/* free-run */
273			tcaddr + ATMEL_TC_REG(0, CMR));
274	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */
275	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
276
277	/* then reset all the timers */
278	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
279}
280
281static int __init tcb_clksrc_init(void)
282{
283	static char bootinfo[] __initdata
284		= KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
285
286	struct platform_device *pdev;
287	struct atmel_tc *tc;
288	struct clk *t0_clk;
289	u32 rate, divided_rate = 0;
290	int best_divisor_idx = -1;
291	int clk32k_divisor_idx = -1;
292	int i;
293	int ret;
294
295	tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK);
296	if (!tc) {
297		pr_debug("can't alloc TC for clocksource\n");
298		return -ENODEV;
299	}
300	tcaddr = tc->regs;
301	pdev = tc->pdev;
302
303	t0_clk = tc->clk[0];
304	ret = clk_prepare_enable(t0_clk);
305	if (ret) {
306		pr_debug("can't enable T0 clk\n");
307		goto err_free_tc;
308	}
309
310	/* How fast will we be counting?  Pick something over 5 MHz.  */
311	rate = (u32) clk_get_rate(t0_clk);
312	for (i = 0; i < 5; i++) {
313		unsigned divisor = atmel_tc_divisors[i];
314		unsigned tmp;
315
316		/* remember 32 KiHz clock for later */
317		if (!divisor) {
318			clk32k_divisor_idx = i;
319			continue;
320		}
321
322		tmp = rate / divisor;
323		pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
324		if (best_divisor_idx > 0) {
325			if (tmp < 5 * 1000 * 1000)
326				continue;
327		}
328		divided_rate = tmp;
329		best_divisor_idx = i;
330	}
331
332
333	printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
334			divided_rate / 1000000,
335			((divided_rate + 500000) % 1000000) / 1000);
336
337	if (tc->tcb_config && tc->tcb_config->counter_width == 32) {
338		/* use apropriate function to read 32 bit counter */
339		clksrc.read = tc_get_cycles32;
340		/* setup ony channel 0 */
341		tcb_setup_single_chan(tc, best_divisor_idx);
342	} else {
343		/* tclib will give us three clocks no matter what the
344		 * underlying platform supports.
345		 */
346		ret = clk_prepare_enable(tc->clk[1]);
347		if (ret) {
348			pr_debug("can't enable T1 clk\n");
349			goto err_disable_t0;
350		}
351		/* setup both channel 0 & 1 */
352		tcb_setup_dual_chan(tc, best_divisor_idx);
353	}
354
355	/* and away we go! */
356	ret = clocksource_register_hz(&clksrc, divided_rate);
357	if (ret)
358		goto err_disable_t1;
359
360	/* channel 2:  periodic and oneshot timer support */
361	ret = setup_clkevents(tc, clk32k_divisor_idx);
362	if (ret)
363		goto err_unregister_clksrc;
364
365	return 0;
366
367err_unregister_clksrc:
368	clocksource_unregister(&clksrc);
369
370err_disable_t1:
371	if (!tc->tcb_config || tc->tcb_config->counter_width != 32)
372		clk_disable_unprepare(tc->clk[1]);
373
374err_disable_t0:
375	clk_disable_unprepare(t0_clk);
376
377err_free_tc:
378	atmel_tc_free(tc);
379	return ret;
380}
381arch_initcall(tcb_clksrc_init);