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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
4 * initial domain support. We also handle the DSDT _PRT callbacks for GSI's
5 * used in HVM and initial domain mode (PV does not parse ACPI, so it has no
6 * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
7 * 0xcf8 PCI configuration read/write.
8 *
9 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
10 * Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
11 * Stefano Stabellini <stefano.stabellini@eu.citrix.com>
12 */
13#include <linux/export.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/acpi.h>
17
18#include <linux/io.h>
19#include <asm/io_apic.h>
20#include <asm/pci_x86.h>
21
22#include <asm/xen/hypervisor.h>
23
24#include <xen/features.h>
25#include <xen/events.h>
26#include <xen/pci.h>
27#include <asm/xen/pci.h>
28#include <asm/xen/cpuid.h>
29#include <asm/apic.h>
30#include <asm/acpi.h>
31#include <asm/i8259.h>
32
33static int xen_pcifront_enable_irq(struct pci_dev *dev)
34{
35 int rc;
36 int share = 1;
37 int pirq;
38 u8 gsi;
39
40 rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
41 if (rc < 0) {
42 dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
43 rc);
44 return rc;
45 }
46 /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
47 pirq = gsi;
48
49 if (gsi < nr_legacy_irqs())
50 share = 0;
51
52 rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
53 if (rc < 0) {
54 dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
55 gsi, pirq, rc);
56 return rc;
57 }
58
59 dev->irq = rc;
60 dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
61 return 0;
62}
63
64#ifdef CONFIG_ACPI
65static int xen_register_pirq(u32 gsi, int triggering, bool set_pirq)
66{
67 int rc, pirq = -1, irq;
68 struct physdev_map_pirq map_irq;
69 int shareable = 0;
70 char *name;
71
72 irq = xen_irq_from_gsi(gsi);
73 if (irq > 0)
74 return irq;
75
76 if (set_pirq)
77 pirq = gsi;
78
79 map_irq.domid = DOMID_SELF;
80 map_irq.type = MAP_PIRQ_TYPE_GSI;
81 map_irq.index = gsi;
82 map_irq.pirq = pirq;
83
84 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
85 if (rc) {
86 printk(KERN_WARNING "xen map irq failed %d\n", rc);
87 return -1;
88 }
89
90 if (triggering == ACPI_EDGE_SENSITIVE) {
91 shareable = 0;
92 name = "ioapic-edge";
93 } else {
94 shareable = 1;
95 name = "ioapic-level";
96 }
97
98 irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
99 if (irq < 0)
100 goto out;
101
102 printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
103out:
104 return irq;
105}
106
107static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
108 int trigger, int polarity)
109{
110 if (!xen_hvm_domain())
111 return -1;
112
113 return xen_register_pirq(gsi, trigger,
114 false /* no mapping of GSI to PIRQ */);
115}
116
117#ifdef CONFIG_XEN_PV_DOM0
118static int xen_register_gsi(u32 gsi, int triggering, int polarity)
119{
120 int rc, irq;
121 struct physdev_setup_gsi setup_gsi;
122
123 if (!xen_pv_domain())
124 return -1;
125
126 printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
127 gsi, triggering, polarity);
128
129 irq = xen_register_pirq(gsi, triggering, true);
130
131 setup_gsi.gsi = gsi;
132 setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
133 setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
134
135 rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
136 if (rc == -EEXIST)
137 printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
138 else if (rc) {
139 printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
140 gsi, rc);
141 }
142
143 return irq;
144}
145
146static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
147 int trigger, int polarity)
148{
149 return xen_register_gsi(gsi, trigger, polarity);
150}
151#endif
152#endif
153
154#if defined(CONFIG_PCI_MSI)
155#include <linux/msi.h>
156
157struct xen_pci_frontend_ops *xen_pci_frontend;
158EXPORT_SYMBOL_GPL(xen_pci_frontend);
159
160struct xen_msi_ops {
161 int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
162 void (*teardown_msi_irqs)(struct pci_dev *dev);
163};
164
165static struct xen_msi_ops xen_msi_ops __ro_after_init;
166
167static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
168{
169 int irq, ret, i;
170 struct msi_desc *msidesc;
171 int *v;
172
173 if (type == PCI_CAP_ID_MSI && nvec > 1)
174 return 1;
175
176 v = kcalloc(max(1, nvec), sizeof(int), GFP_KERNEL);
177 if (!v)
178 return -ENOMEM;
179
180 if (type == PCI_CAP_ID_MSIX)
181 ret = xen_pci_frontend_enable_msix(dev, v, nvec);
182 else
183 ret = xen_pci_frontend_enable_msi(dev, v);
184 if (ret)
185 goto error;
186 i = 0;
187 msi_for_each_desc(msidesc, &dev->dev, MSI_DESC_NOTASSOCIATED) {
188 irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
189 (type == PCI_CAP_ID_MSI) ? nvec : 1,
190 (type == PCI_CAP_ID_MSIX) ?
191 "pcifront-msi-x" :
192 "pcifront-msi",
193 DOMID_SELF);
194 if (irq < 0) {
195 ret = irq;
196 goto free;
197 }
198 i++;
199 }
200 kfree(v);
201 return msi_device_populate_sysfs(&dev->dev);
202
203error:
204 if (ret == -ENOSYS)
205 dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
206 else if (ret)
207 dev_err(&dev->dev, "Xen PCI frontend error: %d!\n", ret);
208free:
209 kfree(v);
210 return ret;
211}
212
213static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
214 struct msi_msg *msg)
215{
216 /*
217 * We set vector == 0 to tell the hypervisor we don't care about
218 * it, but we want a pirq setup instead. We use the dest_id fields
219 * to pass the pirq that we want.
220 */
221 memset(msg, 0, sizeof(*msg));
222 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
223 msg->arch_addr_hi.destid_8_31 = pirq >> 8;
224 msg->arch_addr_lo.destid_0_7 = pirq & 0xFF;
225 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
226 msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
227}
228
229static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
230{
231 int irq, pirq;
232 struct msi_desc *msidesc;
233 struct msi_msg msg;
234
235 if (type == PCI_CAP_ID_MSI && nvec > 1)
236 return 1;
237
238 msi_for_each_desc(msidesc, &dev->dev, MSI_DESC_NOTASSOCIATED) {
239 pirq = xen_allocate_pirq_msi(dev, msidesc);
240 if (pirq < 0) {
241 irq = -ENODEV;
242 goto error;
243 }
244 xen_msi_compose_msg(dev, pirq, &msg);
245 __pci_write_msi_msg(msidesc, &msg);
246 dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
247 irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
248 (type == PCI_CAP_ID_MSI) ? nvec : 1,
249 (type == PCI_CAP_ID_MSIX) ?
250 "msi-x" : "msi",
251 DOMID_SELF);
252 if (irq < 0)
253 goto error;
254 dev_dbg(&dev->dev,
255 "xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
256 }
257 return msi_device_populate_sysfs(&dev->dev);
258
259error:
260 dev_err(&dev->dev, "Failed to create MSI%s! ret=%d!\n",
261 type == PCI_CAP_ID_MSI ? "" : "-X", irq);
262 return irq;
263}
264
265#ifdef CONFIG_XEN_PV_DOM0
266static bool __read_mostly pci_seg_supported = true;
267
268static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
269{
270 int ret = 0;
271 struct msi_desc *msidesc;
272
273 msi_for_each_desc(msidesc, &dev->dev, MSI_DESC_NOTASSOCIATED) {
274 struct physdev_map_pirq map_irq;
275 domid_t domid;
276
277 domid = ret = xen_find_device_domain_owner(dev);
278 /* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
279 * hence check ret value for < 0. */
280 if (ret < 0)
281 domid = DOMID_SELF;
282
283 memset(&map_irq, 0, sizeof(map_irq));
284 map_irq.domid = domid;
285 map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
286 map_irq.index = -1;
287 map_irq.pirq = -1;
288 map_irq.bus = dev->bus->number |
289 (pci_domain_nr(dev->bus) << 16);
290 map_irq.devfn = dev->devfn;
291
292 if (type == PCI_CAP_ID_MSI && nvec > 1) {
293 map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
294 map_irq.entry_nr = nvec;
295 } else if (type == PCI_CAP_ID_MSIX) {
296 int pos;
297 unsigned long flags;
298 u32 table_offset, bir;
299
300 pos = dev->msix_cap;
301 pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
302 &table_offset);
303 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
304 flags = pci_resource_flags(dev, bir);
305 if (!flags || (flags & IORESOURCE_UNSET))
306 return -EINVAL;
307
308 map_irq.table_base = pci_resource_start(dev, bir);
309 map_irq.entry_nr = msidesc->msi_index;
310 }
311
312 ret = -EINVAL;
313 if (pci_seg_supported)
314 ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
315 &map_irq);
316 if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
317 /*
318 * If MAP_PIRQ_TYPE_MULTI_MSI is not available
319 * there's nothing else we can do in this case.
320 * Just set ret > 0 so driver can retry with
321 * single MSI.
322 */
323 ret = 1;
324 goto out;
325 }
326 if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
327 map_irq.type = MAP_PIRQ_TYPE_MSI;
328 map_irq.index = -1;
329 map_irq.pirq = -1;
330 map_irq.bus = dev->bus->number;
331 ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
332 &map_irq);
333 if (ret != -EINVAL)
334 pci_seg_supported = false;
335 }
336 if (ret) {
337 dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
338 ret, domid);
339 goto out;
340 }
341
342 ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
343 (type == PCI_CAP_ID_MSI) ? nvec : 1,
344 (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
345 domid);
346 if (ret < 0)
347 goto out;
348 }
349 ret = msi_device_populate_sysfs(&dev->dev);
350out:
351 return ret;
352}
353
354bool xen_initdom_restore_msi(struct pci_dev *dev)
355{
356 int ret = 0;
357
358 if (!xen_initial_domain())
359 return true;
360
361 if (pci_seg_supported) {
362 struct physdev_pci_device restore_ext;
363
364 restore_ext.seg = pci_domain_nr(dev->bus);
365 restore_ext.bus = dev->bus->number;
366 restore_ext.devfn = dev->devfn;
367 ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
368 &restore_ext);
369 if (ret == -ENOSYS)
370 pci_seg_supported = false;
371 WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
372 }
373 if (!pci_seg_supported) {
374 struct physdev_restore_msi restore;
375
376 restore.bus = dev->bus->number;
377 restore.devfn = dev->devfn;
378 ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
379 WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
380 }
381 return false;
382}
383#else /* CONFIG_XEN_PV_DOM0 */
384#define xen_initdom_setup_msi_irqs NULL
385#endif /* !CONFIG_XEN_PV_DOM0 */
386
387static void xen_teardown_msi_irqs(struct pci_dev *dev)
388{
389 struct msi_desc *msidesc;
390 int i;
391
392 msi_for_each_desc(msidesc, &dev->dev, MSI_DESC_ASSOCIATED) {
393 for (i = 0; i < msidesc->nvec_used; i++)
394 xen_destroy_irq(msidesc->irq + i);
395 msidesc->irq = 0;
396 }
397
398 msi_device_destroy_sysfs(&dev->dev);
399}
400
401static void xen_pv_teardown_msi_irqs(struct pci_dev *dev)
402{
403 if (dev->msix_enabled)
404 xen_pci_frontend_disable_msix(dev);
405 else
406 xen_pci_frontend_disable_msi(dev);
407
408 xen_teardown_msi_irqs(dev);
409}
410
411static int xen_msi_domain_alloc_irqs(struct irq_domain *domain,
412 struct device *dev, int nvec)
413{
414 int type;
415
416 if (WARN_ON_ONCE(!dev_is_pci(dev)))
417 return -EINVAL;
418
419 type = to_pci_dev(dev)->msix_enabled ? PCI_CAP_ID_MSIX : PCI_CAP_ID_MSI;
420
421 return xen_msi_ops.setup_msi_irqs(to_pci_dev(dev), nvec, type);
422}
423
424static void xen_msi_domain_free_irqs(struct irq_domain *domain,
425 struct device *dev)
426{
427 if (WARN_ON_ONCE(!dev_is_pci(dev)))
428 return;
429
430 xen_msi_ops.teardown_msi_irqs(to_pci_dev(dev));
431}
432
433static struct msi_domain_ops xen_pci_msi_domain_ops = {
434 .domain_alloc_irqs = xen_msi_domain_alloc_irqs,
435 .domain_free_irqs = xen_msi_domain_free_irqs,
436};
437
438static struct msi_domain_info xen_pci_msi_domain_info = {
439 .flags = MSI_FLAG_PCI_MSIX | MSI_FLAG_FREE_MSI_DESCS | MSI_FLAG_DEV_SYSFS,
440 .ops = &xen_pci_msi_domain_ops,
441};
442
443/*
444 * This irq domain is a blatant violation of the irq domain design, but
445 * distangling XEN into real irq domains is not a job for mere mortals with
446 * limited XENology. But it's the least dangerous way for a mere mortal to
447 * get rid of the arch_*_msi_irqs() hackery in order to store the irq
448 * domain pointer in struct device. This irq domain wrappery allows to do
449 * that without breaking XEN terminally.
450 */
451static __init struct irq_domain *xen_create_pci_msi_domain(void)
452{
453 struct irq_domain *d = NULL;
454 struct fwnode_handle *fn;
455
456 fn = irq_domain_alloc_named_fwnode("XEN-MSI");
457 if (fn)
458 d = msi_create_irq_domain(fn, &xen_pci_msi_domain_info, NULL);
459
460 /* FIXME: No idea how to survive if this fails */
461 BUG_ON(!d);
462
463 return d;
464}
465
466static __init void xen_setup_pci_msi(void)
467{
468 if (xen_pv_domain()) {
469 if (xen_initial_domain())
470 xen_msi_ops.setup_msi_irqs = xen_initdom_setup_msi_irqs;
471 else
472 xen_msi_ops.setup_msi_irqs = xen_setup_msi_irqs;
473 xen_msi_ops.teardown_msi_irqs = xen_pv_teardown_msi_irqs;
474 } else if (xen_hvm_domain()) {
475 xen_msi_ops.setup_msi_irqs = xen_hvm_setup_msi_irqs;
476 xen_msi_ops.teardown_msi_irqs = xen_teardown_msi_irqs;
477 } else {
478 WARN_ON_ONCE(1);
479 return;
480 }
481
482 /*
483 * Override the PCI/MSI irq domain init function. No point
484 * in allocating the native domain and never use it.
485 */
486 x86_init.irqs.create_pci_msi_domain = xen_create_pci_msi_domain;
487 /*
488 * With XEN PIRQ/Eventchannels in use PCI/MSI[-X] masking is solely
489 * controlled by the hypervisor.
490 */
491 pci_msi_ignore_mask = 1;
492}
493
494#else /* CONFIG_PCI_MSI */
495static inline void xen_setup_pci_msi(void) { }
496#endif /* CONFIG_PCI_MSI */
497
498int __init pci_xen_init(void)
499{
500 if (!xen_pv_domain() || xen_initial_domain())
501 return -ENODEV;
502
503 printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
504
505 pcibios_set_cache_line_size();
506
507 pcibios_enable_irq = xen_pcifront_enable_irq;
508 pcibios_disable_irq = NULL;
509
510 /* Keep ACPI out of the picture */
511 acpi_noirq_set();
512
513 xen_setup_pci_msi();
514 return 0;
515}
516
517#ifdef CONFIG_PCI_MSI
518static void __init xen_hvm_msi_init(void)
519{
520 if (!apic_is_disabled) {
521 /*
522 * If hardware supports (x2)APIC virtualization (as indicated
523 * by hypervisor's leaf 4) then we don't need to use pirqs/
524 * event channels for MSI handling and instead use regular
525 * APIC processing
526 */
527 uint32_t eax = cpuid_eax(xen_cpuid_base() + 4);
528
529 if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) ||
530 ((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && boot_cpu_has(X86_FEATURE_APIC)))
531 return;
532 }
533 xen_setup_pci_msi();
534}
535#endif
536
537int __init pci_xen_hvm_init(void)
538{
539 if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs))
540 return 0;
541
542#ifdef CONFIG_ACPI
543 /*
544 * We don't want to change the actual ACPI delivery model,
545 * just how GSIs get registered.
546 */
547 __acpi_register_gsi = acpi_register_gsi_xen_hvm;
548 __acpi_unregister_gsi = NULL;
549#endif
550
551#ifdef CONFIG_PCI_MSI
552 /*
553 * We need to wait until after x2apic is initialized
554 * before we can set MSI IRQ ops.
555 */
556 x86_platform.apic_post_init = xen_hvm_msi_init;
557#endif
558 return 0;
559}
560
561#ifdef CONFIG_XEN_PV_DOM0
562int __init pci_xen_initial_domain(void)
563{
564 int irq;
565
566 xen_setup_pci_msi();
567 __acpi_register_gsi = acpi_register_gsi_xen;
568 __acpi_unregister_gsi = NULL;
569 /*
570 * Pre-allocate the legacy IRQs. Use NR_LEGACY_IRQS here
571 * because we don't have a PIC and thus nr_legacy_irqs() is zero.
572 */
573 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
574 int trigger, polarity;
575
576 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
577 continue;
578
579 xen_register_pirq(irq,
580 trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
581 true /* Map GSI to PIRQ */);
582 }
583 if (0 == nr_ioapics) {
584 for (irq = 0; irq < nr_legacy_irqs(); irq++)
585 xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
586 }
587 return 0;
588}
589#endif
590
1/*
2 * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
3 * initial domain support. We also handle the DSDT _PRT callbacks for GSI's
4 * used in HVM and initial domain mode (PV does not parse ACPI, so it has no
5 * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
6 * 0xcf8 PCI configuration read/write.
7 *
8 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
9 * Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
10 * Stefano Stabellini <stefano.stabellini@eu.citrix.com>
11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/acpi.h>
16
17#include <linux/io.h>
18#include <asm/io_apic.h>
19#include <asm/pci_x86.h>
20
21#include <asm/xen/hypervisor.h>
22
23#include <xen/features.h>
24#include <xen/events.h>
25#include <asm/xen/pci.h>
26#include <asm/xen/cpuid.h>
27#include <asm/apic.h>
28#include <asm/i8259.h>
29
30static int xen_pcifront_enable_irq(struct pci_dev *dev)
31{
32 int rc;
33 int share = 1;
34 int pirq;
35 u8 gsi;
36
37 rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
38 if (rc < 0) {
39 dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
40 rc);
41 return rc;
42 }
43 /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
44 pirq = gsi;
45
46 if (gsi < nr_legacy_irqs())
47 share = 0;
48
49 rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
50 if (rc < 0) {
51 dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
52 gsi, pirq, rc);
53 return rc;
54 }
55
56 dev->irq = rc;
57 dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
58 return 0;
59}
60
61#ifdef CONFIG_ACPI
62static int xen_register_pirq(u32 gsi, int gsi_override, int triggering,
63 bool set_pirq)
64{
65 int rc, pirq = -1, irq = -1;
66 struct physdev_map_pirq map_irq;
67 int shareable = 0;
68 char *name;
69
70 irq = xen_irq_from_gsi(gsi);
71 if (irq > 0)
72 return irq;
73
74 if (set_pirq)
75 pirq = gsi;
76
77 map_irq.domid = DOMID_SELF;
78 map_irq.type = MAP_PIRQ_TYPE_GSI;
79 map_irq.index = gsi;
80 map_irq.pirq = pirq;
81
82 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
83 if (rc) {
84 printk(KERN_WARNING "xen map irq failed %d\n", rc);
85 return -1;
86 }
87
88 if (triggering == ACPI_EDGE_SENSITIVE) {
89 shareable = 0;
90 name = "ioapic-edge";
91 } else {
92 shareable = 1;
93 name = "ioapic-level";
94 }
95
96 if (gsi_override >= 0)
97 gsi = gsi_override;
98
99 irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
100 if (irq < 0)
101 goto out;
102
103 printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
104out:
105 return irq;
106}
107
108static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
109 int trigger, int polarity)
110{
111 if (!xen_hvm_domain())
112 return -1;
113
114 return xen_register_pirq(gsi, -1 /* no GSI override */, trigger,
115 false /* no mapping of GSI to PIRQ */);
116}
117
118#ifdef CONFIG_XEN_DOM0
119static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity)
120{
121 int rc, irq;
122 struct physdev_setup_gsi setup_gsi;
123
124 if (!xen_pv_domain())
125 return -1;
126
127 printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
128 gsi, triggering, polarity);
129
130 irq = xen_register_pirq(gsi, gsi_override, triggering, true);
131
132 setup_gsi.gsi = gsi;
133 setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
134 setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
135
136 rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
137 if (rc == -EEXIST)
138 printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
139 else if (rc) {
140 printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
141 gsi, rc);
142 }
143
144 return irq;
145}
146
147static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
148 int trigger, int polarity)
149{
150 return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity);
151}
152#endif
153#endif
154
155#if defined(CONFIG_PCI_MSI)
156#include <linux/msi.h>
157#include <asm/msidef.h>
158
159struct xen_pci_frontend_ops *xen_pci_frontend;
160EXPORT_SYMBOL_GPL(xen_pci_frontend);
161
162static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
163{
164 int irq, ret, i;
165 struct msi_desc *msidesc;
166 int *v;
167
168 if (type == PCI_CAP_ID_MSI && nvec > 1)
169 return 1;
170
171 v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL);
172 if (!v)
173 return -ENOMEM;
174
175 if (type == PCI_CAP_ID_MSIX)
176 ret = xen_pci_frontend_enable_msix(dev, v, nvec);
177 else
178 ret = xen_pci_frontend_enable_msi(dev, v);
179 if (ret)
180 goto error;
181 i = 0;
182 for_each_pci_msi_entry(msidesc, dev) {
183 irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
184 (type == PCI_CAP_ID_MSI) ? nvec : 1,
185 (type == PCI_CAP_ID_MSIX) ?
186 "pcifront-msi-x" :
187 "pcifront-msi",
188 DOMID_SELF);
189 if (irq < 0) {
190 ret = irq;
191 goto free;
192 }
193 i++;
194 }
195 kfree(v);
196 return 0;
197
198error:
199 if (ret == -ENOSYS)
200 dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
201 else if (ret)
202 dev_err(&dev->dev, "Xen PCI frontend error: %d!\n", ret);
203free:
204 kfree(v);
205 return ret;
206}
207
208#define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE | \
209 MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0))
210
211static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
212 struct msi_msg *msg)
213{
214 /* We set vector == 0 to tell the hypervisor we don't care about it,
215 * but we want a pirq setup instead.
216 * We use the dest_id field to pass the pirq that we want. */
217 msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq);
218 msg->address_lo =
219 MSI_ADDR_BASE_LO |
220 MSI_ADDR_DEST_MODE_PHYSICAL |
221 MSI_ADDR_REDIRECTION_CPU |
222 MSI_ADDR_DEST_ID(pirq);
223
224 msg->data = XEN_PIRQ_MSI_DATA;
225}
226
227static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
228{
229 int irq, pirq;
230 struct msi_desc *msidesc;
231 struct msi_msg msg;
232
233 if (type == PCI_CAP_ID_MSI && nvec > 1)
234 return 1;
235
236 for_each_pci_msi_entry(msidesc, dev) {
237 __pci_read_msi_msg(msidesc, &msg);
238 pirq = MSI_ADDR_EXT_DEST_ID(msg.address_hi) |
239 ((msg.address_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff);
240 if (msg.data != XEN_PIRQ_MSI_DATA ||
241 xen_irq_from_pirq(pirq) < 0) {
242 pirq = xen_allocate_pirq_msi(dev, msidesc);
243 if (pirq < 0) {
244 irq = -ENODEV;
245 goto error;
246 }
247 xen_msi_compose_msg(dev, pirq, &msg);
248 __pci_write_msi_msg(msidesc, &msg);
249 dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
250 } else {
251 dev_dbg(&dev->dev,
252 "xen: msi already bound to pirq=%d\n", pirq);
253 }
254 irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
255 (type == PCI_CAP_ID_MSI) ? nvec : 1,
256 (type == PCI_CAP_ID_MSIX) ?
257 "msi-x" : "msi",
258 DOMID_SELF);
259 if (irq < 0)
260 goto error;
261 dev_dbg(&dev->dev,
262 "xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
263 }
264 return 0;
265
266error:
267 dev_err(&dev->dev,
268 "Xen PCI frontend has not registered MSI/MSI-X support!\n");
269 return irq;
270}
271
272#ifdef CONFIG_XEN_DOM0
273static bool __read_mostly pci_seg_supported = true;
274
275static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
276{
277 int ret = 0;
278 struct msi_desc *msidesc;
279
280 for_each_pci_msi_entry(msidesc, dev) {
281 struct physdev_map_pirq map_irq;
282 domid_t domid;
283
284 domid = ret = xen_find_device_domain_owner(dev);
285 /* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
286 * hence check ret value for < 0. */
287 if (ret < 0)
288 domid = DOMID_SELF;
289
290 memset(&map_irq, 0, sizeof(map_irq));
291 map_irq.domid = domid;
292 map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
293 map_irq.index = -1;
294 map_irq.pirq = -1;
295 map_irq.bus = dev->bus->number |
296 (pci_domain_nr(dev->bus) << 16);
297 map_irq.devfn = dev->devfn;
298
299 if (type == PCI_CAP_ID_MSI && nvec > 1) {
300 map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
301 map_irq.entry_nr = nvec;
302 } else if (type == PCI_CAP_ID_MSIX) {
303 int pos;
304 unsigned long flags;
305 u32 table_offset, bir;
306
307 pos = dev->msix_cap;
308 pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
309 &table_offset);
310 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
311 flags = pci_resource_flags(dev, bir);
312 if (!flags || (flags & IORESOURCE_UNSET))
313 return -EINVAL;
314
315 map_irq.table_base = pci_resource_start(dev, bir);
316 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
317 }
318
319 ret = -EINVAL;
320 if (pci_seg_supported)
321 ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
322 &map_irq);
323 if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
324 /*
325 * If MAP_PIRQ_TYPE_MULTI_MSI is not available
326 * there's nothing else we can do in this case.
327 * Just set ret > 0 so driver can retry with
328 * single MSI.
329 */
330 ret = 1;
331 goto out;
332 }
333 if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
334 map_irq.type = MAP_PIRQ_TYPE_MSI;
335 map_irq.index = -1;
336 map_irq.pirq = -1;
337 map_irq.bus = dev->bus->number;
338 ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
339 &map_irq);
340 if (ret != -EINVAL)
341 pci_seg_supported = false;
342 }
343 if (ret) {
344 dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
345 ret, domid);
346 goto out;
347 }
348
349 ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
350 (type == PCI_CAP_ID_MSI) ? nvec : 1,
351 (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
352 domid);
353 if (ret < 0)
354 goto out;
355 }
356 ret = 0;
357out:
358 return ret;
359}
360
361static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
362{
363 int ret = 0;
364
365 if (pci_seg_supported) {
366 struct physdev_pci_device restore_ext;
367
368 restore_ext.seg = pci_domain_nr(dev->bus);
369 restore_ext.bus = dev->bus->number;
370 restore_ext.devfn = dev->devfn;
371 ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
372 &restore_ext);
373 if (ret == -ENOSYS)
374 pci_seg_supported = false;
375 WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
376 }
377 if (!pci_seg_supported) {
378 struct physdev_restore_msi restore;
379
380 restore.bus = dev->bus->number;
381 restore.devfn = dev->devfn;
382 ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
383 WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
384 }
385}
386#endif
387
388static void xen_teardown_msi_irqs(struct pci_dev *dev)
389{
390 struct msi_desc *msidesc;
391
392 msidesc = first_pci_msi_entry(dev);
393 if (msidesc->msi_attrib.is_msix)
394 xen_pci_frontend_disable_msix(dev);
395 else
396 xen_pci_frontend_disable_msi(dev);
397
398 /* Free the IRQ's and the msidesc using the generic code. */
399 default_teardown_msi_irqs(dev);
400}
401
402static void xen_teardown_msi_irq(unsigned int irq)
403{
404 xen_destroy_irq(irq);
405}
406
407#endif
408
409int __init pci_xen_init(void)
410{
411 if (!xen_pv_domain() || xen_initial_domain())
412 return -ENODEV;
413
414 printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
415
416 pcibios_set_cache_line_size();
417
418 pcibios_enable_irq = xen_pcifront_enable_irq;
419 pcibios_disable_irq = NULL;
420
421#ifdef CONFIG_ACPI
422 /* Keep ACPI out of the picture */
423 acpi_noirq = 1;
424#endif
425
426#ifdef CONFIG_PCI_MSI
427 x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
428 x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
429 x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
430 pci_msi_ignore_mask = 1;
431#endif
432 return 0;
433}
434
435#ifdef CONFIG_PCI_MSI
436void __init xen_msi_init(void)
437{
438 if (!disable_apic) {
439 /*
440 * If hardware supports (x2)APIC virtualization (as indicated
441 * by hypervisor's leaf 4) then we don't need to use pirqs/
442 * event channels for MSI handling and instead use regular
443 * APIC processing
444 */
445 uint32_t eax = cpuid_eax(xen_cpuid_base() + 4);
446
447 if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) ||
448 ((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && cpu_has_apic))
449 return;
450 }
451
452 x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs;
453 x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
454}
455#endif
456
457int __init pci_xen_hvm_init(void)
458{
459 if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs))
460 return 0;
461
462#ifdef CONFIG_ACPI
463 /*
464 * We don't want to change the actual ACPI delivery model,
465 * just how GSIs get registered.
466 */
467 __acpi_register_gsi = acpi_register_gsi_xen_hvm;
468 __acpi_unregister_gsi = NULL;
469#endif
470
471#ifdef CONFIG_PCI_MSI
472 /*
473 * We need to wait until after x2apic is initialized
474 * before we can set MSI IRQ ops.
475 */
476 x86_platform.apic_post_init = xen_msi_init;
477#endif
478 return 0;
479}
480
481#ifdef CONFIG_XEN_DOM0
482int __init pci_xen_initial_domain(void)
483{
484 int irq;
485
486#ifdef CONFIG_PCI_MSI
487 x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
488 x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
489 x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
490 pci_msi_ignore_mask = 1;
491#endif
492 __acpi_register_gsi = acpi_register_gsi_xen;
493 __acpi_unregister_gsi = NULL;
494 /* Pre-allocate legacy irqs */
495 for (irq = 0; irq < nr_legacy_irqs(); irq++) {
496 int trigger, polarity;
497
498 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
499 continue;
500
501 xen_register_pirq(irq, -1 /* no GSI override */,
502 trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
503 true /* Map GSI to PIRQ */);
504 }
505 if (0 == nr_ioapics) {
506 for (irq = 0; irq < nr_legacy_irqs(); irq++)
507 xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
508 }
509 return 0;
510}
511
512struct xen_device_domain_owner {
513 domid_t domain;
514 struct pci_dev *dev;
515 struct list_head list;
516};
517
518static DEFINE_SPINLOCK(dev_domain_list_spinlock);
519static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list);
520
521static struct xen_device_domain_owner *find_device(struct pci_dev *dev)
522{
523 struct xen_device_domain_owner *owner;
524
525 list_for_each_entry(owner, &dev_domain_list, list) {
526 if (owner->dev == dev)
527 return owner;
528 }
529 return NULL;
530}
531
532int xen_find_device_domain_owner(struct pci_dev *dev)
533{
534 struct xen_device_domain_owner *owner;
535 int domain = -ENODEV;
536
537 spin_lock(&dev_domain_list_spinlock);
538 owner = find_device(dev);
539 if (owner)
540 domain = owner->domain;
541 spin_unlock(&dev_domain_list_spinlock);
542 return domain;
543}
544EXPORT_SYMBOL_GPL(xen_find_device_domain_owner);
545
546int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain)
547{
548 struct xen_device_domain_owner *owner;
549
550 owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL);
551 if (!owner)
552 return -ENODEV;
553
554 spin_lock(&dev_domain_list_spinlock);
555 if (find_device(dev)) {
556 spin_unlock(&dev_domain_list_spinlock);
557 kfree(owner);
558 return -EEXIST;
559 }
560 owner->domain = domain;
561 owner->dev = dev;
562 list_add_tail(&owner->list, &dev_domain_list);
563 spin_unlock(&dev_domain_list_spinlock);
564 return 0;
565}
566EXPORT_SYMBOL_GPL(xen_register_device_domain_owner);
567
568int xen_unregister_device_domain_owner(struct pci_dev *dev)
569{
570 struct xen_device_domain_owner *owner;
571
572 spin_lock(&dev_domain_list_spinlock);
573 owner = find_device(dev);
574 if (!owner) {
575 spin_unlock(&dev_domain_list_spinlock);
576 return -ENODEV;
577 }
578 list_del(&owner->list);
579 spin_unlock(&dev_domain_list_spinlock);
580 kfree(owner);
581 return 0;
582}
583EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner);
584#endif