1/*
  2 * IBM/AMCC PPC4xx SoC setup code
  3 *
  4 * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
  5 *
  6 * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
  7 *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  8 *   Copyright (c) 2003 - 2006 Zultys Technologies
  9 *
 10 * This program is free software; you can redistribute  it and/or modify it
 11 * under  the terms of  the GNU General  Public License as published by the
 12 * Free Software Foundation;  either version 2 of the  License, or (at your
 13 * option) any later version.
 14 */
 15
 16#include <linux/stddef.h>
 17#include <linux/kernel.h>
 18#include <linux/init.h>
 19#include <linux/errno.h>
 20#include <linux/interrupt.h>
 21#include <linux/irq.h>
 22#include <linux/of_irq.h>
 23#include <linux/of_platform.h>
 24
 25#include <asm/dcr.h>
 26#include <asm/dcr-regs.h>
 27#include <asm/reg.h>
 28
 29static u32 dcrbase_l2c;
 30
 31/*
 32 * L2-cache
 33 */
 34
 35/* Issue L2C diagnostic command */
 36static inline u32 l2c_diag(u32 addr)
 37{
 38	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
 39	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
 40	while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
 41		;
 42
 43	return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
 44}
 45
 46static irqreturn_t l2c_error_handler(int irq, void *dev)
 47{
 48	u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
 49
 50	if (sr & L2C_SR_CPE) {
 51		/* Read cache trapped address */
 52		u32 addr = l2c_diag(0x42000000);
 53		printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
 54		       addr);
 55	}
 56	if (sr & L2C_SR_TPE) {
 57		/* Read tag trapped address */
 58		u32 addr = l2c_diag(0x82000000) >> 16;
 59		printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
 60		       addr);
 61	}
 62
 63	/* Clear parity errors */
 64	if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
 65		mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
 66		mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
 67	} else {
 68		printk(KERN_EMERG "L2C: LRU error\n");
 69	}
 70
 71	return IRQ_HANDLED;
 72}
 73
 74static int __init ppc4xx_l2c_probe(void)
 75{
 76	struct device_node *np;
 77	u32 r;
 78	unsigned long flags;
 79	int irq;
 80	const u32 *dcrreg;
 81	u32 dcrbase_isram;
 82	int len;
 83	const u32 *prop;
 84	u32 l2_size;
 85
 86	np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
 87	if (!np)
 88		return 0;
 89
 90	/* Get l2 cache size */
 91	prop = of_get_property(np, "cache-size", NULL);
 92	if (prop == NULL) {
 93		printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
 94		of_node_put(np);
 95		return -ENODEV;
 96	}
 97	l2_size = prop[0];
 98
 99	/* Map DCRs */
100	dcrreg = of_get_property(np, "dcr-reg", &len);
101	if (!dcrreg || (len != 4 * sizeof(u32))) {
102		printk(KERN_ERR "%s: Can't get DCR register base !",
103		       np->full_name);
104		of_node_put(np);
105		return -ENODEV;
106	}
107	dcrbase_isram = dcrreg[0];
108	dcrbase_l2c = dcrreg[2];
109
110	/* Get and map irq number from device tree */
111	irq = irq_of_parse_and_map(np, 0);
112	if (irq == NO_IRQ) {
113		printk(KERN_ERR "irq_of_parse_and_map failed\n");
114		of_node_put(np);
115		return -ENODEV;
116	}
117
118	/* Install error handler */
119	if (request_irq(irq, l2c_error_handler, 0, "L2C", 0) < 0) {
120		printk(KERN_ERR "Cannot install L2C error handler"
121		       ", cache is not enabled\n");
122		of_node_put(np);
123		return -ENODEV;
124	}
125
126	local_irq_save(flags);
127	asm volatile ("sync" ::: "memory");
128
129	/* Disable SRAM */
130	mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
131	      mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
132	mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
133	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
134	mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
135	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
136	mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
137	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
138	mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
139	      mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
140
141	/* Enable L2_MODE without ICU/DCU */
142	r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
143		~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
144	r |= L2C_CFG_L2M | L2C_CFG_SS_256;
145	mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
146
147	mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
148
149	/* Hardware Clear Command */
150	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
151	while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
152		;
153
154	/* Clear Cache Parity and Tag Errors */
155	mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
156
157	/* Enable 64G snoop region starting at 0 */
158	r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
159		~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
160	r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
161	mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
162
163	r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
164		~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
165	r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
166	mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
167
168	asm volatile ("sync" ::: "memory");
169
170	/* Enable ICU/DCU ports */
171	r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
172	r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
173	       | L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
174	r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
175		| L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
176
177	/* Check for 460EX/GT special handling */
178	if (of_device_is_compatible(np, "ibm,l2-cache-460ex") ||
179	    of_device_is_compatible(np, "ibm,l2-cache-460gt"))
180		r |= L2C_CFG_RDBW;
181
182	mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
183
184	asm volatile ("sync; isync" ::: "memory");
185	local_irq_restore(flags);
186
187	printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
188
189	of_node_put(np);
190	return 0;
191}
192arch_initcall(ppc4xx_l2c_probe);
193
194/*
195 * Apply a system reset. Alternatively a board specific value may be
196 * provided via the "reset-type" property in the cpu node.
197 */
198void ppc4xx_reset_system(char *cmd)
199{
200	struct device_node *np;
201	u32 reset_type = DBCR0_RST_SYSTEM;
202	const u32 *prop;
203
204	np = of_find_node_by_type(NULL, "cpu");
205	if (np) {
206		prop = of_get_property(np, "reset-type", NULL);
207
208		/*
209		 * Check if property exists and if it is in range:
210		 * 1 - PPC4xx core reset
211		 * 2 - PPC4xx chip reset
212		 * 3 - PPC4xx system reset (default)
213		 */
214		if ((prop) && ((prop[0] >= 1) && (prop[0] <= 3)))
215			reset_type = prop[0] << 28;
216	}
217
218	mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | reset_type);
219
220	while (1)
221		;	/* Just in case the reset doesn't work */
222}