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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale MPC85xx/MPC86xx RapidIO support
4 *
5 * Copyright 2009 Sysgo AG
6 * Thomas Moll <thomas.moll@sysgo.com>
7 * - fixed maintenance access routines, check for aligned access
8 *
9 * Copyright 2009 Integrated Device Technology, Inc.
10 * Alex Bounine <alexandre.bounine@idt.com>
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
13 *
14 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
15 * Zhang Wei <wei.zhang@freescale.com>
16 *
17 * Copyright 2005 MontaVista Software, Inc.
18 * Matt Porter <mporter@kernel.crashing.org>
19 */
20
21#include <linux/init.h>
22#include <linux/extable.h>
23#include <linux/types.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/platform_device.h>
30#include <linux/delay.h>
31#include <linux/slab.h>
32
33#include <linux/io.h>
34#include <linux/uaccess.h>
35#include <asm/machdep.h>
36#include <asm/rio.h>
37
38#include "fsl_rio.h"
39
40#undef DEBUG_PW /* Port-Write debugging */
41
42#define RIO_PORT1_EDCSR 0x0640
43#define RIO_PORT2_EDCSR 0x0680
44#define RIO_PORT1_IECSR 0x10130
45#define RIO_PORT2_IECSR 0x101B0
46
47#define RIO_GCCSR 0x13c
48#define RIO_ESCSR 0x158
49#define ESCSR_CLEAR 0x07120204
50#define RIO_PORT2_ESCSR 0x178
51#define RIO_CCSR 0x15c
52#define RIO_LTLEDCSR_IER 0x80000000
53#define RIO_LTLEDCSR_PRT 0x01000000
54#define IECSR_CLEAR 0x80000000
55#define RIO_ISR_AACR 0x10120
56#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
57
58#define RIWTAR_TRAD_VAL_SHIFT 12
59#define RIWTAR_TRAD_MASK 0x00FFFFFF
60#define RIWBAR_BADD_VAL_SHIFT 12
61#define RIWBAR_BADD_MASK 0x003FFFFF
62#define RIWAR_ENABLE 0x80000000
63#define RIWAR_TGINT_LOCAL 0x00F00000
64#define RIWAR_RDTYP_NO_SNOOP 0x00040000
65#define RIWAR_RDTYP_SNOOP 0x00050000
66#define RIWAR_WRTYP_NO_SNOOP 0x00004000
67#define RIWAR_WRTYP_SNOOP 0x00005000
68#define RIWAR_WRTYP_ALLOC 0x00006000
69#define RIWAR_SIZE_MASK 0x0000003F
70
71static DEFINE_SPINLOCK(fsl_rio_config_lock);
72
73#define ___fsl_read_rio_config(x, addr, err, op, barrier) \
74 __asm__ __volatile__( \
75 "1: "op" %1,0(%2)\n" \
76 " "barrier"\n" \
77 "2:\n" \
78 ".section .fixup,\"ax\"\n" \
79 "3: li %1,-1\n" \
80 " li %0,%3\n" \
81 " b 2b\n" \
82 ".previous\n" \
83 EX_TABLE(1b, 3b) \
84 : "=r" (err), "=r" (x) \
85 : "b" (addr), "i" (-EFAULT), "0" (err))
86
87#ifdef CONFIG_BOOKE
88#define __fsl_read_rio_config(x, addr, err, op) \
89 ___fsl_read_rio_config(x, addr, err, op, "mbar")
90#else
91#define __fsl_read_rio_config(x, addr, err, op) \
92 ___fsl_read_rio_config(x, addr, err, op, "eieio")
93#endif
94
95void __iomem *rio_regs_win;
96void __iomem *rmu_regs_win;
97resource_size_t rio_law_start;
98
99struct fsl_rio_dbell *dbell;
100struct fsl_rio_pw *pw;
101
102#ifdef CONFIG_PPC_E500
103int fsl_rio_mcheck_exception(struct pt_regs *regs)
104{
105 const struct exception_table_entry *entry;
106 unsigned long reason;
107
108 if (!rio_regs_win)
109 return 0;
110
111 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
112 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
113 /* Check if we are prepared to handle this fault */
114 entry = search_exception_tables(regs->nip);
115 if (entry) {
116 pr_debug("RIO: %s - MC Exception handled\n",
117 __func__);
118 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
119 0);
120 regs_set_recoverable(regs);
121 regs_set_return_ip(regs, extable_fixup(entry));
122 return 1;
123 }
124 }
125
126 return 0;
127}
128EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
129#endif
130
131/**
132 * fsl_local_config_read - Generate a MPC85xx local config space read
133 * @mport: RapidIO master port info
134 * @index: ID of RapdiIO interface
135 * @offset: Offset into configuration space
136 * @len: Length (in bytes) of the maintenance transaction
137 * @data: Value to be read into
138 *
139 * Generates a MPC85xx local configuration space read. Returns %0 on
140 * success or %-EINVAL on failure.
141 */
142static int fsl_local_config_read(struct rio_mport *mport,
143 int index, u32 offset, int len, u32 *data)
144{
145 struct rio_priv *priv = mport->priv;
146 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
147 offset);
148 *data = in_be32(priv->regs_win + offset);
149
150 return 0;
151}
152
153/**
154 * fsl_local_config_write - Generate a MPC85xx local config space write
155 * @mport: RapidIO master port info
156 * @index: ID of RapdiIO interface
157 * @offset: Offset into configuration space
158 * @len: Length (in bytes) of the maintenance transaction
159 * @data: Value to be written
160 *
161 * Generates a MPC85xx local configuration space write. Returns %0 on
162 * success or %-EINVAL on failure.
163 */
164static int fsl_local_config_write(struct rio_mport *mport,
165 int index, u32 offset, int len, u32 data)
166{
167 struct rio_priv *priv = mport->priv;
168 pr_debug
169 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
170 index, offset, data);
171 out_be32(priv->regs_win + offset, data);
172
173 return 0;
174}
175
176/**
177 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
178 * @mport: RapidIO master port info
179 * @index: ID of RapdiIO interface
180 * @destid: Destination ID of transaction
181 * @hopcount: Number of hops to target device
182 * @offset: Offset into configuration space
183 * @len: Length (in bytes) of the maintenance transaction
184 * @val: Location to be read into
185 *
186 * Generates a MPC85xx read maintenance transaction. Returns %0 on
187 * success or %-EINVAL on failure.
188 */
189static int
190fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
191 u8 hopcount, u32 offset, int len, u32 *val)
192{
193 struct rio_priv *priv = mport->priv;
194 unsigned long flags;
195 u8 *data;
196 u32 rval, err = 0;
197
198 pr_debug
199 ("fsl_rio_config_read:"
200 " index %d destid %d hopcount %d offset %8.8x len %d\n",
201 index, destid, hopcount, offset, len);
202
203 /* 16MB maintenance window possible */
204 /* allow only aligned access to maintenance registers */
205 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
206 return -EINVAL;
207
208 spin_lock_irqsave(&fsl_rio_config_lock, flags);
209
210 out_be32(&priv->maint_atmu_regs->rowtar,
211 (destid << 22) | (hopcount << 12) | (offset >> 12));
212 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
213
214 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
215 switch (len) {
216 case 1:
217 __fsl_read_rio_config(rval, data, err, "lbz");
218 break;
219 case 2:
220 __fsl_read_rio_config(rval, data, err, "lhz");
221 break;
222 case 4:
223 __fsl_read_rio_config(rval, data, err, "lwz");
224 break;
225 default:
226 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
227 return -EINVAL;
228 }
229
230 if (err) {
231 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
232 err, destid, hopcount, offset);
233 }
234
235 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
236 *val = rval;
237
238 return err;
239}
240
241/**
242 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
243 * @mport: RapidIO master port info
244 * @index: ID of RapdiIO interface
245 * @destid: Destination ID of transaction
246 * @hopcount: Number of hops to target device
247 * @offset: Offset into configuration space
248 * @len: Length (in bytes) of the maintenance transaction
249 * @val: Value to be written
250 *
251 * Generates an MPC85xx write maintenance transaction. Returns %0 on
252 * success or %-EINVAL on failure.
253 */
254static int
255fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
256 u8 hopcount, u32 offset, int len, u32 val)
257{
258 struct rio_priv *priv = mport->priv;
259 unsigned long flags;
260 u8 *data;
261 int ret = 0;
262
263 pr_debug
264 ("fsl_rio_config_write:"
265 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
266 index, destid, hopcount, offset, len, val);
267
268 /* 16MB maintenance windows possible */
269 /* allow only aligned access to maintenance registers */
270 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
271 return -EINVAL;
272
273 spin_lock_irqsave(&fsl_rio_config_lock, flags);
274
275 out_be32(&priv->maint_atmu_regs->rowtar,
276 (destid << 22) | (hopcount << 12) | (offset >> 12));
277 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
278
279 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
280 switch (len) {
281 case 1:
282 out_8((u8 *) data, val);
283 break;
284 case 2:
285 out_be16((u16 *) data, val);
286 break;
287 case 4:
288 out_be32((u32 *) data, val);
289 break;
290 default:
291 ret = -EINVAL;
292 }
293 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
294
295 return ret;
296}
297
298static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
299{
300 int i;
301
302 /* close inbound windows */
303 for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
304 out_be32(&priv->inb_atmu_regs[i].riwar, 0);
305}
306
307static int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
308 u64 rstart, u64 size, u32 flags)
309{
310 struct rio_priv *priv = mport->priv;
311 u32 base_size;
312 unsigned int base_size_log;
313 u64 win_start, win_end;
314 u32 riwar;
315 int i;
316
317 if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
318 return -EINVAL;
319
320 base_size_log = ilog2(size);
321 base_size = 1 << base_size_log;
322
323 /* check if addresses are aligned with the window size */
324 if (lstart & (base_size - 1))
325 return -EINVAL;
326 if (rstart & (base_size - 1))
327 return -EINVAL;
328
329 /* check for conflicting ranges */
330 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
331 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
332 if ((riwar & RIWAR_ENABLE) == 0)
333 continue;
334 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
335 << RIWBAR_BADD_VAL_SHIFT;
336 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
337 if (rstart < win_end && (rstart + size) > win_start)
338 return -EINVAL;
339 }
340
341 /* find unused atmu */
342 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
343 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
344 if ((riwar & RIWAR_ENABLE) == 0)
345 break;
346 }
347 if (i >= RIO_INB_ATMU_COUNT)
348 return -ENOMEM;
349
350 out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
351 out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
352 out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
353 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
354
355 return 0;
356}
357
358static void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
359{
360 u32 win_start_shift, base_start_shift;
361 struct rio_priv *priv = mport->priv;
362 u32 riwar, riwtar;
363 int i;
364
365 /* skip default window */
366 base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
367 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
368 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
369 if ((riwar & RIWAR_ENABLE) == 0)
370 continue;
371
372 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
373 win_start_shift = riwtar & RIWTAR_TRAD_MASK;
374 if (win_start_shift == base_start_shift) {
375 out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
376 return;
377 }
378 }
379}
380
381void fsl_rio_port_error_handler(int offset)
382{
383 /*XXX: Error recovery is not implemented, we just clear errors */
384 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
385
386 if (offset == 0) {
387 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
388 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
389 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
390 } else {
391 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
392 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
393 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
394 }
395}
396static inline void fsl_rio_info(struct device *dev, u32 ccsr)
397{
398 const char *str;
399 if (ccsr & 1) {
400 /* Serial phy */
401 switch (ccsr >> 30) {
402 case 0:
403 str = "1";
404 break;
405 case 1:
406 str = "4";
407 break;
408 default:
409 str = "Unknown";
410 break;
411 }
412 dev_info(dev, "Hardware port width: %s\n", str);
413
414 switch ((ccsr >> 27) & 7) {
415 case 0:
416 str = "Single-lane 0";
417 break;
418 case 1:
419 str = "Single-lane 2";
420 break;
421 case 2:
422 str = "Four-lane";
423 break;
424 default:
425 str = "Unknown";
426 break;
427 }
428 dev_info(dev, "Training connection status: %s\n", str);
429 } else {
430 /* Parallel phy */
431 if (!(ccsr & 0x80000000))
432 dev_info(dev, "Output port operating in 8-bit mode\n");
433 if (!(ccsr & 0x08000000))
434 dev_info(dev, "Input port operating in 8-bit mode\n");
435 }
436}
437
438/**
439 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
440 * @dev: platform_device pointer
441 *
442 * Initializes MPC85xx RapidIO hardware interface, configures
443 * master port with system-specific info, and registers the
444 * master port with the RapidIO subsystem.
445 */
446static int fsl_rio_setup(struct platform_device *dev)
447{
448 struct rio_ops *ops;
449 struct rio_mport *port;
450 struct rio_priv *priv;
451 int rc = 0;
452 const u32 *port_index;
453 u32 active_ports = 0;
454 struct device_node *np, *rmu_node;
455 u32 ccsr;
456 u64 range_start;
457 u32 i;
458 static int tmp;
459 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
460
461 if (!dev->dev.of_node) {
462 dev_err(&dev->dev, "Device OF-Node is NULL");
463 return -ENODEV;
464 }
465
466 rio_regs_win = of_iomap(dev->dev.of_node, 0);
467 if (!rio_regs_win) {
468 dev_err(&dev->dev, "Unable to map rio register window\n");
469 rc = -ENOMEM;
470 goto err_rio_regs;
471 }
472
473 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
474 if (!ops) {
475 rc = -ENOMEM;
476 goto err_ops;
477 }
478 ops->lcread = fsl_local_config_read;
479 ops->lcwrite = fsl_local_config_write;
480 ops->cread = fsl_rio_config_read;
481 ops->cwrite = fsl_rio_config_write;
482 ops->dsend = fsl_rio_doorbell_send;
483 ops->pwenable = fsl_rio_pw_enable;
484 ops->open_outb_mbox = fsl_open_outb_mbox;
485 ops->open_inb_mbox = fsl_open_inb_mbox;
486 ops->close_outb_mbox = fsl_close_outb_mbox;
487 ops->close_inb_mbox = fsl_close_inb_mbox;
488 ops->add_outb_message = fsl_add_outb_message;
489 ops->add_inb_buffer = fsl_add_inb_buffer;
490 ops->get_inb_message = fsl_get_inb_message;
491 ops->map_inb = fsl_map_inb_mem;
492 ops->unmap_inb = fsl_unmap_inb_mem;
493
494 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
495 if (!rmu_node) {
496 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
497 rc = -ENOENT;
498 goto err_rmu;
499 }
500 rmu_regs_win = of_iomap(rmu_node, 0);
501
502 of_node_put(rmu_node);
503 if (!rmu_regs_win) {
504 dev_err(&dev->dev, "Unable to map rmu register window\n");
505 rc = -ENOMEM;
506 goto err_rmu;
507 }
508 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
509 rmu_np[tmp] = np;
510 tmp++;
511 }
512
513 /*set up doobell node*/
514 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
515 if (!np) {
516 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
517 rc = -ENODEV;
518 goto err_dbell;
519 }
520 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
521 if (!(dbell)) {
522 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
523 rc = -ENOMEM;
524 goto err_dbell;
525 }
526 dbell->dev = &dev->dev;
527 dbell->bellirq = irq_of_parse_and_map(np, 1);
528 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
529
530 if (of_property_read_reg(np, 0, &range_start, NULL)) {
531 pr_err("%pOF: unable to find 'reg' property\n",
532 np);
533 rc = -ENOMEM;
534 goto err_pw;
535 }
536 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
537 (u32)range_start);
538
539 /*set up port write node*/
540 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
541 if (!np) {
542 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
543 rc = -ENODEV;
544 goto err_pw;
545 }
546 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
547 if (!(pw)) {
548 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
549 rc = -ENOMEM;
550 goto err_pw;
551 }
552 pw->dev = &dev->dev;
553 pw->pwirq = irq_of_parse_and_map(np, 0);
554 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
555 if (of_property_read_reg(np, 0, &range_start, NULL)) {
556 pr_err("%pOF: unable to find 'reg' property\n",
557 np);
558 rc = -ENOMEM;
559 goto err;
560 }
561 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
562
563 /*set up ports node*/
564 for_each_child_of_node(dev->dev.of_node, np) {
565 struct resource res;
566
567 port_index = of_get_property(np, "cell-index", NULL);
568 if (!port_index) {
569 dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
570 np);
571 continue;
572 }
573
574 if (of_range_to_resource(np, 0, &res)) {
575 dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
576 np);
577 continue;
578 }
579
580 dev_info(&dev->dev, "%pOF: LAW %pR\n",
581 np, &res);
582
583 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
584 if (!port)
585 continue;
586
587 rc = rio_mport_initialize(port);
588 if (rc) {
589 kfree(port);
590 continue;
591 }
592
593 i = *port_index - 1;
594 port->index = (unsigned char)i;
595
596 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
597 if (!priv) {
598 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
599 kfree(port);
600 continue;
601 }
602
603 INIT_LIST_HEAD(&port->dbells);
604 port->iores = res; /* struct copy */
605 port->iores.name = "rio_io_win";
606
607 if (request_resource(&iomem_resource, &port->iores) < 0) {
608 dev_err(&dev->dev, "RIO: Error requesting master port region"
609 " 0x%016llx-0x%016llx\n",
610 (u64)port->iores.start, (u64)port->iores.end);
611 kfree(priv);
612 kfree(port);
613 continue;
614 }
615 sprintf(port->name, "RIO mport %d", i);
616
617 priv->dev = &dev->dev;
618 port->dev.parent = &dev->dev;
619 port->ops = ops;
620 port->priv = priv;
621 port->phys_efptr = 0x100;
622 port->phys_rmap = 1;
623 priv->regs_win = rio_regs_win;
624
625 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
626
627 /* Checking the port training status */
628 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
629 dev_err(&dev->dev, "Port %d is not ready. "
630 "Try to restart connection...\n", i);
631 /* Disable ports */
632 out_be32(priv->regs_win
633 + RIO_CCSR + i*0x20, 0);
634 /* Set 1x lane */
635 setbits32(priv->regs_win
636 + RIO_CCSR + i*0x20, 0x02000000);
637 /* Enable ports */
638 setbits32(priv->regs_win
639 + RIO_CCSR + i*0x20, 0x00600000);
640 msleep(100);
641 if (in_be32((priv->regs_win
642 + RIO_ESCSR + i*0x20)) & 1) {
643 dev_err(&dev->dev,
644 "Port %d restart failed.\n", i);
645 release_resource(&port->iores);
646 kfree(priv);
647 kfree(port);
648 continue;
649 }
650 dev_info(&dev->dev, "Port %d restart success!\n", i);
651 }
652 fsl_rio_info(&dev->dev, ccsr);
653
654 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
655 & RIO_PEF_CTLS) >> 4;
656 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
657 port->sys_size ? 65536 : 256);
658
659 if (port->host_deviceid >= 0)
660 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
661 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
662 else
663 out_be32(priv->regs_win + RIO_GCCSR,
664 RIO_PORT_GEN_MASTER);
665
666 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
667 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
668 RIO_ATMU_REGS_PORT2_OFFSET));
669
670 priv->maint_atmu_regs = priv->atmu_regs + 1;
671 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
672 (priv->regs_win +
673 ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
674 RIO_INB_ATMU_REGS_PORT2_OFFSET));
675
676 /* Set to receive packets with any dest ID */
677 out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
678 RIO_ISR_AACR_AA);
679
680 /* Configure maintenance transaction window */
681 out_be32(&priv->maint_atmu_regs->rowbar,
682 port->iores.start >> 12);
683 out_be32(&priv->maint_atmu_regs->rowar,
684 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
685
686 priv->maint_win = ioremap(port->iores.start,
687 RIO_MAINT_WIN_SIZE);
688
689 rio_law_start = range_start;
690
691 fsl_rio_setup_rmu(port, rmu_np[i]);
692 fsl_rio_inbound_mem_init(priv);
693
694 dbell->mport[i] = port;
695 pw->mport[i] = port;
696
697 if (rio_register_mport(port)) {
698 release_resource(&port->iores);
699 kfree(priv);
700 kfree(port);
701 continue;
702 }
703 active_ports++;
704 }
705
706 if (!active_ports) {
707 rc = -ENOLINK;
708 goto err;
709 }
710
711 fsl_rio_doorbell_init(dbell);
712 fsl_rio_port_write_init(pw);
713
714 return 0;
715err:
716 kfree(pw);
717 pw = NULL;
718err_pw:
719 kfree(dbell);
720 dbell = NULL;
721err_dbell:
722 iounmap(rmu_regs_win);
723 rmu_regs_win = NULL;
724err_rmu:
725 kfree(ops);
726err_ops:
727 iounmap(rio_regs_win);
728 rio_regs_win = NULL;
729err_rio_regs:
730 return rc;
731}
732
733/* The probe function for RapidIO peer-to-peer network.
734 */
735static int fsl_of_rio_rpn_probe(struct platform_device *dev)
736{
737 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
738 dev->dev.of_node);
739
740 return fsl_rio_setup(dev);
741};
742
743static const struct of_device_id fsl_of_rio_rpn_ids[] = {
744 {
745 .compatible = "fsl,srio",
746 },
747 {},
748};
749
750static struct platform_driver fsl_of_rio_rpn_driver = {
751 .driver = {
752 .name = "fsl-of-rio",
753 .of_match_table = fsl_of_rio_rpn_ids,
754 },
755 .probe = fsl_of_rio_rpn_probe,
756};
757
758static __init int fsl_of_rio_rpn_init(void)
759{
760 return platform_driver_register(&fsl_of_rio_rpn_driver);
761}
762
763subsys_initcall(fsl_of_rio_rpn_init);
1/*
2 * Freescale MPC85xx/MPC86xx RapidIO support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 *
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/dma-mapping.h>
29#include <linux/interrupt.h>
30#include <linux/device.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_platform.h>
34#include <linux/delay.h>
35#include <linux/slab.h>
36
37#include <linux/io.h>
38#include <linux/uaccess.h>
39#include <asm/machdep.h>
40
41#include "fsl_rio.h"
42
43#undef DEBUG_PW /* Port-Write debugging */
44
45#define RIO_PORT1_EDCSR 0x0640
46#define RIO_PORT2_EDCSR 0x0680
47#define RIO_PORT1_IECSR 0x10130
48#define RIO_PORT2_IECSR 0x101B0
49
50#define RIO_GCCSR 0x13c
51#define RIO_ESCSR 0x158
52#define ESCSR_CLEAR 0x07120204
53#define RIO_PORT2_ESCSR 0x178
54#define RIO_CCSR 0x15c
55#define RIO_LTLEDCSR_IER 0x80000000
56#define RIO_LTLEDCSR_PRT 0x01000000
57#define IECSR_CLEAR 0x80000000
58#define RIO_ISR_AACR 0x10120
59#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
60
61#define RIWTAR_TRAD_VAL_SHIFT 12
62#define RIWTAR_TRAD_MASK 0x00FFFFFF
63#define RIWBAR_BADD_VAL_SHIFT 12
64#define RIWBAR_BADD_MASK 0x003FFFFF
65#define RIWAR_ENABLE 0x80000000
66#define RIWAR_TGINT_LOCAL 0x00F00000
67#define RIWAR_RDTYP_NO_SNOOP 0x00040000
68#define RIWAR_RDTYP_SNOOP 0x00050000
69#define RIWAR_WRTYP_NO_SNOOP 0x00004000
70#define RIWAR_WRTYP_SNOOP 0x00005000
71#define RIWAR_WRTYP_ALLOC 0x00006000
72#define RIWAR_SIZE_MASK 0x0000003F
73
74#define __fsl_read_rio_config(x, addr, err, op) \
75 __asm__ __volatile__( \
76 "1: "op" %1,0(%2)\n" \
77 " eieio\n" \
78 "2:\n" \
79 ".section .fixup,\"ax\"\n" \
80 "3: li %1,-1\n" \
81 " li %0,%3\n" \
82 " b 2b\n" \
83 ".section __ex_table,\"a\"\n" \
84 PPC_LONG_ALIGN "\n" \
85 PPC_LONG "1b,3b\n" \
86 ".text" \
87 : "=r" (err), "=r" (x) \
88 : "b" (addr), "i" (-EFAULT), "0" (err))
89
90void __iomem *rio_regs_win;
91void __iomem *rmu_regs_win;
92resource_size_t rio_law_start;
93
94struct fsl_rio_dbell *dbell;
95struct fsl_rio_pw *pw;
96
97#ifdef CONFIG_E500
98int fsl_rio_mcheck_exception(struct pt_regs *regs)
99{
100 const struct exception_table_entry *entry;
101 unsigned long reason;
102
103 if (!rio_regs_win)
104 return 0;
105
106 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
107 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
108 /* Check if we are prepared to handle this fault */
109 entry = search_exception_tables(regs->nip);
110 if (entry) {
111 pr_debug("RIO: %s - MC Exception handled\n",
112 __func__);
113 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
114 0);
115 regs->msr |= MSR_RI;
116 regs->nip = entry->fixup;
117 return 1;
118 }
119 }
120
121 return 0;
122}
123EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
124#endif
125
126/**
127 * fsl_local_config_read - Generate a MPC85xx local config space read
128 * @mport: RapidIO master port info
129 * @index: ID of RapdiIO interface
130 * @offset: Offset into configuration space
131 * @len: Length (in bytes) of the maintenance transaction
132 * @data: Value to be read into
133 *
134 * Generates a MPC85xx local configuration space read. Returns %0 on
135 * success or %-EINVAL on failure.
136 */
137static int fsl_local_config_read(struct rio_mport *mport,
138 int index, u32 offset, int len, u32 *data)
139{
140 struct rio_priv *priv = mport->priv;
141 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
142 offset);
143 *data = in_be32(priv->regs_win + offset);
144
145 return 0;
146}
147
148/**
149 * fsl_local_config_write - Generate a MPC85xx local config space write
150 * @mport: RapidIO master port info
151 * @index: ID of RapdiIO interface
152 * @offset: Offset into configuration space
153 * @len: Length (in bytes) of the maintenance transaction
154 * @data: Value to be written
155 *
156 * Generates a MPC85xx local configuration space write. Returns %0 on
157 * success or %-EINVAL on failure.
158 */
159static int fsl_local_config_write(struct rio_mport *mport,
160 int index, u32 offset, int len, u32 data)
161{
162 struct rio_priv *priv = mport->priv;
163 pr_debug
164 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
165 index, offset, data);
166 out_be32(priv->regs_win + offset, data);
167
168 return 0;
169}
170
171/**
172 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
173 * @mport: RapidIO master port info
174 * @index: ID of RapdiIO interface
175 * @destid: Destination ID of transaction
176 * @hopcount: Number of hops to target device
177 * @offset: Offset into configuration space
178 * @len: Length (in bytes) of the maintenance transaction
179 * @val: Location to be read into
180 *
181 * Generates a MPC85xx read maintenance transaction. Returns %0 on
182 * success or %-EINVAL on failure.
183 */
184static int
185fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
186 u8 hopcount, u32 offset, int len, u32 *val)
187{
188 struct rio_priv *priv = mport->priv;
189 u8 *data;
190 u32 rval, err = 0;
191
192 pr_debug
193 ("fsl_rio_config_read:"
194 " index %d destid %d hopcount %d offset %8.8x len %d\n",
195 index, destid, hopcount, offset, len);
196
197 /* 16MB maintenance window possible */
198 /* allow only aligned access to maintenance registers */
199 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
200 return -EINVAL;
201
202 out_be32(&priv->maint_atmu_regs->rowtar,
203 (destid << 22) | (hopcount << 12) | (offset >> 12));
204 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
205
206 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
207 switch (len) {
208 case 1:
209 __fsl_read_rio_config(rval, data, err, "lbz");
210 break;
211 case 2:
212 __fsl_read_rio_config(rval, data, err, "lhz");
213 break;
214 case 4:
215 __fsl_read_rio_config(rval, data, err, "lwz");
216 break;
217 default:
218 return -EINVAL;
219 }
220
221 if (err) {
222 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
223 err, destid, hopcount, offset);
224 }
225
226 *val = rval;
227
228 return err;
229}
230
231/**
232 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
233 * @mport: RapidIO master port info
234 * @index: ID of RapdiIO interface
235 * @destid: Destination ID of transaction
236 * @hopcount: Number of hops to target device
237 * @offset: Offset into configuration space
238 * @len: Length (in bytes) of the maintenance transaction
239 * @val: Value to be written
240 *
241 * Generates an MPC85xx write maintenance transaction. Returns %0 on
242 * success or %-EINVAL on failure.
243 */
244static int
245fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
246 u8 hopcount, u32 offset, int len, u32 val)
247{
248 struct rio_priv *priv = mport->priv;
249 u8 *data;
250 pr_debug
251 ("fsl_rio_config_write:"
252 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
253 index, destid, hopcount, offset, len, val);
254
255 /* 16MB maintenance windows possible */
256 /* allow only aligned access to maintenance registers */
257 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
258 return -EINVAL;
259
260 out_be32(&priv->maint_atmu_regs->rowtar,
261 (destid << 22) | (hopcount << 12) | (offset >> 12));
262 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
263
264 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
265 switch (len) {
266 case 1:
267 out_8((u8 *) data, val);
268 break;
269 case 2:
270 out_be16((u16 *) data, val);
271 break;
272 case 4:
273 out_be32((u32 *) data, val);
274 break;
275 default:
276 return -EINVAL;
277 }
278
279 return 0;
280}
281
282static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
283{
284 int i;
285
286 /* close inbound windows */
287 for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
288 out_be32(&priv->inb_atmu_regs[i].riwar, 0);
289}
290
291int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
292 u64 rstart, u32 size, u32 flags)
293{
294 struct rio_priv *priv = mport->priv;
295 u32 base_size;
296 unsigned int base_size_log;
297 u64 win_start, win_end;
298 u32 riwar;
299 int i;
300
301 if ((size & (size - 1)) != 0)
302 return -EINVAL;
303
304 base_size_log = ilog2(size);
305 base_size = 1 << base_size_log;
306
307 /* check if addresses are aligned with the window size */
308 if (lstart & (base_size - 1))
309 return -EINVAL;
310 if (rstart & (base_size - 1))
311 return -EINVAL;
312
313 /* check for conflicting ranges */
314 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
315 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
316 if ((riwar & RIWAR_ENABLE) == 0)
317 continue;
318 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
319 << RIWBAR_BADD_VAL_SHIFT;
320 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
321 if (rstart < win_end && (rstart + size) > win_start)
322 return -EINVAL;
323 }
324
325 /* find unused atmu */
326 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
327 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
328 if ((riwar & RIWAR_ENABLE) == 0)
329 break;
330 }
331 if (i >= RIO_INB_ATMU_COUNT)
332 return -ENOMEM;
333
334 out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
335 out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
336 out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
337 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
338
339 return 0;
340}
341
342void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
343{
344 u32 win_start_shift, base_start_shift;
345 struct rio_priv *priv = mport->priv;
346 u32 riwar, riwtar;
347 int i;
348
349 /* skip default window */
350 base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
351 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
352 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
353 if ((riwar & RIWAR_ENABLE) == 0)
354 continue;
355
356 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
357 win_start_shift = riwtar & RIWTAR_TRAD_MASK;
358 if (win_start_shift == base_start_shift) {
359 out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
360 return;
361 }
362 }
363}
364
365void fsl_rio_port_error_handler(int offset)
366{
367 /*XXX: Error recovery is not implemented, we just clear errors */
368 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
369
370 if (offset == 0) {
371 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
372 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
373 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
374 } else {
375 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
376 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
377 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
378 }
379}
380static inline void fsl_rio_info(struct device *dev, u32 ccsr)
381{
382 const char *str;
383 if (ccsr & 1) {
384 /* Serial phy */
385 switch (ccsr >> 30) {
386 case 0:
387 str = "1";
388 break;
389 case 1:
390 str = "4";
391 break;
392 default:
393 str = "Unknown";
394 break;
395 }
396 dev_info(dev, "Hardware port width: %s\n", str);
397
398 switch ((ccsr >> 27) & 7) {
399 case 0:
400 str = "Single-lane 0";
401 break;
402 case 1:
403 str = "Single-lane 2";
404 break;
405 case 2:
406 str = "Four-lane";
407 break;
408 default:
409 str = "Unknown";
410 break;
411 }
412 dev_info(dev, "Training connection status: %s\n", str);
413 } else {
414 /* Parallel phy */
415 if (!(ccsr & 0x80000000))
416 dev_info(dev, "Output port operating in 8-bit mode\n");
417 if (!(ccsr & 0x08000000))
418 dev_info(dev, "Input port operating in 8-bit mode\n");
419 }
420}
421
422/**
423 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
424 * @dev: platform_device pointer
425 *
426 * Initializes MPC85xx RapidIO hardware interface, configures
427 * master port with system-specific info, and registers the
428 * master port with the RapidIO subsystem.
429 */
430int fsl_rio_setup(struct platform_device *dev)
431{
432 struct rio_ops *ops;
433 struct rio_mport *port;
434 struct rio_priv *priv;
435 int rc = 0;
436 const u32 *dt_range, *cell, *port_index;
437 u32 active_ports = 0;
438 struct resource regs, rmu_regs;
439 struct device_node *np, *rmu_node;
440 int rlen;
441 u32 ccsr;
442 u64 range_start, range_size;
443 int paw, aw, sw;
444 u32 i;
445 static int tmp;
446 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
447
448 if (!dev->dev.of_node) {
449 dev_err(&dev->dev, "Device OF-Node is NULL");
450 return -ENODEV;
451 }
452
453 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
454 if (rc) {
455 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
456 dev->dev.of_node->full_name);
457 return -EFAULT;
458 }
459 dev_info(&dev->dev, "Of-device full name %s\n",
460 dev->dev.of_node->full_name);
461 dev_info(&dev->dev, "Regs: %pR\n", ®s);
462
463 rio_regs_win = ioremap(regs.start, resource_size(®s));
464 if (!rio_regs_win) {
465 dev_err(&dev->dev, "Unable to map rio register window\n");
466 rc = -ENOMEM;
467 goto err_rio_regs;
468 }
469
470 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
471 if (!ops) {
472 rc = -ENOMEM;
473 goto err_ops;
474 }
475 ops->lcread = fsl_local_config_read;
476 ops->lcwrite = fsl_local_config_write;
477 ops->cread = fsl_rio_config_read;
478 ops->cwrite = fsl_rio_config_write;
479 ops->dsend = fsl_rio_doorbell_send;
480 ops->pwenable = fsl_rio_pw_enable;
481 ops->open_outb_mbox = fsl_open_outb_mbox;
482 ops->open_inb_mbox = fsl_open_inb_mbox;
483 ops->close_outb_mbox = fsl_close_outb_mbox;
484 ops->close_inb_mbox = fsl_close_inb_mbox;
485 ops->add_outb_message = fsl_add_outb_message;
486 ops->add_inb_buffer = fsl_add_inb_buffer;
487 ops->get_inb_message = fsl_get_inb_message;
488 ops->map_inb = fsl_map_inb_mem;
489 ops->unmap_inb = fsl_unmap_inb_mem;
490
491 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
492 if (!rmu_node) {
493 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
494 goto err_rmu;
495 }
496 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
497 if (rc) {
498 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
499 rmu_node->full_name);
500 goto err_rmu;
501 }
502 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
503 if (!rmu_regs_win) {
504 dev_err(&dev->dev, "Unable to map rmu register window\n");
505 rc = -ENOMEM;
506 goto err_rmu;
507 }
508 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
509 rmu_np[tmp] = np;
510 tmp++;
511 }
512
513 /*set up doobell node*/
514 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
515 if (!np) {
516 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
517 rc = -ENODEV;
518 goto err_dbell;
519 }
520 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
521 if (!(dbell)) {
522 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
523 rc = -ENOMEM;
524 goto err_dbell;
525 }
526 dbell->dev = &dev->dev;
527 dbell->bellirq = irq_of_parse_and_map(np, 1);
528 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
529
530 aw = of_n_addr_cells(np);
531 dt_range = of_get_property(np, "reg", &rlen);
532 if (!dt_range) {
533 pr_err("%s: unable to find 'reg' property\n",
534 np->full_name);
535 rc = -ENOMEM;
536 goto err_pw;
537 }
538 range_start = of_read_number(dt_range, aw);
539 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
540 (u32)range_start);
541
542 /*set up port write node*/
543 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
544 if (!np) {
545 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
546 rc = -ENODEV;
547 goto err_pw;
548 }
549 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
550 if (!(pw)) {
551 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
552 rc = -ENOMEM;
553 goto err_pw;
554 }
555 pw->dev = &dev->dev;
556 pw->pwirq = irq_of_parse_and_map(np, 0);
557 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
558 aw = of_n_addr_cells(np);
559 dt_range = of_get_property(np, "reg", &rlen);
560 if (!dt_range) {
561 pr_err("%s: unable to find 'reg' property\n",
562 np->full_name);
563 rc = -ENOMEM;
564 goto err;
565 }
566 range_start = of_read_number(dt_range, aw);
567 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
568
569 /*set up ports node*/
570 for_each_child_of_node(dev->dev.of_node, np) {
571 port_index = of_get_property(np, "cell-index", NULL);
572 if (!port_index) {
573 dev_err(&dev->dev, "Can't get %s property 'cell-index'\n",
574 np->full_name);
575 continue;
576 }
577
578 dt_range = of_get_property(np, "ranges", &rlen);
579 if (!dt_range) {
580 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
581 np->full_name);
582 continue;
583 }
584
585 /* Get node address wide */
586 cell = of_get_property(np, "#address-cells", NULL);
587 if (cell)
588 aw = *cell;
589 else
590 aw = of_n_addr_cells(np);
591 /* Get node size wide */
592 cell = of_get_property(np, "#size-cells", NULL);
593 if (cell)
594 sw = *cell;
595 else
596 sw = of_n_size_cells(np);
597 /* Get parent address wide wide */
598 paw = of_n_addr_cells(np);
599 range_start = of_read_number(dt_range + aw, paw);
600 range_size = of_read_number(dt_range + aw + paw, sw);
601
602 dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n",
603 np->full_name, range_start, range_size);
604
605 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
606 if (!port)
607 continue;
608
609 rc = rio_mport_initialize(port);
610 if (rc) {
611 kfree(port);
612 continue;
613 }
614
615 i = *port_index - 1;
616 port->index = (unsigned char)i;
617
618 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
619 if (!priv) {
620 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
621 kfree(port);
622 continue;
623 }
624
625 INIT_LIST_HEAD(&port->dbells);
626 port->iores.start = range_start;
627 port->iores.end = port->iores.start + range_size - 1;
628 port->iores.flags = IORESOURCE_MEM;
629 port->iores.name = "rio_io_win";
630
631 if (request_resource(&iomem_resource, &port->iores) < 0) {
632 dev_err(&dev->dev, "RIO: Error requesting master port region"
633 " 0x%016llx-0x%016llx\n",
634 (u64)port->iores.start, (u64)port->iores.end);
635 kfree(priv);
636 kfree(port);
637 continue;
638 }
639 sprintf(port->name, "RIO mport %d", i);
640
641 priv->dev = &dev->dev;
642 port->dev.parent = &dev->dev;
643 port->ops = ops;
644 port->priv = priv;
645 port->phys_efptr = 0x100;
646 priv->regs_win = rio_regs_win;
647
648 /* Probe the master port phy type */
649 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
650 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
651 if (port->phy_type == RIO_PHY_PARALLEL) {
652 dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported port type!\n");
653 release_resource(&port->iores);
654 kfree(priv);
655 kfree(port);
656 continue;
657 }
658 dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
659 /* Checking the port training status */
660 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
661 dev_err(&dev->dev, "Port %d is not ready. "
662 "Try to restart connection...\n", i);
663 /* Disable ports */
664 out_be32(priv->regs_win
665 + RIO_CCSR + i*0x20, 0);
666 /* Set 1x lane */
667 setbits32(priv->regs_win
668 + RIO_CCSR + i*0x20, 0x02000000);
669 /* Enable ports */
670 setbits32(priv->regs_win
671 + RIO_CCSR + i*0x20, 0x00600000);
672 msleep(100);
673 if (in_be32((priv->regs_win
674 + RIO_ESCSR + i*0x20)) & 1) {
675 dev_err(&dev->dev,
676 "Port %d restart failed.\n", i);
677 release_resource(&port->iores);
678 kfree(priv);
679 kfree(port);
680 continue;
681 }
682 dev_info(&dev->dev, "Port %d restart success!\n", i);
683 }
684 fsl_rio_info(&dev->dev, ccsr);
685
686 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
687 & RIO_PEF_CTLS) >> 4;
688 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
689 port->sys_size ? 65536 : 256);
690
691 if (port->host_deviceid >= 0)
692 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
693 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
694 else
695 out_be32(priv->regs_win + RIO_GCCSR,
696 RIO_PORT_GEN_MASTER);
697
698 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
699 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
700 RIO_ATMU_REGS_PORT2_OFFSET));
701
702 priv->maint_atmu_regs = priv->atmu_regs + 1;
703 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
704 (priv->regs_win +
705 ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
706 RIO_INB_ATMU_REGS_PORT2_OFFSET));
707
708
709 /* Set to receive any dist ID for serial RapidIO controller. */
710 if (port->phy_type == RIO_PHY_SERIAL)
711 out_be32((priv->regs_win
712 + RIO_ISR_AACR + i*0x80), RIO_ISR_AACR_AA);
713
714 /* Configure maintenance transaction window */
715 out_be32(&priv->maint_atmu_regs->rowbar,
716 port->iores.start >> 12);
717 out_be32(&priv->maint_atmu_regs->rowar,
718 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
719
720 priv->maint_win = ioremap(port->iores.start,
721 RIO_MAINT_WIN_SIZE);
722
723 rio_law_start = range_start;
724
725 fsl_rio_setup_rmu(port, rmu_np[i]);
726 fsl_rio_inbound_mem_init(priv);
727
728 dbell->mport[i] = port;
729 pw->mport[i] = port;
730
731 if (rio_register_mport(port)) {
732 release_resource(&port->iores);
733 kfree(priv);
734 kfree(port);
735 continue;
736 }
737 active_ports++;
738 }
739
740 if (!active_ports) {
741 rc = -ENOLINK;
742 goto err;
743 }
744
745 fsl_rio_doorbell_init(dbell);
746 fsl_rio_port_write_init(pw);
747
748 return 0;
749err:
750 kfree(pw);
751 pw = NULL;
752err_pw:
753 kfree(dbell);
754 dbell = NULL;
755err_dbell:
756 iounmap(rmu_regs_win);
757 rmu_regs_win = NULL;
758err_rmu:
759 kfree(ops);
760err_ops:
761 iounmap(rio_regs_win);
762 rio_regs_win = NULL;
763err_rio_regs:
764 return rc;
765}
766
767/* The probe function for RapidIO peer-to-peer network.
768 */
769static int fsl_of_rio_rpn_probe(struct platform_device *dev)
770{
771 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
772 dev->dev.of_node->full_name);
773
774 return fsl_rio_setup(dev);
775};
776
777static const struct of_device_id fsl_of_rio_rpn_ids[] = {
778 {
779 .compatible = "fsl,srio",
780 },
781 {},
782};
783
784static struct platform_driver fsl_of_rio_rpn_driver = {
785 .driver = {
786 .name = "fsl-of-rio",
787 .of_match_table = fsl_of_rio_rpn_ids,
788 },
789 .probe = fsl_of_rio_rpn_probe,
790};
791
792static __init int fsl_of_rio_rpn_init(void)
793{
794 return platform_driver_register(&fsl_of_rio_rpn_driver);
795}
796
797subsys_initcall(fsl_of_rio_rpn_init);