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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * MPC85xx/86xx PCI Express structure define
4 *
5 * Copyright 2007,2011 Freescale Semiconductor, Inc
6 */
7
8#ifdef __KERNEL__
9#ifndef __POWERPC_FSL_PCI_H
10#define __POWERPC_FSL_PCI_H
11
12struct platform_device;
13
14
15/* FSL PCI controller BRR1 register */
16#define PCI_FSL_BRR1 0xbf8
17#define PCI_FSL_BRR1_VER 0xffff
18
19#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
20#define PCIE_LTSSM_L0 0x16 /* L0 state */
21#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
22#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
23#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
24#define PIWAR_EN 0x80000000 /* Enable */
25#define PIWAR_PF 0x20000000 /* prefetch */
26#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
27#define PIWAR_READ_SNOOP 0x00050000
28#define PIWAR_WRITE_SNOOP 0x00005000
29#define PIWAR_SZ_MASK 0x0000003f
30
31#define PEX_PMCR_PTOMR 0x1
32#define PEX_PMCR_EXL2S 0x2
33
34#define PME_DISR_EN_PTOD 0x00008000
35#define PME_DISR_EN_ENL23D 0x00002000
36#define PME_DISR_EN_EXL23D 0x00001000
37
38/* PCI/PCI Express outbound window reg */
39struct pci_outbound_window_regs {
40 __be32 potar; /* 0x.0 - Outbound translation address register */
41 __be32 potear; /* 0x.4 - Outbound translation extended address register */
42 __be32 powbar; /* 0x.8 - Outbound window base address register */
43 u8 res1[4];
44 __be32 powar; /* 0x.10 - Outbound window attributes register */
45 u8 res2[12];
46};
47
48/* PCI/PCI Express inbound window reg */
49struct pci_inbound_window_regs {
50 __be32 pitar; /* 0x.0 - Inbound translation address register */
51 u8 res1[4];
52 __be32 piwbar; /* 0x.8 - Inbound window base address register */
53 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
54 __be32 piwar; /* 0x.10 - Inbound window attributes register */
55 u8 res2[12];
56};
57
58/* PCI/PCI Express IO block registers for 85xx/86xx */
59struct ccsr_pci {
60 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
61 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
62 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
63 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
64 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
65 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
66 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
67 u8 res2[4];
68 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
69 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
70 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
71 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
72 u8 res3[3016];
73 __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
74 __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
75
76/* PCI/PCI Express outbound window 0-4
77 * Window 0 is the default window and is the only window enabled upon reset.
78 * The default outbound register set is used when a transaction misses
79 * in all of the other outbound windows.
80 */
81 struct pci_outbound_window_regs pow[5];
82 u8 res14[96];
83 struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
84 u8 res6[96];
85/* PCI/PCI Express inbound window 3-0
86 * inbound window 1 supports only a 32-bit base address and does not
87 * define an inbound window base extended address register.
88 */
89 struct pci_inbound_window_regs piw[4];
90
91 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
92 u8 res21[4];
93 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
94 u8 res22[4];
95 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
96 u8 res23[12];
97 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
98 u8 res24[4];
99 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
100 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
101 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
102 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
103 u8 res_e38[200];
104 __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
105 u8 res_f04[16];
106 __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
107#define PEX_CSR0_LTSSM_MASK 0xFC
108#define PEX_CSR0_LTSSM_SHIFT 2
109#define PEX_CSR0_LTSSM_L0 0x11
110 __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
111 u8 res_f1c[228];
112
113};
114
115extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
116extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
117extern int mpc83xx_add_bridge(struct device_node *dev);
118u64 fsl_pci_immrbar_base(struct pci_controller *hose);
119
120extern struct device_node *fsl_pci_primary;
121
122#ifdef CONFIG_PCI
123void __init fsl_pci_assign_primary(void);
124#else
125static inline void fsl_pci_assign_primary(void) {}
126#endif
127
128#ifdef CONFIG_FSL_PCI
129extern int fsl_pci_mcheck_exception(struct pt_regs *);
130#else
131static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
132#endif
133
134#endif /* __POWERPC_FSL_PCI_H */
135#endif /* __KERNEL__ */
1/*
2 * MPC85xx/86xx PCI Express structure define
3 *
4 * Copyright 2007,2011 Freescale Semiconductor, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifdef __KERNEL__
14#ifndef __POWERPC_FSL_PCI_H
15#define __POWERPC_FSL_PCI_H
16
17struct platform_device;
18
19
20/* FSL PCI controller BRR1 register */
21#define PCI_FSL_BRR1 0xbf8
22#define PCI_FSL_BRR1_VER 0xffff
23
24#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
25#define PCIE_LTSSM_L0 0x16 /* L0 state */
26#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
27#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
28#define PIWAR_EN 0x80000000 /* Enable */
29#define PIWAR_PF 0x20000000 /* prefetch */
30#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
31#define PIWAR_READ_SNOOP 0x00050000
32#define PIWAR_WRITE_SNOOP 0x00005000
33#define PIWAR_SZ_MASK 0x0000003f
34
35#define PEX_PMCR_PTOMR 0x1
36#define PEX_PMCR_EXL2S 0x2
37
38#define PME_DISR_EN_PTOD 0x00008000
39#define PME_DISR_EN_ENL23D 0x00002000
40#define PME_DISR_EN_EXL23D 0x00001000
41
42/* PCI/PCI Express outbound window reg */
43struct pci_outbound_window_regs {
44 __be32 potar; /* 0x.0 - Outbound translation address register */
45 __be32 potear; /* 0x.4 - Outbound translation extended address register */
46 __be32 powbar; /* 0x.8 - Outbound window base address register */
47 u8 res1[4];
48 __be32 powar; /* 0x.10 - Outbound window attributes register */
49 u8 res2[12];
50};
51
52/* PCI/PCI Express inbound window reg */
53struct pci_inbound_window_regs {
54 __be32 pitar; /* 0x.0 - Inbound translation address register */
55 u8 res1[4];
56 __be32 piwbar; /* 0x.8 - Inbound window base address register */
57 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
58 __be32 piwar; /* 0x.10 - Inbound window attributes register */
59 u8 res2[12];
60};
61
62/* PCI/PCI Express IO block registers for 85xx/86xx */
63struct ccsr_pci {
64 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
65 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
66 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
67 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
68 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
69 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
70 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
71 u8 res2[4];
72 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
73 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
74 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
75 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
76 u8 res3[3016];
77 __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
78 __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
79
80/* PCI/PCI Express outbound window 0-4
81 * Window 0 is the default window and is the only window enabled upon reset.
82 * The default outbound register set is used when a transaction misses
83 * in all of the other outbound windows.
84 */
85 struct pci_outbound_window_regs pow[5];
86 u8 res14[96];
87 struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
88 u8 res6[96];
89/* PCI/PCI Express inbound window 3-0
90 * inbound window 1 supports only a 32-bit base address and does not
91 * define an inbound window base extended address register.
92 */
93 struct pci_inbound_window_regs piw[4];
94
95 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
96 u8 res21[4];
97 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
98 u8 res22[4];
99 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
100 u8 res23[12];
101 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
102 u8 res24[4];
103 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
104 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
105 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
106 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
107 u8 res_e38[200];
108 __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
109 u8 res_f04[16];
110 __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
111#define PEX_CSR0_LTSSM_MASK 0xFC
112#define PEX_CSR0_LTSSM_SHIFT 2
113#define PEX_CSR0_LTSSM_L0 0x11
114 __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
115 u8 res_f1c[228];
116
117};
118
119extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
120extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
121extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
122extern int mpc83xx_add_bridge(struct device_node *dev);
123u64 fsl_pci_immrbar_base(struct pci_controller *hose);
124
125extern struct device_node *fsl_pci_primary;
126
127#ifdef CONFIG_PCI
128void fsl_pci_assign_primary(void);
129#else
130static inline void fsl_pci_assign_primary(void) {}
131#endif
132
133#ifdef CONFIG_FSL_PCI
134extern int fsl_pci_mcheck_exception(struct pt_regs *);
135#else
136static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
137#endif
138
139#endif /* __POWERPC_FSL_PCI_H */
140#endif /* __KERNEL__ */