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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
5 *
6 * Derived from book3s_interrupts.S, which is:
7 * Copyright SUSE Linux Products GmbH 2009
8 *
9 * Authors: Alexander Graf <agraf@suse.de>
10 */
11
12#include <linux/linkage.h>
13#include <asm/ppc_asm.h>
14#include <asm/kvm_asm.h>
15#include <asm/reg.h>
16#include <asm/page.h>
17#include <asm/asm-offsets.h>
18#include <asm/exception-64s.h>
19#include <asm/ppc-opcode.h>
20#include <asm/asm-compat.h>
21#include <asm/feature-fixups.h>
22
23/*****************************************************************************
24 * *
25 * Guest entry / exit code that is in kernel module memory (vmalloc) *
26 * *
27 ****************************************************************************/
28
29/* Registers:
30 * none
31 */
32_GLOBAL(__kvmppc_vcore_entry)
33
34 /* Write correct stack frame */
35 mflr r0
36 std r0,PPC_LR_STKOFF(r1)
37
38 /* Save host state to the stack */
39 stdu r1, -SWITCH_FRAME_SIZE(r1)
40
41 /* Save non-volatile registers (r14 - r31) and CR */
42 SAVE_NVGPRS(r1)
43 mfcr r3
44 std r3, _CCR(r1)
45
46 /* Save host DSCR */
47 mfspr r3, SPRN_DSCR
48 std r3, HSTATE_DSCR(r13)
49
50BEGIN_FTR_SECTION
51 /* Save host DABR */
52 mfspr r3, SPRN_DABR
53 std r3, HSTATE_DABR(r13)
54END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
55
56 /* Save host PMU registers */
57 bl kvmhv_save_host_pmu
58
59 /*
60 * Put whatever is in the decrementer into the
61 * hypervisor decrementer.
62 * Because of a hardware deviation in P8,
63 * we need to set LPCR[HDICE] before writing HDEC.
64 */
65 ld r5, HSTATE_KVM_VCORE(r13)
66 ld r6, VCORE_KVM(r5)
67 ld r9, KVM_HOST_LPCR(r6)
68 ori r8, r9, LPCR_HDICE
69 mtspr SPRN_LPCR, r8
70 isync
71 mfspr r8,SPRN_DEC
72 mftb r7
73 extsw r8,r8
74 mtspr SPRN_HDEC,r8
75 add r8,r8,r7
76 std r8,HSTATE_DECEXP(r13)
77
78 /* Jump to partition switch code */
79 bl kvmppc_hv_entry_trampoline
80 nop
81
82/*
83 * We return here in virtual mode after the guest exits
84 * with something that we can't handle in real mode.
85 * Interrupts are still hard-disabled.
86 */
87
88 /*
89 * Register usage at this point:
90 *
91 * R1 = host R1
92 * R2 = host R2
93 * R3 = trap number on this thread
94 * R12 = exit handler id
95 * R13 = PACA
96 */
97
98 /* Restore non-volatile host registers (r14 - r31) and CR */
99 REST_NVGPRS(r1)
100 ld r4, _CCR(r1)
101 mtcr r4
102
103 addi r1, r1, SWITCH_FRAME_SIZE
104 ld r0, PPC_LR_STKOFF(r1)
105 mtlr r0
106 blr
107
108/*
109 * void kvmhv_save_host_pmu(void)
110 */
111SYM_FUNC_START_LOCAL(kvmhv_save_host_pmu)
112BEGIN_FTR_SECTION
113 /* Work around P8 PMAE bug */
114 li r3, -1
115 clrrdi r3, r3, 10
116 mfspr r8, SPRN_MMCR2
117 mtspr SPRN_MMCR2, r3 /* freeze all counters using MMCR2 */
118 isync
119END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
120 li r3, 1
121 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
122 mfspr r7, SPRN_MMCR0 /* save MMCR0 */
123 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
124 mfspr r6, SPRN_MMCRA
125 /* Clear MMCRA in order to disable SDAR updates */
126 li r5, 0
127 mtspr SPRN_MMCRA, r5
128 isync
129 lbz r5, PACA_PMCINUSE(r13) /* is the host using the PMU? */
130 cmpwi r5, 0
131 beq 31f /* skip if not */
132 mfspr r5, SPRN_MMCR1
133 mfspr r9, SPRN_SIAR
134 mfspr r10, SPRN_SDAR
135 std r7, HSTATE_MMCR0(r13)
136 std r5, HSTATE_MMCR1(r13)
137 std r6, HSTATE_MMCRA(r13)
138 std r9, HSTATE_SIAR(r13)
139 std r10, HSTATE_SDAR(r13)
140BEGIN_FTR_SECTION
141 mfspr r9, SPRN_SIER
142 std r8, HSTATE_MMCR2(r13)
143 std r9, HSTATE_SIER(r13)
144END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
145 mfspr r3, SPRN_PMC1
146 mfspr r5, SPRN_PMC2
147 mfspr r6, SPRN_PMC3
148 mfspr r7, SPRN_PMC4
149 mfspr r8, SPRN_PMC5
150 mfspr r9, SPRN_PMC6
151 stw r3, HSTATE_PMC1(r13)
152 stw r5, HSTATE_PMC2(r13)
153 stw r6, HSTATE_PMC3(r13)
154 stw r7, HSTATE_PMC4(r13)
155 stw r8, HSTATE_PMC5(r13)
156 stw r9, HSTATE_PMC6(r13)
15731: blr
158SYM_FUNC_END(kvmhv_save_host_pmu)
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
16 *
17 * Derived from book3s_interrupts.S, which is:
18 * Copyright SUSE Linux Products GmbH 2009
19 *
20 * Authors: Alexander Graf <agraf@suse.de>
21 */
22
23#include <asm/ppc_asm.h>
24#include <asm/kvm_asm.h>
25#include <asm/reg.h>
26#include <asm/page.h>
27#include <asm/asm-offsets.h>
28#include <asm/exception-64s.h>
29#include <asm/ppc-opcode.h>
30
31/*****************************************************************************
32 * *
33 * Guest entry / exit code that is in kernel module memory (vmalloc) *
34 * *
35 ****************************************************************************/
36
37/* Registers:
38 * none
39 */
40_GLOBAL(__kvmppc_vcore_entry)
41
42 /* Write correct stack frame */
43 mflr r0
44 std r0,PPC_LR_STKOFF(r1)
45
46 /* Save host state to the stack */
47 stdu r1, -SWITCH_FRAME_SIZE(r1)
48
49 /* Save non-volatile registers (r14 - r31) and CR */
50 SAVE_NVGPRS(r1)
51 mfcr r3
52 std r3, _CCR(r1)
53
54 /* Save host DSCR */
55 mfspr r3, SPRN_DSCR
56 std r3, HSTATE_DSCR(r13)
57
58BEGIN_FTR_SECTION
59 /* Save host DABR */
60 mfspr r3, SPRN_DABR
61 std r3, HSTATE_DABR(r13)
62END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
63
64 /* Hard-disable interrupts */
65 mfmsr r10
66 std r10, HSTATE_HOST_MSR(r13)
67 rldicl r10,r10,48,1
68 rotldi r10,r10,16
69 mtmsrd r10,1
70
71 /* Save host PMU registers */
72BEGIN_FTR_SECTION
73 /* Work around P8 PMAE bug */
74 li r3, -1
75 clrrdi r3, r3, 10
76 mfspr r8, SPRN_MMCR2
77 mtspr SPRN_MMCR2, r3 /* freeze all counters using MMCR2 */
78 isync
79END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
80 li r3, 1
81 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
82 mfspr r7, SPRN_MMCR0 /* save MMCR0 */
83 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
84 mfspr r6, SPRN_MMCRA
85 /* Clear MMCRA in order to disable SDAR updates */
86 li r5, 0
87 mtspr SPRN_MMCRA, r5
88 isync
89 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
90 lbz r5, LPPACA_PMCINUSE(r3)
91 cmpwi r5, 0
92 beq 31f /* skip if not */
93 mfspr r5, SPRN_MMCR1
94 mfspr r9, SPRN_SIAR
95 mfspr r10, SPRN_SDAR
96 std r7, HSTATE_MMCR0(r13)
97 std r5, HSTATE_MMCR1(r13)
98 std r6, HSTATE_MMCRA(r13)
99 std r9, HSTATE_SIAR(r13)
100 std r10, HSTATE_SDAR(r13)
101BEGIN_FTR_SECTION
102 mfspr r9, SPRN_SIER
103 std r8, HSTATE_MMCR2(r13)
104 std r9, HSTATE_SIER(r13)
105END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
106 mfspr r3, SPRN_PMC1
107 mfspr r5, SPRN_PMC2
108 mfspr r6, SPRN_PMC3
109 mfspr r7, SPRN_PMC4
110 mfspr r8, SPRN_PMC5
111 mfspr r9, SPRN_PMC6
112 stw r3, HSTATE_PMC1(r13)
113 stw r5, HSTATE_PMC2(r13)
114 stw r6, HSTATE_PMC3(r13)
115 stw r7, HSTATE_PMC4(r13)
116 stw r8, HSTATE_PMC5(r13)
117 stw r9, HSTATE_PMC6(r13)
11831:
119
120 /*
121 * Put whatever is in the decrementer into the
122 * hypervisor decrementer.
123 */
124 mfspr r8,SPRN_DEC
125 mftb r7
126 mtspr SPRN_HDEC,r8
127 extsw r8,r8
128 add r8,r8,r7
129 std r8,HSTATE_DECEXP(r13)
130
131 /* Jump to partition switch code */
132 bl kvmppc_hv_entry_trampoline
133 nop
134
135/*
136 * We return here in virtual mode after the guest exits
137 * with something that we can't handle in real mode.
138 * Interrupts are enabled again at this point.
139 */
140
141 /*
142 * Register usage at this point:
143 *
144 * R1 = host R1
145 * R2 = host R2
146 * R12 = exit handler id
147 * R13 = PACA
148 */
149
150 /* Restore non-volatile host registers (r14 - r31) and CR */
151 REST_NVGPRS(r1)
152 ld r4, _CCR(r1)
153 mtcr r4
154
155 addi r1, r1, SWITCH_FRAME_SIZE
156 ld r0, PPC_LR_STKOFF(r1)
157 mtlr r0
158 blr