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1/*
2 * SBC8548 Device Tree Source
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/{
15 soc8548@e0000000 {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 device_type = "soc";
19 ranges = <0x00000000 0xe0000000 0x00100000>;
20 bus-frequency = <0>;
21 compatible = "simple-bus";
22
23 ecm-law@0 {
24 compatible = "fsl,ecm-law";
25 reg = <0x0 0x1000>;
26 fsl,num-laws = <10>;
27 };
28
29 ecm@1000 {
30 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
31 reg = <0x1000 0x1000>;
32 interrupts = <17 2>;
33 interrupt-parent = <&mpic>;
34 };
35
36 memory-controller@2000 {
37 compatible = "fsl,mpc8548-memory-controller";
38 reg = <0x2000 0x1000>;
39 interrupt-parent = <&mpic>;
40 interrupts = <0x12 0x2>;
41 };
42
43 L2: l2-cache-controller@20000 {
44 compatible = "fsl,mpc8548-l2-cache-controller";
45 reg = <0x20000 0x1000>;
46 cache-line-size = <0x20>; // 32 bytes
47 cache-size = <0x80000>; // L2, 512K
48 interrupt-parent = <&mpic>;
49 interrupts = <0x10 0x2>;
50 };
51
52 i2c@3000 {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 cell-index = <0>;
56 compatible = "fsl-i2c";
57 reg = <0x3000 0x100>;
58 interrupts = <0x2b 0x2>;
59 interrupt-parent = <&mpic>;
60 dfsrr;
61 };
62
63 i2c@3100 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 cell-index = <1>;
67 compatible = "fsl-i2c";
68 reg = <0x3100 0x100>;
69 interrupts = <0x2b 0x2>;
70 interrupt-parent = <&mpic>;
71 dfsrr;
72 };
73
74 dma@21300 {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
78 reg = <0x21300 0x4>;
79 ranges = <0x0 0x21100 0x200>;
80 cell-index = <0>;
81 dma-channel@0 {
82 compatible = "fsl,mpc8548-dma-channel",
83 "fsl,eloplus-dma-channel";
84 reg = <0x0 0x80>;
85 cell-index = <0>;
86 interrupt-parent = <&mpic>;
87 interrupts = <20 2>;
88 };
89 dma-channel@80 {
90 compatible = "fsl,mpc8548-dma-channel",
91 "fsl,eloplus-dma-channel";
92 reg = <0x80 0x80>;
93 cell-index = <1>;
94 interrupt-parent = <&mpic>;
95 interrupts = <21 2>;
96 };
97 dma-channel@100 {
98 compatible = "fsl,mpc8548-dma-channel",
99 "fsl,eloplus-dma-channel";
100 reg = <0x100 0x80>;
101 cell-index = <2>;
102 interrupt-parent = <&mpic>;
103 interrupts = <22 2>;
104 };
105 dma-channel@180 {
106 compatible = "fsl,mpc8548-dma-channel",
107 "fsl,eloplus-dma-channel";
108 reg = <0x180 0x80>;
109 cell-index = <3>;
110 interrupt-parent = <&mpic>;
111 interrupts = <23 2>;
112 };
113 };
114
115 enet0: ethernet@24000 {
116 #address-cells = <1>;
117 #size-cells = <1>;
118 cell-index = <0>;
119 device_type = "network";
120 model = "eTSEC";
121 compatible = "gianfar";
122 reg = <0x24000 0x1000>;
123 ranges = <0x0 0x24000 0x1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
126 interrupt-parent = <&mpic>;
127 tbi-handle = <&tbi0>;
128 phy-handle = <&phy0>;
129
130 mdio@520 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 compatible = "fsl,gianfar-mdio";
134 reg = <0x520 0x20>;
135
136 phy0: ethernet-phy@19 {
137 interrupt-parent = <&mpic>;
138 interrupts = <0x6 0x1>;
139 reg = <0x19>;
140 };
141 phy1: ethernet-phy@1a {
142 interrupt-parent = <&mpic>;
143 interrupts = <0x7 0x1>;
144 reg = <0x1a>;
145 };
146 tbi0: tbi-phy@11 {
147 reg = <0x11>;
148 device_type = "tbi-phy";
149 };
150 };
151 };
152
153 enet1: ethernet@25000 {
154 #address-cells = <1>;
155 #size-cells = <1>;
156 cell-index = <1>;
157 device_type = "network";
158 model = "eTSEC";
159 compatible = "gianfar";
160 reg = <0x25000 0x1000>;
161 ranges = <0x0 0x25000 0x1000>;
162 local-mac-address = [ 00 00 00 00 00 00 ];
163 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
164 interrupt-parent = <&mpic>;
165 tbi-handle = <&tbi1>;
166 phy-handle = <&phy1>;
167
168 mdio@520 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 compatible = "fsl,gianfar-tbi";
172 reg = <0x520 0x20>;
173
174 tbi1: tbi-phy@11 {
175 reg = <0x11>;
176 device_type = "tbi-phy";
177 };
178 };
179 };
180
181 serial0: serial@4500 {
182 cell-index = <0>;
183 device_type = "serial";
184 compatible = "fsl,ns16550", "ns16550";
185 reg = <0x4500 0x100>; // reg base, size
186 clock-frequency = <0>; // should we fill in in uboot?
187 interrupts = <0x2a 0x2>;
188 interrupt-parent = <&mpic>;
189 };
190
191 serial1: serial@4600 {
192 cell-index = <1>;
193 device_type = "serial";
194 compatible = "fsl,ns16550", "ns16550";
195 reg = <0x4600 0x100>; // reg base, size
196 clock-frequency = <0>; // should we fill in in uboot?
197 interrupts = <0x2a 0x2>;
198 interrupt-parent = <&mpic>;
199 };
200
201 global-utilities@e0000 { //global utilities reg
202 compatible = "fsl,mpc8548-guts";
203 reg = <0xe0000 0x1000>;
204 fsl,has-rstcr;
205 };
206
207 crypto@30000 {
208 compatible = "fsl,sec2.1", "fsl,sec2.0";
209 reg = <0x30000 0x10000>;
210 interrupts = <45 2>;
211 interrupt-parent = <&mpic>;
212 fsl,num-channels = <4>;
213 fsl,channel-fifo-len = <24>;
214 fsl,exec-units-mask = <0xfe>;
215 fsl,descriptor-types-mask = <0x12b0ebf>;
216 };
217
218 mpic: pic@40000 {
219 interrupt-controller;
220 #address-cells = <0>;
221 #interrupt-cells = <2>;
222 reg = <0x40000 0x40000>;
223 compatible = "chrp,open-pic";
224 device_type = "open-pic";
225 };
226 };
227
228 pci0: pci@e0008000 {
229 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
230 interrupt-map = <
231 /* IDSEL 0x01 (PCI-X slot) @66MHz */
232 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
233 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
234 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
235 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
236
237 /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
238 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
239 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
240 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
241 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
242
243 interrupt-parent = <&mpic>;
244 interrupts = <0x18 0x2>;
245 bus-range = <0 0>;
246 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
247 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
248 clock-frequency = <66000000>;
249 #interrupt-cells = <1>;
250 #size-cells = <2>;
251 #address-cells = <3>;
252 reg = <0xe0008000 0x1000>;
253 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
254 device_type = "pci";
255 };
256
257 pci1: pcie@e000a000 {
258 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
259 interrupt-map = <
260
261 /* IDSEL 0x0 (PEX) */
262 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
263 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
264 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
265 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
266
267 interrupt-parent = <&mpic>;
268 interrupts = <0x1a 0x2>;
269 bus-range = <0x0 0xff>;
270 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
271 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
272 clock-frequency = <33000000>;
273 #interrupt-cells = <1>;
274 #size-cells = <2>;
275 #address-cells = <3>;
276 reg = <0xe000a000 0x1000>;
277 compatible = "fsl,mpc8548-pcie";
278 device_type = "pci";
279 pcie@0 {
280 reg = <0x0 0x0 0x0 0x0 0x0>;
281 #size-cells = <2>;
282 #address-cells = <3>;
283 device_type = "pci";
284 ranges = <0x02000000 0x0 0xa0000000
285 0x02000000 0x0 0xa0000000
286 0x0 0x10000000
287
288 0x01000000 0x0 0x00000000
289 0x01000000 0x0 0x00000000
290 0x0 0x00800000>;
291 };
292 };
293};