Loading...
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
10#include <linux/cpu_pm.h>
11#include <linux/hardirq.h>
12#include <linux/init.h>
13#include <linux/highmem.h>
14#include <linux/kernel.h>
15#include <linux/linkage.h>
16#include <linux/preempt.h>
17#include <linux/sched.h>
18#include <linux/smp.h>
19#include <linux/mm.h>
20#include <linux/export.h>
21#include <linux/bitops.h>
22#include <linux/dma-map-ops.h> /* for dma_default_coherent */
23
24#include <asm/bcache.h>
25#include <asm/bootinfo.h>
26#include <asm/cache.h>
27#include <asm/cacheops.h>
28#include <asm/cpu.h>
29#include <asm/cpu-features.h>
30#include <asm/cpu-type.h>
31#include <asm/io.h>
32#include <asm/page.h>
33#include <asm/r4kcache.h>
34#include <asm/sections.h>
35#include <asm/mmu_context.h>
36#include <asm/cacheflush.h> /* for run_uncached() */
37#include <asm/traps.h>
38#include <asm/mips-cps.h>
39
40/*
41 * Bits describing what cache ops an SMP callback function may perform.
42 *
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
44 * active_mm must be checked before using user addresses, falling
45 * back to kmap.
46 * R4K_INDEX - Index based cache operations.
47 */
48
49#define R4K_HIT BIT(0)
50#define R4K_INDEX BIT(1)
51
52/**
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
54 * @type: Type of cache operations (R4K_HIT or R4K_INDEX).
55 *
56 * Decides whether a cache op needs to be performed on every core in the system.
57 * This may change depending on the @type of cache operation, as well as the set
58 * of online CPUs, so preemption should be disabled by the caller to prevent CPU
59 * hotplug from changing the result.
60 *
61 * Returns: 1 if the cache operation @type should be done on every core in
62 * the system.
63 * 0 if the cache operation @type is globalized and only needs to
64 * be performed on a simple CPU.
65 */
66static inline bool r4k_op_needs_ipi(unsigned int type)
67{
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
69 if (type == R4K_HIT && mips_cm_present())
70 return false;
71
72 /*
73 * Hardware doesn't globalize the required cache ops, so SMP calls may
74 * be needed, but only if there are foreign CPUs (non-siblings with
75 * separate caches).
76 */
77 /* cpu_foreign_map[] undeclared when !CONFIG_SMP */
78#ifdef CONFIG_SMP
79 return !cpumask_empty(&cpu_foreign_map[0]);
80#else
81 return false;
82#endif
83}
84
85/*
86 * Special Variant of smp_call_function for use by cache functions:
87 *
88 * o No return value
89 * o collapses to normal function call on UP kernels
90 * o collapses to normal function call on systems with a single shared
91 * primary cache.
92 * o doesn't disable interrupts on the local CPU
93 */
94static inline void r4k_on_each_cpu(unsigned int type,
95 void (*func)(void *info), void *info)
96{
97 preempt_disable();
98 if (r4k_op_needs_ipi(type))
99 smp_call_function_many(&cpu_foreign_map[smp_processor_id()],
100 func, info, 1);
101 func(info);
102 preempt_enable();
103}
104
105/*
106 * Must die.
107 */
108static unsigned long icache_size __read_mostly;
109static unsigned long dcache_size __read_mostly;
110static unsigned long vcache_size __read_mostly;
111static unsigned long scache_size __read_mostly;
112
113#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
114#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
115
116#define R4600_HIT_CACHEOP_WAR_IMPL \
117do { \
118 if (IS_ENABLED(CONFIG_WAR_R4600_V2_HIT_CACHEOP) && \
119 cpu_is_r4600_v2_x()) \
120 *(volatile unsigned long *)CKSEG1; \
121 if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP)) \
122 __asm__ __volatile__("nop;nop;nop;nop"); \
123} while (0)
124
125static void (*r4k_blast_dcache_page)(unsigned long addr);
126
127static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
128{
129 R4600_HIT_CACHEOP_WAR_IMPL;
130 blast_dcache32_page(addr);
131}
132
133static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
134{
135 blast_dcache64_page(addr);
136}
137
138static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
139{
140 blast_dcache128_page(addr);
141}
142
143static void r4k_blast_dcache_page_setup(void)
144{
145 unsigned long dc_lsize = cpu_dcache_line_size();
146
147 switch (dc_lsize) {
148 case 0:
149 r4k_blast_dcache_page = (void *)cache_noop;
150 break;
151 case 16:
152 r4k_blast_dcache_page = blast_dcache16_page;
153 break;
154 case 32:
155 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
156 break;
157 case 64:
158 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
159 break;
160 case 128:
161 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
162 break;
163 default:
164 break;
165 }
166}
167
168#ifndef CONFIG_EVA
169#define r4k_blast_dcache_user_page r4k_blast_dcache_page
170#else
171
172static void (*r4k_blast_dcache_user_page)(unsigned long addr);
173
174static void r4k_blast_dcache_user_page_setup(void)
175{
176 unsigned long dc_lsize = cpu_dcache_line_size();
177
178 if (dc_lsize == 0)
179 r4k_blast_dcache_user_page = (void *)cache_noop;
180 else if (dc_lsize == 16)
181 r4k_blast_dcache_user_page = blast_dcache16_user_page;
182 else if (dc_lsize == 32)
183 r4k_blast_dcache_user_page = blast_dcache32_user_page;
184 else if (dc_lsize == 64)
185 r4k_blast_dcache_user_page = blast_dcache64_user_page;
186}
187
188#endif
189
190void (* r4k_blast_dcache)(void);
191EXPORT_SYMBOL(r4k_blast_dcache);
192
193static void r4k_blast_dcache_setup(void)
194{
195 unsigned long dc_lsize = cpu_dcache_line_size();
196
197 if (dc_lsize == 0)
198 r4k_blast_dcache = (void *)cache_noop;
199 else if (dc_lsize == 16)
200 r4k_blast_dcache = blast_dcache16;
201 else if (dc_lsize == 32)
202 r4k_blast_dcache = blast_dcache32;
203 else if (dc_lsize == 64)
204 r4k_blast_dcache = blast_dcache64;
205 else if (dc_lsize == 128)
206 r4k_blast_dcache = blast_dcache128;
207}
208
209/* force code alignment (used for CONFIG_WAR_TX49XX_ICACHE_INDEX_INV) */
210#define JUMP_TO_ALIGN(order) \
211 __asm__ __volatile__( \
212 "b\t1f\n\t" \
213 ".align\t" #order "\n\t" \
214 "1:\n\t" \
215 )
216#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
217#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
218
219static inline void blast_r4600_v1_icache32(void)
220{
221 unsigned long flags;
222
223 local_irq_save(flags);
224 blast_icache32();
225 local_irq_restore(flags);
226}
227
228static inline void tx49_blast_icache32(void)
229{
230 unsigned long start = INDEX_BASE;
231 unsigned long end = start + current_cpu_data.icache.waysize;
232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
233 unsigned long ws_end = current_cpu_data.icache.ways <<
234 current_cpu_data.icache.waybit;
235 unsigned long ws, addr;
236
237 CACHE32_UNROLL32_ALIGN2;
238 /* I'm in even chunk. blast odd chunks */
239 for (ws = 0; ws < ws_end; ws += ws_inc)
240 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
241 cache_unroll(32, kernel_cache, Index_Invalidate_I,
242 addr | ws, 32);
243 CACHE32_UNROLL32_ALIGN;
244 /* I'm in odd chunk. blast even chunks */
245 for (ws = 0; ws < ws_end; ws += ws_inc)
246 for (addr = start; addr < end; addr += 0x400 * 2)
247 cache_unroll(32, kernel_cache, Index_Invalidate_I,
248 addr | ws, 32);
249}
250
251static void (* r4k_blast_icache_page)(unsigned long addr);
252
253static void r4k_blast_icache_page_setup(void)
254{
255 unsigned long ic_lsize = cpu_icache_line_size();
256
257 if (ic_lsize == 0)
258 r4k_blast_icache_page = (void *)cache_noop;
259 else if (ic_lsize == 16)
260 r4k_blast_icache_page = blast_icache16_page;
261 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2EF)
262 r4k_blast_icache_page = loongson2_blast_icache32_page;
263 else if (ic_lsize == 32)
264 r4k_blast_icache_page = blast_icache32_page;
265 else if (ic_lsize == 64)
266 r4k_blast_icache_page = blast_icache64_page;
267 else if (ic_lsize == 128)
268 r4k_blast_icache_page = blast_icache128_page;
269}
270
271#ifndef CONFIG_EVA
272#define r4k_blast_icache_user_page r4k_blast_icache_page
273#else
274
275static void (*r4k_blast_icache_user_page)(unsigned long addr);
276
277static void r4k_blast_icache_user_page_setup(void)
278{
279 unsigned long ic_lsize = cpu_icache_line_size();
280
281 if (ic_lsize == 0)
282 r4k_blast_icache_user_page = (void *)cache_noop;
283 else if (ic_lsize == 16)
284 r4k_blast_icache_user_page = blast_icache16_user_page;
285 else if (ic_lsize == 32)
286 r4k_blast_icache_user_page = blast_icache32_user_page;
287 else if (ic_lsize == 64)
288 r4k_blast_icache_user_page = blast_icache64_user_page;
289}
290
291#endif
292
293void (* r4k_blast_icache)(void);
294EXPORT_SYMBOL(r4k_blast_icache);
295
296static void r4k_blast_icache_setup(void)
297{
298 unsigned long ic_lsize = cpu_icache_line_size();
299
300 if (ic_lsize == 0)
301 r4k_blast_icache = (void *)cache_noop;
302 else if (ic_lsize == 16)
303 r4k_blast_icache = blast_icache16;
304 else if (ic_lsize == 32) {
305 if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) &&
306 cpu_is_r4600_v1_x())
307 r4k_blast_icache = blast_r4600_v1_icache32;
308 else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV))
309 r4k_blast_icache = tx49_blast_icache32;
310 else if (current_cpu_type() == CPU_LOONGSON2EF)
311 r4k_blast_icache = loongson2_blast_icache32;
312 else
313 r4k_blast_icache = blast_icache32;
314 } else if (ic_lsize == 64)
315 r4k_blast_icache = blast_icache64;
316 else if (ic_lsize == 128)
317 r4k_blast_icache = blast_icache128;
318}
319
320static void (* r4k_blast_scache_page)(unsigned long addr);
321
322static void r4k_blast_scache_page_setup(void)
323{
324 unsigned long sc_lsize = cpu_scache_line_size();
325
326 if (scache_size == 0)
327 r4k_blast_scache_page = (void *)cache_noop;
328 else if (sc_lsize == 16)
329 r4k_blast_scache_page = blast_scache16_page;
330 else if (sc_lsize == 32)
331 r4k_blast_scache_page = blast_scache32_page;
332 else if (sc_lsize == 64)
333 r4k_blast_scache_page = blast_scache64_page;
334 else if (sc_lsize == 128)
335 r4k_blast_scache_page = blast_scache128_page;
336}
337
338static void (* r4k_blast_scache)(void);
339
340static void r4k_blast_scache_setup(void)
341{
342 unsigned long sc_lsize = cpu_scache_line_size();
343
344 if (scache_size == 0)
345 r4k_blast_scache = (void *)cache_noop;
346 else if (sc_lsize == 16)
347 r4k_blast_scache = blast_scache16;
348 else if (sc_lsize == 32)
349 r4k_blast_scache = blast_scache32;
350 else if (sc_lsize == 64)
351 r4k_blast_scache = blast_scache64;
352 else if (sc_lsize == 128)
353 r4k_blast_scache = blast_scache128;
354}
355
356static void (*r4k_blast_scache_node)(long node);
357
358static void r4k_blast_scache_node_setup(void)
359{
360 unsigned long sc_lsize = cpu_scache_line_size();
361
362 if (current_cpu_type() != CPU_LOONGSON64)
363 r4k_blast_scache_node = (void *)cache_noop;
364 else if (sc_lsize == 16)
365 r4k_blast_scache_node = blast_scache16_node;
366 else if (sc_lsize == 32)
367 r4k_blast_scache_node = blast_scache32_node;
368 else if (sc_lsize == 64)
369 r4k_blast_scache_node = blast_scache64_node;
370 else if (sc_lsize == 128)
371 r4k_blast_scache_node = blast_scache128_node;
372}
373
374static inline void local_r4k___flush_cache_all(void * args)
375{
376 switch (current_cpu_type()) {
377 case CPU_LOONGSON2EF:
378 case CPU_R4000SC:
379 case CPU_R4000MC:
380 case CPU_R4400SC:
381 case CPU_R4400MC:
382 case CPU_R10000:
383 case CPU_R12000:
384 case CPU_R14000:
385 case CPU_R16000:
386 /*
387 * These caches are inclusive caches, that is, if something
388 * is not cached in the S-cache, we know it also won't be
389 * in one of the primary caches.
390 */
391 r4k_blast_scache();
392 break;
393
394 case CPU_LOONGSON64:
395 /* Use get_ebase_cpunum() for both NUMA=y/n */
396 r4k_blast_scache_node(get_ebase_cpunum() >> 2);
397 break;
398
399 case CPU_BMIPS5000:
400 r4k_blast_scache();
401 __sync();
402 break;
403
404 default:
405 r4k_blast_dcache();
406 r4k_blast_icache();
407 break;
408 }
409}
410
411static void r4k___flush_cache_all(void)
412{
413 r4k_on_each_cpu(R4K_INDEX, local_r4k___flush_cache_all, NULL);
414}
415
416/**
417 * has_valid_asid() - Determine if an mm already has an ASID.
418 * @mm: Memory map.
419 * @type: R4K_HIT or R4K_INDEX, type of cache op.
420 *
421 * Determines whether @mm already has an ASID on any of the CPUs which cache ops
422 * of type @type within an r4k_on_each_cpu() call will affect. If
423 * r4k_on_each_cpu() does an SMP call to a single VPE in each core, then the
424 * scope of the operation is confined to sibling CPUs, otherwise all online CPUs
425 * will need to be checked.
426 *
427 * Must be called in non-preemptive context.
428 *
429 * Returns: 1 if the CPUs affected by @type cache ops have an ASID for @mm.
430 * 0 otherwise.
431 */
432static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
433{
434 unsigned int i;
435 const cpumask_t *mask = cpu_present_mask;
436
437 if (cpu_has_mmid)
438 return cpu_context(0, mm) != 0;
439
440 /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
441#ifdef CONFIG_SMP
442 /*
443 * If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
444 * each foreign core, so we only need to worry about siblings.
445 * Otherwise we need to worry about all present CPUs.
446 */
447 if (r4k_op_needs_ipi(type))
448 mask = &cpu_sibling_map[smp_processor_id()];
449#endif
450 for_each_cpu(i, mask)
451 if (cpu_context(i, mm))
452 return 1;
453 return 0;
454}
455
456static void r4k__flush_cache_vmap(void)
457{
458 r4k_blast_dcache();
459}
460
461static void r4k__flush_cache_vunmap(void)
462{
463 r4k_blast_dcache();
464}
465
466/*
467 * Note: flush_tlb_range() assumes flush_cache_range() sufficiently flushes
468 * whole caches when vma is executable.
469 */
470static inline void local_r4k_flush_cache_range(void * args)
471{
472 struct vm_area_struct *vma = args;
473 int exec = vma->vm_flags & VM_EXEC;
474
475 if (!has_valid_asid(vma->vm_mm, R4K_INDEX))
476 return;
477
478 /*
479 * If dcache can alias, we must blast it since mapping is changing.
480 * If executable, we must ensure any dirty lines are written back far
481 * enough to be visible to icache.
482 */
483 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
484 r4k_blast_dcache();
485 /* If executable, blast stale lines from icache */
486 if (exec)
487 r4k_blast_icache();
488}
489
490static void r4k_flush_cache_range(struct vm_area_struct *vma,
491 unsigned long start, unsigned long end)
492{
493 int exec = vma->vm_flags & VM_EXEC;
494
495 if (cpu_has_dc_aliases || exec)
496 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_range, vma);
497}
498
499static inline void local_r4k_flush_cache_mm(void * args)
500{
501 struct mm_struct *mm = args;
502
503 if (!has_valid_asid(mm, R4K_INDEX))
504 return;
505
506 /*
507 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
508 * only flush the primary caches but R1x000 behave sane ...
509 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
510 * caches, so we can bail out early.
511 */
512 if (current_cpu_type() == CPU_R4000SC ||
513 current_cpu_type() == CPU_R4000MC ||
514 current_cpu_type() == CPU_R4400SC ||
515 current_cpu_type() == CPU_R4400MC) {
516 r4k_blast_scache();
517 return;
518 }
519
520 r4k_blast_dcache();
521}
522
523static void r4k_flush_cache_mm(struct mm_struct *mm)
524{
525 if (!cpu_has_dc_aliases)
526 return;
527
528 r4k_on_each_cpu(R4K_INDEX, local_r4k_flush_cache_mm, mm);
529}
530
531struct flush_cache_page_args {
532 struct vm_area_struct *vma;
533 unsigned long addr;
534 unsigned long pfn;
535};
536
537static inline void local_r4k_flush_cache_page(void *args)
538{
539 struct flush_cache_page_args *fcp_args = args;
540 struct vm_area_struct *vma = fcp_args->vma;
541 unsigned long addr = fcp_args->addr;
542 struct page *page = pfn_to_page(fcp_args->pfn);
543 int exec = vma->vm_flags & VM_EXEC;
544 struct mm_struct *mm = vma->vm_mm;
545 int map_coherent = 0;
546 pmd_t *pmdp;
547 pte_t *ptep;
548 void *vaddr;
549
550 /*
551 * If owns no valid ASID yet, cannot possibly have gotten
552 * this page into the cache.
553 */
554 if (!has_valid_asid(mm, R4K_HIT))
555 return;
556
557 addr &= PAGE_MASK;
558 pmdp = pmd_off(mm, addr);
559 ptep = pte_offset_kernel(pmdp, addr);
560
561 /*
562 * If the page isn't marked valid, the page cannot possibly be
563 * in the cache.
564 */
565 if (!(pte_present(*ptep)))
566 return;
567
568 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
569 vaddr = NULL;
570 else {
571 struct folio *folio = page_folio(page);
572 /*
573 * Use kmap_coherent or kmap_atomic to do flushes for
574 * another ASID than the current one.
575 */
576 map_coherent = (cpu_has_dc_aliases &&
577 folio_mapped(folio) &&
578 !folio_test_dcache_dirty(folio));
579 if (map_coherent)
580 vaddr = kmap_coherent(page, addr);
581 else
582 vaddr = kmap_atomic(page);
583 addr = (unsigned long)vaddr;
584 }
585
586 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
587 vaddr ? r4k_blast_dcache_page(addr) :
588 r4k_blast_dcache_user_page(addr);
589 if (exec && !cpu_icache_snoops_remote_store)
590 r4k_blast_scache_page(addr);
591 }
592 if (exec) {
593 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
594 drop_mmu_context(mm);
595 } else
596 vaddr ? r4k_blast_icache_page(addr) :
597 r4k_blast_icache_user_page(addr);
598 }
599
600 if (vaddr) {
601 if (map_coherent)
602 kunmap_coherent();
603 else
604 kunmap_atomic(vaddr);
605 }
606}
607
608static void r4k_flush_cache_page(struct vm_area_struct *vma,
609 unsigned long addr, unsigned long pfn)
610{
611 struct flush_cache_page_args args;
612
613 args.vma = vma;
614 args.addr = addr;
615 args.pfn = pfn;
616
617 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_cache_page, &args);
618}
619
620static inline void local_r4k_flush_data_cache_page(void * addr)
621{
622 r4k_blast_dcache_page((unsigned long) addr);
623}
624
625static void r4k_flush_data_cache_page(unsigned long addr)
626{
627 if (in_atomic())
628 local_r4k_flush_data_cache_page((void *)addr);
629 else
630 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_data_cache_page,
631 (void *) addr);
632}
633
634struct flush_icache_range_args {
635 unsigned long start;
636 unsigned long end;
637 unsigned int type;
638 bool user;
639};
640
641static inline void __local_r4k_flush_icache_range(unsigned long start,
642 unsigned long end,
643 unsigned int type,
644 bool user)
645{
646 if (!cpu_has_ic_fills_f_dc) {
647 if (type == R4K_INDEX ||
648 (type & R4K_INDEX && end - start >= dcache_size)) {
649 r4k_blast_dcache();
650 } else {
651 R4600_HIT_CACHEOP_WAR_IMPL;
652 if (user)
653 protected_blast_dcache_range(start, end);
654 else
655 blast_dcache_range(start, end);
656 }
657 }
658
659 if (type == R4K_INDEX ||
660 (type & R4K_INDEX && end - start > icache_size))
661 r4k_blast_icache();
662 else {
663 switch (boot_cpu_type()) {
664 case CPU_LOONGSON2EF:
665 protected_loongson2_blast_icache_range(start, end);
666 break;
667
668 default:
669 if (user)
670 protected_blast_icache_range(start, end);
671 else
672 blast_icache_range(start, end);
673 break;
674 }
675 }
676}
677
678static inline void local_r4k_flush_icache_range(unsigned long start,
679 unsigned long end)
680{
681 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, false);
682}
683
684static inline void local_r4k_flush_icache_user_range(unsigned long start,
685 unsigned long end)
686{
687 __local_r4k_flush_icache_range(start, end, R4K_HIT | R4K_INDEX, true);
688}
689
690static inline void local_r4k_flush_icache_range_ipi(void *args)
691{
692 struct flush_icache_range_args *fir_args = args;
693 unsigned long start = fir_args->start;
694 unsigned long end = fir_args->end;
695 unsigned int type = fir_args->type;
696 bool user = fir_args->user;
697
698 __local_r4k_flush_icache_range(start, end, type, user);
699}
700
701static void __r4k_flush_icache_range(unsigned long start, unsigned long end,
702 bool user)
703{
704 struct flush_icache_range_args args;
705 unsigned long size, cache_size;
706
707 args.start = start;
708 args.end = end;
709 args.type = R4K_HIT | R4K_INDEX;
710 args.user = user;
711
712 /*
713 * Indexed cache ops require an SMP call.
714 * Consider if that can or should be avoided.
715 */
716 preempt_disable();
717 if (r4k_op_needs_ipi(R4K_INDEX) && !r4k_op_needs_ipi(R4K_HIT)) {
718 /*
719 * If address-based cache ops don't require an SMP call, then
720 * use them exclusively for small flushes.
721 */
722 size = end - start;
723 cache_size = icache_size;
724 if (!cpu_has_ic_fills_f_dc) {
725 size *= 2;
726 cache_size += dcache_size;
727 }
728 if (size <= cache_size)
729 args.type &= ~R4K_INDEX;
730 }
731 r4k_on_each_cpu(args.type, local_r4k_flush_icache_range_ipi, &args);
732 preempt_enable();
733 instruction_hazard();
734}
735
736static void r4k_flush_icache_range(unsigned long start, unsigned long end)
737{
738 return __r4k_flush_icache_range(start, end, false);
739}
740
741static void r4k_flush_icache_user_range(unsigned long start, unsigned long end)
742{
743 return __r4k_flush_icache_range(start, end, true);
744}
745
746#ifdef CONFIG_DMA_NONCOHERENT
747
748static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
749{
750 /* Catch bad driver code */
751 if (WARN_ON(size == 0))
752 return;
753
754 preempt_disable();
755 if (cpu_has_inclusive_pcaches) {
756 if (size >= scache_size) {
757 if (current_cpu_type() != CPU_LOONGSON64)
758 r4k_blast_scache();
759 else
760 r4k_blast_scache_node(pa_to_nid(addr));
761 } else {
762 blast_scache_range(addr, addr + size);
763 }
764 preempt_enable();
765 __sync();
766 return;
767 }
768
769 /*
770 * Either no secondary cache or the available caches don't have the
771 * subset property so we have to flush the primary caches
772 * explicitly.
773 * If we would need IPI to perform an INDEX-type operation, then
774 * we have to use the HIT-type alternative as IPI cannot be used
775 * here due to interrupts possibly being disabled.
776 */
777 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
778 r4k_blast_dcache();
779 } else {
780 R4600_HIT_CACHEOP_WAR_IMPL;
781 blast_dcache_range(addr, addr + size);
782 }
783 preempt_enable();
784
785 bc_wback_inv(addr, size);
786 __sync();
787}
788
789static void prefetch_cache_inv(unsigned long addr, unsigned long size)
790{
791 unsigned int linesz = cpu_scache_line_size();
792 unsigned long addr0 = addr, addr1;
793
794 addr0 &= ~(linesz - 1);
795 addr1 = (addr0 + size - 1) & ~(linesz - 1);
796
797 protected_writeback_scache_line(addr0);
798 if (likely(addr1 != addr0))
799 protected_writeback_scache_line(addr1);
800 else
801 return;
802
803 addr0 += linesz;
804 if (likely(addr1 != addr0))
805 protected_writeback_scache_line(addr0);
806 else
807 return;
808
809 addr1 -= linesz;
810 if (likely(addr1 > addr0))
811 protected_writeback_scache_line(addr0);
812}
813
814static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
815{
816 /* Catch bad driver code */
817 if (WARN_ON(size == 0))
818 return;
819
820 preempt_disable();
821
822 if (current_cpu_type() == CPU_BMIPS5000)
823 prefetch_cache_inv(addr, size);
824
825 if (cpu_has_inclusive_pcaches) {
826 if (size >= scache_size) {
827 if (current_cpu_type() != CPU_LOONGSON64)
828 r4k_blast_scache();
829 else
830 r4k_blast_scache_node(pa_to_nid(addr));
831 } else {
832 /*
833 * There is no clearly documented alignment requirement
834 * for the cache instruction on MIPS processors and
835 * some processors, among them the RM5200 and RM7000
836 * QED processors will throw an address error for cache
837 * hit ops with insufficient alignment. Solved by
838 * aligning the address to cache line size.
839 */
840 blast_inv_scache_range(addr, addr + size);
841 }
842 preempt_enable();
843 __sync();
844 return;
845 }
846
847 if (!r4k_op_needs_ipi(R4K_INDEX) && size >= dcache_size) {
848 r4k_blast_dcache();
849 } else {
850 R4600_HIT_CACHEOP_WAR_IMPL;
851 blast_inv_dcache_range(addr, addr + size);
852 }
853 preempt_enable();
854
855 bc_inv(addr, size);
856 __sync();
857}
858#endif /* CONFIG_DMA_NONCOHERENT */
859
860static void r4k_flush_icache_all(void)
861{
862 if (cpu_has_vtag_icache)
863 r4k_blast_icache();
864}
865
866struct flush_kernel_vmap_range_args {
867 unsigned long vaddr;
868 int size;
869};
870
871static inline void local_r4k_flush_kernel_vmap_range_index(void *args)
872{
873 /*
874 * Aliases only affect the primary caches so don't bother with
875 * S-caches or T-caches.
876 */
877 r4k_blast_dcache();
878}
879
880static inline void local_r4k_flush_kernel_vmap_range(void *args)
881{
882 struct flush_kernel_vmap_range_args *vmra = args;
883 unsigned long vaddr = vmra->vaddr;
884 int size = vmra->size;
885
886 /*
887 * Aliases only affect the primary caches so don't bother with
888 * S-caches or T-caches.
889 */
890 R4600_HIT_CACHEOP_WAR_IMPL;
891 blast_dcache_range(vaddr, vaddr + size);
892}
893
894static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
895{
896 struct flush_kernel_vmap_range_args args;
897
898 args.vaddr = (unsigned long) vaddr;
899 args.size = size;
900
901 if (size >= dcache_size)
902 r4k_on_each_cpu(R4K_INDEX,
903 local_r4k_flush_kernel_vmap_range_index, NULL);
904 else
905 r4k_on_each_cpu(R4K_HIT, local_r4k_flush_kernel_vmap_range,
906 &args);
907}
908
909static inline void rm7k_erratum31(void)
910{
911 const unsigned long ic_lsize = 32;
912 unsigned long addr;
913
914 /* RM7000 erratum #31. The icache is screwed at startup. */
915 write_c0_taglo(0);
916 write_c0_taghi(0);
917
918 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
919 __asm__ __volatile__ (
920 ".set push\n\t"
921 ".set noreorder\n\t"
922 ".set mips3\n\t"
923 "cache\t%1, 0(%0)\n\t"
924 "cache\t%1, 0x1000(%0)\n\t"
925 "cache\t%1, 0x2000(%0)\n\t"
926 "cache\t%1, 0x3000(%0)\n\t"
927 "cache\t%2, 0(%0)\n\t"
928 "cache\t%2, 0x1000(%0)\n\t"
929 "cache\t%2, 0x2000(%0)\n\t"
930 "cache\t%2, 0x3000(%0)\n\t"
931 "cache\t%1, 0(%0)\n\t"
932 "cache\t%1, 0x1000(%0)\n\t"
933 "cache\t%1, 0x2000(%0)\n\t"
934 "cache\t%1, 0x3000(%0)\n\t"
935 ".set pop\n"
936 :
937 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I));
938 }
939}
940
941static inline int alias_74k_erratum(struct cpuinfo_mips *c)
942{
943 unsigned int imp = c->processor_id & PRID_IMP_MASK;
944 unsigned int rev = c->processor_id & PRID_REV_MASK;
945 int present = 0;
946
947 /*
948 * Early versions of the 74K do not update the cache tags on a
949 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
950 * aliases. In this case it is better to treat the cache as always
951 * having aliases. Also disable the synonym tag update feature
952 * where available. In this case no opportunistic tag update will
953 * happen where a load causes a virtual address miss but a physical
954 * address hit during a D-cache look-up.
955 */
956 switch (imp) {
957 case PRID_IMP_74K:
958 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
959 present = 1;
960 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
961 write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
962 break;
963 case PRID_IMP_1074K:
964 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
965 present = 1;
966 write_c0_config6(read_c0_config6() | MTI_CONF6_SYND);
967 }
968 break;
969 default:
970 BUG();
971 }
972
973 return present;
974}
975
976static void b5k_instruction_hazard(void)
977{
978 __sync();
979 __sync();
980 __asm__ __volatile__(
981 " nop; nop; nop; nop; nop; nop; nop; nop\n"
982 " nop; nop; nop; nop; nop; nop; nop; nop\n"
983 " nop; nop; nop; nop; nop; nop; nop; nop\n"
984 " nop; nop; nop; nop; nop; nop; nop; nop\n"
985 : : : "memory");
986}
987
988static char *way_string[] = { NULL, "direct mapped", "2-way",
989 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
990 "9-way", "10-way", "11-way", "12-way",
991 "13-way", "14-way", "15-way", "16-way",
992};
993
994static void probe_pcache(void)
995{
996 struct cpuinfo_mips *c = ¤t_cpu_data;
997 unsigned int config = read_c0_config();
998 unsigned int prid = read_c0_prid();
999 int has_74k_erratum = 0;
1000 unsigned long config1;
1001 unsigned int lsize;
1002
1003 switch (current_cpu_type()) {
1004 case CPU_R4600: /* QED style two way caches? */
1005 case CPU_R4700:
1006 case CPU_R5000:
1007 case CPU_NEVADA:
1008 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1009 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1010 c->icache.ways = 2;
1011 c->icache.waybit = __ffs(icache_size/2);
1012
1013 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1014 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1015 c->dcache.ways = 2;
1016 c->dcache.waybit= __ffs(dcache_size/2);
1017
1018 c->options |= MIPS_CPU_CACHE_CDEX_P;
1019 break;
1020
1021 case CPU_R5500:
1022 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1023 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1024 c->icache.ways = 2;
1025 c->icache.waybit= 0;
1026
1027 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1028 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1029 c->dcache.ways = 2;
1030 c->dcache.waybit = 0;
1031
1032 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
1033 break;
1034
1035 case CPU_TX49XX:
1036 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1037 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1038 c->icache.ways = 4;
1039 c->icache.waybit= 0;
1040
1041 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1042 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1043 c->dcache.ways = 4;
1044 c->dcache.waybit = 0;
1045
1046 c->options |= MIPS_CPU_CACHE_CDEX_P;
1047 c->options |= MIPS_CPU_PREFETCH;
1048 break;
1049
1050 case CPU_R4000PC:
1051 case CPU_R4000SC:
1052 case CPU_R4000MC:
1053 case CPU_R4400PC:
1054 case CPU_R4400SC:
1055 case CPU_R4400MC:
1056 case CPU_R4300:
1057 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1058 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1059 c->icache.ways = 1;
1060 c->icache.waybit = 0; /* doesn't matter */
1061
1062 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1063 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1064 c->dcache.ways = 1;
1065 c->dcache.waybit = 0; /* does not matter */
1066
1067 c->options |= MIPS_CPU_CACHE_CDEX_P;
1068 break;
1069
1070 case CPU_R10000:
1071 case CPU_R12000:
1072 case CPU_R14000:
1073 case CPU_R16000:
1074 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1075 c->icache.linesz = 64;
1076 c->icache.ways = 2;
1077 c->icache.waybit = 0;
1078
1079 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1080 c->dcache.linesz = 32;
1081 c->dcache.ways = 2;
1082 c->dcache.waybit = 0;
1083
1084 c->options |= MIPS_CPU_PREFETCH;
1085 break;
1086
1087 case CPU_RM7000:
1088 rm7k_erratum31();
1089
1090 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1091 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1092 c->icache.ways = 4;
1093 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1094
1095 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1096 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1097 c->dcache.ways = 4;
1098 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1099
1100 c->options |= MIPS_CPU_CACHE_CDEX_P;
1101 c->options |= MIPS_CPU_PREFETCH;
1102 break;
1103
1104 case CPU_LOONGSON2EF:
1105 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1106 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1107 if (prid & 0x3)
1108 c->icache.ways = 4;
1109 else
1110 c->icache.ways = 2;
1111 c->icache.waybit = 0;
1112
1113 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1114 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1115 if (prid & 0x3)
1116 c->dcache.ways = 4;
1117 else
1118 c->dcache.ways = 2;
1119 c->dcache.waybit = 0;
1120 break;
1121
1122 case CPU_LOONGSON64:
1123 config1 = read_c0_config1();
1124 lsize = (config1 >> 19) & 7;
1125 if (lsize)
1126 c->icache.linesz = 2 << lsize;
1127 else
1128 c->icache.linesz = 0;
1129 c->icache.sets = 64 << ((config1 >> 22) & 7);
1130 c->icache.ways = 1 + ((config1 >> 16) & 7);
1131 icache_size = c->icache.sets *
1132 c->icache.ways *
1133 c->icache.linesz;
1134 c->icache.waybit = 0;
1135
1136 lsize = (config1 >> 10) & 7;
1137 if (lsize)
1138 c->dcache.linesz = 2 << lsize;
1139 else
1140 c->dcache.linesz = 0;
1141 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1142 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1143 dcache_size = c->dcache.sets *
1144 c->dcache.ways *
1145 c->dcache.linesz;
1146 c->dcache.waybit = 0;
1147 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
1148 (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
1149 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1150 c->options |= MIPS_CPU_PREFETCH;
1151 break;
1152
1153 case CPU_CAVIUM_OCTEON3:
1154 /* For now lie about the number of ways. */
1155 c->icache.linesz = 128;
1156 c->icache.sets = 16;
1157 c->icache.ways = 8;
1158 c->icache.flags |= MIPS_CACHE_VTAG;
1159 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1160
1161 c->dcache.linesz = 128;
1162 c->dcache.ways = 8;
1163 c->dcache.sets = 8;
1164 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1165 c->options |= MIPS_CPU_PREFETCH;
1166 break;
1167
1168 default:
1169 if (!(config & MIPS_CONF_M))
1170 panic("Don't know how to probe P-caches on this cpu.");
1171
1172 /*
1173 * So we seem to be a MIPS32 or MIPS64 CPU
1174 * So let's probe the I-cache ...
1175 */
1176 config1 = read_c0_config1();
1177
1178 lsize = (config1 >> 19) & 7;
1179
1180 /* IL == 7 is reserved */
1181 if (lsize == 7)
1182 panic("Invalid icache line size");
1183
1184 c->icache.linesz = lsize ? 2 << lsize : 0;
1185
1186 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1187 c->icache.ways = 1 + ((config1 >> 16) & 7);
1188
1189 icache_size = c->icache.sets *
1190 c->icache.ways *
1191 c->icache.linesz;
1192 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1193
1194 if (config & MIPS_CONF_VI)
1195 c->icache.flags |= MIPS_CACHE_VTAG;
1196
1197 /*
1198 * Now probe the MIPS32 / MIPS64 data cache.
1199 */
1200 c->dcache.flags = 0;
1201
1202 lsize = (config1 >> 10) & 7;
1203
1204 /* DL == 7 is reserved */
1205 if (lsize == 7)
1206 panic("Invalid dcache line size");
1207
1208 c->dcache.linesz = lsize ? 2 << lsize : 0;
1209
1210 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1211 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1212
1213 dcache_size = c->dcache.sets *
1214 c->dcache.ways *
1215 c->dcache.linesz;
1216 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1217
1218 c->options |= MIPS_CPU_PREFETCH;
1219 break;
1220 }
1221
1222 /*
1223 * Processor configuration sanity check for the R4000SC erratum
1224 * #5. With page sizes larger than 32kB there is no possibility
1225 * to get a VCE exception anymore so we don't care about this
1226 * misconfiguration. The case is rather theoretical anyway;
1227 * presumably no vendor is shipping his hardware in the "bad"
1228 * configuration.
1229 */
1230 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1231 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1232 !(config & CONF_SC) && c->icache.linesz != 16 &&
1233 PAGE_SIZE <= 0x8000)
1234 panic("Improper R4000SC processor configuration detected");
1235
1236 /* compute a couple of other cache variables */
1237 c->icache.waysize = icache_size / c->icache.ways;
1238 c->dcache.waysize = dcache_size / c->dcache.ways;
1239
1240 c->icache.sets = c->icache.linesz ?
1241 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1242 c->dcache.sets = c->dcache.linesz ?
1243 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1244
1245 /*
1246 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1247 * virtually indexed so normally would suffer from aliases. So
1248 * normally they'd suffer from aliases but magic in the hardware deals
1249 * with that for us so we don't need to take care ourselves.
1250 */
1251 switch (current_cpu_type()) {
1252 case CPU_20KC:
1253 case CPU_25KF:
1254 case CPU_I6400:
1255 case CPU_I6500:
1256 case CPU_SB1:
1257 case CPU_SB1A:
1258 c->dcache.flags |= MIPS_CACHE_PINDEX;
1259 break;
1260
1261 case CPU_R10000:
1262 case CPU_R12000:
1263 case CPU_R14000:
1264 case CPU_R16000:
1265 break;
1266
1267 case CPU_74K:
1268 case CPU_1074K:
1269 has_74k_erratum = alias_74k_erratum(c);
1270 fallthrough;
1271 case CPU_M14KC:
1272 case CPU_M14KEC:
1273 case CPU_24K:
1274 case CPU_34K:
1275 case CPU_1004K:
1276 case CPU_INTERAPTIV:
1277 case CPU_P5600:
1278 case CPU_PROAPTIV:
1279 case CPU_M5150:
1280 case CPU_QEMU_GENERIC:
1281 case CPU_P6600:
1282 case CPU_M6250:
1283 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1284 (c->icache.waysize > PAGE_SIZE))
1285 c->icache.flags |= MIPS_CACHE_ALIASES;
1286 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1287 /*
1288 * Effectively physically indexed dcache,
1289 * thus no virtual aliases.
1290 */
1291 c->dcache.flags |= MIPS_CACHE_PINDEX;
1292 break;
1293 }
1294 fallthrough;
1295 default:
1296 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1297 c->dcache.flags |= MIPS_CACHE_ALIASES;
1298 }
1299
1300 /* Physically indexed caches don't suffer from virtual aliasing */
1301 if (c->dcache.flags & MIPS_CACHE_PINDEX)
1302 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1303
1304 /*
1305 * In systems with CM the icache fills from L2 or closer caches, and
1306 * thus sees remote stores without needing to write them back any
1307 * further than that.
1308 */
1309 if (mips_cm_present())
1310 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE;
1311
1312 switch (current_cpu_type()) {
1313 case CPU_20KC:
1314 /*
1315 * Some older 20Kc chips doesn't have the 'VI' bit in
1316 * the config register.
1317 */
1318 c->icache.flags |= MIPS_CACHE_VTAG;
1319 break;
1320
1321 case CPU_ALCHEMY:
1322 case CPU_I6400:
1323 case CPU_I6500:
1324 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1325 break;
1326
1327 case CPU_BMIPS5000:
1328 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1329 /* Cache aliases are handled in hardware; allow HIGHMEM */
1330 c->dcache.flags &= ~MIPS_CACHE_ALIASES;
1331 break;
1332
1333 case CPU_LOONGSON2EF:
1334 /*
1335 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1336 * one op will act on all 4 ways
1337 */
1338 c->icache.ways = 1;
1339 }
1340
1341 pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1342 icache_size >> 10,
1343 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1344 way_string[c->icache.ways], c->icache.linesz);
1345
1346 pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1347 dcache_size >> 10, way_string[c->dcache.ways],
1348 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1349 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1350 "cache aliases" : "no aliases",
1351 c->dcache.linesz);
1352}
1353
1354static void probe_vcache(void)
1355{
1356 struct cpuinfo_mips *c = ¤t_cpu_data;
1357 unsigned int config2, lsize;
1358
1359 if (current_cpu_type() != CPU_LOONGSON64)
1360 return;
1361
1362 config2 = read_c0_config2();
1363 if ((lsize = ((config2 >> 20) & 15)))
1364 c->vcache.linesz = 2 << lsize;
1365 else
1366 c->vcache.linesz = lsize;
1367
1368 c->vcache.sets = 64 << ((config2 >> 24) & 15);
1369 c->vcache.ways = 1 + ((config2 >> 16) & 15);
1370
1371 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz;
1372
1373 c->vcache.waybit = 0;
1374 c->vcache.waysize = vcache_size / c->vcache.ways;
1375
1376 pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n",
1377 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz);
1378}
1379
1380/*
1381 * If you even _breathe_ on this function, look at the gcc output and make sure
1382 * it does not pop things on and off the stack for the cache sizing loop that
1383 * executes in KSEG1 space or else you will crash and burn badly. You have
1384 * been warned.
1385 */
1386static int probe_scache(void)
1387{
1388 unsigned long flags, addr, begin, end, pow2;
1389 unsigned int config = read_c0_config();
1390 struct cpuinfo_mips *c = ¤t_cpu_data;
1391
1392 if (config & CONF_SC)
1393 return 0;
1394
1395 begin = (unsigned long) &_stext;
1396 begin &= ~((4 * 1024 * 1024) - 1);
1397 end = begin + (4 * 1024 * 1024);
1398
1399 /*
1400 * This is such a bitch, you'd think they would make it easy to do
1401 * this. Away you daemons of stupidity!
1402 */
1403 local_irq_save(flags);
1404
1405 /* Fill each size-multiple cache line with a valid tag. */
1406 pow2 = (64 * 1024);
1407 for (addr = begin; addr < end; addr = (begin + pow2)) {
1408 unsigned long *p = (unsigned long *) addr;
1409 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1410 pow2 <<= 1;
1411 }
1412
1413 /* Load first line with zero (therefore invalid) tag. */
1414 write_c0_taglo(0);
1415 write_c0_taghi(0);
1416 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1417 cache_op(Index_Store_Tag_I, begin);
1418 cache_op(Index_Store_Tag_D, begin);
1419 cache_op(Index_Store_Tag_SD, begin);
1420
1421 /* Now search for the wrap around point. */
1422 pow2 = (128 * 1024);
1423 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1424 cache_op(Index_Load_Tag_SD, addr);
1425 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1426 if (!read_c0_taglo())
1427 break;
1428 pow2 <<= 1;
1429 }
1430 local_irq_restore(flags);
1431 addr -= begin;
1432
1433 scache_size = addr;
1434 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1435 c->scache.ways = 1;
1436 c->scache.waybit = 0; /* does not matter */
1437
1438 return 1;
1439}
1440
1441static void loongson2_sc_init(void)
1442{
1443 struct cpuinfo_mips *c = ¤t_cpu_data;
1444
1445 scache_size = 512*1024;
1446 c->scache.linesz = 32;
1447 c->scache.ways = 4;
1448 c->scache.waybit = 0;
1449 c->scache.waysize = scache_size / (c->scache.ways);
1450 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1451 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1452 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1453
1454 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1455}
1456
1457static void loongson3_sc_init(void)
1458{
1459 struct cpuinfo_mips *c = ¤t_cpu_data;
1460 unsigned int config2, lsize;
1461
1462 config2 = read_c0_config2();
1463 lsize = (config2 >> 4) & 15;
1464 if (lsize)
1465 c->scache.linesz = 2 << lsize;
1466 else
1467 c->scache.linesz = 0;
1468 c->scache.sets = 64 << ((config2 >> 8) & 15);
1469 c->scache.ways = 1 + (config2 & 15);
1470
1471 /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
1472 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
1473 c->scache.sets *= 2;
1474 else
1475 c->scache.sets *= 4;
1476
1477 scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
1478
1479 c->scache.waybit = 0;
1480 c->scache.waysize = scache_size / c->scache.ways;
1481 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1482 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1483 if (scache_size)
1484 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1485 return;
1486}
1487
1488static void setup_scache(void)
1489{
1490 struct cpuinfo_mips *c = ¤t_cpu_data;
1491 unsigned int config = read_c0_config();
1492 int sc_present = 0;
1493
1494 /*
1495 * Do the probing thing on R4000SC and R4400SC processors. Other
1496 * processors don't have a S-cache that would be relevant to the
1497 * Linux memory management.
1498 */
1499 switch (current_cpu_type()) {
1500 case CPU_R4000SC:
1501 case CPU_R4000MC:
1502 case CPU_R4400SC:
1503 case CPU_R4400MC:
1504 sc_present = run_uncached(probe_scache);
1505 if (sc_present)
1506 c->options |= MIPS_CPU_CACHE_CDEX_S;
1507 break;
1508
1509 case CPU_R10000:
1510 case CPU_R12000:
1511 case CPU_R14000:
1512 case CPU_R16000:
1513 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1514 c->scache.linesz = 64 << ((config >> 13) & 1);
1515 c->scache.ways = 2;
1516 c->scache.waybit= 0;
1517 sc_present = 1;
1518 break;
1519
1520 case CPU_R5000:
1521 case CPU_NEVADA:
1522#ifdef CONFIG_R5000_CPU_SCACHE
1523 r5k_sc_init();
1524#endif
1525 return;
1526
1527 case CPU_RM7000:
1528#ifdef CONFIG_RM7000_CPU_SCACHE
1529 rm7k_sc_init();
1530#endif
1531 return;
1532
1533 case CPU_LOONGSON2EF:
1534 loongson2_sc_init();
1535 return;
1536
1537 case CPU_LOONGSON64:
1538 loongson3_sc_init();
1539 return;
1540
1541 case CPU_CAVIUM_OCTEON3:
1542 /* don't need to worry about L2, fully coherent */
1543 return;
1544
1545 default:
1546 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1547 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1548 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
1549 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
1550#ifdef CONFIG_MIPS_CPU_SCACHE
1551 if (mips_sc_init ()) {
1552 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1553 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1554 scache_size >> 10,
1555 way_string[c->scache.ways], c->scache.linesz);
1556
1557 if (current_cpu_type() == CPU_BMIPS5000)
1558 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1559 }
1560
1561#else
1562 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1563 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1564#endif
1565 return;
1566 }
1567 sc_present = 0;
1568 }
1569
1570 if (!sc_present)
1571 return;
1572
1573 /* compute a couple of other cache variables */
1574 c->scache.waysize = scache_size / c->scache.ways;
1575
1576 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1577
1578 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1579 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1580
1581 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1582}
1583
1584void au1x00_fixup_config_od(void)
1585{
1586 /*
1587 * c0_config.od (bit 19) was write only (and read as 0)
1588 * on the early revisions of Alchemy SOCs. It disables the bus
1589 * transaction overlapping and needs to be set to fix various errata.
1590 */
1591 switch (read_c0_prid()) {
1592 case 0x00030100: /* Au1000 DA */
1593 case 0x00030201: /* Au1000 HA */
1594 case 0x00030202: /* Au1000 HB */
1595 case 0x01030200: /* Au1500 AB */
1596 /*
1597 * Au1100 errata actually keeps silence about this bit, so we set it
1598 * just in case for those revisions that require it to be set according
1599 * to the (now gone) cpu table.
1600 */
1601 case 0x02030200: /* Au1100 AB */
1602 case 0x02030201: /* Au1100 BA */
1603 case 0x02030202: /* Au1100 BC */
1604 set_c0_config(1 << 19);
1605 break;
1606 }
1607}
1608
1609/* CP0 hazard avoidance. */
1610#define NXP_BARRIER() \
1611 __asm__ __volatile__( \
1612 ".set noreorder\n\t" \
1613 "nop; nop; nop; nop; nop; nop;\n\t" \
1614 ".set reorder\n\t")
1615
1616static void nxp_pr4450_fixup_config(void)
1617{
1618 unsigned long config0;
1619
1620 config0 = read_c0_config();
1621
1622 /* clear all three cache coherency fields */
1623 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1624 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1625 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1626 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1627 write_c0_config(config0);
1628 NXP_BARRIER();
1629}
1630
1631static int cca = -1;
1632
1633static int __init cca_setup(char *str)
1634{
1635 get_option(&str, &cca);
1636
1637 return 0;
1638}
1639
1640early_param("cca", cca_setup);
1641
1642static void coherency_setup(void)
1643{
1644 if (cca < 0 || cca > 7)
1645 cca = read_c0_config() & CONF_CM_CMASK;
1646 _page_cachable_default = cca << _CACHE_SHIFT;
1647
1648 pr_debug("Using cache attribute %d\n", cca);
1649 change_c0_config(CONF_CM_CMASK, cca);
1650
1651 /*
1652 * c0_status.cu=0 specifies that updates by the sc instruction use
1653 * the coherency mode specified by the TLB; 1 means cacheable
1654 * coherent update on write will be used. Not all processors have
1655 * this bit and; some wire it to zero, others like Toshiba had the
1656 * silly idea of putting something else there ...
1657 */
1658 switch (current_cpu_type()) {
1659 case CPU_R4000PC:
1660 case CPU_R4000SC:
1661 case CPU_R4000MC:
1662 case CPU_R4400PC:
1663 case CPU_R4400SC:
1664 case CPU_R4400MC:
1665 clear_c0_config(CONF_CU);
1666 break;
1667 /*
1668 * We need to catch the early Alchemy SOCs with
1669 * the write-only co_config.od bit and set it back to one on:
1670 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1671 */
1672 case CPU_ALCHEMY:
1673 au1x00_fixup_config_od();
1674 break;
1675
1676 case PRID_IMP_PR4450:
1677 nxp_pr4450_fixup_config();
1678 break;
1679 }
1680}
1681
1682static void r4k_cache_error_setup(void)
1683{
1684 extern char __weak except_vec2_generic;
1685 extern char __weak except_vec2_sb1;
1686
1687 switch (current_cpu_type()) {
1688 case CPU_SB1:
1689 case CPU_SB1A:
1690 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1691 break;
1692
1693 default:
1694 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1695 break;
1696 }
1697}
1698
1699void r4k_cache_init(void)
1700{
1701 extern void build_clear_page(void);
1702 extern void build_copy_page(void);
1703 struct cpuinfo_mips *c = ¤t_cpu_data;
1704
1705 probe_pcache();
1706 probe_vcache();
1707 setup_scache();
1708
1709 r4k_blast_dcache_page_setup();
1710 r4k_blast_dcache_setup();
1711 r4k_blast_icache_page_setup();
1712 r4k_blast_icache_setup();
1713 r4k_blast_scache_page_setup();
1714 r4k_blast_scache_setup();
1715 r4k_blast_scache_node_setup();
1716#ifdef CONFIG_EVA
1717 r4k_blast_dcache_user_page_setup();
1718 r4k_blast_icache_user_page_setup();
1719#endif
1720
1721 /*
1722 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1723 * This code supports virtually indexed processors and will be
1724 * unnecessarily inefficient on physically indexed processors.
1725 */
1726 if (c->dcache.linesz && cpu_has_dc_aliases)
1727 shm_align_mask = max_t( unsigned long,
1728 c->dcache.sets * c->dcache.linesz - 1,
1729 PAGE_SIZE - 1);
1730 else
1731 shm_align_mask = PAGE_SIZE-1;
1732
1733 __flush_cache_vmap = r4k__flush_cache_vmap;
1734 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1735
1736 flush_cache_all = cache_noop;
1737 __flush_cache_all = r4k___flush_cache_all;
1738 flush_cache_mm = r4k_flush_cache_mm;
1739 flush_cache_page = r4k_flush_cache_page;
1740 flush_cache_range = r4k_flush_cache_range;
1741
1742 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1743
1744 flush_icache_all = r4k_flush_icache_all;
1745 flush_data_cache_page = r4k_flush_data_cache_page;
1746 flush_icache_range = r4k_flush_icache_range;
1747 local_flush_icache_range = local_r4k_flush_icache_range;
1748 __flush_icache_user_range = r4k_flush_icache_user_range;
1749 __local_flush_icache_user_range = local_r4k_flush_icache_user_range;
1750
1751#ifdef CONFIG_DMA_NONCOHERENT
1752 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1753 _dma_cache_wback = r4k_dma_cache_wback_inv;
1754 _dma_cache_inv = r4k_dma_cache_inv;
1755#endif /* CONFIG_DMA_NONCOHERENT */
1756
1757 build_clear_page();
1758 build_copy_page();
1759
1760 /*
1761 * We want to run CMP kernels on core with and without coherent
1762 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1763 * or not to flush caches.
1764 */
1765 local_r4k___flush_cache_all(NULL);
1766
1767 coherency_setup();
1768 board_cache_error_setup = r4k_cache_error_setup;
1769
1770 /*
1771 * Per-CPU overrides
1772 */
1773 switch (current_cpu_type()) {
1774 case CPU_BMIPS4350:
1775 case CPU_BMIPS4380:
1776 /* No IPI is needed because all CPUs share the same D$ */
1777 flush_data_cache_page = r4k_blast_dcache_page;
1778 break;
1779 case CPU_BMIPS5000:
1780 /* We lose our superpowers if L2 is disabled */
1781 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1782 break;
1783
1784 /* I$ fills from D$ just by emptying the write buffers */
1785 flush_cache_page = (void *)b5k_instruction_hazard;
1786 flush_cache_range = (void *)b5k_instruction_hazard;
1787 flush_data_cache_page = (void *)b5k_instruction_hazard;
1788 flush_icache_range = (void *)b5k_instruction_hazard;
1789 local_flush_icache_range = (void *)b5k_instruction_hazard;
1790
1791
1792 /* Optimization: an L2 flush implicitly flushes the L1 */
1793 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1794 break;
1795 case CPU_LOONGSON64:
1796 /* Loongson-3 maintains cache coherency by hardware */
1797 __flush_cache_all = cache_noop;
1798 __flush_cache_vmap = cache_noop;
1799 __flush_cache_vunmap = cache_noop;
1800 __flush_kernel_vmap_range = (void *)cache_noop;
1801 flush_cache_mm = (void *)cache_noop;
1802 flush_cache_page = (void *)cache_noop;
1803 flush_cache_range = (void *)cache_noop;
1804 flush_icache_all = (void *)cache_noop;
1805 flush_data_cache_page = (void *)cache_noop;
1806 break;
1807 }
1808}
1809
1810static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1811 void *v)
1812{
1813 switch (cmd) {
1814 case CPU_PM_ENTER_FAILED:
1815 case CPU_PM_EXIT:
1816 coherency_setup();
1817 break;
1818 }
1819
1820 return NOTIFY_OK;
1821}
1822
1823static struct notifier_block r4k_cache_pm_notifier_block = {
1824 .notifier_call = r4k_cache_pm_notifier,
1825};
1826
1827static int __init r4k_cache_init_pm(void)
1828{
1829 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1830}
1831arch_initcall(r4k_cache_init_pm);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */
10#include <linux/cpu_pm.h>
11#include <linux/hardirq.h>
12#include <linux/init.h>
13#include <linux/highmem.h>
14#include <linux/kernel.h>
15#include <linux/linkage.h>
16#include <linux/preempt.h>
17#include <linux/sched.h>
18#include <linux/smp.h>
19#include <linux/mm.h>
20#include <linux/module.h>
21#include <linux/bitops.h>
22
23#include <asm/bcache.h>
24#include <asm/bootinfo.h>
25#include <asm/cache.h>
26#include <asm/cacheops.h>
27#include <asm/cpu.h>
28#include <asm/cpu-features.h>
29#include <asm/cpu-type.h>
30#include <asm/io.h>
31#include <asm/page.h>
32#include <asm/pgtable.h>
33#include <asm/r4kcache.h>
34#include <asm/sections.h>
35#include <asm/mmu_context.h>
36#include <asm/war.h>
37#include <asm/cacheflush.h> /* for run_uncached() */
38#include <asm/traps.h>
39#include <asm/dma-coherence.h>
40#include <asm/mips-cm.h>
41
42/*
43 * Special Variant of smp_call_function for use by cache functions:
44 *
45 * o No return value
46 * o collapses to normal function call on UP kernels
47 * o collapses to normal function call on systems with a single shared
48 * primary cache.
49 * o doesn't disable interrupts on the local CPU
50 */
51static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
52{
53 preempt_disable();
54
55 /*
56 * The Coherent Manager propagates address-based cache ops to other
57 * cores but not index-based ops. However, r4k_on_each_cpu is used
58 * in both cases so there is no easy way to tell what kind of op is
59 * executed to the other cores. The best we can probably do is
60 * to restrict that call when a CM is not present because both
61 * CM-based SMP protocols (CMP & CPS) restrict index-based cache ops.
62 */
63 if (!mips_cm_present())
64 smp_call_function_many(&cpu_foreign_map, func, info, 1);
65 func(info);
66 preempt_enable();
67}
68
69#if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
70#define cpu_has_safe_index_cacheops 0
71#else
72#define cpu_has_safe_index_cacheops 1
73#endif
74
75/*
76 * Must die.
77 */
78static unsigned long icache_size __read_mostly;
79static unsigned long dcache_size __read_mostly;
80static unsigned long scache_size __read_mostly;
81
82/*
83 * Dummy cache handling routines for machines without boardcaches
84 */
85static void cache_noop(void) {}
86
87static struct bcache_ops no_sc_ops = {
88 .bc_enable = (void *)cache_noop,
89 .bc_disable = (void *)cache_noop,
90 .bc_wback_inv = (void *)cache_noop,
91 .bc_inv = (void *)cache_noop
92};
93
94struct bcache_ops *bcops = &no_sc_ops;
95
96#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
97#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
98
99#define R4600_HIT_CACHEOP_WAR_IMPL \
100do { \
101 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
102 *(volatile unsigned long *)CKSEG1; \
103 if (R4600_V1_HIT_CACHEOP_WAR) \
104 __asm__ __volatile__("nop;nop;nop;nop"); \
105} while (0)
106
107static void (*r4k_blast_dcache_page)(unsigned long addr);
108
109static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
110{
111 R4600_HIT_CACHEOP_WAR_IMPL;
112 blast_dcache32_page(addr);
113}
114
115static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
116{
117 blast_dcache64_page(addr);
118}
119
120static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
121{
122 blast_dcache128_page(addr);
123}
124
125static void r4k_blast_dcache_page_setup(void)
126{
127 unsigned long dc_lsize = cpu_dcache_line_size();
128
129 switch (dc_lsize) {
130 case 0:
131 r4k_blast_dcache_page = (void *)cache_noop;
132 break;
133 case 16:
134 r4k_blast_dcache_page = blast_dcache16_page;
135 break;
136 case 32:
137 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
138 break;
139 case 64:
140 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
141 break;
142 case 128:
143 r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
144 break;
145 default:
146 break;
147 }
148}
149
150#ifndef CONFIG_EVA
151#define r4k_blast_dcache_user_page r4k_blast_dcache_page
152#else
153
154static void (*r4k_blast_dcache_user_page)(unsigned long addr);
155
156static void r4k_blast_dcache_user_page_setup(void)
157{
158 unsigned long dc_lsize = cpu_dcache_line_size();
159
160 if (dc_lsize == 0)
161 r4k_blast_dcache_user_page = (void *)cache_noop;
162 else if (dc_lsize == 16)
163 r4k_blast_dcache_user_page = blast_dcache16_user_page;
164 else if (dc_lsize == 32)
165 r4k_blast_dcache_user_page = blast_dcache32_user_page;
166 else if (dc_lsize == 64)
167 r4k_blast_dcache_user_page = blast_dcache64_user_page;
168}
169
170#endif
171
172static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
173
174static void r4k_blast_dcache_page_indexed_setup(void)
175{
176 unsigned long dc_lsize = cpu_dcache_line_size();
177
178 if (dc_lsize == 0)
179 r4k_blast_dcache_page_indexed = (void *)cache_noop;
180 else if (dc_lsize == 16)
181 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
182 else if (dc_lsize == 32)
183 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
184 else if (dc_lsize == 64)
185 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
186 else if (dc_lsize == 128)
187 r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
188}
189
190void (* r4k_blast_dcache)(void);
191EXPORT_SYMBOL(r4k_blast_dcache);
192
193static void r4k_blast_dcache_setup(void)
194{
195 unsigned long dc_lsize = cpu_dcache_line_size();
196
197 if (dc_lsize == 0)
198 r4k_blast_dcache = (void *)cache_noop;
199 else if (dc_lsize == 16)
200 r4k_blast_dcache = blast_dcache16;
201 else if (dc_lsize == 32)
202 r4k_blast_dcache = blast_dcache32;
203 else if (dc_lsize == 64)
204 r4k_blast_dcache = blast_dcache64;
205 else if (dc_lsize == 128)
206 r4k_blast_dcache = blast_dcache128;
207}
208
209/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
210#define JUMP_TO_ALIGN(order) \
211 __asm__ __volatile__( \
212 "b\t1f\n\t" \
213 ".align\t" #order "\n\t" \
214 "1:\n\t" \
215 )
216#define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
217#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
218
219static inline void blast_r4600_v1_icache32(void)
220{
221 unsigned long flags;
222
223 local_irq_save(flags);
224 blast_icache32();
225 local_irq_restore(flags);
226}
227
228static inline void tx49_blast_icache32(void)
229{
230 unsigned long start = INDEX_BASE;
231 unsigned long end = start + current_cpu_data.icache.waysize;
232 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
233 unsigned long ws_end = current_cpu_data.icache.ways <<
234 current_cpu_data.icache.waybit;
235 unsigned long ws, addr;
236
237 CACHE32_UNROLL32_ALIGN2;
238 /* I'm in even chunk. blast odd chunks */
239 for (ws = 0; ws < ws_end; ws += ws_inc)
240 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
241 cache32_unroll32(addr|ws, Index_Invalidate_I);
242 CACHE32_UNROLL32_ALIGN;
243 /* I'm in odd chunk. blast even chunks */
244 for (ws = 0; ws < ws_end; ws += ws_inc)
245 for (addr = start; addr < end; addr += 0x400 * 2)
246 cache32_unroll32(addr|ws, Index_Invalidate_I);
247}
248
249static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
250{
251 unsigned long flags;
252
253 local_irq_save(flags);
254 blast_icache32_page_indexed(page);
255 local_irq_restore(flags);
256}
257
258static inline void tx49_blast_icache32_page_indexed(unsigned long page)
259{
260 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
261 unsigned long start = INDEX_BASE + (page & indexmask);
262 unsigned long end = start + PAGE_SIZE;
263 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
264 unsigned long ws_end = current_cpu_data.icache.ways <<
265 current_cpu_data.icache.waybit;
266 unsigned long ws, addr;
267
268 CACHE32_UNROLL32_ALIGN2;
269 /* I'm in even chunk. blast odd chunks */
270 for (ws = 0; ws < ws_end; ws += ws_inc)
271 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
272 cache32_unroll32(addr|ws, Index_Invalidate_I);
273 CACHE32_UNROLL32_ALIGN;
274 /* I'm in odd chunk. blast even chunks */
275 for (ws = 0; ws < ws_end; ws += ws_inc)
276 for (addr = start; addr < end; addr += 0x400 * 2)
277 cache32_unroll32(addr|ws, Index_Invalidate_I);
278}
279
280static void (* r4k_blast_icache_page)(unsigned long addr);
281
282static void r4k_blast_icache_page_setup(void)
283{
284 unsigned long ic_lsize = cpu_icache_line_size();
285
286 if (ic_lsize == 0)
287 r4k_blast_icache_page = (void *)cache_noop;
288 else if (ic_lsize == 16)
289 r4k_blast_icache_page = blast_icache16_page;
290 else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
291 r4k_blast_icache_page = loongson2_blast_icache32_page;
292 else if (ic_lsize == 32)
293 r4k_blast_icache_page = blast_icache32_page;
294 else if (ic_lsize == 64)
295 r4k_blast_icache_page = blast_icache64_page;
296 else if (ic_lsize == 128)
297 r4k_blast_icache_page = blast_icache128_page;
298}
299
300#ifndef CONFIG_EVA
301#define r4k_blast_icache_user_page r4k_blast_icache_page
302#else
303
304static void (*r4k_blast_icache_user_page)(unsigned long addr);
305
306static void r4k_blast_icache_user_page_setup(void)
307{
308 unsigned long ic_lsize = cpu_icache_line_size();
309
310 if (ic_lsize == 0)
311 r4k_blast_icache_user_page = (void *)cache_noop;
312 else if (ic_lsize == 16)
313 r4k_blast_icache_user_page = blast_icache16_user_page;
314 else if (ic_lsize == 32)
315 r4k_blast_icache_user_page = blast_icache32_user_page;
316 else if (ic_lsize == 64)
317 r4k_blast_icache_user_page = blast_icache64_user_page;
318}
319
320#endif
321
322static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
323
324static void r4k_blast_icache_page_indexed_setup(void)
325{
326 unsigned long ic_lsize = cpu_icache_line_size();
327
328 if (ic_lsize == 0)
329 r4k_blast_icache_page_indexed = (void *)cache_noop;
330 else if (ic_lsize == 16)
331 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
332 else if (ic_lsize == 32) {
333 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
334 r4k_blast_icache_page_indexed =
335 blast_icache32_r4600_v1_page_indexed;
336 else if (TX49XX_ICACHE_INDEX_INV_WAR)
337 r4k_blast_icache_page_indexed =
338 tx49_blast_icache32_page_indexed;
339 else if (current_cpu_type() == CPU_LOONGSON2)
340 r4k_blast_icache_page_indexed =
341 loongson2_blast_icache32_page_indexed;
342 else
343 r4k_blast_icache_page_indexed =
344 blast_icache32_page_indexed;
345 } else if (ic_lsize == 64)
346 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
347}
348
349void (* r4k_blast_icache)(void);
350EXPORT_SYMBOL(r4k_blast_icache);
351
352static void r4k_blast_icache_setup(void)
353{
354 unsigned long ic_lsize = cpu_icache_line_size();
355
356 if (ic_lsize == 0)
357 r4k_blast_icache = (void *)cache_noop;
358 else if (ic_lsize == 16)
359 r4k_blast_icache = blast_icache16;
360 else if (ic_lsize == 32) {
361 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
362 r4k_blast_icache = blast_r4600_v1_icache32;
363 else if (TX49XX_ICACHE_INDEX_INV_WAR)
364 r4k_blast_icache = tx49_blast_icache32;
365 else if (current_cpu_type() == CPU_LOONGSON2)
366 r4k_blast_icache = loongson2_blast_icache32;
367 else
368 r4k_blast_icache = blast_icache32;
369 } else if (ic_lsize == 64)
370 r4k_blast_icache = blast_icache64;
371 else if (ic_lsize == 128)
372 r4k_blast_icache = blast_icache128;
373}
374
375static void (* r4k_blast_scache_page)(unsigned long addr);
376
377static void r4k_blast_scache_page_setup(void)
378{
379 unsigned long sc_lsize = cpu_scache_line_size();
380
381 if (scache_size == 0)
382 r4k_blast_scache_page = (void *)cache_noop;
383 else if (sc_lsize == 16)
384 r4k_blast_scache_page = blast_scache16_page;
385 else if (sc_lsize == 32)
386 r4k_blast_scache_page = blast_scache32_page;
387 else if (sc_lsize == 64)
388 r4k_blast_scache_page = blast_scache64_page;
389 else if (sc_lsize == 128)
390 r4k_blast_scache_page = blast_scache128_page;
391}
392
393static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
394
395static void r4k_blast_scache_page_indexed_setup(void)
396{
397 unsigned long sc_lsize = cpu_scache_line_size();
398
399 if (scache_size == 0)
400 r4k_blast_scache_page_indexed = (void *)cache_noop;
401 else if (sc_lsize == 16)
402 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
403 else if (sc_lsize == 32)
404 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
405 else if (sc_lsize == 64)
406 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
407 else if (sc_lsize == 128)
408 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
409}
410
411static void (* r4k_blast_scache)(void);
412
413static void r4k_blast_scache_setup(void)
414{
415 unsigned long sc_lsize = cpu_scache_line_size();
416
417 if (scache_size == 0)
418 r4k_blast_scache = (void *)cache_noop;
419 else if (sc_lsize == 16)
420 r4k_blast_scache = blast_scache16;
421 else if (sc_lsize == 32)
422 r4k_blast_scache = blast_scache32;
423 else if (sc_lsize == 64)
424 r4k_blast_scache = blast_scache64;
425 else if (sc_lsize == 128)
426 r4k_blast_scache = blast_scache128;
427}
428
429static inline void local_r4k___flush_cache_all(void * args)
430{
431 switch (current_cpu_type()) {
432 case CPU_LOONGSON2:
433 case CPU_LOONGSON3:
434 case CPU_R4000SC:
435 case CPU_R4000MC:
436 case CPU_R4400SC:
437 case CPU_R4400MC:
438 case CPU_R10000:
439 case CPU_R12000:
440 case CPU_R14000:
441 case CPU_R16000:
442 /*
443 * These caches are inclusive caches, that is, if something
444 * is not cached in the S-cache, we know it also won't be
445 * in one of the primary caches.
446 */
447 r4k_blast_scache();
448 break;
449
450 default:
451 r4k_blast_dcache();
452 r4k_blast_icache();
453 break;
454 }
455}
456
457static void r4k___flush_cache_all(void)
458{
459 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
460}
461
462static inline int has_valid_asid(const struct mm_struct *mm)
463{
464#ifdef CONFIG_MIPS_MT_SMP
465 int i;
466
467 for_each_online_cpu(i)
468 if (cpu_context(i, mm))
469 return 1;
470
471 return 0;
472#else
473 return cpu_context(smp_processor_id(), mm);
474#endif
475}
476
477static void r4k__flush_cache_vmap(void)
478{
479 r4k_blast_dcache();
480}
481
482static void r4k__flush_cache_vunmap(void)
483{
484 r4k_blast_dcache();
485}
486
487static inline void local_r4k_flush_cache_range(void * args)
488{
489 struct vm_area_struct *vma = args;
490 int exec = vma->vm_flags & VM_EXEC;
491
492 if (!(has_valid_asid(vma->vm_mm)))
493 return;
494
495 r4k_blast_dcache();
496 if (exec)
497 r4k_blast_icache();
498}
499
500static void r4k_flush_cache_range(struct vm_area_struct *vma,
501 unsigned long start, unsigned long end)
502{
503 int exec = vma->vm_flags & VM_EXEC;
504
505 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
506 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
507}
508
509static inline void local_r4k_flush_cache_mm(void * args)
510{
511 struct mm_struct *mm = args;
512
513 if (!has_valid_asid(mm))
514 return;
515
516 /*
517 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
518 * only flush the primary caches but R1x000 behave sane ...
519 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
520 * caches, so we can bail out early.
521 */
522 if (current_cpu_type() == CPU_R4000SC ||
523 current_cpu_type() == CPU_R4000MC ||
524 current_cpu_type() == CPU_R4400SC ||
525 current_cpu_type() == CPU_R4400MC) {
526 r4k_blast_scache();
527 return;
528 }
529
530 r4k_blast_dcache();
531}
532
533static void r4k_flush_cache_mm(struct mm_struct *mm)
534{
535 if (!cpu_has_dc_aliases)
536 return;
537
538 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
539}
540
541struct flush_cache_page_args {
542 struct vm_area_struct *vma;
543 unsigned long addr;
544 unsigned long pfn;
545};
546
547static inline void local_r4k_flush_cache_page(void *args)
548{
549 struct flush_cache_page_args *fcp_args = args;
550 struct vm_area_struct *vma = fcp_args->vma;
551 unsigned long addr = fcp_args->addr;
552 struct page *page = pfn_to_page(fcp_args->pfn);
553 int exec = vma->vm_flags & VM_EXEC;
554 struct mm_struct *mm = vma->vm_mm;
555 int map_coherent = 0;
556 pgd_t *pgdp;
557 pud_t *pudp;
558 pmd_t *pmdp;
559 pte_t *ptep;
560 void *vaddr;
561
562 /*
563 * If ownes no valid ASID yet, cannot possibly have gotten
564 * this page into the cache.
565 */
566 if (!has_valid_asid(mm))
567 return;
568
569 addr &= PAGE_MASK;
570 pgdp = pgd_offset(mm, addr);
571 pudp = pud_offset(pgdp, addr);
572 pmdp = pmd_offset(pudp, addr);
573 ptep = pte_offset(pmdp, addr);
574
575 /*
576 * If the page isn't marked valid, the page cannot possibly be
577 * in the cache.
578 */
579 if (!(pte_present(*ptep)))
580 return;
581
582 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
583 vaddr = NULL;
584 else {
585 /*
586 * Use kmap_coherent or kmap_atomic to do flushes for
587 * another ASID than the current one.
588 */
589 map_coherent = (cpu_has_dc_aliases &&
590 page_mapcount(page) &&
591 !Page_dcache_dirty(page));
592 if (map_coherent)
593 vaddr = kmap_coherent(page, addr);
594 else
595 vaddr = kmap_atomic(page);
596 addr = (unsigned long)vaddr;
597 }
598
599 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
600 vaddr ? r4k_blast_dcache_page(addr) :
601 r4k_blast_dcache_user_page(addr);
602 if (exec && !cpu_icache_snoops_remote_store)
603 r4k_blast_scache_page(addr);
604 }
605 if (exec) {
606 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
607 int cpu = smp_processor_id();
608
609 if (cpu_context(cpu, mm) != 0)
610 drop_mmu_context(mm, cpu);
611 } else
612 vaddr ? r4k_blast_icache_page(addr) :
613 r4k_blast_icache_user_page(addr);
614 }
615
616 if (vaddr) {
617 if (map_coherent)
618 kunmap_coherent();
619 else
620 kunmap_atomic(vaddr);
621 }
622}
623
624static void r4k_flush_cache_page(struct vm_area_struct *vma,
625 unsigned long addr, unsigned long pfn)
626{
627 struct flush_cache_page_args args;
628
629 args.vma = vma;
630 args.addr = addr;
631 args.pfn = pfn;
632
633 r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
634}
635
636static inline void local_r4k_flush_data_cache_page(void * addr)
637{
638 r4k_blast_dcache_page((unsigned long) addr);
639}
640
641static void r4k_flush_data_cache_page(unsigned long addr)
642{
643 if (in_atomic())
644 local_r4k_flush_data_cache_page((void *)addr);
645 else
646 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
647}
648
649struct flush_icache_range_args {
650 unsigned long start;
651 unsigned long end;
652};
653
654static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
655{
656 if (!cpu_has_ic_fills_f_dc) {
657 if (end - start >= dcache_size) {
658 r4k_blast_dcache();
659 } else {
660 R4600_HIT_CACHEOP_WAR_IMPL;
661 protected_blast_dcache_range(start, end);
662 }
663 }
664
665 if (end - start > icache_size)
666 r4k_blast_icache();
667 else {
668 switch (boot_cpu_type()) {
669 case CPU_LOONGSON2:
670 protected_loongson2_blast_icache_range(start, end);
671 break;
672
673 default:
674 protected_blast_icache_range(start, end);
675 break;
676 }
677 }
678#ifdef CONFIG_EVA
679 /*
680 * Due to all possible segment mappings, there might cache aliases
681 * caused by the bootloader being in non-EVA mode, and the CPU switching
682 * to EVA during early kernel init. It's best to flush the scache
683 * to avoid having secondary cores fetching stale data and lead to
684 * kernel crashes.
685 */
686 bc_wback_inv(start, (end - start));
687 __sync();
688#endif
689}
690
691static inline void local_r4k_flush_icache_range_ipi(void *args)
692{
693 struct flush_icache_range_args *fir_args = args;
694 unsigned long start = fir_args->start;
695 unsigned long end = fir_args->end;
696
697 local_r4k_flush_icache_range(start, end);
698}
699
700static void r4k_flush_icache_range(unsigned long start, unsigned long end)
701{
702 struct flush_icache_range_args args;
703
704 args.start = start;
705 args.end = end;
706
707 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
708 instruction_hazard();
709}
710
711#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
712
713static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
714{
715 /* Catch bad driver code */
716 BUG_ON(size == 0);
717
718 preempt_disable();
719 if (cpu_has_inclusive_pcaches) {
720 if (size >= scache_size)
721 r4k_blast_scache();
722 else
723 blast_scache_range(addr, addr + size);
724 preempt_enable();
725 __sync();
726 return;
727 }
728
729 /*
730 * Either no secondary cache or the available caches don't have the
731 * subset property so we have to flush the primary caches
732 * explicitly
733 */
734 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
735 r4k_blast_dcache();
736 } else {
737 R4600_HIT_CACHEOP_WAR_IMPL;
738 blast_dcache_range(addr, addr + size);
739 }
740 preempt_enable();
741
742 bc_wback_inv(addr, size);
743 __sync();
744}
745
746static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
747{
748 /* Catch bad driver code */
749 BUG_ON(size == 0);
750
751 preempt_disable();
752 if (cpu_has_inclusive_pcaches) {
753 if (size >= scache_size)
754 r4k_blast_scache();
755 else {
756 /*
757 * There is no clearly documented alignment requirement
758 * for the cache instruction on MIPS processors and
759 * some processors, among them the RM5200 and RM7000
760 * QED processors will throw an address error for cache
761 * hit ops with insufficient alignment. Solved by
762 * aligning the address to cache line size.
763 */
764 blast_inv_scache_range(addr, addr + size);
765 }
766 preempt_enable();
767 __sync();
768 return;
769 }
770
771 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
772 r4k_blast_dcache();
773 } else {
774 R4600_HIT_CACHEOP_WAR_IMPL;
775 blast_inv_dcache_range(addr, addr + size);
776 }
777 preempt_enable();
778
779 bc_inv(addr, size);
780 __sync();
781}
782#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
783
784/*
785 * While we're protected against bad userland addresses we don't care
786 * very much about what happens in that case. Usually a segmentation
787 * fault will dump the process later on anyway ...
788 */
789static void local_r4k_flush_cache_sigtramp(void * arg)
790{
791 unsigned long ic_lsize = cpu_icache_line_size();
792 unsigned long dc_lsize = cpu_dcache_line_size();
793 unsigned long sc_lsize = cpu_scache_line_size();
794 unsigned long addr = (unsigned long) arg;
795
796 R4600_HIT_CACHEOP_WAR_IMPL;
797 if (dc_lsize)
798 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
799 if (!cpu_icache_snoops_remote_store && scache_size)
800 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
801 if (ic_lsize)
802 protected_flush_icache_line(addr & ~(ic_lsize - 1));
803 if (MIPS4K_ICACHE_REFILL_WAR) {
804 __asm__ __volatile__ (
805 ".set push\n\t"
806 ".set noat\n\t"
807 ".set "MIPS_ISA_LEVEL"\n\t"
808#ifdef CONFIG_32BIT
809 "la $at,1f\n\t"
810#endif
811#ifdef CONFIG_64BIT
812 "dla $at,1f\n\t"
813#endif
814 "cache %0,($at)\n\t"
815 "nop; nop; nop\n"
816 "1:\n\t"
817 ".set pop"
818 :
819 : "i" (Hit_Invalidate_I));
820 }
821 if (MIPS_CACHE_SYNC_WAR)
822 __asm__ __volatile__ ("sync");
823}
824
825static void r4k_flush_cache_sigtramp(unsigned long addr)
826{
827 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
828}
829
830static void r4k_flush_icache_all(void)
831{
832 if (cpu_has_vtag_icache)
833 r4k_blast_icache();
834}
835
836struct flush_kernel_vmap_range_args {
837 unsigned long vaddr;
838 int size;
839};
840
841static inline void local_r4k_flush_kernel_vmap_range(void *args)
842{
843 struct flush_kernel_vmap_range_args *vmra = args;
844 unsigned long vaddr = vmra->vaddr;
845 int size = vmra->size;
846
847 /*
848 * Aliases only affect the primary caches so don't bother with
849 * S-caches or T-caches.
850 */
851 if (cpu_has_safe_index_cacheops && size >= dcache_size)
852 r4k_blast_dcache();
853 else {
854 R4600_HIT_CACHEOP_WAR_IMPL;
855 blast_dcache_range(vaddr, vaddr + size);
856 }
857}
858
859static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
860{
861 struct flush_kernel_vmap_range_args args;
862
863 args.vaddr = (unsigned long) vaddr;
864 args.size = size;
865
866 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
867}
868
869static inline void rm7k_erratum31(void)
870{
871 const unsigned long ic_lsize = 32;
872 unsigned long addr;
873
874 /* RM7000 erratum #31. The icache is screwed at startup. */
875 write_c0_taglo(0);
876 write_c0_taghi(0);
877
878 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
879 __asm__ __volatile__ (
880 ".set push\n\t"
881 ".set noreorder\n\t"
882 ".set mips3\n\t"
883 "cache\t%1, 0(%0)\n\t"
884 "cache\t%1, 0x1000(%0)\n\t"
885 "cache\t%1, 0x2000(%0)\n\t"
886 "cache\t%1, 0x3000(%0)\n\t"
887 "cache\t%2, 0(%0)\n\t"
888 "cache\t%2, 0x1000(%0)\n\t"
889 "cache\t%2, 0x2000(%0)\n\t"
890 "cache\t%2, 0x3000(%0)\n\t"
891 "cache\t%1, 0(%0)\n\t"
892 "cache\t%1, 0x1000(%0)\n\t"
893 "cache\t%1, 0x2000(%0)\n\t"
894 "cache\t%1, 0x3000(%0)\n\t"
895 ".set pop\n"
896 :
897 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
898 }
899}
900
901static inline int alias_74k_erratum(struct cpuinfo_mips *c)
902{
903 unsigned int imp = c->processor_id & PRID_IMP_MASK;
904 unsigned int rev = c->processor_id & PRID_REV_MASK;
905 int present = 0;
906
907 /*
908 * Early versions of the 74K do not update the cache tags on a
909 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
910 * aliases. In this case it is better to treat the cache as always
911 * having aliases. Also disable the synonym tag update feature
912 * where available. In this case no opportunistic tag update will
913 * happen where a load causes a virtual address miss but a physical
914 * address hit during a D-cache look-up.
915 */
916 switch (imp) {
917 case PRID_IMP_74K:
918 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
919 present = 1;
920 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
921 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
922 break;
923 case PRID_IMP_1074K:
924 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
925 present = 1;
926 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
927 }
928 break;
929 default:
930 BUG();
931 }
932
933 return present;
934}
935
936static void b5k_instruction_hazard(void)
937{
938 __sync();
939 __sync();
940 __asm__ __volatile__(
941 " nop; nop; nop; nop; nop; nop; nop; nop\n"
942 " nop; nop; nop; nop; nop; nop; nop; nop\n"
943 " nop; nop; nop; nop; nop; nop; nop; nop\n"
944 " nop; nop; nop; nop; nop; nop; nop; nop\n"
945 : : : "memory");
946}
947
948static char *way_string[] = { NULL, "direct mapped", "2-way",
949 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
950 "9-way", "10-way", "11-way", "12-way",
951 "13-way", "14-way", "15-way", "16-way",
952};
953
954static void probe_pcache(void)
955{
956 struct cpuinfo_mips *c = ¤t_cpu_data;
957 unsigned int config = read_c0_config();
958 unsigned int prid = read_c0_prid();
959 int has_74k_erratum = 0;
960 unsigned long config1;
961 unsigned int lsize;
962
963 switch (current_cpu_type()) {
964 case CPU_R4600: /* QED style two way caches? */
965 case CPU_R4700:
966 case CPU_R5000:
967 case CPU_NEVADA:
968 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
969 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
970 c->icache.ways = 2;
971 c->icache.waybit = __ffs(icache_size/2);
972
973 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
974 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
975 c->dcache.ways = 2;
976 c->dcache.waybit= __ffs(dcache_size/2);
977
978 c->options |= MIPS_CPU_CACHE_CDEX_P;
979 break;
980
981 case CPU_R5432:
982 case CPU_R5500:
983 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
984 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
985 c->icache.ways = 2;
986 c->icache.waybit= 0;
987
988 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
989 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
990 c->dcache.ways = 2;
991 c->dcache.waybit = 0;
992
993 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
994 break;
995
996 case CPU_TX49XX:
997 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
998 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
999 c->icache.ways = 4;
1000 c->icache.waybit= 0;
1001
1002 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1003 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1004 c->dcache.ways = 4;
1005 c->dcache.waybit = 0;
1006
1007 c->options |= MIPS_CPU_CACHE_CDEX_P;
1008 c->options |= MIPS_CPU_PREFETCH;
1009 break;
1010
1011 case CPU_R4000PC:
1012 case CPU_R4000SC:
1013 case CPU_R4000MC:
1014 case CPU_R4400PC:
1015 case CPU_R4400SC:
1016 case CPU_R4400MC:
1017 case CPU_R4300:
1018 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1019 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1020 c->icache.ways = 1;
1021 c->icache.waybit = 0; /* doesn't matter */
1022
1023 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1024 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1025 c->dcache.ways = 1;
1026 c->dcache.waybit = 0; /* does not matter */
1027
1028 c->options |= MIPS_CPU_CACHE_CDEX_P;
1029 break;
1030
1031 case CPU_R10000:
1032 case CPU_R12000:
1033 case CPU_R14000:
1034 case CPU_R16000:
1035 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
1036 c->icache.linesz = 64;
1037 c->icache.ways = 2;
1038 c->icache.waybit = 0;
1039
1040 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
1041 c->dcache.linesz = 32;
1042 c->dcache.ways = 2;
1043 c->dcache.waybit = 0;
1044
1045 c->options |= MIPS_CPU_PREFETCH;
1046 break;
1047
1048 case CPU_VR4133:
1049 write_c0_config(config & ~VR41_CONF_P4K);
1050 case CPU_VR4131:
1051 /* Workaround for cache instruction bug of VR4131 */
1052 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
1053 c->processor_id == 0x0c82U) {
1054 config |= 0x00400000U;
1055 if (c->processor_id == 0x0c80U)
1056 config |= VR41_CONF_BP;
1057 write_c0_config(config);
1058 } else
1059 c->options |= MIPS_CPU_CACHE_CDEX_P;
1060
1061 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1062 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1063 c->icache.ways = 2;
1064 c->icache.waybit = __ffs(icache_size/2);
1065
1066 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1067 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1068 c->dcache.ways = 2;
1069 c->dcache.waybit = __ffs(dcache_size/2);
1070 break;
1071
1072 case CPU_VR41XX:
1073 case CPU_VR4111:
1074 case CPU_VR4121:
1075 case CPU_VR4122:
1076 case CPU_VR4181:
1077 case CPU_VR4181A:
1078 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
1079 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1080 c->icache.ways = 1;
1081 c->icache.waybit = 0; /* doesn't matter */
1082
1083 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
1084 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1085 c->dcache.ways = 1;
1086 c->dcache.waybit = 0; /* does not matter */
1087
1088 c->options |= MIPS_CPU_CACHE_CDEX_P;
1089 break;
1090
1091 case CPU_RM7000:
1092 rm7k_erratum31();
1093
1094 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1095 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1096 c->icache.ways = 4;
1097 c->icache.waybit = __ffs(icache_size / c->icache.ways);
1098
1099 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1100 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1101 c->dcache.ways = 4;
1102 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
1103
1104 c->options |= MIPS_CPU_CACHE_CDEX_P;
1105 c->options |= MIPS_CPU_PREFETCH;
1106 break;
1107
1108 case CPU_LOONGSON2:
1109 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
1110 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
1111 if (prid & 0x3)
1112 c->icache.ways = 4;
1113 else
1114 c->icache.ways = 2;
1115 c->icache.waybit = 0;
1116
1117 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
1118 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
1119 if (prid & 0x3)
1120 c->dcache.ways = 4;
1121 else
1122 c->dcache.ways = 2;
1123 c->dcache.waybit = 0;
1124 break;
1125
1126 case CPU_LOONGSON3:
1127 config1 = read_c0_config1();
1128 lsize = (config1 >> 19) & 7;
1129 if (lsize)
1130 c->icache.linesz = 2 << lsize;
1131 else
1132 c->icache.linesz = 0;
1133 c->icache.sets = 64 << ((config1 >> 22) & 7);
1134 c->icache.ways = 1 + ((config1 >> 16) & 7);
1135 icache_size = c->icache.sets *
1136 c->icache.ways *
1137 c->icache.linesz;
1138 c->icache.waybit = 0;
1139
1140 lsize = (config1 >> 10) & 7;
1141 if (lsize)
1142 c->dcache.linesz = 2 << lsize;
1143 else
1144 c->dcache.linesz = 0;
1145 c->dcache.sets = 64 << ((config1 >> 13) & 7);
1146 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1147 dcache_size = c->dcache.sets *
1148 c->dcache.ways *
1149 c->dcache.linesz;
1150 c->dcache.waybit = 0;
1151 break;
1152
1153 case CPU_CAVIUM_OCTEON3:
1154 /* For now lie about the number of ways. */
1155 c->icache.linesz = 128;
1156 c->icache.sets = 16;
1157 c->icache.ways = 8;
1158 c->icache.flags |= MIPS_CACHE_VTAG;
1159 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
1160
1161 c->dcache.linesz = 128;
1162 c->dcache.ways = 8;
1163 c->dcache.sets = 8;
1164 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
1165 c->options |= MIPS_CPU_PREFETCH;
1166 break;
1167
1168 default:
1169 if (!(config & MIPS_CONF_M))
1170 panic("Don't know how to probe P-caches on this cpu.");
1171
1172 /*
1173 * So we seem to be a MIPS32 or MIPS64 CPU
1174 * So let's probe the I-cache ...
1175 */
1176 config1 = read_c0_config1();
1177
1178 lsize = (config1 >> 19) & 7;
1179
1180 /* IL == 7 is reserved */
1181 if (lsize == 7)
1182 panic("Invalid icache line size");
1183
1184 c->icache.linesz = lsize ? 2 << lsize : 0;
1185
1186 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1187 c->icache.ways = 1 + ((config1 >> 16) & 7);
1188
1189 icache_size = c->icache.sets *
1190 c->icache.ways *
1191 c->icache.linesz;
1192 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1193
1194 if (config & 0x8) /* VI bit */
1195 c->icache.flags |= MIPS_CACHE_VTAG;
1196
1197 /*
1198 * Now probe the MIPS32 / MIPS64 data cache.
1199 */
1200 c->dcache.flags = 0;
1201
1202 lsize = (config1 >> 10) & 7;
1203
1204 /* DL == 7 is reserved */
1205 if (lsize == 7)
1206 panic("Invalid dcache line size");
1207
1208 c->dcache.linesz = lsize ? 2 << lsize : 0;
1209
1210 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1211 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1212
1213 dcache_size = c->dcache.sets *
1214 c->dcache.ways *
1215 c->dcache.linesz;
1216 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1217
1218 c->options |= MIPS_CPU_PREFETCH;
1219 break;
1220 }
1221
1222 /*
1223 * Processor configuration sanity check for the R4000SC erratum
1224 * #5. With page sizes larger than 32kB there is no possibility
1225 * to get a VCE exception anymore so we don't care about this
1226 * misconfiguration. The case is rather theoretical anyway;
1227 * presumably no vendor is shipping his hardware in the "bad"
1228 * configuration.
1229 */
1230 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1231 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1232 !(config & CONF_SC) && c->icache.linesz != 16 &&
1233 PAGE_SIZE <= 0x8000)
1234 panic("Improper R4000SC processor configuration detected");
1235
1236 /* compute a couple of other cache variables */
1237 c->icache.waysize = icache_size / c->icache.ways;
1238 c->dcache.waysize = dcache_size / c->dcache.ways;
1239
1240 c->icache.sets = c->icache.linesz ?
1241 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1242 c->dcache.sets = c->dcache.linesz ?
1243 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1244
1245 /*
1246 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
1247 * virtually indexed so normally would suffer from aliases. So
1248 * normally they'd suffer from aliases but magic in the hardware deals
1249 * with that for us so we don't need to take care ourselves.
1250 */
1251 switch (current_cpu_type()) {
1252 case CPU_20KC:
1253 case CPU_25KF:
1254 case CPU_SB1:
1255 case CPU_SB1A:
1256 case CPU_XLR:
1257 c->dcache.flags |= MIPS_CACHE_PINDEX;
1258 break;
1259
1260 case CPU_R10000:
1261 case CPU_R12000:
1262 case CPU_R14000:
1263 case CPU_R16000:
1264 break;
1265
1266 case CPU_74K:
1267 case CPU_1074K:
1268 has_74k_erratum = alias_74k_erratum(c);
1269 /* Fall through. */
1270 case CPU_M14KC:
1271 case CPU_M14KEC:
1272 case CPU_24K:
1273 case CPU_34K:
1274 case CPU_1004K:
1275 case CPU_INTERAPTIV:
1276 case CPU_P5600:
1277 case CPU_PROAPTIV:
1278 case CPU_M5150:
1279 case CPU_QEMU_GENERIC:
1280 case CPU_I6400:
1281 if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
1282 (c->icache.waysize > PAGE_SIZE))
1283 c->icache.flags |= MIPS_CACHE_ALIASES;
1284 if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
1285 /*
1286 * Effectively physically indexed dcache,
1287 * thus no virtual aliases.
1288 */
1289 c->dcache.flags |= MIPS_CACHE_PINDEX;
1290 break;
1291 }
1292 default:
1293 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
1294 c->dcache.flags |= MIPS_CACHE_ALIASES;
1295 }
1296
1297 switch (current_cpu_type()) {
1298 case CPU_20KC:
1299 /*
1300 * Some older 20Kc chips doesn't have the 'VI' bit in
1301 * the config register.
1302 */
1303 c->icache.flags |= MIPS_CACHE_VTAG;
1304 break;
1305
1306 case CPU_ALCHEMY:
1307 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1308 break;
1309
1310 case CPU_LOONGSON2:
1311 /*
1312 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1313 * one op will act on all 4 ways
1314 */
1315 c->icache.ways = 1;
1316 }
1317
1318 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1319 icache_size >> 10,
1320 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1321 way_string[c->icache.ways], c->icache.linesz);
1322
1323 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1324 dcache_size >> 10, way_string[c->dcache.ways],
1325 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1326 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1327 "cache aliases" : "no aliases",
1328 c->dcache.linesz);
1329}
1330
1331/*
1332 * If you even _breathe_ on this function, look at the gcc output and make sure
1333 * it does not pop things on and off the stack for the cache sizing loop that
1334 * executes in KSEG1 space or else you will crash and burn badly. You have
1335 * been warned.
1336 */
1337static int probe_scache(void)
1338{
1339 unsigned long flags, addr, begin, end, pow2;
1340 unsigned int config = read_c0_config();
1341 struct cpuinfo_mips *c = ¤t_cpu_data;
1342
1343 if (config & CONF_SC)
1344 return 0;
1345
1346 begin = (unsigned long) &_stext;
1347 begin &= ~((4 * 1024 * 1024) - 1);
1348 end = begin + (4 * 1024 * 1024);
1349
1350 /*
1351 * This is such a bitch, you'd think they would make it easy to do
1352 * this. Away you daemons of stupidity!
1353 */
1354 local_irq_save(flags);
1355
1356 /* Fill each size-multiple cache line with a valid tag. */
1357 pow2 = (64 * 1024);
1358 for (addr = begin; addr < end; addr = (begin + pow2)) {
1359 unsigned long *p = (unsigned long *) addr;
1360 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1361 pow2 <<= 1;
1362 }
1363
1364 /* Load first line with zero (therefore invalid) tag. */
1365 write_c0_taglo(0);
1366 write_c0_taghi(0);
1367 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1368 cache_op(Index_Store_Tag_I, begin);
1369 cache_op(Index_Store_Tag_D, begin);
1370 cache_op(Index_Store_Tag_SD, begin);
1371
1372 /* Now search for the wrap around point. */
1373 pow2 = (128 * 1024);
1374 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1375 cache_op(Index_Load_Tag_SD, addr);
1376 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1377 if (!read_c0_taglo())
1378 break;
1379 pow2 <<= 1;
1380 }
1381 local_irq_restore(flags);
1382 addr -= begin;
1383
1384 scache_size = addr;
1385 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1386 c->scache.ways = 1;
1387 c->scache.waybit = 0; /* does not matter */
1388
1389 return 1;
1390}
1391
1392static void __init loongson2_sc_init(void)
1393{
1394 struct cpuinfo_mips *c = ¤t_cpu_data;
1395
1396 scache_size = 512*1024;
1397 c->scache.linesz = 32;
1398 c->scache.ways = 4;
1399 c->scache.waybit = 0;
1400 c->scache.waysize = scache_size / (c->scache.ways);
1401 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1402 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1403 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1404
1405 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1406}
1407
1408static void __init loongson3_sc_init(void)
1409{
1410 struct cpuinfo_mips *c = ¤t_cpu_data;
1411 unsigned int config2, lsize;
1412
1413 config2 = read_c0_config2();
1414 lsize = (config2 >> 4) & 15;
1415 if (lsize)
1416 c->scache.linesz = 2 << lsize;
1417 else
1418 c->scache.linesz = 0;
1419 c->scache.sets = 64 << ((config2 >> 8) & 15);
1420 c->scache.ways = 1 + (config2 & 15);
1421
1422 scache_size = c->scache.sets *
1423 c->scache.ways *
1424 c->scache.linesz;
1425 /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
1426 scache_size *= 4;
1427 c->scache.waybit = 0;
1428 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1429 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1430 if (scache_size)
1431 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1432 return;
1433}
1434
1435extern int r5k_sc_init(void);
1436extern int rm7k_sc_init(void);
1437extern int mips_sc_init(void);
1438
1439static void setup_scache(void)
1440{
1441 struct cpuinfo_mips *c = ¤t_cpu_data;
1442 unsigned int config = read_c0_config();
1443 int sc_present = 0;
1444
1445 /*
1446 * Do the probing thing on R4000SC and R4400SC processors. Other
1447 * processors don't have a S-cache that would be relevant to the
1448 * Linux memory management.
1449 */
1450 switch (current_cpu_type()) {
1451 case CPU_R4000SC:
1452 case CPU_R4000MC:
1453 case CPU_R4400SC:
1454 case CPU_R4400MC:
1455 sc_present = run_uncached(probe_scache);
1456 if (sc_present)
1457 c->options |= MIPS_CPU_CACHE_CDEX_S;
1458 break;
1459
1460 case CPU_R10000:
1461 case CPU_R12000:
1462 case CPU_R14000:
1463 case CPU_R16000:
1464 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1465 c->scache.linesz = 64 << ((config >> 13) & 1);
1466 c->scache.ways = 2;
1467 c->scache.waybit= 0;
1468 sc_present = 1;
1469 break;
1470
1471 case CPU_R5000:
1472 case CPU_NEVADA:
1473#ifdef CONFIG_R5000_CPU_SCACHE
1474 r5k_sc_init();
1475#endif
1476 return;
1477
1478 case CPU_RM7000:
1479#ifdef CONFIG_RM7000_CPU_SCACHE
1480 rm7k_sc_init();
1481#endif
1482 return;
1483
1484 case CPU_LOONGSON2:
1485 loongson2_sc_init();
1486 return;
1487
1488 case CPU_LOONGSON3:
1489 loongson3_sc_init();
1490 return;
1491
1492 case CPU_CAVIUM_OCTEON3:
1493 case CPU_XLP:
1494 /* don't need to worry about L2, fully coherent */
1495 return;
1496
1497 default:
1498 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1499 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
1500 MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
1501#ifdef CONFIG_MIPS_CPU_SCACHE
1502 if (mips_sc_init ()) {
1503 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1504 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1505 scache_size >> 10,
1506 way_string[c->scache.ways], c->scache.linesz);
1507 }
1508#else
1509 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1510 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1511#endif
1512 return;
1513 }
1514 sc_present = 0;
1515 }
1516
1517 if (!sc_present)
1518 return;
1519
1520 /* compute a couple of other cache variables */
1521 c->scache.waysize = scache_size / c->scache.ways;
1522
1523 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1524
1525 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1526 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1527
1528 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1529}
1530
1531void au1x00_fixup_config_od(void)
1532{
1533 /*
1534 * c0_config.od (bit 19) was write only (and read as 0)
1535 * on the early revisions of Alchemy SOCs. It disables the bus
1536 * transaction overlapping and needs to be set to fix various errata.
1537 */
1538 switch (read_c0_prid()) {
1539 case 0x00030100: /* Au1000 DA */
1540 case 0x00030201: /* Au1000 HA */
1541 case 0x00030202: /* Au1000 HB */
1542 case 0x01030200: /* Au1500 AB */
1543 /*
1544 * Au1100 errata actually keeps silence about this bit, so we set it
1545 * just in case for those revisions that require it to be set according
1546 * to the (now gone) cpu table.
1547 */
1548 case 0x02030200: /* Au1100 AB */
1549 case 0x02030201: /* Au1100 BA */
1550 case 0x02030202: /* Au1100 BC */
1551 set_c0_config(1 << 19);
1552 break;
1553 }
1554}
1555
1556/* CP0 hazard avoidance. */
1557#define NXP_BARRIER() \
1558 __asm__ __volatile__( \
1559 ".set noreorder\n\t" \
1560 "nop; nop; nop; nop; nop; nop;\n\t" \
1561 ".set reorder\n\t")
1562
1563static void nxp_pr4450_fixup_config(void)
1564{
1565 unsigned long config0;
1566
1567 config0 = read_c0_config();
1568
1569 /* clear all three cache coherency fields */
1570 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1571 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1572 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1573 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1574 write_c0_config(config0);
1575 NXP_BARRIER();
1576}
1577
1578static int cca = -1;
1579
1580static int __init cca_setup(char *str)
1581{
1582 get_option(&str, &cca);
1583
1584 return 0;
1585}
1586
1587early_param("cca", cca_setup);
1588
1589static void coherency_setup(void)
1590{
1591 if (cca < 0 || cca > 7)
1592 cca = read_c0_config() & CONF_CM_CMASK;
1593 _page_cachable_default = cca << _CACHE_SHIFT;
1594
1595 pr_debug("Using cache attribute %d\n", cca);
1596 change_c0_config(CONF_CM_CMASK, cca);
1597
1598 /*
1599 * c0_status.cu=0 specifies that updates by the sc instruction use
1600 * the coherency mode specified by the TLB; 1 means cachable
1601 * coherent update on write will be used. Not all processors have
1602 * this bit and; some wire it to zero, others like Toshiba had the
1603 * silly idea of putting something else there ...
1604 */
1605 switch (current_cpu_type()) {
1606 case CPU_R4000PC:
1607 case CPU_R4000SC:
1608 case CPU_R4000MC:
1609 case CPU_R4400PC:
1610 case CPU_R4400SC:
1611 case CPU_R4400MC:
1612 clear_c0_config(CONF_CU);
1613 break;
1614 /*
1615 * We need to catch the early Alchemy SOCs with
1616 * the write-only co_config.od bit and set it back to one on:
1617 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1618 */
1619 case CPU_ALCHEMY:
1620 au1x00_fixup_config_od();
1621 break;
1622
1623 case PRID_IMP_PR4450:
1624 nxp_pr4450_fixup_config();
1625 break;
1626 }
1627}
1628
1629static void r4k_cache_error_setup(void)
1630{
1631 extern char __weak except_vec2_generic;
1632 extern char __weak except_vec2_sb1;
1633
1634 switch (current_cpu_type()) {
1635 case CPU_SB1:
1636 case CPU_SB1A:
1637 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1638 break;
1639
1640 default:
1641 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1642 break;
1643 }
1644}
1645
1646void r4k_cache_init(void)
1647{
1648 extern void build_clear_page(void);
1649 extern void build_copy_page(void);
1650 struct cpuinfo_mips *c = ¤t_cpu_data;
1651
1652 probe_pcache();
1653 setup_scache();
1654
1655 r4k_blast_dcache_page_setup();
1656 r4k_blast_dcache_page_indexed_setup();
1657 r4k_blast_dcache_setup();
1658 r4k_blast_icache_page_setup();
1659 r4k_blast_icache_page_indexed_setup();
1660 r4k_blast_icache_setup();
1661 r4k_blast_scache_page_setup();
1662 r4k_blast_scache_page_indexed_setup();
1663 r4k_blast_scache_setup();
1664#ifdef CONFIG_EVA
1665 r4k_blast_dcache_user_page_setup();
1666 r4k_blast_icache_user_page_setup();
1667#endif
1668
1669 /*
1670 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1671 * This code supports virtually indexed processors and will be
1672 * unnecessarily inefficient on physically indexed processors.
1673 */
1674 if (c->dcache.linesz)
1675 shm_align_mask = max_t( unsigned long,
1676 c->dcache.sets * c->dcache.linesz - 1,
1677 PAGE_SIZE - 1);
1678 else
1679 shm_align_mask = PAGE_SIZE-1;
1680
1681 __flush_cache_vmap = r4k__flush_cache_vmap;
1682 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1683
1684 flush_cache_all = cache_noop;
1685 __flush_cache_all = r4k___flush_cache_all;
1686 flush_cache_mm = r4k_flush_cache_mm;
1687 flush_cache_page = r4k_flush_cache_page;
1688 flush_cache_range = r4k_flush_cache_range;
1689
1690 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1691
1692 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1693 flush_icache_all = r4k_flush_icache_all;
1694 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1695 flush_data_cache_page = r4k_flush_data_cache_page;
1696 flush_icache_range = r4k_flush_icache_range;
1697 local_flush_icache_range = local_r4k_flush_icache_range;
1698
1699#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
1700 if (coherentio) {
1701 _dma_cache_wback_inv = (void *)cache_noop;
1702 _dma_cache_wback = (void *)cache_noop;
1703 _dma_cache_inv = (void *)cache_noop;
1704 } else {
1705 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1706 _dma_cache_wback = r4k_dma_cache_wback_inv;
1707 _dma_cache_inv = r4k_dma_cache_inv;
1708 }
1709#endif
1710
1711 build_clear_page();
1712 build_copy_page();
1713
1714 /*
1715 * We want to run CMP kernels on core with and without coherent
1716 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1717 * or not to flush caches.
1718 */
1719 local_r4k___flush_cache_all(NULL);
1720
1721 coherency_setup();
1722 board_cache_error_setup = r4k_cache_error_setup;
1723
1724 /*
1725 * Per-CPU overrides
1726 */
1727 switch (current_cpu_type()) {
1728 case CPU_BMIPS4350:
1729 case CPU_BMIPS4380:
1730 /* No IPI is needed because all CPUs share the same D$ */
1731 flush_data_cache_page = r4k_blast_dcache_page;
1732 break;
1733 case CPU_BMIPS5000:
1734 /* We lose our superpowers if L2 is disabled */
1735 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
1736 break;
1737
1738 /* I$ fills from D$ just by emptying the write buffers */
1739 flush_cache_page = (void *)b5k_instruction_hazard;
1740 flush_cache_range = (void *)b5k_instruction_hazard;
1741 flush_cache_sigtramp = (void *)b5k_instruction_hazard;
1742 local_flush_data_cache_page = (void *)b5k_instruction_hazard;
1743 flush_data_cache_page = (void *)b5k_instruction_hazard;
1744 flush_icache_range = (void *)b5k_instruction_hazard;
1745 local_flush_icache_range = (void *)b5k_instruction_hazard;
1746
1747 /* Cache aliases are handled in hardware; allow HIGHMEM */
1748 current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
1749
1750 /* Optimization: an L2 flush implicitly flushes the L1 */
1751 current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
1752 break;
1753 }
1754}
1755
1756static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
1757 void *v)
1758{
1759 switch (cmd) {
1760 case CPU_PM_ENTER_FAILED:
1761 case CPU_PM_EXIT:
1762 coherency_setup();
1763 break;
1764 }
1765
1766 return NOTIFY_OK;
1767}
1768
1769static struct notifier_block r4k_cache_pm_notifier_block = {
1770 .notifier_call = r4k_cache_pm_notifier,
1771};
1772
1773int __init r4k_cache_init_pm(void)
1774{
1775 return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
1776}
1777arch_initcall(r4k_cache_init_pm);