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1/*
2* This file is subject to the terms and conditions of the GNU General Public
3* License. See the file "COPYING" in the main directory of this archive
4* for more details.
5*
6* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7* Authors: Sanjay Lal <sanjayl@kymasys.com>
8*/
9
10#ifndef __MIPS_KVM_HOST_H__
11#define __MIPS_KVM_HOST_H__
12
13#include <linux/cpumask.h>
14#include <linux/mutex.h>
15#include <linux/hrtimer.h>
16#include <linux/interrupt.h>
17#include <linux/types.h>
18#include <linux/kvm.h>
19#include <linux/kvm_types.h>
20#include <linux/threads.h>
21#include <linux/spinlock.h>
22
23#include <asm/asm.h>
24#include <asm/inst.h>
25#include <asm/mipsregs.h>
26
27#include <kvm/iodev.h>
28
29/* MIPS KVM register ids */
30#define MIPS_CP0_32(_R, _S) \
31 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
32
33#define MIPS_CP0_64(_R, _S) \
34 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
35
36#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
37#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
38#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
39#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
40#define KVM_REG_MIPS_CP0_CONTEXTCONFIG MIPS_CP0_32(4, 1)
41#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
42#define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3)
43#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
44#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
45#define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2)
46#define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3)
47#define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4)
48#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5)
49#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6)
50#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7)
51#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
52#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6)
53#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
54#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
55#define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1)
56#define KVM_REG_MIPS_CP0_BADINSTRP MIPS_CP0_32(8, 2)
57#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
58#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
59#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
60#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
61#define KVM_REG_MIPS_CP0_INTCTL MIPS_CP0_32(12, 1)
62#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
63#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
64#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
65#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
66#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
67#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
68#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
69#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
70#define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
71#define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
72#define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6)
73#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
74#define KVM_REG_MIPS_CP0_MAARI MIPS_CP0_64(17, 2)
75#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
76#define KVM_REG_MIPS_CP0_DIAG MIPS_CP0_32(22, 0)
77#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
78#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
79#define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3)
80#define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4)
81#define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5)
82#define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6)
83#define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7)
84
85
86#define KVM_MAX_VCPUS 16
87
88#define KVM_HALT_POLL_NS_DEFAULT 500000
89
90extern unsigned long GUESTID_MASK;
91extern unsigned long GUESTID_FIRST_VERSION;
92extern unsigned long GUESTID_VERSION_MASK;
93
94#define KVM_INVALID_ADDR 0xdeadbeef
95
96/*
97 * EVA has overlapping user & kernel address spaces, so user VAs may be >
98 * PAGE_OFFSET. For this reason we can't use the default KVM_HVA_ERR_BAD of
99 * PAGE_OFFSET.
100 */
101
102#define KVM_HVA_ERR_BAD (-1UL)
103#define KVM_HVA_ERR_RO_BAD (-2UL)
104
105static inline bool kvm_is_error_hva(unsigned long addr)
106{
107 return IS_ERR_VALUE(addr);
108}
109
110struct kvm_vm_stat {
111 struct kvm_vm_stat_generic generic;
112};
113
114struct kvm_vcpu_stat {
115 struct kvm_vcpu_stat_generic generic;
116 u64 wait_exits;
117 u64 cache_exits;
118 u64 signal_exits;
119 u64 int_exits;
120 u64 cop_unusable_exits;
121 u64 tlbmod_exits;
122 u64 tlbmiss_ld_exits;
123 u64 tlbmiss_st_exits;
124 u64 addrerr_st_exits;
125 u64 addrerr_ld_exits;
126 u64 syscall_exits;
127 u64 resvd_inst_exits;
128 u64 break_inst_exits;
129 u64 trap_inst_exits;
130 u64 msa_fpe_exits;
131 u64 fpe_exits;
132 u64 msa_disabled_exits;
133 u64 flush_dcache_exits;
134 u64 vz_gpsi_exits;
135 u64 vz_gsfc_exits;
136 u64 vz_hc_exits;
137 u64 vz_grr_exits;
138 u64 vz_gva_exits;
139 u64 vz_ghfc_exits;
140 u64 vz_gpa_exits;
141 u64 vz_resvd_exits;
142#ifdef CONFIG_CPU_LOONGSON64
143 u64 vz_cpucfg_exits;
144#endif
145};
146
147struct kvm_arch_memory_slot {
148};
149
150#ifdef CONFIG_CPU_LOONGSON64
151struct ipi_state {
152 uint32_t status;
153 uint32_t en;
154 uint32_t set;
155 uint32_t clear;
156 uint64_t buf[4];
157};
158
159struct loongson_kvm_ipi;
160
161struct ipi_io_device {
162 int node_id;
163 struct loongson_kvm_ipi *ipi;
164 struct kvm_io_device device;
165};
166
167struct loongson_kvm_ipi {
168 spinlock_t lock;
169 struct kvm *kvm;
170 struct ipi_state ipistate[16];
171 struct ipi_io_device dev_ipi[4];
172};
173#endif
174
175struct kvm_arch {
176 /* Guest physical mm */
177 struct mm_struct gpa_mm;
178 /* Mask of CPUs needing GPA ASID flush */
179 cpumask_t asid_flush_mask;
180#ifdef CONFIG_CPU_LOONGSON64
181 struct loongson_kvm_ipi ipi;
182#endif
183};
184
185#define N_MIPS_COPROC_REGS 32
186#define N_MIPS_COPROC_SEL 8
187
188struct mips_coproc {
189 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
190#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
191 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
192#endif
193};
194
195/*
196 * Coprocessor 0 register names
197 */
198#define MIPS_CP0_TLB_INDEX 0
199#define MIPS_CP0_TLB_RANDOM 1
200#define MIPS_CP0_TLB_LOW 2
201#define MIPS_CP0_TLB_LO0 2
202#define MIPS_CP0_TLB_LO1 3
203#define MIPS_CP0_TLB_CONTEXT 4
204#define MIPS_CP0_TLB_PG_MASK 5
205#define MIPS_CP0_TLB_WIRED 6
206#define MIPS_CP0_HWRENA 7
207#define MIPS_CP0_BAD_VADDR 8
208#define MIPS_CP0_COUNT 9
209#define MIPS_CP0_TLB_HI 10
210#define MIPS_CP0_COMPARE 11
211#define MIPS_CP0_STATUS 12
212#define MIPS_CP0_CAUSE 13
213#define MIPS_CP0_EXC_PC 14
214#define MIPS_CP0_PRID 15
215#define MIPS_CP0_CONFIG 16
216#define MIPS_CP0_LLADDR 17
217#define MIPS_CP0_WATCH_LO 18
218#define MIPS_CP0_WATCH_HI 19
219#define MIPS_CP0_TLB_XCONTEXT 20
220#define MIPS_CP0_DIAG 22
221#define MIPS_CP0_ECC 26
222#define MIPS_CP0_CACHE_ERR 27
223#define MIPS_CP0_TAG_LO 28
224#define MIPS_CP0_TAG_HI 29
225#define MIPS_CP0_ERROR_PC 30
226#define MIPS_CP0_DEBUG 23
227#define MIPS_CP0_DEPC 24
228#define MIPS_CP0_PERFCNT 25
229#define MIPS_CP0_ERRCTL 26
230#define MIPS_CP0_DATA_LO 28
231#define MIPS_CP0_DATA_HI 29
232#define MIPS_CP0_DESAVE 31
233
234#define MIPS_CP0_CONFIG_SEL 0
235#define MIPS_CP0_CONFIG1_SEL 1
236#define MIPS_CP0_CONFIG2_SEL 2
237#define MIPS_CP0_CONFIG3_SEL 3
238#define MIPS_CP0_CONFIG4_SEL 4
239#define MIPS_CP0_CONFIG5_SEL 5
240
241#define MIPS_CP0_GUESTCTL2 10
242#define MIPS_CP0_GUESTCTL2_SEL 5
243#define MIPS_CP0_GTOFFSET 12
244#define MIPS_CP0_GTOFFSET_SEL 7
245
246/* Resume Flags */
247#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
248#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
249
250#define RESUME_GUEST 0
251#define RESUME_GUEST_DR RESUME_FLAG_DR
252#define RESUME_HOST RESUME_FLAG_HOST
253
254enum emulation_result {
255 EMULATE_DONE, /* no further processing */
256 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
257 EMULATE_FAIL, /* can't emulate this instruction */
258 EMULATE_WAIT, /* WAIT instruction */
259 EMULATE_PRIV_FAIL,
260 EMULATE_EXCEPT, /* A guest exception has been generated */
261 EMULATE_HYPERCALL, /* HYPCALL instruction */
262};
263
264#if defined(CONFIG_64BIT)
265#define VPN2_MASK GENMASK(cpu_vmbits - 1, 13)
266#else
267#define VPN2_MASK 0xffffe000
268#endif
269#define KVM_ENTRYHI_ASID cpu_asid_mask(&boot_cpu_data)
270#define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
271#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
272#define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
273#define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1)
274#define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
275#define TLB_IS_DIRTY(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_D)
276#define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
277 ((y) & VPN2_MASK & ~(x).tlb_mask))
278#define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
279 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
280
281struct kvm_mips_tlb {
282 long tlb_mask;
283 long tlb_hi;
284 long tlb_lo[2];
285};
286
287#define KVM_MIPS_AUX_FPU 0x1
288#define KVM_MIPS_AUX_MSA 0x2
289
290struct kvm_vcpu_arch {
291 void *guest_ebase;
292 int (*vcpu_run)(struct kvm_vcpu *vcpu);
293
294 /* Host registers preserved across guest mode execution */
295 unsigned long host_stack;
296 unsigned long host_gp;
297 unsigned long host_pgd;
298 unsigned long host_entryhi;
299
300 /* Host CP0 registers used when handling exits from guest */
301 unsigned long host_cp0_badvaddr;
302 unsigned long host_cp0_epc;
303 u32 host_cp0_cause;
304 u32 host_cp0_guestctl0;
305 u32 host_cp0_badinstr;
306 u32 host_cp0_badinstrp;
307
308 /* GPRS */
309 unsigned long gprs[32];
310 unsigned long hi;
311 unsigned long lo;
312 unsigned long pc;
313
314 /* FPU State */
315 struct mips_fpu_struct fpu;
316 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
317 unsigned int aux_inuse;
318
319 /* COP0 State */
320 struct mips_coproc cop0;
321
322 /* Resume PC after MMIO completion */
323 unsigned long io_pc;
324 /* GPR used as IO source/target */
325 u32 io_gpr;
326
327 struct hrtimer comparecount_timer;
328 /* Count timer control KVM register */
329 u32 count_ctl;
330 /* Count bias from the raw time */
331 u32 count_bias;
332 /* Frequency of timer in Hz */
333 u32 count_hz;
334 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
335 s64 count_dyn_bias;
336 /* Resume time */
337 ktime_t count_resume;
338 /* Period of timer tick in ns */
339 u64 count_period;
340
341 /* Bitmask of exceptions that are pending */
342 unsigned long pending_exceptions;
343
344 /* Bitmask of pending exceptions to be cleared */
345 unsigned long pending_exceptions_clr;
346
347 /* Cache some mmu pages needed inside spinlock regions */
348 struct kvm_mmu_memory_cache mmu_page_cache;
349
350 /* vcpu's vzguestid is different on each host cpu in an smp system */
351 u32 vzguestid[NR_CPUS];
352
353 /* wired guest TLB entries */
354 struct kvm_mips_tlb *wired_tlb;
355 unsigned int wired_tlb_limit;
356 unsigned int wired_tlb_used;
357
358 /* emulated guest MAAR registers */
359 unsigned long maar[6];
360
361 /* Last CPU the VCPU state was loaded on */
362 int last_sched_cpu;
363 /* Last CPU the VCPU actually executed guest code on */
364 int last_exec_cpu;
365
366 /* WAIT executed */
367 int wait;
368
369 u8 fpu_enabled;
370 u8 msa_enabled;
371};
372
373static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
374 unsigned long val)
375{
376 unsigned long temp;
377 do {
378 __asm__ __volatile__(
379 " .set push \n"
380 " .set "MIPS_ISA_ARCH_LEVEL" \n"
381 " "__stringify(LONG_LL) " %0, %1 \n"
382 " or %0, %2 \n"
383 " "__stringify(LONG_SC) " %0, %1 \n"
384 " .set pop \n"
385 : "=&r" (temp), "+m" (*reg)
386 : "r" (val));
387 } while (unlikely(!temp));
388}
389
390static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
391 unsigned long val)
392{
393 unsigned long temp;
394 do {
395 __asm__ __volatile__(
396 " .set push \n"
397 " .set "MIPS_ISA_ARCH_LEVEL" \n"
398 " "__stringify(LONG_LL) " %0, %1 \n"
399 " and %0, %2 \n"
400 " "__stringify(LONG_SC) " %0, %1 \n"
401 " .set pop \n"
402 : "=&r" (temp), "+m" (*reg)
403 : "r" (~val));
404 } while (unlikely(!temp));
405}
406
407static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
408 unsigned long change,
409 unsigned long val)
410{
411 unsigned long temp;
412 do {
413 __asm__ __volatile__(
414 " .set push \n"
415 " .set "MIPS_ISA_ARCH_LEVEL" \n"
416 " "__stringify(LONG_LL) " %0, %1 \n"
417 " and %0, %2 \n"
418 " or %0, %3 \n"
419 " "__stringify(LONG_SC) " %0, %1 \n"
420 " .set pop \n"
421 : "=&r" (temp), "+m" (*reg)
422 : "r" (~change), "r" (val & change));
423 } while (unlikely(!temp));
424}
425
426/* Guest register types, used in accessor build below */
427#define __KVMT32 u32
428#define __KVMTl unsigned long
429
430/*
431 * __BUILD_KVM_$ops_SAVED(): kvm_$op_sw_gc0_$reg()
432 * These operate on the saved guest C0 state in RAM.
433 */
434
435/* Generate saved context simple accessors */
436#define __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \
437static inline __KVMT##type kvm_read_sw_gc0_##name(struct mips_coproc *cop0) \
438{ \
439 return cop0->reg[(_reg)][(sel)]; \
440} \
441static inline void kvm_write_sw_gc0_##name(struct mips_coproc *cop0, \
442 __KVMT##type val) \
443{ \
444 cop0->reg[(_reg)][(sel)] = val; \
445}
446
447/* Generate saved context bitwise modifiers */
448#define __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \
449static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \
450 __KVMT##type val) \
451{ \
452 cop0->reg[(_reg)][(sel)] |= val; \
453} \
454static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \
455 __KVMT##type val) \
456{ \
457 cop0->reg[(_reg)][(sel)] &= ~val; \
458} \
459static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \
460 __KVMT##type mask, \
461 __KVMT##type val) \
462{ \
463 unsigned long _mask = mask; \
464 cop0->reg[(_reg)][(sel)] &= ~_mask; \
465 cop0->reg[(_reg)][(sel)] |= val & _mask; \
466}
467
468/* Generate saved context atomic bitwise modifiers */
469#define __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \
470static inline void kvm_set_sw_gc0_##name(struct mips_coproc *cop0, \
471 __KVMT##type val) \
472{ \
473 _kvm_atomic_set_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
474} \
475static inline void kvm_clear_sw_gc0_##name(struct mips_coproc *cop0, \
476 __KVMT##type val) \
477{ \
478 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[(_reg)][(sel)], val); \
479} \
480static inline void kvm_change_sw_gc0_##name(struct mips_coproc *cop0, \
481 __KVMT##type mask, \
482 __KVMT##type val) \
483{ \
484 _kvm_atomic_change_c0_guest_reg(&cop0->reg[(_reg)][(sel)], mask, \
485 val); \
486}
487
488/*
489 * __BUILD_KVM_$ops_VZ(): kvm_$op_vz_gc0_$reg()
490 * These operate on the VZ guest C0 context in hardware.
491 */
492
493/* Generate VZ guest context simple accessors */
494#define __BUILD_KVM_RW_VZ(name, type, _reg, sel) \
495static inline __KVMT##type kvm_read_vz_gc0_##name(struct mips_coproc *cop0) \
496{ \
497 return read_gc0_##name(); \
498} \
499static inline void kvm_write_vz_gc0_##name(struct mips_coproc *cop0, \
500 __KVMT##type val) \
501{ \
502 write_gc0_##name(val); \
503}
504
505/* Generate VZ guest context bitwise modifiers */
506#define __BUILD_KVM_SET_VZ(name, type, _reg, sel) \
507static inline void kvm_set_vz_gc0_##name(struct mips_coproc *cop0, \
508 __KVMT##type val) \
509{ \
510 set_gc0_##name(val); \
511} \
512static inline void kvm_clear_vz_gc0_##name(struct mips_coproc *cop0, \
513 __KVMT##type val) \
514{ \
515 clear_gc0_##name(val); \
516} \
517static inline void kvm_change_vz_gc0_##name(struct mips_coproc *cop0, \
518 __KVMT##type mask, \
519 __KVMT##type val) \
520{ \
521 change_gc0_##name(mask, val); \
522}
523
524/* Generate VZ guest context save/restore to/from saved context */
525#define __BUILD_KVM_SAVE_VZ(name, _reg, sel) \
526static inline void kvm_restore_gc0_##name(struct mips_coproc *cop0) \
527{ \
528 write_gc0_##name(cop0->reg[(_reg)][(sel)]); \
529} \
530static inline void kvm_save_gc0_##name(struct mips_coproc *cop0) \
531{ \
532 cop0->reg[(_reg)][(sel)] = read_gc0_##name(); \
533}
534
535/*
536 * __BUILD_KVM_$ops_WRAP(): kvm_$op_$name1() -> kvm_$op_$name2()
537 * These wrap a set of operations to provide them with a different name.
538 */
539
540/* Generate simple accessor wrapper */
541#define __BUILD_KVM_RW_WRAP(name1, name2, type) \
542static inline __KVMT##type kvm_read_##name1(struct mips_coproc *cop0) \
543{ \
544 return kvm_read_##name2(cop0); \
545} \
546static inline void kvm_write_##name1(struct mips_coproc *cop0, \
547 __KVMT##type val) \
548{ \
549 kvm_write_##name2(cop0, val); \
550}
551
552/* Generate bitwise modifier wrapper */
553#define __BUILD_KVM_SET_WRAP(name1, name2, type) \
554static inline void kvm_set_##name1(struct mips_coproc *cop0, \
555 __KVMT##type val) \
556{ \
557 kvm_set_##name2(cop0, val); \
558} \
559static inline void kvm_clear_##name1(struct mips_coproc *cop0, \
560 __KVMT##type val) \
561{ \
562 kvm_clear_##name2(cop0, val); \
563} \
564static inline void kvm_change_##name1(struct mips_coproc *cop0, \
565 __KVMT##type mask, \
566 __KVMT##type val) \
567{ \
568 kvm_change_##name2(cop0, mask, val); \
569}
570
571/*
572 * __BUILD_KVM_$ops_SW(): kvm_$op_c0_guest_$reg() -> kvm_$op_sw_gc0_$reg()
573 * These generate accessors operating on the saved context in RAM, and wrap them
574 * with the common guest C0 accessors (for use by common emulation code).
575 */
576
577#define __BUILD_KVM_RW_SW(name, type, _reg, sel) \
578 __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \
579 __BUILD_KVM_RW_WRAP(c0_guest_##name, sw_gc0_##name, type)
580
581#define __BUILD_KVM_SET_SW(name, type, _reg, sel) \
582 __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \
583 __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
584
585#define __BUILD_KVM_ATOMIC_SW(name, type, _reg, sel) \
586 __BUILD_KVM_ATOMIC_SAVED(name, type, _reg, sel) \
587 __BUILD_KVM_SET_WRAP(c0_guest_##name, sw_gc0_##name, type)
588
589/*
590 * VZ (hardware assisted virtualisation)
591 * These macros use the active guest state in VZ mode (hardware registers),
592 */
593
594/*
595 * __BUILD_KVM_$ops_HW(): kvm_$op_c0_guest_$reg() -> kvm_$op_vz_gc0_$reg()
596 * These generate accessors operating on the VZ guest context in hardware, and
597 * wrap them with the common guest C0 accessors (for use by common emulation
598 * code).
599 *
600 * Accessors operating on the saved context in RAM are also generated to allow
601 * convenient explicit saving and restoring of the state.
602 */
603
604#define __BUILD_KVM_RW_HW(name, type, _reg, sel) \
605 __BUILD_KVM_RW_SAVED(name, type, _reg, sel) \
606 __BUILD_KVM_RW_VZ(name, type, _reg, sel) \
607 __BUILD_KVM_RW_WRAP(c0_guest_##name, vz_gc0_##name, type) \
608 __BUILD_KVM_SAVE_VZ(name, _reg, sel)
609
610#define __BUILD_KVM_SET_HW(name, type, _reg, sel) \
611 __BUILD_KVM_SET_SAVED(name, type, _reg, sel) \
612 __BUILD_KVM_SET_VZ(name, type, _reg, sel) \
613 __BUILD_KVM_SET_WRAP(c0_guest_##name, vz_gc0_##name, type)
614
615/*
616 * We can't do atomic modifications of COP0 state if hardware can modify it.
617 * Races must be handled explicitly.
618 */
619#define __BUILD_KVM_ATOMIC_HW __BUILD_KVM_SET_HW
620
621/*
622 * Define accessors for CP0 registers that are accessible to the guest. These
623 * are primarily used by common emulation code, which may need to access the
624 * registers differently depending on the implementation.
625 *
626 * fns_hw/sw name type reg num select
627 */
628__BUILD_KVM_RW_HW(index, 32, MIPS_CP0_TLB_INDEX, 0)
629__BUILD_KVM_RW_HW(entrylo0, l, MIPS_CP0_TLB_LO0, 0)
630__BUILD_KVM_RW_HW(entrylo1, l, MIPS_CP0_TLB_LO1, 0)
631__BUILD_KVM_RW_HW(context, l, MIPS_CP0_TLB_CONTEXT, 0)
632__BUILD_KVM_RW_HW(contextconfig, 32, MIPS_CP0_TLB_CONTEXT, 1)
633__BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT, 2)
634__BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3)
635__BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0)
636__BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1)
637__BUILD_KVM_RW_HW(segctl0, l, MIPS_CP0_TLB_PG_MASK, 2)
638__BUILD_KVM_RW_HW(segctl1, l, MIPS_CP0_TLB_PG_MASK, 3)
639__BUILD_KVM_RW_HW(segctl2, l, MIPS_CP0_TLB_PG_MASK, 4)
640__BUILD_KVM_RW_HW(pwbase, l, MIPS_CP0_TLB_PG_MASK, 5)
641__BUILD_KVM_RW_HW(pwfield, l, MIPS_CP0_TLB_PG_MASK, 6)
642__BUILD_KVM_RW_HW(pwsize, l, MIPS_CP0_TLB_PG_MASK, 7)
643__BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0)
644__BUILD_KVM_RW_HW(pwctl, 32, MIPS_CP0_TLB_WIRED, 6)
645__BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0)
646__BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR, 0)
647__BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR, 1)
648__BUILD_KVM_RW_HW(badinstrp, 32, MIPS_CP0_BAD_VADDR, 2)
649__BUILD_KVM_RW_SW(count, 32, MIPS_CP0_COUNT, 0)
650__BUILD_KVM_RW_HW(entryhi, l, MIPS_CP0_TLB_HI, 0)
651__BUILD_KVM_RW_HW(compare, 32, MIPS_CP0_COMPARE, 0)
652__BUILD_KVM_RW_HW(status, 32, MIPS_CP0_STATUS, 0)
653__BUILD_KVM_RW_HW(intctl, 32, MIPS_CP0_STATUS, 1)
654__BUILD_KVM_RW_HW(cause, 32, MIPS_CP0_CAUSE, 0)
655__BUILD_KVM_RW_HW(epc, l, MIPS_CP0_EXC_PC, 0)
656__BUILD_KVM_RW_SW(prid, 32, MIPS_CP0_PRID, 0)
657__BUILD_KVM_RW_HW(ebase, l, MIPS_CP0_PRID, 1)
658__BUILD_KVM_RW_HW(config, 32, MIPS_CP0_CONFIG, 0)
659__BUILD_KVM_RW_HW(config1, 32, MIPS_CP0_CONFIG, 1)
660__BUILD_KVM_RW_HW(config2, 32, MIPS_CP0_CONFIG, 2)
661__BUILD_KVM_RW_HW(config3, 32, MIPS_CP0_CONFIG, 3)
662__BUILD_KVM_RW_HW(config4, 32, MIPS_CP0_CONFIG, 4)
663__BUILD_KVM_RW_HW(config5, 32, MIPS_CP0_CONFIG, 5)
664__BUILD_KVM_RW_HW(config6, 32, MIPS_CP0_CONFIG, 6)
665__BUILD_KVM_RW_HW(config7, 32, MIPS_CP0_CONFIG, 7)
666__BUILD_KVM_RW_SW(maari, l, MIPS_CP0_LLADDR, 2)
667__BUILD_KVM_RW_HW(xcontext, l, MIPS_CP0_TLB_XCONTEXT, 0)
668__BUILD_KVM_RW_HW(errorepc, l, MIPS_CP0_ERROR_PC, 0)
669__BUILD_KVM_RW_HW(kscratch1, l, MIPS_CP0_DESAVE, 2)
670__BUILD_KVM_RW_HW(kscratch2, l, MIPS_CP0_DESAVE, 3)
671__BUILD_KVM_RW_HW(kscratch3, l, MIPS_CP0_DESAVE, 4)
672__BUILD_KVM_RW_HW(kscratch4, l, MIPS_CP0_DESAVE, 5)
673__BUILD_KVM_RW_HW(kscratch5, l, MIPS_CP0_DESAVE, 6)
674__BUILD_KVM_RW_HW(kscratch6, l, MIPS_CP0_DESAVE, 7)
675
676/* Bitwise operations (on HW state) */
677__BUILD_KVM_SET_HW(status, 32, MIPS_CP0_STATUS, 0)
678/* Cause can be modified asynchronously from hardirq hrtimer callback */
679__BUILD_KVM_ATOMIC_HW(cause, 32, MIPS_CP0_CAUSE, 0)
680__BUILD_KVM_SET_HW(ebase, l, MIPS_CP0_PRID, 1)
681
682/* Bitwise operations (on saved state) */
683__BUILD_KVM_SET_SAVED(config, 32, MIPS_CP0_CONFIG, 0)
684__BUILD_KVM_SET_SAVED(config1, 32, MIPS_CP0_CONFIG, 1)
685__BUILD_KVM_SET_SAVED(config2, 32, MIPS_CP0_CONFIG, 2)
686__BUILD_KVM_SET_SAVED(config3, 32, MIPS_CP0_CONFIG, 3)
687__BUILD_KVM_SET_SAVED(config4, 32, MIPS_CP0_CONFIG, 4)
688__BUILD_KVM_SET_SAVED(config5, 32, MIPS_CP0_CONFIG, 5)
689
690/* Helpers */
691
692static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
693{
694 return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
695 vcpu->fpu_enabled;
696}
697
698static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
699{
700 return kvm_mips_guest_can_have_fpu(vcpu) &&
701 kvm_read_c0_guest_config1(&vcpu->cop0) & MIPS_CONF1_FP;
702}
703
704static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
705{
706 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
707 vcpu->msa_enabled;
708}
709
710static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
711{
712 return kvm_mips_guest_can_have_msa(vcpu) &&
713 kvm_read_c0_guest_config3(&vcpu->cop0) & MIPS_CONF3_MSA;
714}
715
716struct kvm_mips_callbacks {
717 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
718 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
719 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
720 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
721 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
722 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
723 int (*handle_syscall)(struct kvm_vcpu *vcpu);
724 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
725 int (*handle_break)(struct kvm_vcpu *vcpu);
726 int (*handle_trap)(struct kvm_vcpu *vcpu);
727 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
728 int (*handle_fpe)(struct kvm_vcpu *vcpu);
729 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
730 int (*handle_guest_exit)(struct kvm_vcpu *vcpu);
731 int (*hardware_enable)(void);
732 void (*hardware_disable)(void);
733 int (*check_extension)(struct kvm *kvm, long ext);
734 int (*vcpu_init)(struct kvm_vcpu *vcpu);
735 void (*vcpu_uninit)(struct kvm_vcpu *vcpu);
736 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
737 void (*prepare_flush_shadow)(struct kvm *kvm);
738 gpa_t (*gva_to_gpa)(gva_t gva);
739 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
740 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
741 void (*queue_io_int)(struct kvm_vcpu *vcpu,
742 struct kvm_mips_interrupt *irq);
743 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
744 struct kvm_mips_interrupt *irq);
745 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
746 u32 cause);
747 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
748 u32 cause);
749 unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
750 int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
751 int (*get_one_reg)(struct kvm_vcpu *vcpu,
752 const struct kvm_one_reg *reg, s64 *v);
753 int (*set_one_reg)(struct kvm_vcpu *vcpu,
754 const struct kvm_one_reg *reg, s64 v);
755 int (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
756 int (*vcpu_put)(struct kvm_vcpu *vcpu, int cpu);
757 int (*vcpu_run)(struct kvm_vcpu *vcpu);
758 void (*vcpu_reenter)(struct kvm_vcpu *vcpu);
759};
760extern const struct kvm_mips_callbacks * const kvm_mips_callbacks;
761int kvm_mips_emulation_init(void);
762
763/* Debug: dump vcpu state */
764int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
765
766extern int kvm_mips_handle_exit(struct kvm_vcpu *vcpu);
767
768/* Building of entry/exception code */
769int kvm_mips_entry_setup(void);
770void *kvm_mips_build_vcpu_run(void *addr);
771void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler);
772void *kvm_mips_build_exception(void *addr, void *handler);
773void *kvm_mips_build_exit(void *addr);
774
775/* FPU/MSA context management */
776void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
777void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
778void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
779void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
780void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
781void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
782void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
783void kvm_own_fpu(struct kvm_vcpu *vcpu);
784void kvm_own_msa(struct kvm_vcpu *vcpu);
785void kvm_drop_fpu(struct kvm_vcpu *vcpu);
786void kvm_lose_fpu(struct kvm_vcpu *vcpu);
787
788/* TLB handling */
789int kvm_mips_handle_vz_root_tlb_fault(unsigned long badvaddr,
790 struct kvm_vcpu *vcpu, bool write_fault);
791
792int kvm_vz_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
793int kvm_vz_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long gva,
794 unsigned long *gpa);
795void kvm_vz_local_flush_roottlb_all_guests(void);
796void kvm_vz_local_flush_guesttlb_all(void);
797void kvm_vz_save_guesttlb(struct kvm_mips_tlb *buf, unsigned int index,
798 unsigned int count);
799void kvm_vz_load_guesttlb(const struct kvm_mips_tlb *buf, unsigned int index,
800 unsigned int count);
801#ifdef CONFIG_CPU_LOONGSON64
802void kvm_loongson_clear_guest_vtlb(void);
803void kvm_loongson_clear_guest_ftlb(void);
804#endif
805
806/* MMU handling */
807
808bool kvm_mips_flush_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
809int kvm_mips_mkclean_gpa_pt(struct kvm *kvm, gfn_t start_gfn, gfn_t end_gfn);
810pgd_t *kvm_pgd_alloc(void);
811void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
812
813/* Emulation */
814enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
815int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
816int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out);
817
818/**
819 * kvm_is_ifetch_fault() - Find whether a TLBL exception is due to ifetch fault.
820 * @vcpu: Virtual CPU.
821 *
822 * Returns: Whether the TLBL exception was likely due to an instruction
823 * fetch fault rather than a data load fault.
824 */
825static inline bool kvm_is_ifetch_fault(struct kvm_vcpu_arch *vcpu)
826{
827 unsigned long badvaddr = vcpu->host_cp0_badvaddr;
828 unsigned long epc = msk_isa16_mode(vcpu->pc);
829 u32 cause = vcpu->host_cp0_cause;
830
831 if (epc == badvaddr)
832 return true;
833
834 /*
835 * Branches may be 32-bit or 16-bit instructions.
836 * This isn't exact, but we don't really support MIPS16 or microMIPS yet
837 * in KVM anyway.
838 */
839 if ((cause & CAUSEF_BD) && badvaddr - epc <= 4)
840 return true;
841
842 return false;
843}
844
845extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu);
846
847u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
848void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
849void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
850void kvm_mips_init_count(struct kvm_vcpu *vcpu, unsigned long count_hz);
851int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
852int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
853int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
854void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
855void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
856enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
857
858/* fairly internal functions requiring some care to use */
859int kvm_mips_count_disabled(struct kvm_vcpu *vcpu);
860ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu, u32 *count);
861int kvm_mips_restore_hrtimer(struct kvm_vcpu *vcpu, ktime_t before,
862 u32 count, int min_drift);
863
864void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu);
865void kvm_vz_lose_htimer(struct kvm_vcpu *vcpu);
866
867enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
868 u32 cause,
869 struct kvm_vcpu *vcpu);
870enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
871 u32 cause,
872 struct kvm_vcpu *vcpu);
873
874/* COP0 */
875enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu);
876
877/* Hypercalls (hypcall.c) */
878
879enum emulation_result kvm_mips_emul_hypcall(struct kvm_vcpu *vcpu,
880 union mips_instruction inst);
881int kvm_mips_handle_hypcall(struct kvm_vcpu *vcpu);
882
883/* Misc */
884extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
885extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
886extern int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
887 struct kvm_mips_interrupt *irq);
888
889static inline void kvm_arch_sync_events(struct kvm *kvm) {}
890static inline void kvm_arch_free_memslot(struct kvm *kvm,
891 struct kvm_memory_slot *slot) {}
892static inline void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) {}
893static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
894static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
895static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
896
897#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
898
899#endif /* __MIPS_KVM_HOST_H__ */
1/*
2* This file is subject to the terms and conditions of the GNU General Public
3* License. See the file "COPYING" in the main directory of this archive
4* for more details.
5*
6* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7* Authors: Sanjay Lal <sanjayl@kymasys.com>
8*/
9
10#ifndef __MIPS_KVM_HOST_H__
11#define __MIPS_KVM_HOST_H__
12
13#include <linux/mutex.h>
14#include <linux/hrtimer.h>
15#include <linux/interrupt.h>
16#include <linux/types.h>
17#include <linux/kvm.h>
18#include <linux/kvm_types.h>
19#include <linux/threads.h>
20#include <linux/spinlock.h>
21
22/* MIPS KVM register ids */
23#define MIPS_CP0_32(_R, _S) \
24 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
25
26#define MIPS_CP0_64(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
28
29#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
46#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
47#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
48#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
49#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
50#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
51#define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
52#define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
53#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
54#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
55#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
56
57
58#define KVM_MAX_VCPUS 1
59#define KVM_USER_MEM_SLOTS 8
60/* memory slots that does not exposed to userspace */
61#define KVM_PRIVATE_MEM_SLOTS 0
62
63#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
64#define KVM_HALT_POLL_NS_DEFAULT 500000
65
66
67
68/* Special address that contains the comm page, used for reducing # of traps */
69#define KVM_GUEST_COMMPAGE_ADDR 0x0
70
71#define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
72 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
73
74#define KVM_GUEST_KUSEG 0x00000000UL
75#define KVM_GUEST_KSEG0 0x40000000UL
76#define KVM_GUEST_KSEG23 0x60000000UL
77#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
78#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
79
80#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
81#define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
82#define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
83
84/*
85 * Map an address to a certain kernel segment
86 */
87#define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
88#define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
89#define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
90
91#define KVM_INVALID_PAGE 0xdeadbeef
92#define KVM_INVALID_INST 0xdeadbeef
93#define KVM_INVALID_ADDR 0xdeadbeef
94
95extern atomic_t kvm_mips_instance;
96extern kvm_pfn_t (*kvm_mips_gfn_to_pfn)(struct kvm *kvm, gfn_t gfn);
97extern void (*kvm_mips_release_pfn_clean)(kvm_pfn_t pfn);
98extern bool (*kvm_mips_is_error_pfn)(kvm_pfn_t pfn);
99
100struct kvm_vm_stat {
101 u32 remote_tlb_flush;
102};
103
104struct kvm_vcpu_stat {
105 u32 wait_exits;
106 u32 cache_exits;
107 u32 signal_exits;
108 u32 int_exits;
109 u32 cop_unusable_exits;
110 u32 tlbmod_exits;
111 u32 tlbmiss_ld_exits;
112 u32 tlbmiss_st_exits;
113 u32 addrerr_st_exits;
114 u32 addrerr_ld_exits;
115 u32 syscall_exits;
116 u32 resvd_inst_exits;
117 u32 break_inst_exits;
118 u32 trap_inst_exits;
119 u32 msa_fpe_exits;
120 u32 fpe_exits;
121 u32 msa_disabled_exits;
122 u32 flush_dcache_exits;
123 u32 halt_successful_poll;
124 u32 halt_attempted_poll;
125 u32 halt_wakeup;
126};
127
128enum kvm_mips_exit_types {
129 WAIT_EXITS,
130 CACHE_EXITS,
131 SIGNAL_EXITS,
132 INT_EXITS,
133 COP_UNUSABLE_EXITS,
134 TLBMOD_EXITS,
135 TLBMISS_LD_EXITS,
136 TLBMISS_ST_EXITS,
137 ADDRERR_ST_EXITS,
138 ADDRERR_LD_EXITS,
139 SYSCALL_EXITS,
140 RESVD_INST_EXITS,
141 BREAK_INST_EXITS,
142 TRAP_INST_EXITS,
143 MSA_FPE_EXITS,
144 FPE_EXITS,
145 MSA_DISABLED_EXITS,
146 FLUSH_DCACHE_EXITS,
147 MAX_KVM_MIPS_EXIT_TYPES
148};
149
150struct kvm_arch_memory_slot {
151};
152
153struct kvm_arch {
154 /* Guest GVA->HPA page table */
155 unsigned long *guest_pmap;
156 unsigned long guest_pmap_npages;
157
158 /* Wired host TLB used for the commpage */
159 int commpage_tlb;
160};
161
162#define N_MIPS_COPROC_REGS 32
163#define N_MIPS_COPROC_SEL 8
164
165struct mips_coproc {
166 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
167#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
168 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
169#endif
170};
171
172/*
173 * Coprocessor 0 register names
174 */
175#define MIPS_CP0_TLB_INDEX 0
176#define MIPS_CP0_TLB_RANDOM 1
177#define MIPS_CP0_TLB_LOW 2
178#define MIPS_CP0_TLB_LO0 2
179#define MIPS_CP0_TLB_LO1 3
180#define MIPS_CP0_TLB_CONTEXT 4
181#define MIPS_CP0_TLB_PG_MASK 5
182#define MIPS_CP0_TLB_WIRED 6
183#define MIPS_CP0_HWRENA 7
184#define MIPS_CP0_BAD_VADDR 8
185#define MIPS_CP0_COUNT 9
186#define MIPS_CP0_TLB_HI 10
187#define MIPS_CP0_COMPARE 11
188#define MIPS_CP0_STATUS 12
189#define MIPS_CP0_CAUSE 13
190#define MIPS_CP0_EXC_PC 14
191#define MIPS_CP0_PRID 15
192#define MIPS_CP0_CONFIG 16
193#define MIPS_CP0_LLADDR 17
194#define MIPS_CP0_WATCH_LO 18
195#define MIPS_CP0_WATCH_HI 19
196#define MIPS_CP0_TLB_XCONTEXT 20
197#define MIPS_CP0_ECC 26
198#define MIPS_CP0_CACHE_ERR 27
199#define MIPS_CP0_TAG_LO 28
200#define MIPS_CP0_TAG_HI 29
201#define MIPS_CP0_ERROR_PC 30
202#define MIPS_CP0_DEBUG 23
203#define MIPS_CP0_DEPC 24
204#define MIPS_CP0_PERFCNT 25
205#define MIPS_CP0_ERRCTL 26
206#define MIPS_CP0_DATA_LO 28
207#define MIPS_CP0_DATA_HI 29
208#define MIPS_CP0_DESAVE 31
209
210#define MIPS_CP0_CONFIG_SEL 0
211#define MIPS_CP0_CONFIG1_SEL 1
212#define MIPS_CP0_CONFIG2_SEL 2
213#define MIPS_CP0_CONFIG3_SEL 3
214#define MIPS_CP0_CONFIG4_SEL 4
215#define MIPS_CP0_CONFIG5_SEL 5
216
217/* Config0 register bits */
218#define CP0C0_M 31
219#define CP0C0_K23 28
220#define CP0C0_KU 25
221#define CP0C0_MDU 20
222#define CP0C0_MM 17
223#define CP0C0_BM 16
224#define CP0C0_BE 15
225#define CP0C0_AT 13
226#define CP0C0_AR 10
227#define CP0C0_MT 7
228#define CP0C0_VI 3
229#define CP0C0_K0 0
230
231/* Config1 register bits */
232#define CP0C1_M 31
233#define CP0C1_MMU 25
234#define CP0C1_IS 22
235#define CP0C1_IL 19
236#define CP0C1_IA 16
237#define CP0C1_DS 13
238#define CP0C1_DL 10
239#define CP0C1_DA 7
240#define CP0C1_C2 6
241#define CP0C1_MD 5
242#define CP0C1_PC 4
243#define CP0C1_WR 3
244#define CP0C1_CA 2
245#define CP0C1_EP 1
246#define CP0C1_FP 0
247
248/* Config2 Register bits */
249#define CP0C2_M 31
250#define CP0C2_TU 28
251#define CP0C2_TS 24
252#define CP0C2_TL 20
253#define CP0C2_TA 16
254#define CP0C2_SU 12
255#define CP0C2_SS 8
256#define CP0C2_SL 4
257#define CP0C2_SA 0
258
259/* Config3 Register bits */
260#define CP0C3_M 31
261#define CP0C3_ISA_ON_EXC 16
262#define CP0C3_ULRI 13
263#define CP0C3_DSPP 10
264#define CP0C3_LPA 7
265#define CP0C3_VEIC 6
266#define CP0C3_VInt 5
267#define CP0C3_SP 4
268#define CP0C3_MT 2
269#define CP0C3_SM 1
270#define CP0C3_TL 0
271
272/* MMU types, the first four entries have the same layout as the
273 CP0C0_MT field. */
274enum mips_mmu_types {
275 MMU_TYPE_NONE,
276 MMU_TYPE_R4000,
277 MMU_TYPE_RESERVED,
278 MMU_TYPE_FMT,
279 MMU_TYPE_R3000,
280 MMU_TYPE_R6000,
281 MMU_TYPE_R8000
282};
283
284/* Resume Flags */
285#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
286#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
287
288#define RESUME_GUEST 0
289#define RESUME_GUEST_DR RESUME_FLAG_DR
290#define RESUME_HOST RESUME_FLAG_HOST
291
292enum emulation_result {
293 EMULATE_DONE, /* no further processing */
294 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
295 EMULATE_FAIL, /* can't emulate this instruction */
296 EMULATE_WAIT, /* WAIT instruction */
297 EMULATE_PRIV_FAIL,
298};
299
300#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
301#define MIPS3_PG_V 0x00000002 /* Valid */
302#define MIPS3_PG_NV 0x00000000
303#define MIPS3_PG_D 0x00000004 /* Dirty */
304
305#define mips3_paddr_to_tlbpfn(x) \
306 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
307#define mips3_tlbpfn_to_paddr(x) \
308 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
309
310#define MIPS3_PG_SHIFT 6
311#define MIPS3_PG_FRAME 0x3fffffc0
312
313#define VPN2_MASK 0xffffe000
314#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
315 ((x).tlb_lo1 & MIPS3_PG_G))
316#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
317#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
318#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
319 ? ((x).tlb_lo1 & MIPS3_PG_V) \
320 : ((x).tlb_lo0 & MIPS3_PG_V))
321#define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
322 ((y) & VPN2_MASK & ~(x).tlb_mask))
323#define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
324 TLB_ASID(x) == ((y) & ASID_MASK))
325
326struct kvm_mips_tlb {
327 long tlb_mask;
328 long tlb_hi;
329 long tlb_lo0;
330 long tlb_lo1;
331};
332
333#define KVM_MIPS_FPU_FPU 0x1
334#define KVM_MIPS_FPU_MSA 0x2
335
336#define KVM_MIPS_GUEST_TLB_SIZE 64
337struct kvm_vcpu_arch {
338 void *host_ebase, *guest_ebase;
339 unsigned long host_stack;
340 unsigned long host_gp;
341
342 /* Host CP0 registers used when handling exits from guest */
343 unsigned long host_cp0_badvaddr;
344 unsigned long host_cp0_cause;
345 unsigned long host_cp0_epc;
346 unsigned long host_cp0_entryhi;
347 uint32_t guest_inst;
348
349 /* GPRS */
350 unsigned long gprs[32];
351 unsigned long hi;
352 unsigned long lo;
353 unsigned long pc;
354
355 /* FPU State */
356 struct mips_fpu_struct fpu;
357 /* Which FPU state is loaded (KVM_MIPS_FPU_*) */
358 unsigned int fpu_inuse;
359
360 /* COP0 State */
361 struct mips_coproc *cop0;
362
363 /* Host KSEG0 address of the EI/DI offset */
364 void *kseg0_commpage;
365
366 u32 io_gpr; /* GPR used as IO source/target */
367
368 struct hrtimer comparecount_timer;
369 /* Count timer control KVM register */
370 uint32_t count_ctl;
371 /* Count bias from the raw time */
372 uint32_t count_bias;
373 /* Frequency of timer in Hz */
374 uint32_t count_hz;
375 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
376 s64 count_dyn_bias;
377 /* Resume time */
378 ktime_t count_resume;
379 /* Period of timer tick in ns */
380 u64 count_period;
381
382 /* Bitmask of exceptions that are pending */
383 unsigned long pending_exceptions;
384
385 /* Bitmask of pending exceptions to be cleared */
386 unsigned long pending_exceptions_clr;
387
388 unsigned long pending_load_cause;
389
390 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
391 unsigned long preempt_entryhi;
392
393 /* S/W Based TLB for guest */
394 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
395
396 /* Cached guest kernel/user ASIDs */
397 uint32_t guest_user_asid[NR_CPUS];
398 uint32_t guest_kernel_asid[NR_CPUS];
399 struct mm_struct guest_kernel_mm, guest_user_mm;
400
401 int last_sched_cpu;
402
403 /* WAIT executed */
404 int wait;
405
406 u8 fpu_enabled;
407 u8 msa_enabled;
408};
409
410
411#define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
412#define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
413#define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
414#define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
415#define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
416#define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
417#define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
418#define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
419#define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
420#define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
421#define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
422#define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
423#define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
424#define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
425#define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
426#define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
427#define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
428#define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
429#define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
430#define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
431#define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
432#define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
433#define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
434#define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
435#define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
436#define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
437#define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
438#define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
439#define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
440#define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
441#define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
442#define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
443#define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
444#define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
445#define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
446#define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
447#define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
448#define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
449#define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
450#define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
451#define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
452#define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
453#define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
454#define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
455#define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
456#define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
457#define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
458#define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
459#define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
460#define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
461
462/*
463 * Some of the guest registers may be modified asynchronously (e.g. from a
464 * hrtimer callback in hard irq context) and therefore need stronger atomicity
465 * guarantees than other registers.
466 */
467
468static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
469 unsigned long val)
470{
471 unsigned long temp;
472 do {
473 __asm__ __volatile__(
474 " .set mips3 \n"
475 " " __LL "%0, %1 \n"
476 " or %0, %2 \n"
477 " " __SC "%0, %1 \n"
478 " .set mips0 \n"
479 : "=&r" (temp), "+m" (*reg)
480 : "r" (val));
481 } while (unlikely(!temp));
482}
483
484static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
485 unsigned long val)
486{
487 unsigned long temp;
488 do {
489 __asm__ __volatile__(
490 " .set mips3 \n"
491 " " __LL "%0, %1 \n"
492 " and %0, %2 \n"
493 " " __SC "%0, %1 \n"
494 " .set mips0 \n"
495 : "=&r" (temp), "+m" (*reg)
496 : "r" (~val));
497 } while (unlikely(!temp));
498}
499
500static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
501 unsigned long change,
502 unsigned long val)
503{
504 unsigned long temp;
505 do {
506 __asm__ __volatile__(
507 " .set mips3 \n"
508 " " __LL "%0, %1 \n"
509 " and %0, %2 \n"
510 " or %0, %3 \n"
511 " " __SC "%0, %1 \n"
512 " .set mips0 \n"
513 : "=&r" (temp), "+m" (*reg)
514 : "r" (~change), "r" (val & change));
515 } while (unlikely(!temp));
516}
517
518#define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
519#define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
520
521/* Cause can be modified asynchronously from hardirq hrtimer callback */
522#define kvm_set_c0_guest_cause(cop0, val) \
523 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
524#define kvm_clear_c0_guest_cause(cop0, val) \
525 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
526#define kvm_change_c0_guest_cause(cop0, change, val) \
527 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
528 change, val)
529
530#define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
531#define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
532#define kvm_change_c0_guest_ebase(cop0, change, val) \
533{ \
534 kvm_clear_c0_guest_ebase(cop0, change); \
535 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
536}
537
538/* Helpers */
539
540static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
541{
542 return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
543 vcpu->fpu_enabled;
544}
545
546static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
547{
548 return kvm_mips_guest_can_have_fpu(vcpu) &&
549 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
550}
551
552static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
553{
554 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
555 vcpu->msa_enabled;
556}
557
558static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
559{
560 return kvm_mips_guest_can_have_msa(vcpu) &&
561 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
562}
563
564struct kvm_mips_callbacks {
565 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
566 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
567 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
568 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
569 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
570 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
571 int (*handle_syscall)(struct kvm_vcpu *vcpu);
572 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
573 int (*handle_break)(struct kvm_vcpu *vcpu);
574 int (*handle_trap)(struct kvm_vcpu *vcpu);
575 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
576 int (*handle_fpe)(struct kvm_vcpu *vcpu);
577 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
578 int (*vm_init)(struct kvm *kvm);
579 int (*vcpu_init)(struct kvm_vcpu *vcpu);
580 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
581 gpa_t (*gva_to_gpa)(gva_t gva);
582 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
583 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
584 void (*queue_io_int)(struct kvm_vcpu *vcpu,
585 struct kvm_mips_interrupt *irq);
586 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
587 struct kvm_mips_interrupt *irq);
588 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
589 uint32_t cause);
590 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
591 uint32_t cause);
592 int (*get_one_reg)(struct kvm_vcpu *vcpu,
593 const struct kvm_one_reg *reg, s64 *v);
594 int (*set_one_reg)(struct kvm_vcpu *vcpu,
595 const struct kvm_one_reg *reg, s64 v);
596 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
597 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
598};
599extern struct kvm_mips_callbacks *kvm_mips_callbacks;
600int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
601
602/* Debug: dump vcpu state */
603int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
604
605/* Trampoline ASM routine to start running in "Guest" context */
606extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
607
608/* FPU/MSA context management */
609void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
610void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
611void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
612void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
613void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
614void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
615void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
616void kvm_own_fpu(struct kvm_vcpu *vcpu);
617void kvm_own_msa(struct kvm_vcpu *vcpu);
618void kvm_drop_fpu(struct kvm_vcpu *vcpu);
619void kvm_lose_fpu(struct kvm_vcpu *vcpu);
620
621/* TLB handling */
622uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
623
624uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
625
626uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
627
628extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
629 struct kvm_vcpu *vcpu);
630
631extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
632 struct kvm_vcpu *vcpu);
633
634extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
635 struct kvm_mips_tlb *tlb,
636 unsigned long *hpa0,
637 unsigned long *hpa1);
638
639extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
640 uint32_t *opc,
641 struct kvm_run *run,
642 struct kvm_vcpu *vcpu);
643
644extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
645 uint32_t *opc,
646 struct kvm_run *run,
647 struct kvm_vcpu *vcpu);
648
649extern void kvm_mips_dump_host_tlbs(void);
650extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
651extern void kvm_mips_flush_host_tlb(int skip_kseg0);
652extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
653
654extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
655 unsigned long entryhi);
656extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
657extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
658 unsigned long gva);
659extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
660 struct kvm_vcpu *vcpu);
661extern void kvm_local_flush_tlb_all(void);
662extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
663extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
664extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
665
666/* Emulation */
667uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
668enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
669
670extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
671 uint32_t *opc,
672 struct kvm_run *run,
673 struct kvm_vcpu *vcpu);
674
675extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
676 uint32_t *opc,
677 struct kvm_run *run,
678 struct kvm_vcpu *vcpu);
679
680extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
681 uint32_t *opc,
682 struct kvm_run *run,
683 struct kvm_vcpu *vcpu);
684
685extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
686 uint32_t *opc,
687 struct kvm_run *run,
688 struct kvm_vcpu *vcpu);
689
690extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
691 uint32_t *opc,
692 struct kvm_run *run,
693 struct kvm_vcpu *vcpu);
694
695extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
696 uint32_t *opc,
697 struct kvm_run *run,
698 struct kvm_vcpu *vcpu);
699
700extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
701 uint32_t *opc,
702 struct kvm_run *run,
703 struct kvm_vcpu *vcpu);
704
705extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
706 uint32_t *opc,
707 struct kvm_run *run,
708 struct kvm_vcpu *vcpu);
709
710extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
711 uint32_t *opc,
712 struct kvm_run *run,
713 struct kvm_vcpu *vcpu);
714
715extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
716 uint32_t *opc,
717 struct kvm_run *run,
718 struct kvm_vcpu *vcpu);
719
720extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
721 uint32_t *opc,
722 struct kvm_run *run,
723 struct kvm_vcpu *vcpu);
724
725extern enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
726 uint32_t *opc,
727 struct kvm_run *run,
728 struct kvm_vcpu *vcpu);
729
730extern enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
731 uint32_t *opc,
732 struct kvm_run *run,
733 struct kvm_vcpu *vcpu);
734
735extern enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
736 uint32_t *opc,
737 struct kvm_run *run,
738 struct kvm_vcpu *vcpu);
739
740extern enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
741 uint32_t *opc,
742 struct kvm_run *run,
743 struct kvm_vcpu *vcpu);
744
745extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
746 struct kvm_run *run);
747
748uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu);
749void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count);
750void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare);
751void kvm_mips_init_count(struct kvm_vcpu *vcpu);
752int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
753int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
754int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
755void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
756void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
757enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
758
759enum emulation_result kvm_mips_check_privilege(unsigned long cause,
760 uint32_t *opc,
761 struct kvm_run *run,
762 struct kvm_vcpu *vcpu);
763
764enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
765 uint32_t *opc,
766 uint32_t cause,
767 struct kvm_run *run,
768 struct kvm_vcpu *vcpu);
769enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
770 uint32_t *opc,
771 uint32_t cause,
772 struct kvm_run *run,
773 struct kvm_vcpu *vcpu);
774enum emulation_result kvm_mips_emulate_store(uint32_t inst,
775 uint32_t cause,
776 struct kvm_run *run,
777 struct kvm_vcpu *vcpu);
778enum emulation_result kvm_mips_emulate_load(uint32_t inst,
779 uint32_t cause,
780 struct kvm_run *run,
781 struct kvm_vcpu *vcpu);
782
783unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
784unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
785unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
786unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
787
788/* Dynamic binary translation */
789extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
790 struct kvm_vcpu *vcpu);
791extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
792 struct kvm_vcpu *vcpu);
793extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
794 struct kvm_vcpu *vcpu);
795extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
796 struct kvm_vcpu *vcpu);
797
798/* Misc */
799extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
800extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
801
802static inline void kvm_arch_hardware_disable(void) {}
803static inline void kvm_arch_hardware_unsetup(void) {}
804static inline void kvm_arch_sync_events(struct kvm *kvm) {}
805static inline void kvm_arch_free_memslot(struct kvm *kvm,
806 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
807static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
808static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
809static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
810 struct kvm_memory_slot *slot) {}
811static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
812static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
813static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
814static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
815
816#endif /* __MIPS_KVM_HOST_H__ */