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1// SPDX-License-Identifier: GPL-2.0
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5 compatible = "brcm,bcm7435";
6
7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 mips-hpt-frequency = <175625000>;
12
13 cpu@0 {
14 compatible = "brcm,bmips5200";
15 device_type = "cpu";
16 reg = <0>;
17 };
18
19 cpu@1 {
20 compatible = "brcm,bmips5200";
21 device_type = "cpu";
22 reg = <1>;
23 };
24
25 cpu@2 {
26 compatible = "brcm,bmips5200";
27 device_type = "cpu";
28 reg = <2>;
29 };
30
31 cpu@3 {
32 compatible = "brcm,bmips5200";
33 device_type = "cpu";
34 reg = <3>;
35 };
36 };
37
38 aliases {
39 uart0 = &uart0;
40 };
41
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
45
46 interrupt-controller;
47 #interrupt-cells = <1>;
48 };
49
50 clocks {
51 uart_clk: uart_clk {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <81000000>;
55 };
56
57 upg_clk: upg_clk {
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <27000000>;
61 };
62 };
63
64 rdb {
65 #address-cells = <1>;
66 #size-cells = <1>;
67
68 compatible = "simple-bus";
69 ranges = <0 0x10000000 0x01000000>;
70
71 periph_intc: interrupt-controller@41b500 {
72 compatible = "brcm,bcm7038-l1-intc";
73 reg = <0x41b500 0x40>, <0x41b600 0x40>,
74 <0x41b700 0x40>, <0x41b800 0x40>;
75
76 interrupt-controller;
77 #interrupt-cells = <1>;
78
79 interrupt-parent = <&cpu_intc>;
80 interrupts = <2>, <3>, <2>, <3>;
81 };
82
83 sun_l2_intc: interrupt-controller@403000 {
84 compatible = "brcm,l2-intc";
85 reg = <0x403000 0x30>;
86 interrupt-controller;
87 #interrupt-cells = <1>;
88 interrupt-parent = <&periph_intc>;
89 interrupts = <52>;
90 };
91
92 gisb-arb@400000 {
93 compatible = "brcm,bcm7435-gisb-arb";
94 reg = <0x400000 0xdc>;
95 native-endian;
96 interrupt-parent = <&sun_l2_intc>;
97 interrupts = <0>, <2>;
98 brcm,gisb-arb-master-mask = <0xf77f>;
99 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0",
100 "pcie_0", "bsp_0",
101 "rdc_0", "raaga_0",
102 "avd_1", "jtag_0",
103 "svd_0", "vice_0",
104 "vice_1", "raaga_1",
105 "scpu";
106 };
107
108 upg_irq0_intc: interrupt-controller@406780 {
109 compatible = "brcm,bcm7120-l2-intc";
110 reg = <0x406780 0x8>;
111
112 brcm,int-map-mask = <0x44>, <0x7000000>;
113 brcm,int-fwd-mask = <0x70000>;
114
115 interrupt-controller;
116 #interrupt-cells = <1>;
117
118 interrupt-parent = <&periph_intc>;
119 interrupts = <60>, <58>;
120 interrupt-names = "upg_main", "upg_bsc";
121 };
122
123 upg_aon_irq0_intc: interrupt-controller@409480 {
124 compatible = "brcm,bcm7120-l2-intc";
125 reg = <0x409480 0x8>;
126
127 brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
128 brcm,int-fwd-mask = <0>;
129 brcm,irq-can-wake;
130
131 interrupt-controller;
132 #interrupt-cells = <1>;
133
134 interrupt-parent = <&periph_intc>;
135 interrupts = <61>, <59>, <64>;
136 interrupt-names = "upg_main_aon", "upg_bsc_aon",
137 "upg_spi";
138 };
139
140 sun_top_ctrl: syscon@404000 {
141 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
142 reg = <0x404000 0x51c>;
143 native-endian;
144 };
145
146 reboot {
147 compatible = "brcm,brcmstb-reboot";
148 syscon = <&sun_top_ctrl 0x304 0x308>;
149 };
150
151 uart0: serial@406b00 {
152 compatible = "ns16550a";
153 reg = <0x406b00 0x20>;
154 reg-io-width = <0x4>;
155 reg-shift = <0x2>;
156 interrupt-parent = <&periph_intc>;
157 interrupts = <66>;
158 clocks = <&uart_clk>;
159 status = "disabled";
160 };
161
162 uart1: serial@406b40 {
163 compatible = "ns16550a";
164 reg = <0x406b40 0x20>;
165 reg-io-width = <0x4>;
166 reg-shift = <0x2>;
167 interrupt-parent = <&periph_intc>;
168 interrupts = <67>;
169 clocks = <&uart_clk>;
170 status = "disabled";
171 };
172
173 uart2: serial@406b80 {
174 compatible = "ns16550a";
175 reg = <0x406b80 0x20>;
176 reg-io-width = <0x4>;
177 reg-shift = <0x2>;
178 interrupt-parent = <&periph_intc>;
179 interrupts = <68>;
180 clocks = <&uart_clk>;
181 status = "disabled";
182 };
183
184 bsca: i2c@406300 {
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
188 reg = <0x406300 0x58>;
189 interrupts = <26>;
190 interrupt-names = "upg_bsca";
191 status = "disabled";
192 };
193
194 bscb: i2c@409400 {
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_aon_irq0_intc>;
198 reg = <0x409400 0x58>;
199 interrupts = <28>;
200 interrupt-names = "upg_bscb";
201 status = "disabled";
202 };
203
204 bscc: i2c@406200 {
205 clock-frequency = <390000>;
206 compatible = "brcm,brcmstb-i2c";
207 interrupt-parent = <&upg_irq0_intc>;
208 reg = <0x406200 0x58>;
209 interrupts = <24>;
210 interrupt-names = "upg_bscc";
211 status = "disabled";
212 };
213
214 bscd: i2c@406280 {
215 clock-frequency = <390000>;
216 compatible = "brcm,brcmstb-i2c";
217 interrupt-parent = <&upg_irq0_intc>;
218 reg = <0x406280 0x58>;
219 interrupts = <25>;
220 interrupt-names = "upg_bscd";
221 status = "disabled";
222 };
223
224 bsce: i2c@409180 {
225 clock-frequency = <390000>;
226 compatible = "brcm,brcmstb-i2c";
227 interrupt-parent = <&upg_aon_irq0_intc>;
228 reg = <0x409180 0x58>;
229 interrupts = <27>;
230 interrupt-names = "upg_bsce";
231 status = "disabled";
232 };
233
234 pwma: pwm@406580 {
235 compatible = "brcm,bcm7038-pwm";
236 reg = <0x406580 0x28>;
237 #pwm-cells = <2>;
238 clocks = <&upg_clk>;
239 status = "disabled";
240 };
241
242 pwmb: pwm@406800 {
243 compatible = "brcm,bcm7038-pwm";
244 reg = <0x406800 0x28>;
245 #pwm-cells = <2>;
246 clocks = <&upg_clk>;
247 status = "disabled";
248 };
249
250 watchdog: watchdog@4067e8 {
251 clocks = <&upg_clk>;
252 compatible = "brcm,bcm7038-wdt";
253 reg = <0x4067e8 0x14>;
254 status = "disabled";
255 };
256
257 aon_pm_l2_intc: interrupt-controller@408440 {
258 compatible = "brcm,l2-intc";
259 reg = <0x408440 0x30>;
260 interrupt-controller;
261 #interrupt-cells = <1>;
262 interrupt-parent = <&periph_intc>;
263 interrupts = <54>;
264 brcm,irq-can-wake;
265 };
266
267 aon_ctrl: syscon@408000 {
268 compatible = "brcm,brcmstb-aon-ctrl";
269 reg = <0x408000 0x100>, <0x408200 0x200>;
270 reg-names = "aon-ctrl", "aon-sram";
271 };
272
273 timers: timer@4067c0 {
274 compatible = "brcm,brcmstb-timers";
275 reg = <0x4067c0 0x40>;
276 };
277
278 upg_gio: gpio@406700 {
279 compatible = "brcm,brcmstb-gpio";
280 reg = <0x406700 0x80>;
281 #gpio-cells = <2>;
282 #interrupt-cells = <2>;
283 gpio-controller;
284 interrupt-controller;
285 interrupt-parent = <&upg_irq0_intc>;
286 interrupts = <6>;
287 brcm,gpio-bank-widths = <32 32 32 21>;
288 };
289
290 upg_gio_aon: gpio@4094c0 {
291 compatible = "brcm,brcmstb-gpio";
292 reg = <0x4094c0 0x40>;
293 #gpio-cells = <2>;
294 #interrupt-cells = <2>;
295 gpio-controller;
296 interrupt-controller;
297 interrupt-parent = <&upg_aon_irq0_intc>;
298 interrupts = <6>;
299 interrupts-extended = <&upg_aon_irq0_intc 6>,
300 <&aon_pm_l2_intc 5>;
301 wakeup-source;
302 brcm,gpio-bank-widths = <18 4>;
303 };
304
305 enet0: ethernet@b80000 {
306 phy-mode = "internal";
307 phy-handle = <&phy1>;
308 mac-address = [ 00 10 18 36 23 1a ];
309 compatible = "brcm,genet-v3";
310 #address-cells = <0x1>;
311 #size-cells = <0x1>;
312 reg = <0xb80000 0x11c88>;
313 interrupts = <17>, <18>;
314 interrupt-parent = <&periph_intc>;
315 status = "disabled";
316
317 mdio@e14 {
318 compatible = "brcm,genet-mdio-v3";
319 #address-cells = <0x1>;
320 #size-cells = <0x0>;
321 reg = <0xe14 0x8>;
322
323 phy1: ethernet-phy@1 {
324 max-speed = <100>;
325 reg = <0x1>;
326 compatible = "brcm,40nm-ephy",
327 "ethernet-phy-ieee802.3-c22";
328 };
329 };
330 };
331
332 ehci0: usb@480300 {
333 compatible = "brcm,bcm7435-ehci", "generic-ehci";
334 reg = <0x480300 0x100>;
335 native-endian;
336 interrupt-parent = <&periph_intc>;
337 interrupts = <70>;
338 status = "disabled";
339 };
340
341 ohci0: usb@480400 {
342 compatible = "brcm,bcm7435-ohci", "generic-ohci";
343 reg = <0x480400 0x100>;
344 native-endian;
345 no-big-frame-no;
346 interrupt-parent = <&periph_intc>;
347 interrupts = <72>;
348 status = "disabled";
349 };
350
351 ehci1: usb@480500 {
352 compatible = "brcm,bcm7435-ehci", "generic-ehci";
353 reg = <0x480500 0x100>;
354 native-endian;
355 interrupt-parent = <&periph_intc>;
356 interrupts = <71>;
357 status = "disabled";
358 };
359
360 ohci1: usb@480600 {
361 compatible = "brcm,bcm7435-ohci", "generic-ohci";
362 reg = <0x480600 0x100>;
363 native-endian;
364 no-big-frame-no;
365 interrupt-parent = <&periph_intc>;
366 interrupts = <73>;
367 status = "disabled";
368 };
369
370 ehci2: usb@490300 {
371 compatible = "brcm,bcm7435-ehci", "generic-ehci";
372 reg = <0x490300 0x100>;
373 native-endian;
374 interrupt-parent = <&periph_intc>;
375 interrupts = <75>;
376 status = "disabled";
377 };
378
379 ohci2: usb@490400 {
380 compatible = "brcm,bcm7435-ohci", "generic-ohci";
381 reg = <0x490400 0x100>;
382 native-endian;
383 no-big-frame-no;
384 interrupt-parent = <&periph_intc>;
385 interrupts = <77>;
386 status = "disabled";
387 };
388
389 ehci3: usb@490500 {
390 compatible = "brcm,bcm7435-ehci", "generic-ehci";
391 reg = <0x490500 0x100>;
392 native-endian;
393 interrupt-parent = <&periph_intc>;
394 interrupts = <76>;
395 status = "disabled";
396 };
397
398 ohci3: usb@490600 {
399 compatible = "brcm,bcm7435-ohci", "generic-ohci";
400 reg = <0x490600 0x100>;
401 native-endian;
402 no-big-frame-no;
403 interrupt-parent = <&periph_intc>;
404 interrupts = <78>;
405 status = "disabled";
406 };
407
408 hif_l2_intc: interrupt-controller@41b000 {
409 compatible = "brcm,l2-intc";
410 reg = <0x41b000 0x30>;
411 interrupt-controller;
412 #interrupt-cells = <1>;
413 interrupt-parent = <&periph_intc>;
414 interrupts = <24>;
415 };
416
417 nand: nand@41c800 {
418 compatible = "brcm,brcmnand-v6.2", "brcm,brcmnand";
419 #address-cells = <1>;
420 #size-cells = <0>;
421 reg-names = "nand", "flash-dma";
422 reg = <0x41c800 0x600>, <0x41d000 0x100>;
423 interrupt-parent = <&hif_l2_intc>;
424 interrupts = <24>, <4>;
425 interrupt-names = "nand_ctlrdy", "flash_dma_done";
426 status = "disabled";
427 };
428
429 sata: sata@181000 {
430 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
431 reg-names = "ahci", "top-ctrl";
432 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
433 interrupt-parent = <&periph_intc>;
434 interrupts = <45>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 status = "disabled";
438
439 sata0: sata-port@0 {
440 reg = <0>;
441 phys = <&sata_phy0>;
442 };
443
444 sata1: sata-port@1 {
445 reg = <1>;
446 phys = <&sata_phy1>;
447 };
448 };
449
450 sata_phy: sata-phy@180100 {
451 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
452 reg = <0x180100 0x0eff>;
453 reg-names = "phy";
454 #address-cells = <1>;
455 #size-cells = <0>;
456 status = "disabled";
457
458 sata_phy0: sata-phy@0 {
459 reg = <0>;
460 #phy-cells = <0>;
461 };
462
463 sata_phy1: sata-phy@1 {
464 reg = <1>;
465 #phy-cells = <0>;
466 };
467 };
468
469 sdhci0: sdhci@41a000 {
470 compatible = "brcm,bcm7425-sdhci";
471 reg = <0x41a000 0x100>;
472 interrupt-parent = <&periph_intc>;
473 interrupts = <47>;
474 sd-uhs-sdr50;
475 mmc-hs200-1_8v;
476 status = "disabled";
477 };
478
479 sdhci1: sdhci@41a200 {
480 compatible = "brcm,bcm7425-sdhci";
481 reg = <0x41a200 0x100>;
482 interrupt-parent = <&periph_intc>;
483 interrupts = <48>;
484 sd-uhs-sdr50;
485 mmc-hs200-1_8v;
486 status = "disabled";
487 };
488
489 spi_l2_intc: interrupt-controller@41bd00 {
490 compatible = "brcm,l2-intc";
491 reg = <0x41bd00 0x30>;
492 interrupt-controller;
493 #interrupt-cells = <1>;
494 interrupt-parent = <&periph_intc>;
495 interrupts = <25>;
496 };
497
498 qspi: spi@41d200 {
499 #address-cells = <0x1>;
500 #size-cells = <0x0>;
501 compatible = "brcm,spi-bcm-qspi",
502 "brcm,spi-brcmstb-qspi";
503 clocks = <&upg_clk>;
504 reg = <0x41a920 0x4 0x41d400 0x188 0x41d200 0x50>;
505 reg-names = "cs_reg", "hif_mspi", "bspi";
506 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
507 interrupt-parent = <&spi_l2_intc>;
508 interrupt-names = "spi_lr_fullness_reached",
509 "spi_lr_session_aborted",
510 "spi_lr_impatient",
511 "spi_lr_session_done",
512 "spi_lr_overread",
513 "mspi_done",
514 "mspi_halted";
515 status = "disabled";
516 };
517
518 mspi: spi@409200 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "brcm,spi-bcm-qspi",
522 "brcm,spi-brcmstb-mspi";
523 clocks = <&upg_clk>;
524 reg = <0x409200 0x180>;
525 reg-names = "mspi";
526 interrupts = <0x14>;
527 interrupt-parent = <&upg_aon_irq0_intc>;
528 interrupt-names = "mspi_done";
529 status = "disabled";
530 };
531
532 waketimer: waketimer@409580 {
533 compatible = "brcm,brcmstb-waketimer";
534 reg = <0x409580 0x14>;
535 interrupts = <0x3>;
536 interrupt-parent = <&aon_pm_l2_intc>;
537 interrupt-names = "timer";
538 clocks = <&upg_clk>;
539 status = "disabled";
540 };
541 };
542
543 memory_controllers {
544 compatible = "simple-bus";
545 ranges = <0x0 0x103b0000 0x1a000>;
546 #address-cells = <1>;
547 #size-cells = <1>;
548
549 memory-controller@0 {
550 compatible = "brcm,brcmstb-memc", "simple-bus";
551 ranges = <0x0 0x0 0xa000>;
552 #address-cells = <1>;
553 #size-cells = <1>;
554
555 memc-arb@1000 {
556 compatible = "brcm,brcmstb-memc-arb";
557 reg = <0x1000 0x248>;
558 };
559
560 memc-ddr@2000 {
561 compatible = "brcm,brcmstb-memc-ddr";
562 reg = <0x2000 0x300>;
563 };
564
565 ddr-phy@6000 {
566 compatible = "brcm,brcmstb-ddr-phy";
567 reg = <0x6000 0xc8>;
568 };
569
570 shimphy@8000 {
571 compatible = "brcm,brcmstb-ddr-shimphy";
572 reg = <0x8000 0x13c>;
573 };
574 };
575
576 memory-controller@1 {
577 compatible = "brcm,brcmstb-memc", "simple-bus";
578 ranges = <0x0 0x10000 0xa000>;
579 #address-cells = <1>;
580 #size-cells = <1>;
581
582 memc-arb@1000 {
583 compatible = "brcm,brcmstb-memc-arb";
584 reg = <0x1000 0x248>;
585 };
586
587 memc-ddr@2000 {
588 compatible = "brcm,brcmstb-memc-ddr";
589 reg = <0x2000 0x300>;
590 };
591
592 ddr-phy@6000 {
593 compatible = "brcm,brcmstb-ddr-phy";
594 reg = <0x6000 0xc8>;
595 };
596
597 shimphy@8000 {
598 compatible = "brcm,brcmstb-ddr-shimphy";
599 reg = <0x8000 0x13c>;
600 };
601 };
602 };
603
604 pcie_0: pcie@8b20000 {
605 status = "disabled";
606 compatible = "brcm,bcm7435-pcie";
607
608 ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
609 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
610 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
611 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
612
613 reg = <0x10410000 0x19310>;
614 aspm-no-l0s;
615 device_type = "pci";
616 msi-controller;
617 msi-parent = <&pcie_0>;
618 #address-cells = <0x3>;
619 #size-cells = <0x2>;
620 bus-range = <0x0 0xff>;
621 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
622 linux,pci-domain = <0x0>;
623
624 interrupt-parent = <&periph_intc>;
625 interrupts = <39>, <39>;
626 interrupt-names = "pcie", "msi";
627 #interrupt-cells = <0x1>;
628 interrupt-map = <0 0 0 1 &periph_intc 0x23
629 0 0 0 1 &periph_intc 0x24
630 0 0 0 1 &periph_intc 0x25
631 0 0 0 1 &periph_intc 0x26>;
632 };
633};
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7435";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 mips-hpt-frequency = <163125000>;
11
12 cpu@0 {
13 compatible = "brcm,bmips5200";
14 device_type = "cpu";
15 reg = <0>;
16 };
17
18 cpu@1 {
19 compatible = "brcm,bmips5200";
20 device_type = "cpu";
21 reg = <1>;
22 };
23
24 cpu@2 {
25 compatible = "brcm,bmips5200";
26 device_type = "cpu";
27 reg = <2>;
28 };
29
30 cpu@3 {
31 compatible = "brcm,bmips5200";
32 device_type = "cpu";
33 reg = <3>;
34 };
35 };
36
37 aliases {
38 uart0 = &uart0;
39 };
40
41 cpu_intc: cpu_intc {
42 #address-cells = <0>;
43 compatible = "mti,cpu-interrupt-controller";
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47 };
48
49 clocks {
50 uart_clk: uart_clk {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <81000000>;
54 };
55 };
56
57 rdb {
58 #address-cells = <1>;
59 #size-cells = <1>;
60
61 compatible = "simple-bus";
62 ranges = <0 0x10000000 0x01000000>;
63
64 periph_intc: periph_intc@41b500 {
65 compatible = "brcm,bcm7038-l1-intc";
66 reg = <0x41b500 0x40>, <0x41b600 0x40>;
67
68 interrupt-controller;
69 #interrupt-cells = <1>;
70
71 interrupt-parent = <&cpu_intc>;
72 interrupts = <2>, <3>;
73 };
74
75 sun_l2_intc: sun_l2_intc@403000 {
76 compatible = "brcm,l2-intc";
77 reg = <0x403000 0x30>;
78 interrupt-controller;
79 #interrupt-cells = <1>;
80 interrupt-parent = <&periph_intc>;
81 interrupts = <52>;
82 };
83
84 gisb-arb@400000 {
85 compatible = "brcm,bcm7435-gisb-arb";
86 reg = <0x400000 0xdc>;
87 native-endian;
88 interrupt-parent = <&sun_l2_intc>;
89 interrupts = <0>, <2>;
90 brcm,gisb-arb-master-mask = <0xf77f>;
91 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "webcpu_0",
92 "pcie_0", "bsp_0",
93 "rdc_0", "raaga_0",
94 "avd_1", "jtag_0",
95 "svd_0", "vice_0",
96 "vice_1", "raaga_1",
97 "scpu";
98 };
99
100 upg_irq0_intc: upg_irq0_intc@406780 {
101 compatible = "brcm,bcm7120-l2-intc";
102 reg = <0x406780 0x8>;
103
104 brcm,int-map-mask = <0x44>;
105 brcm,int-fwd-mask = <0x70000>;
106
107 interrupt-controller;
108 #interrupt-cells = <1>;
109
110 interrupt-parent = <&periph_intc>;
111 interrupts = <60>;
112 };
113
114 sun_top_ctrl: syscon@404000 {
115 compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
116 reg = <0x404000 0x51c>;
117 native-endian;
118 };
119
120 reboot {
121 compatible = "brcm,brcmstb-reboot";
122 syscon = <&sun_top_ctrl 0x304 0x308>;
123 };
124
125 uart0: serial@406b00 {
126 compatible = "ns16550a";
127 reg = <0x406b00 0x20>;
128 reg-io-width = <0x4>;
129 reg-shift = <0x2>;
130 interrupt-parent = <&periph_intc>;
131 interrupts = <66>;
132 clocks = <&uart_clk>;
133 status = "disabled";
134 };
135
136 enet0: ethernet@b80000 {
137 phy-mode = "internal";
138 phy-handle = <&phy1>;
139 mac-address = [ 00 10 18 36 23 1a ];
140 compatible = "brcm,genet-v3";
141 #address-cells = <0x1>;
142 #size-cells = <0x1>;
143 reg = <0xb80000 0x11c88>;
144 interrupts = <17>, <18>;
145 interrupt-parent = <&periph_intc>;
146 status = "disabled";
147
148 mdio@e14 {
149 compatible = "brcm,genet-mdio-v3";
150 #address-cells = <0x1>;
151 #size-cells = <0x0>;
152 reg = <0xe14 0x8>;
153
154 phy1: ethernet-phy@1 {
155 max-speed = <100>;
156 reg = <0x1>;
157 compatible = "brcm,40nm-ephy",
158 "ethernet-phy-ieee802.3-c22";
159 };
160 };
161 };
162
163 ehci0: usb@480300 {
164 compatible = "brcm,bcm7435-ehci", "generic-ehci";
165 reg = <0x480300 0x100>;
166 native-endian;
167 interrupt-parent = <&periph_intc>;
168 interrupts = <70>;
169 status = "disabled";
170 };
171
172 ohci0: usb@480400 {
173 compatible = "brcm,bcm7435-ohci", "generic-ohci";
174 reg = <0x480400 0x100>;
175 native-endian;
176 no-big-frame-no;
177 interrupt-parent = <&periph_intc>;
178 interrupts = <72>;
179 status = "disabled";
180 };
181
182 ehci1: usb@480500 {
183 compatible = "brcm,bcm7435-ehci", "generic-ehci";
184 reg = <0x480500 0x100>;
185 native-endian;
186 interrupt-parent = <&periph_intc>;
187 interrupts = <71>;
188 status = "disabled";
189 };
190
191 ohci1: usb@480600 {
192 compatible = "brcm,bcm7435-ohci", "generic-ohci";
193 reg = <0x480600 0x100>;
194 native-endian;
195 no-big-frame-no;
196 interrupt-parent = <&periph_intc>;
197 interrupts = <73>;
198 status = "disabled";
199 };
200
201 ehci2: usb@490300 {
202 compatible = "brcm,bcm7435-ehci", "generic-ehci";
203 reg = <0x490300 0x100>;
204 native-endian;
205 interrupt-parent = <&periph_intc>;
206 interrupts = <75>;
207 status = "disabled";
208 };
209
210 ohci2: usb@490400 {
211 compatible = "brcm,bcm7435-ohci", "generic-ohci";
212 reg = <0x490400 0x100>;
213 native-endian;
214 no-big-frame-no;
215 interrupt-parent = <&periph_intc>;
216 interrupts = <77>;
217 status = "disabled";
218 };
219
220 ehci3: usb@490500 {
221 compatible = "brcm,bcm7435-ehci", "generic-ehci";
222 reg = <0x490500 0x100>;
223 native-endian;
224 interrupt-parent = <&periph_intc>;
225 interrupts = <76>;
226 status = "disabled";
227 };
228
229 ohci3: usb@490600 {
230 compatible = "brcm,bcm7435-ohci", "generic-ohci";
231 reg = <0x490600 0x100>;
232 native-endian;
233 no-big-frame-no;
234 interrupt-parent = <&periph_intc>;
235 interrupts = <78>;
236 status = "disabled";
237 };
238 };
239};