1/*
  2 * stmark2.c -- Support for Sysam AMCORE open board
  3 *
  4 * (C) Copyright 2017, Angelo Dureghello <angelo@sysam.it>
  5 *
  6 * This file is subject to the terms and conditions of the GNU General Public
  7 * License.  See the file COPYING in the main directory of this archive
  8 * for more details.
  9 */
 10
 11#include <linux/platform_device.h>
 12#include <linux/mtd/partitions.h>
 13#include <linux/spi/spi.h>
 14#include <linux/spi/spi-fsl-dspi.h>
 15#include <linux/spi/flash.h>
 16#include <linux/dma-mapping.h>
 17#include <asm/mcfsim.h>
 18
 19/*
 20 * Partitioning of parallel NOR flash (39VF3201B)
 21 */
 22static struct mtd_partition stmark2_partitions[] = {
 23	{
 24		.name = "U-Boot (1024K)",
 25		.size = 0x100000,
 26		.offset = 0x0
 27	}, {
 28		.name = "Kernel+initramfs (7168K)",
 29		.size = 0x700000,
 30		.offset = MTDPART_OFS_APPEND
 31	}, {
 32		.name = "Flash Free Space (8192K)",
 33		.size = MTDPART_SIZ_FULL,
 34		.offset = MTDPART_OFS_APPEND
 35	}
 36};
 37
 38static struct flash_platform_data stmark2_spi_flash_data = {
 39	.name = "is25lp128",
 40	.parts = stmark2_partitions,
 41	.nr_parts = ARRAY_SIZE(stmark2_partitions),
 42	.type = "is25lp128",
 43};
 44
 45static struct spi_board_info stmark2_board_info[] __initdata = {
 46	{
 47		.modalias = "m25p80",
 48		.max_speed_hz = 5000000,
 49		.bus_num = 0,
 50		.chip_select = 1,
 51		.platform_data = &stmark2_spi_flash_data,
 52		.mode = SPI_MODE_3,
 53	}
 54};
 55
 56/* SPI controller data, SPI (0) */
 57static struct fsl_dspi_platform_data dspi_spi0_info = {
 58	.cs_num = 4,
 59	.bus_num = 0,
 60	.sck_cs_delay = 100,
 61	.cs_sck_delay = 100,
 62};
 63
 64static struct resource dspi_spi0_resource[] = {
 65	[0] = {
 66		.start = MCFDSPI_BASE0,
 67		.end   = MCFDSPI_BASE0 + 0xFF,
 68		.flags = IORESOURCE_MEM,
 69		},
 70	[1] = {
 71		.start = 12,
 72		.end   = 13,
 73		.flags = IORESOURCE_DMA,
 74	},
 75	[2] = {
 76		.start = MCF_IRQ_DSPI0,
 77		.end   = MCF_IRQ_DSPI0,
 78		.flags = IORESOURCE_IRQ,
 79	},
 80};
 81
 82static u64 stmark2_dspi_mask = DMA_BIT_MASK(32);
 83
 84/* SPI controller, id = bus number */
 85static struct platform_device dspi_spi0_device = {
 86	.name = "fsl-dspi",
 87	.id = 0,
 88	.num_resources = ARRAY_SIZE(dspi_spi0_resource),
 89	.resource = dspi_spi0_resource,
 90	.dev = {
 91		.platform_data = &dspi_spi0_info,
 92		.dma_mask = &stmark2_dspi_mask,
 93		.coherent_dma_mask = DMA_BIT_MASK(32),
 94	},
 95};
 96
 97static struct platform_device *stmark2_devices[] __initdata = {
 98	&dspi_spi0_device,
 99};
100
101/*
102 * Note: proper pin-mux setup is mandatory for proper SPI functionality.
103 */
104static int __init init_stmark2(void)
105{
106	/* DSPI0, all pins as DSPI, and using CS1 */
107	__raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL);
108	__raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH);
109
110	/* Board gpio setup */
111	__raw_writeb(0x00, MCFGPIO_PAR_BE);
112	__raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
113	__raw_writeb(0x00, MCFGPIO_PAR_CS);
114
115	/* CAN pads */
116	__raw_writeb(0x50, MCFGPIO_PAR_CANI2C);
117
118	platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices));
119
120	spi_register_board_info(stmark2_board_info,
121				ARRAY_SIZE(stmark2_board_info));
122
123	return 0;
124}
125
126device_initcall(init_stmark2);