1// SPDX-License-Identifier: GPL-2.0
 2/***************************************************************************/
 3
 4/*
 5 *	525x.c  -- platform support for ColdFire 525x based boards
 6 *
 7 *	Copyright (C) 2012, Steven King <sfking@fdwdc.com>
 8 */
 9
10/***************************************************************************/
11
12#include <linux/clkdev.h>
13#include <linux/kernel.h>
14#include <linux/param.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <asm/machdep.h>
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfclk.h>
22
23/***************************************************************************/
24
25DEFINE_CLK(pll, "pll.0", MCF_CLK);
26DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
27
28static struct clk_lookup m525x_clk_lookup[] = {
29	CLKDEV_INIT(NULL, "pll.0", &clk_pll),
30	CLKDEV_INIT(NULL, "sys.0", &clk_sys),
31	CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
32	CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
33	CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
34	CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
35	CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
36	CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
37	CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
 
 
 
 
38};
39
40/***************************************************************************/
41
42static void __init m525x_qspi_init(void)
43{
44#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
45	/* set the GPIO function for the qspi cs gpios */
46	/* FIXME: replace with pinmux/pinctl support */
47	u32 f = readl(MCFSIM2_GPIOFUNC);
48	f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
49	writel(f, MCFSIM2_GPIOFUNC);
50
51	/* QSPI irq setup */
52	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
53	       MCFSIM_QSPIICR);
54	mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
55#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
56}
57
58static void __init m525x_i2c_init(void)
59{
60#if IS_ENABLED(CONFIG_I2C_IMX)
61	u32 r;
62
63	/* first I2C controller uses regular irq setup */
64	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
65	       MCFSIM_I2CICR);
66	mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
67
68	/* second I2C controller is completely different */
69	r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
70	r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
71	r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
72	writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
73#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
74}
75
76/***************************************************************************/
77
78void __init config_BSP(char *commandp, int size)
79{
80	mach_sched_init = hw_timer_init;
81
82	m525x_qspi_init();
83	m525x_i2c_init();
84
85	clkdev_add_table(m525x_clk_lookup, ARRAY_SIZE(m525x_clk_lookup));
86}
87
88/***************************************************************************/

 
 1/***************************************************************************/
 2
 3/*
 4 *	525x.c  -- platform support for ColdFire 525x based boards
 5 *
 6 *	Copyright (C) 2012, Steven King <sfking@fdwdc.com>
 7 */
 8
 9/***************************************************************************/
10
 
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/mcfclk.h>
20
21/***************************************************************************/
22
23DEFINE_CLK(pll, "pll.0", MCF_CLK);
24DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
30
31struct clk *mcf_clks[] = {
32	&clk_pll,
33	&clk_sys,
34	&clk_mcftmr0,
35	&clk_mcftmr1,
36	&clk_mcfuart0,
37	&clk_mcfuart1,
38	&clk_mcfqspi0,
39	NULL
40};
41
42/***************************************************************************/
43
44static void __init m525x_qspi_init(void)
45{
46#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
47	/* set the GPIO function for the qspi cs gpios */
48	/* FIXME: replace with pinmux/pinctl support */
49	u32 f = readl(MCFSIM2_GPIOFUNC);
50	f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
51	writel(f, MCFSIM2_GPIOFUNC);
52
53	/* QSPI irq setup */
54	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
55	       MCFSIM_QSPIICR);
56	mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
57#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
58}
59
60static void __init m525x_i2c_init(void)
61{
62#if IS_ENABLED(CONFIG_I2C_COLDFIRE)
63	u32 r;
64
65	/* first I2C controller uses regular irq setup */
66	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
67		MCFSIM_I2CICR);
68	mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
69
70	/* second I2C controller is completely different */
71	r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
72	r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
73	r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
74	writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
75#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
76}
77
78/***************************************************************************/
79
80void __init config_BSP(char *commandp, int size)
81{
82	mach_sched_init = hw_timer_init;
83
84	m525x_qspi_init();
85	m525x_i2c_init();
 
 
86}
87
88/***************************************************************************/