1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Device Tree Source for AM6 SoC family in Quad core configuration
  4 *
  5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
  6 */
  7
  8#include "k3-am65.dtsi"
  9
 10/ {
 11	cpus {
 12		#address-cells = <1>;
 13		#size-cells = <0>;
 14		cpu-map {
 15			cluster0: cluster0 {
 16				core0 {
 17					cpu = <&cpu0>;
 18				};
 19
 20				core1 {
 21					cpu = <&cpu1>;
 22				};
 23			};
 24
 25			cluster1: cluster1 {
 26				core0 {
 27					cpu = <&cpu2>;
 28				};
 29
 30				core1 {
 31					cpu = <&cpu3>;
 32				};
 33			};
 34		};
 35
 36		cpu0: cpu@0 {
 37			compatible = "arm,cortex-a53";
 38			reg = <0x000>;
 39			device_type = "cpu";
 40			enable-method = "psci";
 41			i-cache-size = <0x8000>;
 42			i-cache-line-size = <64>;
 43			i-cache-sets = <256>;
 44			d-cache-size = <0x8000>;
 45			d-cache-line-size = <64>;
 46			d-cache-sets = <128>;
 47			next-level-cache = <&L2_0>;
 48		};
 49
 50		cpu1: cpu@1 {
 51			compatible = "arm,cortex-a53";
 52			reg = <0x001>;
 53			device_type = "cpu";
 54			enable-method = "psci";
 55			i-cache-size = <0x8000>;
 56			i-cache-line-size = <64>;
 57			i-cache-sets = <256>;
 58			d-cache-size = <0x8000>;
 59			d-cache-line-size = <64>;
 60			d-cache-sets = <128>;
 61			next-level-cache = <&L2_0>;
 62		};
 63
 64		cpu2: cpu@100 {
 65			compatible = "arm,cortex-a53";
 66			reg = <0x100>;
 67			device_type = "cpu";
 68			enable-method = "psci";
 69			i-cache-size = <0x8000>;
 70			i-cache-line-size = <64>;
 71			i-cache-sets = <256>;
 72			d-cache-size = <0x8000>;
 73			d-cache-line-size = <64>;
 74			d-cache-sets = <128>;
 75			next-level-cache = <&L2_1>;
 76		};
 77
 78		cpu3: cpu@101 {
 79			compatible = "arm,cortex-a53";
 80			reg = <0x101>;
 81			device_type = "cpu";
 82			enable-method = "psci";
 83			i-cache-size = <0x8000>;
 84			i-cache-line-size = <64>;
 85			i-cache-sets = <256>;
 86			d-cache-size = <0x8000>;
 87			d-cache-line-size = <64>;
 88			d-cache-sets = <128>;
 89			next-level-cache = <&L2_1>;
 90		};
 91	};
 92
 93	L2_0: l2-cache0 {
 94		compatible = "cache";
 95		cache-level = <2>;
 96		cache-unified;
 97		cache-size = <0x80000>;
 98		cache-line-size = <64>;
 99		cache-sets = <512>;
100		next-level-cache = <&msmc_l3>;
101	};
102
103	L2_1: l2-cache1 {
104		compatible = "cache";
105		cache-level = <2>;
106		cache-unified;
107		cache-size = <0x80000>;
108		cache-line-size = <64>;
109		cache-sets = <512>;
110		next-level-cache = <&msmc_l3>;
111	};
112
113	msmc_l3: l3-cache0 {
114		compatible = "cache";
115		cache-level = <3>;
116		cache-unified;
117	};
118
119	thermal_zones: thermal-zones {
120		#include "k3-am654-industrial-thermal.dtsi"
121	};
122};