1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
  4 * Copyright 2016-2018 NXP
  5 */
  6
  7#include <dt-bindings/interrupt-controller/arm-gic.h>
  8
  9/memreserve/ 0x80000000 0x00010000;
 10
 11/ {
 12	compatible = "fsl,s32v234";
 13	interrupt-parent = <&gic>;
 14	#address-cells = <2>;
 15	#size-cells = <2>;
 16
 17	aliases {
 18		serial0 = &uart0;
 19		serial1 = &uart1;
 20	};
 21
 22	cpus {
 23		#address-cells = <2>;
 24		#size-cells = <0>;
 25
 26		cpu0: cpu@0 {
 27			device_type = "cpu";
 28			compatible = "arm,cortex-a53";
 29			reg = <0x0 0x0>;
 30			enable-method = "spin-table";
 31			cpu-release-addr = <0x0 0x80000000>;
 32			next-level-cache = <&cluster0_l2_cache>;
 33		};
 34
 35		cpu1: cpu@1 {
 36			device_type = "cpu";
 37			compatible = "arm,cortex-a53";
 38			reg = <0x0 0x1>;
 39			enable-method = "spin-table";
 40			cpu-release-addr = <0x0 0x80000000>;
 41			next-level-cache = <&cluster0_l2_cache>;
 42		};
 43
 44		cpu2: cpu@100 {
 45			device_type = "cpu";
 46			compatible = "arm,cortex-a53";
 47			reg = <0x0 0x100>;
 48			enable-method = "spin-table";
 49			cpu-release-addr = <0x0 0x80000000>;
 50			next-level-cache = <&cluster1_l2_cache>;
 51		};
 52
 53		cpu3: cpu@101 {
 54			device_type = "cpu";
 55			compatible = "arm,cortex-a53";
 56			reg = <0x0 0x101>;
 57			enable-method = "spin-table";
 58			cpu-release-addr = <0x0 0x80000000>;
 59			next-level-cache = <&cluster1_l2_cache>;
 60		};
 61
 62		cluster0_l2_cache: l2-cache0 {
 63			compatible = "cache";
 64			cache-level = <2>;
 65			cache-unified;
 66		};
 67
 68		cluster1_l2_cache: l2-cache1 {
 69			compatible = "cache";
 70			cache-level = <2>;
 71			cache-unified;
 72		};
 73	};
 74
 75	timer {
 76		compatible = "arm,armv8-timer";
 77		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
 78					  IRQ_TYPE_LEVEL_LOW)>,
 79			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
 80					  IRQ_TYPE_LEVEL_LOW)>,
 81			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
 82					  IRQ_TYPE_LEVEL_LOW)>,
 83			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
 84					  IRQ_TYPE_LEVEL_LOW)>;
 85		/* clock-frequency might be modified by u-boot, depending on the
 86		 * chip version.
 87		 */
 88		clock-frequency = <10000000>;
 89	};
 90
 91	gic: interrupt-controller@7d001000 {
 92		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 93		#interrupt-cells = <3>;
 94		#address-cells = <0>;
 95		interrupt-controller;
 96		reg = <0 0x7d001000 0 0x1000>,
 97		      <0 0x7d002000 0 0x2000>,
 98		      <0 0x7d004000 0 0x2000>,
 99		      <0 0x7d006000 0 0x2000>;
100		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
101					 IRQ_TYPE_LEVEL_HIGH)>;
102	};
103
104	soc {
105		#address-cells = <2>;
106		#size-cells = <2>;
107		compatible = "simple-bus";
108		interrupt-parent = <&gic>;
109		ranges;
110
111		aips0: bus@40000000 {
112			compatible = "simple-bus";
113			#address-cells = <2>;
114			#size-cells = <2>;
115			interrupt-parent = <&gic>;
116			reg = <0x0 0x40000000 0x0 0x7d000>;
117			ranges;
118
119			uart0: serial@40053000 {
120				compatible = "fsl,s32v234-linflexuart";
121				reg = <0x0 0x40053000 0x0 0x1000>;
122				interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
123				status = "disabled";
124			};
125		};
126
127		aips1: bus@40080000 {
128			compatible = "simple-bus";
129			#address-cells = <2>;
130			#size-cells = <2>;
131			interrupt-parent = <&gic>;
132			reg = <0x0 0x40080000 0x0 0x70000>;
133			ranges;
134
135			uart1: serial@400bc000 {
136				compatible = "fsl,s32v234-linflexuart";
137				reg = <0x0 0x400bc000 0x0 0x1000>;
138				interrupts = <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>;
139				status = "disabled";
140			};
141		};
142	};
143};