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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Device Tree Include file for Layerscape-LX2160A family SoC.
4//
5// Copyright 2018-2020 NXP
6
7#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/thermal/thermal.h>
11
12/memreserve/ 0x80000000 0x00010000;
13
14/ {
15 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 rtc1 = &ftm_alarm0;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 // 8 clusters having 2 Cortex-A72 cores each
29 cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
36 d-cache-line-size = <64>;
37 d-cache-sets = <128>;
38 i-cache-size = <0xC000>;
39 i-cache-line-size = <64>;
40 i-cache-sets = <192>;
41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>;
44 };
45
46 cpu1: cpu@1 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 reg = <0x1>;
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
53 d-cache-line-size = <64>;
54 d-cache-sets = <128>;
55 i-cache-size = <0xC000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <192>;
58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>;
61 };
62
63 cpu100: cpu@100 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a72";
66 enable-method = "psci";
67 reg = <0x100>;
68 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
69 d-cache-size = <0x8000>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 i-cache-size = <0xC000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <192>;
75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>;
78 };
79
80 cpu101: cpu@101 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a72";
83 enable-method = "psci";
84 reg = <0x101>;
85 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
86 d-cache-size = <0x8000>;
87 d-cache-line-size = <64>;
88 d-cache-sets = <128>;
89 i-cache-size = <0xC000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <192>;
92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>;
95 };
96
97 cpu200: cpu@200 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a72";
100 enable-method = "psci";
101 reg = <0x200>;
102 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
103 d-cache-size = <0x8000>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <192>;
109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>;
112 };
113
114 cpu201: cpu@201 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a72";
117 enable-method = "psci";
118 reg = <0x201>;
119 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
120 d-cache-size = <0x8000>;
121 d-cache-line-size = <64>;
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <192>;
126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>;
129 };
130
131 cpu300: cpu@300 {
132 device_type = "cpu";
133 compatible = "arm,cortex-a72";
134 enable-method = "psci";
135 reg = <0x300>;
136 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
137 d-cache-size = <0x8000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>;
146 };
147
148 cpu301: cpu@301 {
149 device_type = "cpu";
150 compatible = "arm,cortex-a72";
151 enable-method = "psci";
152 reg = <0x301>;
153 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
154 d-cache-size = <0x8000>;
155 d-cache-line-size = <64>;
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <192>;
160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>;
163 };
164
165 cpu400: cpu@400 {
166 device_type = "cpu";
167 compatible = "arm,cortex-a72";
168 enable-method = "psci";
169 reg = <0x400>;
170 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000>;
175 i-cache-line-size = <64>;
176 i-cache-sets = <192>;
177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>;
180 };
181
182 cpu401: cpu@401 {
183 device_type = "cpu";
184 compatible = "arm,cortex-a72";
185 enable-method = "psci";
186 reg = <0x401>;
187 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
188 d-cache-size = <0x8000>;
189 d-cache-line-size = <64>;
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000>;
192 i-cache-line-size = <64>;
193 i-cache-sets = <192>;
194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>;
197 };
198
199 cpu500: cpu@500 {
200 device_type = "cpu";
201 compatible = "arm,cortex-a72";
202 enable-method = "psci";
203 reg = <0x500>;
204 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
205 d-cache-size = <0x8000>;
206 d-cache-line-size = <64>;
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000>;
209 i-cache-line-size = <64>;
210 i-cache-sets = <192>;
211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>;
214 };
215
216 cpu501: cpu@501 {
217 device_type = "cpu";
218 compatible = "arm,cortex-a72";
219 enable-method = "psci";
220 reg = <0x501>;
221 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
222 d-cache-size = <0x8000>;
223 d-cache-line-size = <64>;
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000>;
226 i-cache-line-size = <64>;
227 i-cache-sets = <192>;
228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>;
231 };
232
233 cpu600: cpu@600 {
234 device_type = "cpu";
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
237 reg = <0x600>;
238 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>;
248 };
249
250 cpu601: cpu@601 {
251 device_type = "cpu";
252 compatible = "arm,cortex-a72";
253 enable-method = "psci";
254 reg = <0x601>;
255 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
256 d-cache-size = <0x8000>;
257 d-cache-line-size = <64>;
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000>;
260 i-cache-line-size = <64>;
261 i-cache-sets = <192>;
262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>;
265 };
266
267 cpu700: cpu@700 {
268 device_type = "cpu";
269 compatible = "arm,cortex-a72";
270 enable-method = "psci";
271 reg = <0x700>;
272 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
273 d-cache-size = <0x8000>;
274 d-cache-line-size = <64>;
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000>;
277 i-cache-line-size = <64>;
278 i-cache-sets = <192>;
279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>;
282 };
283
284 cpu701: cpu@701 {
285 device_type = "cpu";
286 compatible = "arm,cortex-a72";
287 enable-method = "psci";
288 reg = <0x701>;
289 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
290 d-cache-size = <0x8000>;
291 d-cache-line-size = <64>;
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000>;
294 i-cache-line-size = <64>;
295 i-cache-sets = <192>;
296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>;
299 };
300
301 cluster0_l2: l2-cache0 {
302 compatible = "cache";
303 cache-unified;
304 cache-size = <0x100000>;
305 cache-line-size = <64>;
306 cache-sets = <1024>;
307 cache-level = <2>;
308 };
309
310 cluster1_l2: l2-cache1 {
311 compatible = "cache";
312 cache-unified;
313 cache-size = <0x100000>;
314 cache-line-size = <64>;
315 cache-sets = <1024>;
316 cache-level = <2>;
317 };
318
319 cluster2_l2: l2-cache2 {
320 compatible = "cache";
321 cache-unified;
322 cache-size = <0x100000>;
323 cache-line-size = <64>;
324 cache-sets = <1024>;
325 cache-level = <2>;
326 };
327
328 cluster3_l2: l2-cache3 {
329 compatible = "cache";
330 cache-unified;
331 cache-size = <0x100000>;
332 cache-line-size = <64>;
333 cache-sets = <1024>;
334 cache-level = <2>;
335 };
336
337 cluster4_l2: l2-cache4 {
338 compatible = "cache";
339 cache-unified;
340 cache-size = <0x100000>;
341 cache-line-size = <64>;
342 cache-sets = <1024>;
343 cache-level = <2>;
344 };
345
346 cluster5_l2: l2-cache5 {
347 compatible = "cache";
348 cache-unified;
349 cache-size = <0x100000>;
350 cache-line-size = <64>;
351 cache-sets = <1024>;
352 cache-level = <2>;
353 };
354
355 cluster6_l2: l2-cache6 {
356 compatible = "cache";
357 cache-unified;
358 cache-size = <0x100000>;
359 cache-line-size = <64>;
360 cache-sets = <1024>;
361 cache-level = <2>;
362 };
363
364 cluster7_l2: l2-cache7 {
365 compatible = "cache";
366 cache-unified;
367 cache-size = <0x100000>;
368 cache-line-size = <64>;
369 cache-sets = <1024>;
370 cache-level = <2>;
371 };
372
373 cpu_pw15: cpu-pw15 {
374 compatible = "arm,idle-state";
375 idle-state-name = "PW15";
376 arm,psci-suspend-param = <0x0>;
377 entry-latency-us = <2000>;
378 exit-latency-us = <2000>;
379 min-residency-us = <6000>;
380 };
381 };
382
383 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3";
385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
387 // SGI_base)
388 <0x0 0x0c0c0000 0 0x2000>, // GICC
389 <0x0 0x0c0d0000 0 0x1000>, // GICH
390 <0x0 0x0c0e0000 0 0x20000>; // GICV
391 #interrupt-cells = <3>;
392 #address-cells = <2>;
393 #size-cells = <2>;
394 ranges;
395 interrupt-controller;
396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
397
398 its: msi-controller@6020000 {
399 compatible = "arm,gic-v3-its";
400 msi-controller;
401 reg = <0x0 0x6020000 0 0x20000>;
402 };
403 };
404
405 timer {
406 compatible = "arm,armv8-timer";
407 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
411 };
412
413 pmu {
414 compatible = "arm,cortex-a72-pmu";
415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
416 };
417
418 psci {
419 compatible = "arm,psci-0.2";
420 method = "smc";
421 };
422
423 memory@80000000 {
424 // DRAM space - 1, size : 2 GB DRAM
425 device_type = "memory";
426 reg = <0x00000000 0x80000000 0 0x80000000>;
427 };
428
429 ddr1: memory-controller@1080000 {
430 compatible = "fsl,qoriq-memory-controller";
431 reg = <0x0 0x1080000 0x0 0x1000>;
432 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
433 little-endian;
434 };
435
436 ddr2: memory-controller@1090000 {
437 compatible = "fsl,qoriq-memory-controller";
438 reg = <0x0 0x1090000 0x0 0x1000>;
439 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
440 little-endian;
441 };
442
443 // One clock unit-sysclk node which bootloader require during DT fix-up
444 sysclk: sysclk {
445 compatible = "fixed-clock";
446 #clock-cells = <0>;
447 clock-frequency = <100000000>; // fixed up by bootloader
448 clock-output-names = "sysclk";
449 };
450
451 thermal-zones {
452 cluster6-7 {
453 polling-delay-passive = <1000>;
454 polling-delay = <5000>;
455 thermal-sensors = <&tmu 0>;
456
457 trips {
458 cluster6_7_alert: cluster6-7-alert {
459 temperature = <85000>;
460 hysteresis = <2000>;
461 type = "passive";
462 };
463
464 cluster6_7_crit: cluster6-7-crit {
465 temperature = <95000>;
466 hysteresis = <2000>;
467 type = "critical";
468 };
469 };
470
471 cooling-maps {
472 map0 {
473 trip = <&cluster6_7_alert>;
474 cooling-device =
475 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
476 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
477 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
478 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
479 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
480 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
481 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
482 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
483 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
484 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
485 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
486 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
487 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
488 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
489 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
490 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
491 };
492 };
493 };
494
495 ddr-cluster5 {
496 polling-delay-passive = <1000>;
497 polling-delay = <5000>;
498 thermal-sensors = <&tmu 1>;
499
500 trips {
501 ddr-cluster5-alert {
502 temperature = <85000>;
503 hysteresis = <2000>;
504 type = "passive";
505 };
506
507 ddr-cluster5-crit {
508 temperature = <95000>;
509 hysteresis = <2000>;
510 type = "critical";
511 };
512 };
513 };
514
515 wriop {
516 polling-delay-passive = <1000>;
517 polling-delay = <5000>;
518 thermal-sensors = <&tmu 2>;
519
520 trips {
521 wriop-alert {
522 temperature = <85000>;
523 hysteresis = <2000>;
524 type = "passive";
525 };
526
527 wriop-crit {
528 temperature = <95000>;
529 hysteresis = <2000>;
530 type = "critical";
531 };
532 };
533 };
534
535 dce-qbman-hsio2 {
536 polling-delay-passive = <1000>;
537 polling-delay = <5000>;
538 thermal-sensors = <&tmu 3>;
539
540 trips {
541 dce-qbman-alert {
542 temperature = <85000>;
543 hysteresis = <2000>;
544 type = "passive";
545 };
546
547 dce-qbman-crit {
548 temperature = <95000>;
549 hysteresis = <2000>;
550 type = "critical";
551 };
552 };
553 };
554
555 ccn-dpaa-tbu {
556 polling-delay-passive = <1000>;
557 polling-delay = <5000>;
558 thermal-sensors = <&tmu 4>;
559
560 trips {
561 ccn-dpaa-alert {
562 temperature = <85000>;
563 hysteresis = <2000>;
564 type = "passive";
565 };
566
567 ccn-dpaa-crit {
568 temperature = <95000>;
569 hysteresis = <2000>;
570 type = "critical";
571 };
572 };
573 };
574
575 cluster4-hsio3 {
576 polling-delay-passive = <1000>;
577 polling-delay = <5000>;
578 thermal-sensors = <&tmu 5>;
579
580 trips {
581 clust4-hsio3-alert {
582 temperature = <85000>;
583 hysteresis = <2000>;
584 type = "passive";
585 };
586
587 clust4-hsio3-crit {
588 temperature = <95000>;
589 hysteresis = <2000>;
590 type = "critical";
591 };
592 };
593 };
594
595 cluster2-3 {
596 polling-delay-passive = <1000>;
597 polling-delay = <5000>;
598 thermal-sensors = <&tmu 6>;
599
600 trips {
601 cluster2-3-alert {
602 temperature = <85000>;
603 hysteresis = <2000>;
604 type = "passive";
605 };
606
607 cluster2-3-crit {
608 temperature = <95000>;
609 hysteresis = <2000>;
610 type = "critical";
611 };
612 };
613 };
614 };
615
616 soc {
617 compatible = "simple-bus";
618 #address-cells = <2>;
619 #size-cells = <2>;
620 ranges;
621 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
622
623 serdes_1: phy@1ea0000 {
624 compatible = "fsl,lynx-28g";
625 reg = <0x0 0x1ea0000 0x0 0x1e30>;
626 #phy-cells = <1>;
627 };
628
629 serdes_2: phy@1eb0000 {
630 compatible = "fsl,lynx-28g";
631 reg = <0x0 0x1eb0000 0x0 0x1e30>;
632 #phy-cells = <1>;
633 status = "disabled";
634 };
635
636 crypto: crypto@8000000 {
637 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
638 fsl,sec-era = <10>;
639 #address-cells = <1>;
640 #size-cells = <1>;
641 ranges = <0x0 0x00 0x8000000 0x100000>;
642 reg = <0x00 0x8000000 0x0 0x100000>;
643 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
644 dma-coherent;
645 status = "disabled";
646
647 sec_jr0: jr@10000 {
648 compatible = "fsl,sec-v5.0-job-ring",
649 "fsl,sec-v4.0-job-ring";
650 reg = <0x10000 0x10000>;
651 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
652 };
653
654 sec_jr1: jr@20000 {
655 compatible = "fsl,sec-v5.0-job-ring",
656 "fsl,sec-v4.0-job-ring";
657 reg = <0x20000 0x10000>;
658 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
659 };
660
661 sec_jr2: jr@30000 {
662 compatible = "fsl,sec-v5.0-job-ring",
663 "fsl,sec-v4.0-job-ring";
664 reg = <0x30000 0x10000>;
665 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
666 };
667
668 sec_jr3: jr@40000 {
669 compatible = "fsl,sec-v5.0-job-ring",
670 "fsl,sec-v4.0-job-ring";
671 reg = <0x40000 0x10000>;
672 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
673 };
674 };
675
676 clockgen: clock-controller@1300000 {
677 compatible = "fsl,lx2160a-clockgen";
678 reg = <0 0x1300000 0 0xa0000>;
679 #clock-cells = <2>;
680 clocks = <&sysclk>;
681 };
682
683 dcfg: syscon@1e00000 {
684 compatible = "fsl,lx2160a-dcfg", "syscon";
685 reg = <0x0 0x1e00000 0x0 0x10000>;
686 little-endian;
687 };
688
689 sfp: efuse@1e80000 {
690 compatible = "fsl,ls1028a-sfp";
691 reg = <0x0 0x1e80000 0x0 0x10000>;
692 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
693 QORIQ_CLK_PLL_DIV(4)>;
694 clock-names = "sfp";
695 };
696
697 isc: syscon@1f70000 {
698 compatible = "fsl,lx2160a-isc", "syscon";
699 reg = <0x0 0x1f70000 0x0 0x10000>;
700 little-endian;
701 #address-cells = <1>;
702 #size-cells = <1>;
703 ranges = <0x0 0x0 0x1f70000 0x10000>;
704
705 extirq: interrupt-controller@14 {
706 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
707 #interrupt-cells = <2>;
708 #address-cells = <0>;
709 interrupt-controller;
710 reg = <0x14 4>;
711 interrupt-map =
712 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
713 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
714 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
715 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
716 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
717 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
718 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
719 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
720 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
721 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
722 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
723 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-map-mask = <0xf 0x0>;
725 };
726 };
727
728 tmu: tmu@1f80000 {
729 compatible = "fsl,qoriq-tmu";
730 reg = <0x0 0x1f80000 0x0 0x10000>;
731 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
732 fsl,tmu-range = <0x800000e6 0x8001017d>;
733 fsl,tmu-calibration =
734 /* Calibration data group 1 */
735 <0x00000000 0x00000035>,
736 /* Calibration data group 2 */
737 <0x00000001 0x00000154>;
738 little-endian;
739 #thermal-sensor-cells = <1>;
740 };
741
742 i2c0: i2c@2000000 {
743 compatible = "fsl,vf610-i2c";
744 #address-cells = <1>;
745 #size-cells = <0>;
746 reg = <0x0 0x2000000 0x0 0x10000>;
747 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
748 clock-names = "i2c";
749 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
750 QORIQ_CLK_PLL_DIV(16)>;
751 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
752 status = "disabled";
753 };
754
755 i2c1: i2c@2010000 {
756 compatible = "fsl,vf610-i2c";
757 #address-cells = <1>;
758 #size-cells = <0>;
759 reg = <0x0 0x2010000 0x0 0x10000>;
760 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
761 clock-names = "i2c";
762 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
763 QORIQ_CLK_PLL_DIV(16)>;
764 status = "disabled";
765 };
766
767 i2c2: i2c@2020000 {
768 compatible = "fsl,vf610-i2c";
769 #address-cells = <1>;
770 #size-cells = <0>;
771 reg = <0x0 0x2020000 0x0 0x10000>;
772 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
773 clock-names = "i2c";
774 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
775 QORIQ_CLK_PLL_DIV(16)>;
776 status = "disabled";
777 };
778
779 i2c3: i2c@2030000 {
780 compatible = "fsl,vf610-i2c";
781 #address-cells = <1>;
782 #size-cells = <0>;
783 reg = <0x0 0x2030000 0x0 0x10000>;
784 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
785 clock-names = "i2c";
786 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
787 QORIQ_CLK_PLL_DIV(16)>;
788 status = "disabled";
789 };
790
791 i2c4: i2c@2040000 {
792 compatible = "fsl,vf610-i2c";
793 #address-cells = <1>;
794 #size-cells = <0>;
795 reg = <0x0 0x2040000 0x0 0x10000>;
796 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
797 clock-names = "i2c";
798 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
799 QORIQ_CLK_PLL_DIV(16)>;
800 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
801 status = "disabled";
802 };
803
804 i2c5: i2c@2050000 {
805 compatible = "fsl,vf610-i2c";
806 #address-cells = <1>;
807 #size-cells = <0>;
808 reg = <0x0 0x2050000 0x0 0x10000>;
809 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
810 clock-names = "i2c";
811 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
812 QORIQ_CLK_PLL_DIV(16)>;
813 status = "disabled";
814 };
815
816 i2c6: i2c@2060000 {
817 compatible = "fsl,vf610-i2c";
818 #address-cells = <1>;
819 #size-cells = <0>;
820 reg = <0x0 0x2060000 0x0 0x10000>;
821 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
822 clock-names = "i2c";
823 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
824 QORIQ_CLK_PLL_DIV(16)>;
825 status = "disabled";
826 };
827
828 i2c7: i2c@2070000 {
829 compatible = "fsl,vf610-i2c";
830 #address-cells = <1>;
831 #size-cells = <0>;
832 reg = <0x0 0x2070000 0x0 0x10000>;
833 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
834 clock-names = "i2c";
835 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
836 QORIQ_CLK_PLL_DIV(16)>;
837 status = "disabled";
838 };
839
840 fspi: spi@20c0000 {
841 compatible = "nxp,lx2160a-fspi";
842 #address-cells = <1>;
843 #size-cells = <0>;
844 reg = <0x0 0x20c0000 0x0 0x10000>,
845 <0x0 0x20000000 0x0 0x10000000>;
846 reg-names = "fspi_base", "fspi_mmap";
847 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
849 QORIQ_CLK_PLL_DIV(4)>,
850 <&clockgen QORIQ_CLK_PLATFORM_PLL
851 QORIQ_CLK_PLL_DIV(4)>;
852 clock-names = "fspi_en", "fspi";
853 status = "disabled";
854 };
855
856 dspi0: spi@2100000 {
857 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
858 #address-cells = <1>;
859 #size-cells = <0>;
860 reg = <0x0 0x2100000 0x0 0x10000>;
861 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
863 QORIQ_CLK_PLL_DIV(8)>;
864 clock-names = "dspi";
865 spi-num-chipselects = <5>;
866 bus-num = <0>;
867 status = "disabled";
868 };
869
870 dspi1: spi@2110000 {
871 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
872 #address-cells = <1>;
873 #size-cells = <0>;
874 reg = <0x0 0x2110000 0x0 0x10000>;
875 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
877 QORIQ_CLK_PLL_DIV(8)>;
878 clock-names = "dspi";
879 spi-num-chipselects = <5>;
880 bus-num = <1>;
881 status = "disabled";
882 };
883
884 dspi2: spi@2120000 {
885 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
886 #address-cells = <1>;
887 #size-cells = <0>;
888 reg = <0x0 0x2120000 0x0 0x10000>;
889 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
890 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
891 QORIQ_CLK_PLL_DIV(8)>;
892 clock-names = "dspi";
893 spi-num-chipselects = <5>;
894 bus-num = <2>;
895 status = "disabled";
896 };
897
898 esdhc0: esdhc@2140000 {
899 compatible = "fsl,esdhc";
900 reg = <0x0 0x2140000 0x0 0x10000>;
901 interrupts = <0 28 0x4>; /* Level high type */
902 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
903 QORIQ_CLK_PLL_DIV(2)>;
904 dma-coherent;
905 voltage-ranges = <1800 1800 3300 3300>;
906 sdhci,auto-cmd12;
907 little-endian;
908 bus-width = <4>;
909 status = "disabled";
910 };
911
912 esdhc1: esdhc@2150000 {
913 compatible = "fsl,esdhc";
914 reg = <0x0 0x2150000 0x0 0x10000>;
915 interrupts = <0 63 0x4>; /* Level high type */
916 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
917 QORIQ_CLK_PLL_DIV(2)>;
918 dma-coherent;
919 voltage-ranges = <1800 1800 3300 3300>;
920 sdhci,auto-cmd12;
921 broken-cd;
922 little-endian;
923 bus-width = <4>;
924 status = "disabled";
925 };
926
927 can0: can@2180000 {
928 compatible = "fsl,lx2160ar1-flexcan";
929 reg = <0x0 0x2180000 0x0 0x10000>;
930 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
932 QORIQ_CLK_PLL_DIV(8)>,
933 <&clockgen QORIQ_CLK_SYSCLK 0>;
934 clock-names = "ipg", "per";
935 fsl,clk-source = /bits/ 8 <0>;
936 status = "disabled";
937 };
938
939 can1: can@2190000 {
940 compatible = "fsl,lx2160ar1-flexcan";
941 reg = <0x0 0x2190000 0x0 0x10000>;
942 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
944 QORIQ_CLK_PLL_DIV(8)>,
945 <&clockgen QORIQ_CLK_SYSCLK 0>;
946 clock-names = "ipg", "per";
947 fsl,clk-source = /bits/ 8 <0>;
948 status = "disabled";
949 };
950
951 uart0: serial@21c0000 {
952 compatible = "arm,sbsa-uart","arm,pl011";
953 reg = <0x0 0x21c0000 0x0 0x1000>;
954 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
955 current-speed = <115200>;
956 status = "disabled";
957 };
958
959 uart1: serial@21d0000 {
960 compatible = "arm,sbsa-uart","arm,pl011";
961 reg = <0x0 0x21d0000 0x0 0x1000>;
962 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
963 current-speed = <115200>;
964 status = "disabled";
965 };
966
967 uart2: serial@21e0000 {
968 compatible = "arm,sbsa-uart","arm,pl011";
969 reg = <0x0 0x21e0000 0x0 0x1000>;
970 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
971 current-speed = <115200>;
972 status = "disabled";
973 };
974
975 uart3: serial@21f0000 {
976 compatible = "arm,sbsa-uart","arm,pl011";
977 reg = <0x0 0x21f0000 0x0 0x1000>;
978 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
979 current-speed = <115200>;
980 status = "disabled";
981 };
982
983 gpio0: gpio@2300000 {
984 compatible = "fsl,qoriq-gpio";
985 reg = <0x0 0x2300000 0x0 0x10000>;
986 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
987 gpio-controller;
988 little-endian;
989 #gpio-cells = <2>;
990 interrupt-controller;
991 #interrupt-cells = <2>;
992 };
993
994 gpio1: gpio@2310000 {
995 compatible = "fsl,qoriq-gpio";
996 reg = <0x0 0x2310000 0x0 0x10000>;
997 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
998 gpio-controller;
999 little-endian;
1000 #gpio-cells = <2>;
1001 interrupt-controller;
1002 #interrupt-cells = <2>;
1003 };
1004
1005 gpio2: gpio@2320000 {
1006 compatible = "fsl,qoriq-gpio";
1007 reg = <0x0 0x2320000 0x0 0x10000>;
1008 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1009 gpio-controller;
1010 little-endian;
1011 #gpio-cells = <2>;
1012 interrupt-controller;
1013 #interrupt-cells = <2>;
1014 };
1015
1016 gpio3: gpio@2330000 {
1017 compatible = "fsl,qoriq-gpio";
1018 reg = <0x0 0x2330000 0x0 0x10000>;
1019 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1020 gpio-controller;
1021 little-endian;
1022 #gpio-cells = <2>;
1023 interrupt-controller;
1024 #interrupt-cells = <2>;
1025 };
1026
1027 watchdog@23a0000 {
1028 compatible = "arm,sbsa-gwdt";
1029 reg = <0x0 0x23a0000 0 0x1000>,
1030 <0x0 0x2390000 0 0x1000>;
1031 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1032 timeout-sec = <30>;
1033 };
1034
1035 rcpm: power-controller@1e34040 {
1036 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1037 reg = <0x0 0x1e34040 0x0 0x1c>;
1038 #fsl,rcpm-wakeup-cells = <7>;
1039 little-endian;
1040 };
1041
1042 ftm_alarm0: timer@2800000 {
1043 compatible = "fsl,lx2160a-ftm-alarm";
1044 reg = <0x0 0x2800000 0x0 0x10000>;
1045 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1046 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1047 };
1048
1049 usb0: usb@3100000 {
1050 compatible = "snps,dwc3";
1051 reg = <0x0 0x3100000 0x0 0x10000>;
1052 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1053 dr_mode = "host";
1054 snps,quirk-frame-length-adjustment = <0x20>;
1055 usb3-lpm-capable;
1056 snps,dis_rxdet_inp3_quirk;
1057 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1058 status = "disabled";
1059 };
1060
1061 usb1: usb@3110000 {
1062 compatible = "snps,dwc3";
1063 reg = <0x0 0x3110000 0x0 0x10000>;
1064 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1065 dr_mode = "host";
1066 snps,quirk-frame-length-adjustment = <0x20>;
1067 usb3-lpm-capable;
1068 snps,dis_rxdet_inp3_quirk;
1069 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1070 status = "disabled";
1071 };
1072
1073 sata0: sata@3200000 {
1074 compatible = "fsl,lx2160a-ahci";
1075 reg = <0x0 0x3200000 0x0 0x10000>,
1076 <0x7 0x100520 0x0 0x4>;
1077 reg-names = "ahci", "sata-ecc";
1078 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1080 QORIQ_CLK_PLL_DIV(4)>;
1081 dma-coherent;
1082 status = "disabled";
1083 };
1084
1085 sata1: sata@3210000 {
1086 compatible = "fsl,lx2160a-ahci";
1087 reg = <0x0 0x3210000 0x0 0x10000>,
1088 <0x7 0x100520 0x0 0x4>;
1089 reg-names = "ahci", "sata-ecc";
1090 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1092 QORIQ_CLK_PLL_DIV(4)>;
1093 dma-coherent;
1094 status = "disabled";
1095 };
1096
1097 sata2: sata@3220000 {
1098 compatible = "fsl,lx2160a-ahci";
1099 reg = <0x0 0x3220000 0x0 0x10000>,
1100 <0x7 0x100520 0x0 0x4>;
1101 reg-names = "ahci", "sata-ecc";
1102 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1104 QORIQ_CLK_PLL_DIV(4)>;
1105 dma-coherent;
1106 status = "disabled";
1107 };
1108
1109 sata3: sata@3230000 {
1110 compatible = "fsl,lx2160a-ahci";
1111 reg = <0x0 0x3230000 0x0 0x10000>,
1112 <0x7 0x100520 0x0 0x4>;
1113 reg-names = "ahci", "sata-ecc";
1114 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1115 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1116 QORIQ_CLK_PLL_DIV(4)>;
1117 dma-coherent;
1118 status = "disabled";
1119 };
1120
1121 pcie1: pcie@3400000 {
1122 compatible = "fsl,lx2160a-pcie";
1123 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
1124 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1125 reg-names = "csr_axi_slave", "config_axi_slave";
1126 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1127 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1128 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1129 interrupt-names = "aer", "pme", "intr";
1130 #address-cells = <3>;
1131 #size-cells = <2>;
1132 device_type = "pci";
1133 dma-coherent;
1134 apio-wins = <8>;
1135 ppio-wins = <8>;
1136 bus-range = <0x0 0xff>;
1137 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1138 msi-parent = <&its>;
1139 #interrupt-cells = <1>;
1140 interrupt-map-mask = <0 0 0 7>;
1141 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1142 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1143 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1144 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1145 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1146 status = "disabled";
1147 };
1148
1149 pcie2: pcie@3500000 {
1150 compatible = "fsl,lx2160a-pcie";
1151 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
1152 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1153 reg-names = "csr_axi_slave", "config_axi_slave";
1154 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1155 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1156 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1157 interrupt-names = "aer", "pme", "intr";
1158 #address-cells = <3>;
1159 #size-cells = <2>;
1160 device_type = "pci";
1161 dma-coherent;
1162 apio-wins = <8>;
1163 ppio-wins = <8>;
1164 bus-range = <0x0 0xff>;
1165 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1166 msi-parent = <&its>;
1167 #interrupt-cells = <1>;
1168 interrupt-map-mask = <0 0 0 7>;
1169 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1170 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1171 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1172 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1173 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1174 status = "disabled";
1175 };
1176
1177 pcie3: pcie@3600000 {
1178 compatible = "fsl,lx2160a-pcie";
1179 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
1180 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1181 reg-names = "csr_axi_slave", "config_axi_slave";
1182 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1183 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1184 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1185 interrupt-names = "aer", "pme", "intr";
1186 #address-cells = <3>;
1187 #size-cells = <2>;
1188 device_type = "pci";
1189 dma-coherent;
1190 apio-wins = <256>;
1191 ppio-wins = <24>;
1192 bus-range = <0x0 0xff>;
1193 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1194 msi-parent = <&its>;
1195 #interrupt-cells = <1>;
1196 interrupt-map-mask = <0 0 0 7>;
1197 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1198 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1199 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1200 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1201 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1202 status = "disabled";
1203 };
1204
1205 pcie4: pcie@3700000 {
1206 compatible = "fsl,lx2160a-pcie";
1207 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
1208 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1209 reg-names = "csr_axi_slave", "config_axi_slave";
1210 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1211 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1212 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1213 interrupt-names = "aer", "pme", "intr";
1214 #address-cells = <3>;
1215 #size-cells = <2>;
1216 device_type = "pci";
1217 dma-coherent;
1218 apio-wins = <8>;
1219 ppio-wins = <8>;
1220 bus-range = <0x0 0xff>;
1221 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1222 msi-parent = <&its>;
1223 #interrupt-cells = <1>;
1224 interrupt-map-mask = <0 0 0 7>;
1225 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1226 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1227 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1228 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1229 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1230 status = "disabled";
1231 };
1232
1233 pcie5: pcie@3800000 {
1234 compatible = "fsl,lx2160a-pcie";
1235 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
1236 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1237 reg-names = "csr_axi_slave", "config_axi_slave";
1238 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1239 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1240 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1241 interrupt-names = "aer", "pme", "intr";
1242 #address-cells = <3>;
1243 #size-cells = <2>;
1244 device_type = "pci";
1245 dma-coherent;
1246 apio-wins = <256>;
1247 ppio-wins = <24>;
1248 bus-range = <0x0 0xff>;
1249 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1250 msi-parent = <&its>;
1251 #interrupt-cells = <1>;
1252 interrupt-map-mask = <0 0 0 7>;
1253 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1254 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1255 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1256 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1257 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1258 status = "disabled";
1259 };
1260
1261 pcie6: pcie@3900000 {
1262 compatible = "fsl,lx2160a-pcie";
1263 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
1264 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1265 reg-names = "csr_axi_slave", "config_axi_slave";
1266 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1267 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1268 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1269 interrupt-names = "aer", "pme", "intr";
1270 #address-cells = <3>;
1271 #size-cells = <2>;
1272 device_type = "pci";
1273 dma-coherent;
1274 apio-wins = <8>;
1275 ppio-wins = <8>;
1276 bus-range = <0x0 0xff>;
1277 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1278 msi-parent = <&its>;
1279 #interrupt-cells = <1>;
1280 interrupt-map-mask = <0 0 0 7>;
1281 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1282 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1283 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1284 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1285 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1286 status = "disabled";
1287 };
1288
1289 smmu: iommu@5000000 {
1290 compatible = "arm,mmu-500";
1291 reg = <0 0x5000000 0 0x800000>;
1292 #iommu-cells = <1>;
1293 #global-interrupts = <14>;
1294 // global secure fault
1295 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1296 // combined secure
1297 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1298 // global non-secure fault
1299 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1300 // combined non-secure
1301 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1302 // performance counter interrupts 0-9
1303 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1305 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1306 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1307 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1308 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1309 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1310 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1312 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1313 // per context interrupt, 64 interrupts
1314 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1315 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1316 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1320 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1322 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1323 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1326 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1327 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1328 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1329 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1378 dma-coherent;
1379 };
1380
1381 console@8340020 {
1382 compatible = "fsl,dpaa2-console";
1383 reg = <0x00000000 0x08340020 0 0x2>;
1384 };
1385
1386 ptp-timer@8b95000 {
1387 compatible = "fsl,dpaa2-ptp";
1388 reg = <0x0 0x8b95000 0x0 0x100>;
1389 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1390 QORIQ_CLK_PLL_DIV(2)>;
1391 little-endian;
1392 fsl,extts-fifo;
1393 };
1394
1395 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1396 emdio1: mdio@8b96000 {
1397 compatible = "fsl,fman-memac-mdio";
1398 reg = <0x0 0x8b96000 0x0 0x1000>;
1399 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1400 #address-cells = <1>;
1401 #size-cells = <0>;
1402 little-endian;
1403 clock-frequency = <2500000>;
1404 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1405 QORIQ_CLK_PLL_DIV(2)>;
1406 status = "disabled";
1407 };
1408
1409 emdio2: mdio@8b97000 {
1410 compatible = "fsl,fman-memac-mdio";
1411 reg = <0x0 0x8b97000 0x0 0x1000>;
1412 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1413 little-endian;
1414 #address-cells = <1>;
1415 #size-cells = <0>;
1416 clock-frequency = <2500000>;
1417 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1418 QORIQ_CLK_PLL_DIV(2)>;
1419 status = "disabled";
1420 };
1421
1422 pcs_mdio1: mdio@8c07000 {
1423 compatible = "fsl,fman-memac-mdio";
1424 reg = <0x0 0x8c07000 0x0 0x1000>;
1425 little-endian;
1426 #address-cells = <1>;
1427 #size-cells = <0>;
1428 status = "disabled";
1429
1430 pcs1: ethernet-phy@0 {
1431 reg = <0>;
1432 };
1433 };
1434
1435 pcs_mdio2: mdio@8c0b000 {
1436 compatible = "fsl,fman-memac-mdio";
1437 reg = <0x0 0x8c0b000 0x0 0x1000>;
1438 little-endian;
1439 #address-cells = <1>;
1440 #size-cells = <0>;
1441 status = "disabled";
1442
1443 pcs2: ethernet-phy@0 {
1444 reg = <0>;
1445 };
1446 };
1447
1448 pcs_mdio3: mdio@8c0f000 {
1449 compatible = "fsl,fman-memac-mdio";
1450 reg = <0x0 0x8c0f000 0x0 0x1000>;
1451 little-endian;
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1454 status = "disabled";
1455
1456 pcs3: ethernet-phy@0 {
1457 reg = <0>;
1458 };
1459 };
1460
1461 pcs_mdio4: mdio@8c13000 {
1462 compatible = "fsl,fman-memac-mdio";
1463 reg = <0x0 0x8c13000 0x0 0x1000>;
1464 little-endian;
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1467 status = "disabled";
1468
1469 pcs4: ethernet-phy@0 {
1470 reg = <0>;
1471 };
1472 };
1473
1474 pcs_mdio5: mdio@8c17000 {
1475 compatible = "fsl,fman-memac-mdio";
1476 reg = <0x0 0x8c17000 0x0 0x1000>;
1477 little-endian;
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1480 status = "disabled";
1481
1482 pcs5: ethernet-phy@0 {
1483 reg = <0>;
1484 };
1485 };
1486
1487 pcs_mdio6: mdio@8c1b000 {
1488 compatible = "fsl,fman-memac-mdio";
1489 reg = <0x0 0x8c1b000 0x0 0x1000>;
1490 little-endian;
1491 #address-cells = <1>;
1492 #size-cells = <0>;
1493 status = "disabled";
1494
1495 pcs6: ethernet-phy@0 {
1496 reg = <0>;
1497 };
1498 };
1499
1500 pcs_mdio7: mdio@8c1f000 {
1501 compatible = "fsl,fman-memac-mdio";
1502 reg = <0x0 0x8c1f000 0x0 0x1000>;
1503 little-endian;
1504 #address-cells = <1>;
1505 #size-cells = <0>;
1506 status = "disabled";
1507
1508 pcs7: ethernet-phy@0 {
1509 reg = <0>;
1510 };
1511 };
1512
1513 pcs_mdio8: mdio@8c23000 {
1514 compatible = "fsl,fman-memac-mdio";
1515 reg = <0x0 0x8c23000 0x0 0x1000>;
1516 little-endian;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 status = "disabled";
1520
1521 pcs8: ethernet-phy@0 {
1522 reg = <0>;
1523 };
1524 };
1525
1526 pcs_mdio9: mdio@8c27000 {
1527 compatible = "fsl,fman-memac-mdio";
1528 reg = <0x0 0x8c27000 0x0 0x1000>;
1529 little-endian;
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1532 status = "disabled";
1533
1534 pcs9: ethernet-phy@0 {
1535 reg = <0>;
1536 };
1537 };
1538
1539 pcs_mdio10: mdio@8c2b000 {
1540 compatible = "fsl,fman-memac-mdio";
1541 reg = <0x0 0x8c2b000 0x0 0x1000>;
1542 little-endian;
1543 #address-cells = <1>;
1544 #size-cells = <0>;
1545 status = "disabled";
1546
1547 pcs10: ethernet-phy@0 {
1548 reg = <0>;
1549 };
1550 };
1551
1552 pcs_mdio11: mdio@8c2f000 {
1553 compatible = "fsl,fman-memac-mdio";
1554 reg = <0x0 0x8c2f000 0x0 0x1000>;
1555 little-endian;
1556 #address-cells = <1>;
1557 #size-cells = <0>;
1558 status = "disabled";
1559
1560 pcs11: ethernet-phy@0 {
1561 reg = <0>;
1562 };
1563 };
1564
1565 pcs_mdio12: mdio@8c33000 {
1566 compatible = "fsl,fman-memac-mdio";
1567 reg = <0x0 0x8c33000 0x0 0x1000>;
1568 little-endian;
1569 #address-cells = <1>;
1570 #size-cells = <0>;
1571 status = "disabled";
1572
1573 pcs12: ethernet-phy@0 {
1574 reg = <0>;
1575 };
1576 };
1577
1578 pcs_mdio13: mdio@8c37000 {
1579 compatible = "fsl,fman-memac-mdio";
1580 reg = <0x0 0x8c37000 0x0 0x1000>;
1581 little-endian;
1582 #address-cells = <1>;
1583 #size-cells = <0>;
1584 status = "disabled";
1585
1586 pcs13: ethernet-phy@0 {
1587 reg = <0>;
1588 };
1589 };
1590
1591 pcs_mdio14: mdio@8c3b000 {
1592 compatible = "fsl,fman-memac-mdio";
1593 reg = <0x0 0x8c3b000 0x0 0x1000>;
1594 little-endian;
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1597 status = "disabled";
1598
1599 pcs14: ethernet-phy@0 {
1600 reg = <0>;
1601 };
1602 };
1603
1604 pcs_mdio15: mdio@8c3f000 {
1605 compatible = "fsl,fman-memac-mdio";
1606 reg = <0x0 0x8c3f000 0x0 0x1000>;
1607 little-endian;
1608 #address-cells = <1>;
1609 #size-cells = <0>;
1610 status = "disabled";
1611
1612 pcs15: ethernet-phy@0 {
1613 reg = <0>;
1614 };
1615 };
1616
1617 pcs_mdio16: mdio@8c43000 {
1618 compatible = "fsl,fman-memac-mdio";
1619 reg = <0x0 0x8c43000 0x0 0x1000>;
1620 little-endian;
1621 #address-cells = <1>;
1622 #size-cells = <0>;
1623 status = "disabled";
1624
1625 pcs16: ethernet-phy@0 {
1626 reg = <0>;
1627 };
1628 };
1629
1630 pcs_mdio17: mdio@8c47000 {
1631 compatible = "fsl,fman-memac-mdio";
1632 reg = <0x0 0x8c47000 0x0 0x1000>;
1633 little-endian;
1634 #address-cells = <1>;
1635 #size-cells = <0>;
1636 status = "disabled";
1637
1638 pcs17: ethernet-phy@0 {
1639 reg = <0>;
1640 };
1641 };
1642
1643 pcs_mdio18: mdio@8c4b000 {
1644 compatible = "fsl,fman-memac-mdio";
1645 reg = <0x0 0x8c4b000 0x0 0x1000>;
1646 little-endian;
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1649 status = "disabled";
1650
1651 pcs18: ethernet-phy@0 {
1652 reg = <0>;
1653 };
1654 };
1655
1656 fsl_mc: fsl-mc@80c000000 {
1657 compatible = "fsl,qoriq-mc";
1658 reg = <0x00000008 0x0c000000 0 0x40>,
1659 <0x00000000 0x08340000 0 0x40000>;
1660 msi-parent = <&its>;
1661 /* iommu-map property is fixed up by u-boot */
1662 iommu-map = <0 &smmu 0 0>;
1663 dma-coherent;
1664 #address-cells = <3>;
1665 #size-cells = <1>;
1666
1667 /*
1668 * Region type 0x0 - MC portals
1669 * Region type 0x1 - QBMAN portals
1670 */
1671 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1672 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1673
1674 /*
1675 * Define the maximum number of MACs present on the SoC.
1676 */
1677 dpmacs {
1678 #address-cells = <1>;
1679 #size-cells = <0>;
1680
1681 dpmac1: ethernet@1 {
1682 compatible = "fsl,qoriq-mc-dpmac";
1683 reg = <0x1>;
1684 pcs-handle = <&pcs1>;
1685 };
1686
1687 dpmac2: ethernet@2 {
1688 compatible = "fsl,qoriq-mc-dpmac";
1689 reg = <0x2>;
1690 pcs-handle = <&pcs2>;
1691 };
1692
1693 dpmac3: ethernet@3 {
1694 compatible = "fsl,qoriq-mc-dpmac";
1695 reg = <0x3>;
1696 pcs-handle = <&pcs3>;
1697 };
1698
1699 dpmac4: ethernet@4 {
1700 compatible = "fsl,qoriq-mc-dpmac";
1701 reg = <0x4>;
1702 pcs-handle = <&pcs4>;
1703 };
1704
1705 dpmac5: ethernet@5 {
1706 compatible = "fsl,qoriq-mc-dpmac";
1707 reg = <0x5>;
1708 pcs-handle = <&pcs5>;
1709 };
1710
1711 dpmac6: ethernet@6 {
1712 compatible = "fsl,qoriq-mc-dpmac";
1713 reg = <0x6>;
1714 pcs-handle = <&pcs6>;
1715 };
1716
1717 dpmac7: ethernet@7 {
1718 compatible = "fsl,qoriq-mc-dpmac";
1719 reg = <0x7>;
1720 pcs-handle = <&pcs7>;
1721 };
1722
1723 dpmac8: ethernet@8 {
1724 compatible = "fsl,qoriq-mc-dpmac";
1725 reg = <0x8>;
1726 pcs-handle = <&pcs8>;
1727 };
1728
1729 dpmac9: ethernet@9 {
1730 compatible = "fsl,qoriq-mc-dpmac";
1731 reg = <0x9>;
1732 pcs-handle = <&pcs9>;
1733 };
1734
1735 dpmac10: ethernet@a {
1736 compatible = "fsl,qoriq-mc-dpmac";
1737 reg = <0xa>;
1738 pcs-handle = <&pcs10>;
1739 };
1740
1741 dpmac11: ethernet@b {
1742 compatible = "fsl,qoriq-mc-dpmac";
1743 reg = <0xb>;
1744 pcs-handle = <&pcs11>;
1745 };
1746
1747 dpmac12: ethernet@c {
1748 compatible = "fsl,qoriq-mc-dpmac";
1749 reg = <0xc>;
1750 pcs-handle = <&pcs12>;
1751 };
1752
1753 dpmac13: ethernet@d {
1754 compatible = "fsl,qoriq-mc-dpmac";
1755 reg = <0xd>;
1756 pcs-handle = <&pcs13>;
1757 };
1758
1759 dpmac14: ethernet@e {
1760 compatible = "fsl,qoriq-mc-dpmac";
1761 reg = <0xe>;
1762 pcs-handle = <&pcs14>;
1763 };
1764
1765 dpmac15: ethernet@f {
1766 compatible = "fsl,qoriq-mc-dpmac";
1767 reg = <0xf>;
1768 pcs-handle = <&pcs15>;
1769 };
1770
1771 dpmac16: ethernet@10 {
1772 compatible = "fsl,qoriq-mc-dpmac";
1773 reg = <0x10>;
1774 pcs-handle = <&pcs16>;
1775 };
1776
1777 dpmac17: ethernet@11 {
1778 compatible = "fsl,qoriq-mc-dpmac";
1779 reg = <0x11>;
1780 pcs-handle = <&pcs17>;
1781 };
1782
1783 dpmac18: ethernet@12 {
1784 compatible = "fsl,qoriq-mc-dpmac";
1785 reg = <0x12>;
1786 pcs-handle = <&pcs18>;
1787 };
1788 };
1789 };
1790 };
1791
1792 firmware {
1793 optee: optee {
1794 compatible = "linaro,optee-tz";
1795 method = "smc";
1796 status = "disabled";
1797 };
1798 };
1799};