1// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
  2/*
  3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
  4 */
  5
  6#include <dt-bindings/gpio/gpio.h>
  7#include "dt-bindings/interrupt-controller/arm-gic.h"
  8
  9/ {
 10	model = "Elba ASIC Board";
 11	compatible = "amd,pensando-elba";
 12	interrupt-parent = <&gic>;
 13	#address-cells = <2>;
 14	#size-cells = <2>;
 15
 16	dma-coherent;
 17
 18	ahb_clk: oscillator0 {
 19		compatible = "fixed-clock";
 20		#clock-cells = <0>;
 21	};
 22
 23	emmc_clk: oscillator2 {
 24		compatible = "fixed-clock";
 25		#clock-cells = <0>;
 26	};
 27
 28	flash_clk: oscillator3 {
 29		compatible = "fixed-clock";
 30		#clock-cells = <0>;
 31	};
 32
 33	ref_clk: oscillator4 {
 34		compatible = "fixed-clock";
 35		#clock-cells = <0>;
 36	};
 37
 38	psci {
 39		compatible = "arm,psci-0.2";
 40		method = "smc";
 41	};
 42
 43	timer {
 44		compatible = "arm,armv8-timer";
 45		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 46			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 47			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 48			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 49	};
 50
 51	pmu {
 52		compatible = "arm,cortex-a72-pmu";
 53		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 54	};
 55
 56	soc: soc {
 57		compatible = "simple-bus";
 58		#address-cells = <2>;
 59		#size-cells = <2>;
 60		ranges;
 61
 62		i2c0: i2c@400 {
 63			compatible = "snps,designware-i2c";
 64			reg = <0x0 0x400 0x0 0x100>;
 65			clocks = <&ahb_clk>;
 66			#address-cells = <1>;
 67			#size-cells = <0>;
 68			i2c-sda-hold-time-ns = <480>;
 69			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 70			status = "disabled";
 71		};
 72
 73		wdt0: watchdog@1400 {
 74			compatible = "snps,dw-wdt";
 75			reg = <0x0 0x1400 0x0 0x100>;
 76			clocks = <&ahb_clk>;
 77			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 78			status = "disabled";
 79		};
 80
 81		qspi: spi@2400 {
 82			compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor";
 83			reg = <0x0 0x2400 0x0 0x400>,
 84			      <0x0 0x7fff0000 0x0 0x1000>;
 85			#address-cells = <1>;
 86			#size-cells = <0>;
 87			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 88			clocks = <&flash_clk>;
 89			cdns,fifo-depth = <1024>;
 90			cdns,fifo-width = <4>;
 91			cdns,trigger-address = <0x7fff0000>;
 92			status = "disabled";
 93		};
 94
 95		spi0: spi@2800 {
 96			compatible = "amd,pensando-elba-spi";
 97			reg = <0x0 0x2800 0x0 0x100>;
 98			#address-cells = <1>;
 99			#size-cells = <0>;
100			amd,pensando-elba-syscon = <&syscon>;
101			clocks = <&ahb_clk>;
102			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
103			num-cs = <2>;
104			status = "disabled";
105		};
106
107		gpio0: gpio@4000 {
108			compatible = "snps,dw-apb-gpio";
109			reg = <0x0 0x4000 0x0 0x78>;
110			#address-cells = <1>;
111			#size-cells = <0>;
112			status = "disabled";
113
114			porta: gpio-port@0 {
115				compatible = "snps,dw-apb-gpio-port";
116				reg = <0>;
117				gpio-controller;
118				#gpio-cells = <2>;
119				ngpios = <8>;
120				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
121				interrupt-controller;
122				interrupt-parent = <&gic>;
123				#interrupt-cells = <2>;
124			};
125
126			portb: gpio-port@1 {
127				compatible = "snps,dw-apb-gpio-port";
128				reg = <1>;
129				gpio-controller;
130				#gpio-cells = <2>;
131				ngpios = <8>;
132			};
133		};
134
135		uart0: serial@4800 {
136			compatible = "ns16550a";
137			reg = <0x0 0x4800 0x0 0x100>;
138			clocks = <&ref_clk>;
139			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
140			reg-shift = <2>;
141			reg-io-width = <4>;
142		};
143
144		gic: interrupt-controller@800000 {
145			compatible = "arm,gic-v3";
146			reg = <0x0 0x800000 0x0 0x200000>,	/* GICD */
147			      <0x0 0xa00000 0x0 0x200000>,	/* GICR */
148			      <0x0 0x60000000 0x0 0x2000>,	/* GICC */
149			      <0x0 0x60010000 0x0 0x1000>,	/* GICH */
150			      <0x0 0x60020000 0x0 0x2000>;	/* GICV */
151			#address-cells = <2>;
152			#size-cells = <2>;
153			#interrupt-cells = <3>;
154			ranges;
155			interrupt-controller;
156			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
157
158			/*
159			 * Elba specific pre-ITS is enabled using the
160			 * existing property socionext,synquacer-pre-its
161			 */
162			gic_its: msi-controller@820000 {
163				compatible = "arm,gic-v3-its";
164				reg = <0x0 0x820000 0x0 0x10000>;
165				msi-controller;
166				#msi-cells = <1>;
167				socionext,synquacer-pre-its =
168							<0xc00000 0x1000000>;
169			};
170		};
171
172		emmc: mmc@30440000 {
173			compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc";
174			reg = <0x0 0x30440000 0x0 0x10000>,
175			      <0x0 0x30480044 0x0 0x4>;	/* byte-lane ctrl */
176			clocks = <&emmc_clk>;
177			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
178			cdns,phy-input-delay-sd-highspeed = <0x4>;
179			cdns,phy-input-delay-legacy = <0x4>;
180			cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
181			cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
182			mmc-ddr-1_8v;
183			status = "disabled";
184		};
185
186		syscon: syscon@307c0000 {
187			compatible = "amd,pensando-elba-syscon", "syscon";
188			reg = <0x0 0x307c0000 0x0 0x3000>;
189		};
190	};
191};