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1/*
2 * Copyright (C) 2011 - 2014 Xilinx
3 * Copyright (C) 2012 National Instruments Corp.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14/dts-v1/;
15/include/ "zynq-7000.dtsi"
16
17/ {
18 model = "Zynq ZC702 Development Board";
19 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
20
21 aliases {
22 ethernet0 = &gem0;
23 i2c0 = &i2c0;
24 serial0 = &uart1;
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0x0 0x40000000>;
30 };
31
32 chosen {
33 bootargs = "earlycon";
34 stdout-path = "serial0:115200n8";
35 };
36
37 gpio-keys {
38 compatible = "gpio-keys";
39 #address-cells = <1>;
40 #size-cells = <0>;
41 autorepeat;
42 sw14 {
43 label = "sw14";
44 gpios = <&gpio0 12 0>;
45 linux,code = <108>; /* down */
46 wakeup-source;
47 autorepeat;
48 };
49 sw13 {
50 label = "sw13";
51 gpios = <&gpio0 14 0>;
52 linux,code = <103>; /* up */
53 wakeup-source;
54 autorepeat;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60
61 ds23 {
62 label = "ds23";
63 gpios = <&gpio0 10 0>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
67
68 usb_phy0: phy0 {
69 compatible = "usb-nop-xceiv";
70 #phy-cells = <0>;
71 };
72};
73
74&amba {
75 ocm: sram@fffc0000 {
76 compatible = "mmio-sram";
77 reg = <0xfffc0000 0x10000>;
78 };
79};
80
81&can0 {
82 status = "okay";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_can0_default>;
85};
86
87&clkc {
88 ps-clk-frequency = <33333333>;
89};
90
91&gem0 {
92 status = "okay";
93 phy-mode = "rgmii-id";
94 phy-handle = <ðernet_phy>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_gem0_default>;
97
98 ethernet_phy: ethernet-phy@7 {
99 reg = <7>;
100 };
101};
102
103&gpio0 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_gpio0_default>;
106};
107
108&i2c0 {
109 status = "okay";
110 clock-frequency = <400000>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_i2c0_default>;
113
114 i2cswitch@74 {
115 compatible = "nxp,pca9548";
116 #address-cells = <1>;
117 #size-cells = <0>;
118 reg = <0x74>;
119
120 i2c@0 {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 reg = <0>;
124 si570: clock-generator@5d {
125 #clock-cells = <0>;
126 compatible = "silabs,si570";
127 temperature-stability = <50>;
128 reg = <0x5d>;
129 factory-fout = <156250000>;
130 clock-frequency = <148500000>;
131 };
132 };
133
134 i2c@2 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 reg = <2>;
138 eeprom@54 {
139 compatible = "at,24c08";
140 reg = <0x54>;
141 };
142 };
143
144 i2c@3 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 reg = <3>;
148 gpio@21 {
149 compatible = "ti,tca6416";
150 reg = <0x21>;
151 gpio-controller;
152 #gpio-cells = <2>;
153 };
154 };
155
156 i2c@4 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 reg = <4>;
160 rtc@51 {
161 compatible = "nxp,pcf8563";
162 reg = <0x51>;
163 };
164 };
165
166 i2c@7 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 reg = <7>;
170 hwmon@52 {
171 compatible = "ti,ucd9248";
172 reg = <52>;
173 };
174 hwmon@53 {
175 compatible = "ti,ucd9248";
176 reg = <53>;
177 };
178 hwmon@54 {
179 compatible = "ti,ucd9248";
180 reg = <54>;
181 };
182 };
183 };
184};
185
186&pinctrl0 {
187 pinctrl_can0_default: can0-default {
188 mux {
189 function = "can0";
190 groups = "can0_9_grp";
191 };
192
193 conf {
194 groups = "can0_9_grp";
195 slew-rate = <0>;
196 io-standard = <1>;
197 };
198
199 conf-rx {
200 pins = "MIO46";
201 bias-high-impedance;
202 };
203
204 conf-tx {
205 pins = "MIO47";
206 bias-disable;
207 };
208 };
209
210 pinctrl_gem0_default: gem0-default {
211 mux {
212 function = "ethernet0";
213 groups = "ethernet0_0_grp";
214 };
215
216 conf {
217 groups = "ethernet0_0_grp";
218 slew-rate = <0>;
219 io-standard = <4>;
220 };
221
222 conf-rx {
223 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
224 bias-high-impedance;
225 low-power-disable;
226 };
227
228 conf-tx {
229 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
230 bias-disable;
231 low-power-enable;
232 };
233
234 mux-mdio {
235 function = "mdio0";
236 groups = "mdio0_0_grp";
237 };
238
239 conf-mdio {
240 groups = "mdio0_0_grp";
241 slew-rate = <0>;
242 io-standard = <1>;
243 bias-disable;
244 };
245 };
246
247 pinctrl_gpio0_default: gpio0-default {
248 mux {
249 function = "gpio0";
250 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
251 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
252 "gpio0_13_grp", "gpio0_14_grp";
253 };
254
255 conf {
256 groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
257 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
258 "gpio0_13_grp", "gpio0_14_grp";
259 slew-rate = <0>;
260 io-standard = <1>;
261 };
262
263 conf-pull-up {
264 pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
265 bias-pull-up;
266 };
267
268 conf-pull-none {
269 pins = "MIO7", "MIO8";
270 bias-disable;
271 };
272 };
273
274 pinctrl_i2c0_default: i2c0-default {
275 mux {
276 groups = "i2c0_10_grp";
277 function = "i2c0";
278 };
279
280 conf {
281 groups = "i2c0_10_grp";
282 bias-pull-up;
283 slew-rate = <0>;
284 io-standard = <1>;
285 };
286 };
287
288 pinctrl_sdhci0_default: sdhci0-default {
289 mux {
290 groups = "sdio0_2_grp";
291 function = "sdio0";
292 };
293
294 conf {
295 groups = "sdio0_2_grp";
296 slew-rate = <0>;
297 io-standard = <1>;
298 bias-disable;
299 };
300
301 mux-cd {
302 groups = "gpio0_0_grp";
303 function = "sdio0_cd";
304 };
305
306 conf-cd {
307 groups = "gpio0_0_grp";
308 bias-high-impedance;
309 bias-pull-up;
310 slew-rate = <0>;
311 io-standard = <1>;
312 };
313
314 mux-wp {
315 groups = "gpio0_15_grp";
316 function = "sdio0_wp";
317 };
318
319 conf-wp {
320 groups = "gpio0_15_grp";
321 bias-high-impedance;
322 bias-pull-up;
323 slew-rate = <0>;
324 io-standard = <1>;
325 };
326 };
327
328 pinctrl_uart1_default: uart1-default {
329 mux {
330 groups = "uart1_10_grp";
331 function = "uart1";
332 };
333
334 conf {
335 groups = "uart1_10_grp";
336 slew-rate = <0>;
337 io-standard = <1>;
338 };
339
340 conf-rx {
341 pins = "MIO49";
342 bias-high-impedance;
343 };
344
345 conf-tx {
346 pins = "MIO48";
347 bias-disable;
348 };
349 };
350
351 pinctrl_usb0_default: usb0-default {
352 mux {
353 groups = "usb0_0_grp";
354 function = "usb0";
355 };
356
357 conf {
358 groups = "usb0_0_grp";
359 slew-rate = <0>;
360 io-standard = <1>;
361 };
362
363 conf-rx {
364 pins = "MIO29", "MIO31", "MIO36";
365 bias-high-impedance;
366 };
367
368 conf-tx {
369 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
370 "MIO35", "MIO37", "MIO38", "MIO39";
371 bias-disable;
372 };
373 };
374};
375
376&sdhci0 {
377 status = "okay";
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_sdhci0_default>;
380};
381
382&uart1 {
383 status = "okay";
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_uart1_default>;
386};
387
388&usb0 {
389 status = "okay";
390 dr_mode = "host";
391 usb-phy = <&usb_phy0>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_usb0_default>;
394};