Loading...
Note: File does not exist in v6.8.
1/*
2 * Device Tree Source for the r8a7793 SoC
3 *
4 * Copyright (C) 2014-2015 Renesas Electronics Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7793-clock.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15/ {
16 compatible = "renesas,r8a7793";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28 i2c6 = &i2c6;
29 i2c7 = &i2c7;
30 i2c8 = &i2c8;
31 spi0 = &qspi;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@0 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a15";
41 reg = <0>;
42 clock-frequency = <1500000000>;
43 voltage-tolerance = <1>; /* 1% */
44 clocks = <&cpg_clocks R8A7793_CLK_Z>;
45 clock-latency = <300000>; /* 300 us */
46
47 /* kHz - uV - OPPs unknown yet */
48 operating-points = <1500000 1000000>,
49 <1312500 1000000>,
50 <1125000 1000000>,
51 < 937500 1000000>,
52 < 750000 1000000>,
53 < 375000 1000000>;
54 next-level-cache = <&L2_CA15>;
55 };
56 };
57
58 thermal-zones {
59 cpu_thermal: cpu-thermal {
60 polling-delay-passive = <0>;
61 polling-delay = <0>;
62
63 thermal-sensors = <&thermal>;
64
65 trips {
66 cpu-crit {
67 temperature = <115000>;
68 hysteresis = <0>;
69 type = "critical";
70 };
71 };
72 cooling-maps {
73 };
74 };
75 };
76
77 L2_CA15: cache-controller@0 {
78 compatible = "cache";
79 cache-unified;
80 cache-level = <2>;
81 };
82
83 gic: interrupt-controller@f1001000 {
84 compatible = "arm,gic-400";
85 #interrupt-cells = <3>;
86 #address-cells = <0>;
87 interrupt-controller;
88 reg = <0 0xf1001000 0 0x1000>,
89 <0 0xf1002000 0 0x1000>,
90 <0 0xf1004000 0 0x2000>,
91 <0 0xf1006000 0 0x2000>;
92 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
93 };
94
95 gpio0: gpio@e6050000 {
96 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
97 reg = <0 0xe6050000 0 0x50>;
98 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
99 #gpio-cells = <2>;
100 gpio-controller;
101 gpio-ranges = <&pfc 0 0 32>;
102 #interrupt-cells = <2>;
103 interrupt-controller;
104 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
105 power-domains = <&cpg_clocks>;
106 };
107
108 gpio1: gpio@e6051000 {
109 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
110 reg = <0 0xe6051000 0 0x50>;
111 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
112 #gpio-cells = <2>;
113 gpio-controller;
114 gpio-ranges = <&pfc 0 32 26>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
117 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
118 power-domains = <&cpg_clocks>;
119 };
120
121 gpio2: gpio@e6052000 {
122 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
123 reg = <0 0xe6052000 0 0x50>;
124 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
125 #gpio-cells = <2>;
126 gpio-controller;
127 gpio-ranges = <&pfc 0 64 32>;
128 #interrupt-cells = <2>;
129 interrupt-controller;
130 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
131 power-domains = <&cpg_clocks>;
132 };
133
134 gpio3: gpio@e6053000 {
135 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
136 reg = <0 0xe6053000 0 0x50>;
137 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
138 #gpio-cells = <2>;
139 gpio-controller;
140 gpio-ranges = <&pfc 0 96 32>;
141 #interrupt-cells = <2>;
142 interrupt-controller;
143 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
144 power-domains = <&cpg_clocks>;
145 };
146
147 gpio4: gpio@e6054000 {
148 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
149 reg = <0 0xe6054000 0 0x50>;
150 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
151 #gpio-cells = <2>;
152 gpio-controller;
153 gpio-ranges = <&pfc 0 128 32>;
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
157 power-domains = <&cpg_clocks>;
158 };
159
160 gpio5: gpio@e6055000 {
161 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
162 reg = <0 0xe6055000 0 0x50>;
163 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
164 #gpio-cells = <2>;
165 gpio-controller;
166 gpio-ranges = <&pfc 0 160 32>;
167 #interrupt-cells = <2>;
168 interrupt-controller;
169 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
170 power-domains = <&cpg_clocks>;
171 };
172
173 gpio6: gpio@e6055400 {
174 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
175 reg = <0 0xe6055400 0 0x50>;
176 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
177 #gpio-cells = <2>;
178 gpio-controller;
179 gpio-ranges = <&pfc 0 192 32>;
180 #interrupt-cells = <2>;
181 interrupt-controller;
182 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
183 power-domains = <&cpg_clocks>;
184 };
185
186 gpio7: gpio@e6055800 {
187 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
188 reg = <0 0xe6055800 0 0x50>;
189 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
190 #gpio-cells = <2>;
191 gpio-controller;
192 gpio-ranges = <&pfc 0 224 26>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
195 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
196 power-domains = <&cpg_clocks>;
197 };
198
199 thermal: thermal@e61f0000 {
200 compatible = "renesas,thermal-r8a7793",
201 "renesas,rcar-gen2-thermal",
202 "renesas,rcar-thermal";
203 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
204 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
206 power-domains = <&cpg_clocks>;
207 #thermal-sensor-cells = <0>;
208 };
209
210 timer {
211 compatible = "arm,armv7-timer";
212 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
213 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
214 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
215 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
216 };
217
218 cmt0: timer@ffca0000 {
219 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
220 reg = <0 0xffca0000 0 0x1004>;
221 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
224 clock-names = "fck";
225 power-domains = <&cpg_clocks>;
226
227 renesas,channels-mask = <0x60>;
228
229 status = "disabled";
230 };
231
232 cmt1: timer@e6130000 {
233 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
234 reg = <0 0xe6130000 0 0x1004>;
235 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
244 clock-names = "fck";
245 power-domains = <&cpg_clocks>;
246
247 renesas,channels-mask = <0xff>;
248
249 status = "disabled";
250 };
251
252 irqc0: interrupt-controller@e61c0000 {
253 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
254 #interrupt-cells = <2>;
255 interrupt-controller;
256 reg = <0 0xe61c0000 0 0x200>;
257 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
268 power-domains = <&cpg_clocks>;
269 };
270
271 dmac0: dma-controller@e6700000 {
272 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
273 reg = <0 0xe6700000 0 0x20000>;
274 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
275 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
276 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
277 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
278 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
279 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
280 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
281 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
282 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
283 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
284 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
285 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
286 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
287 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
288 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
289 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "error",
291 "ch0", "ch1", "ch2", "ch3",
292 "ch4", "ch5", "ch6", "ch7",
293 "ch8", "ch9", "ch10", "ch11",
294 "ch12", "ch13", "ch14";
295 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
296 clock-names = "fck";
297 power-domains = <&cpg_clocks>;
298 #dma-cells = <1>;
299 dma-channels = <15>;
300 };
301
302 dmac1: dma-controller@e6720000 {
303 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
304 reg = <0 0xe6720000 0 0x20000>;
305 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
306 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
307 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
308 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
309 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
310 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
311 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
312 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
313 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
321 interrupt-names = "error",
322 "ch0", "ch1", "ch2", "ch3",
323 "ch4", "ch5", "ch6", "ch7",
324 "ch8", "ch9", "ch10", "ch11",
325 "ch12", "ch13", "ch14";
326 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
327 clock-names = "fck";
328 power-domains = <&cpg_clocks>;
329 #dma-cells = <1>;
330 dma-channels = <15>;
331 };
332
333 audma0: dma-controller@ec700000 {
334 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
335 reg = <0 0xec700000 0 0x10000>;
336 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
337 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
338 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
339 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
340 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
341 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
342 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
343 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "error",
351 "ch0", "ch1", "ch2", "ch3",
352 "ch4", "ch5", "ch6", "ch7",
353 "ch8", "ch9", "ch10", "ch11",
354 "ch12";
355 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
356 clock-names = "fck";
357 power-domains = <&cpg_clocks>;
358 #dma-cells = <1>;
359 dma-channels = <13>;
360 };
361
362 audma1: dma-controller@ec720000 {
363 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
364 reg = <0 0xec720000 0 0x10000>;
365 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
369 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
372 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
373 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
374 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
375 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-names = "error",
380 "ch0", "ch1", "ch2", "ch3",
381 "ch4", "ch5", "ch6", "ch7",
382 "ch8", "ch9", "ch10", "ch11",
383 "ch12";
384 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
385 clock-names = "fck";
386 power-domains = <&cpg_clocks>;
387 #dma-cells = <1>;
388 dma-channels = <13>;
389 };
390
391 /* The memory map in the User's Manual maps the cores to bus numbers */
392 i2c0: i2c@e6508000 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 compatible = "renesas,i2c-r8a7793";
396 reg = <0 0xe6508000 0 0x40>;
397 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
399 power-domains = <&cpg_clocks>;
400 i2c-scl-internal-delay-ns = <6>;
401 status = "disabled";
402 };
403
404 i2c1: i2c@e6518000 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 compatible = "renesas,i2c-r8a7793";
408 reg = <0 0xe6518000 0 0x40>;
409 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
411 power-domains = <&cpg_clocks>;
412 i2c-scl-internal-delay-ns = <6>;
413 status = "disabled";
414 };
415
416 i2c2: i2c@e6530000 {
417 #address-cells = <1>;
418 #size-cells = <0>;
419 compatible = "renesas,i2c-r8a7793";
420 reg = <0 0xe6530000 0 0x40>;
421 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
423 power-domains = <&cpg_clocks>;
424 i2c-scl-internal-delay-ns = <6>;
425 status = "disabled";
426 };
427
428 i2c3: i2c@e6540000 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "renesas,i2c-r8a7793";
432 reg = <0 0xe6540000 0 0x40>;
433 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
435 power-domains = <&cpg_clocks>;
436 i2c-scl-internal-delay-ns = <6>;
437 status = "disabled";
438 };
439
440 i2c4: i2c@e6520000 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 compatible = "renesas,i2c-r8a7793";
444 reg = <0 0xe6520000 0 0x40>;
445 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
447 power-domains = <&cpg_clocks>;
448 i2c-scl-internal-delay-ns = <6>;
449 status = "disabled";
450 };
451
452 i2c5: i2c@e6528000 {
453 /* doesn't need pinmux */
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "renesas,i2c-r8a7793";
457 reg = <0 0xe6528000 0 0x40>;
458 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
460 power-domains = <&cpg_clocks>;
461 i2c-scl-internal-delay-ns = <110>;
462 status = "disabled";
463 };
464
465 i2c6: i2c@e60b0000 {
466 /* doesn't need pinmux */
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
470 reg = <0 0xe60b0000 0 0x425>;
471 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
473 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
474 dma-names = "tx", "rx";
475 power-domains = <&cpg_clocks>;
476 status = "disabled";
477 };
478
479 i2c7: i2c@e6500000 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
483 reg = <0 0xe6500000 0 0x425>;
484 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
486 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
487 dma-names = "tx", "rx";
488 power-domains = <&cpg_clocks>;
489 status = "disabled";
490 };
491
492 i2c8: i2c@e6510000 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic";
496 reg = <0 0xe6510000 0 0x425>;
497 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
499 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
500 dma-names = "tx", "rx";
501 power-domains = <&cpg_clocks>;
502 status = "disabled";
503 };
504
505 pfc: pfc@e6060000 {
506 compatible = "renesas,pfc-r8a7793";
507 reg = <0 0xe6060000 0 0x250>;
508 };
509
510 scifa0: serial@e6c40000 {
511 compatible = "renesas,scifa-r8a7793",
512 "renesas,rcar-gen2-scifa", "renesas,scifa";
513 reg = <0 0xe6c40000 0 64>;
514 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
516 clock-names = "fck";
517 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
518 dma-names = "tx", "rx";
519 power-domains = <&cpg_clocks>;
520 status = "disabled";
521 };
522
523 scifa1: serial@e6c50000 {
524 compatible = "renesas,scifa-r8a7793",
525 "renesas,rcar-gen2-scifa", "renesas,scifa";
526 reg = <0 0xe6c50000 0 64>;
527 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
529 clock-names = "fck";
530 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
531 dma-names = "tx", "rx";
532 power-domains = <&cpg_clocks>;
533 status = "disabled";
534 };
535
536 scifa2: serial@e6c60000 {
537 compatible = "renesas,scifa-r8a7793",
538 "renesas,rcar-gen2-scifa", "renesas,scifa";
539 reg = <0 0xe6c60000 0 64>;
540 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
542 clock-names = "fck";
543 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
544 dma-names = "tx", "rx";
545 power-domains = <&cpg_clocks>;
546 status = "disabled";
547 };
548
549 scifa3: serial@e6c70000 {
550 compatible = "renesas,scifa-r8a7793",
551 "renesas,rcar-gen2-scifa", "renesas,scifa";
552 reg = <0 0xe6c70000 0 64>;
553 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
555 clock-names = "fck";
556 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
557 dma-names = "tx", "rx";
558 power-domains = <&cpg_clocks>;
559 status = "disabled";
560 };
561
562 scifa4: serial@e6c78000 {
563 compatible = "renesas,scifa-r8a7793",
564 "renesas,rcar-gen2-scifa", "renesas,scifa";
565 reg = <0 0xe6c78000 0 64>;
566 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
568 clock-names = "fck";
569 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
570 dma-names = "tx", "rx";
571 power-domains = <&cpg_clocks>;
572 status = "disabled";
573 };
574
575 scifa5: serial@e6c80000 {
576 compatible = "renesas,scifa-r8a7793",
577 "renesas,rcar-gen2-scifa", "renesas,scifa";
578 reg = <0 0xe6c80000 0 64>;
579 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
581 clock-names = "fck";
582 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
583 dma-names = "tx", "rx";
584 power-domains = <&cpg_clocks>;
585 status = "disabled";
586 };
587
588 scifb0: serial@e6c20000 {
589 compatible = "renesas,scifb-r8a7793",
590 "renesas,rcar-gen2-scifb", "renesas,scifb";
591 reg = <0 0xe6c20000 0 64>;
592 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
594 clock-names = "fck";
595 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
596 dma-names = "tx", "rx";
597 power-domains = <&cpg_clocks>;
598 status = "disabled";
599 };
600
601 scifb1: serial@e6c30000 {
602 compatible = "renesas,scifb-r8a7793",
603 "renesas,rcar-gen2-scifb", "renesas,scifb";
604 reg = <0 0xe6c30000 0 64>;
605 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
607 clock-names = "fck";
608 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
609 dma-names = "tx", "rx";
610 power-domains = <&cpg_clocks>;
611 status = "disabled";
612 };
613
614 scifb2: serial@e6ce0000 {
615 compatible = "renesas,scifb-r8a7793",
616 "renesas,rcar-gen2-scifb", "renesas,scifb";
617 reg = <0 0xe6ce0000 0 64>;
618 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
620 clock-names = "fck";
621 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
622 dma-names = "tx", "rx";
623 power-domains = <&cpg_clocks>;
624 status = "disabled";
625 };
626
627 scif0: serial@e6e60000 {
628 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
629 "renesas,scif";
630 reg = <0 0xe6e60000 0 64>;
631 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
633 <&scif_clk>;
634 clock-names = "fck", "brg_int", "scif_clk";
635 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
636 dma-names = "tx", "rx";
637 power-domains = <&cpg_clocks>;
638 status = "disabled";
639 };
640
641 scif1: serial@e6e68000 {
642 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
643 "renesas,scif";
644 reg = <0 0xe6e68000 0 64>;
645 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
647 <&scif_clk>;
648 clock-names = "fck", "brg_int", "scif_clk";
649 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
650 dma-names = "tx", "rx";
651 power-domains = <&cpg_clocks>;
652 status = "disabled";
653 };
654
655 scif2: serial@e6e58000 {
656 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
657 "renesas,scif";
658 reg = <0 0xe6e58000 0 64>;
659 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
661 <&scif_clk>;
662 clock-names = "fck", "brg_int", "scif_clk";
663 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
664 dma-names = "tx", "rx";
665 power-domains = <&cpg_clocks>;
666 status = "disabled";
667 };
668
669 scif3: serial@e6ea8000 {
670 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
671 "renesas,scif";
672 reg = <0 0xe6ea8000 0 64>;
673 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
675 <&scif_clk>;
676 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
678 dma-names = "tx", "rx";
679 power-domains = <&cpg_clocks>;
680 status = "disabled";
681 };
682
683 scif4: serial@e6ee0000 {
684 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
685 "renesas,scif";
686 reg = <0 0xe6ee0000 0 64>;
687 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
689 <&scif_clk>;
690 clock-names = "fck", "brg_int", "scif_clk";
691 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
692 dma-names = "tx", "rx";
693 power-domains = <&cpg_clocks>;
694 status = "disabled";
695 };
696
697 scif5: serial@e6ee8000 {
698 compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif",
699 "renesas,scif";
700 reg = <0 0xe6ee8000 0 64>;
701 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
703 <&scif_clk>;
704 clock-names = "fck", "brg_int", "scif_clk";
705 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
706 dma-names = "tx", "rx";
707 power-domains = <&cpg_clocks>;
708 status = "disabled";
709 };
710
711 hscif0: serial@e62c0000 {
712 compatible = "renesas,hscif-r8a7793",
713 "renesas,rcar-gen2-hscif", "renesas,hscif";
714 reg = <0 0xe62c0000 0 96>;
715 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
717 <&scif_clk>;
718 clock-names = "fck", "brg_int", "scif_clk";
719 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
720 dma-names = "tx", "rx";
721 power-domains = <&cpg_clocks>;
722 status = "disabled";
723 };
724
725 hscif1: serial@e62c8000 {
726 compatible = "renesas,hscif-r8a7793",
727 "renesas,rcar-gen2-hscif", "renesas,hscif";
728 reg = <0 0xe62c8000 0 96>;
729 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
731 <&scif_clk>;
732 clock-names = "fck", "brg_int", "scif_clk";
733 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
734 dma-names = "tx", "rx";
735 power-domains = <&cpg_clocks>;
736 status = "disabled";
737 };
738
739 hscif2: serial@e62d0000 {
740 compatible = "renesas,hscif-r8a7793",
741 "renesas,rcar-gen2-hscif", "renesas,hscif";
742 reg = <0 0xe62d0000 0 96>;
743 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
745 <&scif_clk>;
746 clock-names = "fck", "brg_int", "scif_clk";
747 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
748 dma-names = "tx", "rx";
749 power-domains = <&cpg_clocks>;
750 status = "disabled";
751 };
752
753 ether: ethernet@ee700000 {
754 compatible = "renesas,ether-r8a7793";
755 reg = <0 0xee700000 0 0x400>;
756 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
758 power-domains = <&cpg_clocks>;
759 phy-mode = "rmii";
760 #address-cells = <1>;
761 #size-cells = <0>;
762 status = "disabled";
763 };
764
765 qspi: spi@e6b10000 {
766 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
767 reg = <0 0xe6b10000 0 0x2c>;
768 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
770 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
771 dma-names = "tx", "rx";
772 power-domains = <&cpg_clocks>;
773 num-cs = <1>;
774 #address-cells = <1>;
775 #size-cells = <0>;
776 status = "disabled";
777 };
778
779 du: display@feb00000 {
780 compatible = "renesas,du-r8a7793";
781 reg = <0 0xfeb00000 0 0x40000>,
782 <0 0xfeb90000 0 0x1c>;
783 reg-names = "du", "lvds.0";
784 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
787 <&mstp7_clks R8A7793_CLK_DU1>,
788 <&mstp7_clks R8A7793_CLK_LVDS0>;
789 clock-names = "du.0", "du.1", "lvds.0";
790 status = "disabled";
791
792 ports {
793 #address-cells = <1>;
794 #size-cells = <0>;
795
796 port@0 {
797 reg = <0>;
798 du_out_rgb: endpoint {
799 };
800 };
801 port@1 {
802 reg = <1>;
803 du_out_lvds0: endpoint {
804 };
805 };
806 };
807 };
808
809 clocks {
810 #address-cells = <2>;
811 #size-cells = <2>;
812 ranges;
813
814 /* External root clock */
815 extal_clk: extal_clk {
816 compatible = "fixed-clock";
817 #clock-cells = <0>;
818 /* This value must be overridden by the board. */
819 clock-frequency = <0>;
820 clock-output-names = "extal";
821 };
822
823 /*
824 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
825 * default. Boards that provide audio clocks should override them.
826 */
827 audio_clk_a: audio_clk_a {
828 compatible = "fixed-clock";
829 #clock-cells = <0>;
830 clock-frequency = <0>;
831 clock-output-names = "audio_clk_a";
832 };
833 audio_clk_b: audio_clk_b {
834 compatible = "fixed-clock";
835 #clock-cells = <0>;
836 clock-frequency = <0>;
837 clock-output-names = "audio_clk_b";
838 };
839 audio_clk_c: audio_clk_c {
840 compatible = "fixed-clock";
841 #clock-cells = <0>;
842 clock-frequency = <0>;
843 clock-output-names = "audio_clk_c";
844 };
845
846 /* External SCIF clock */
847 scif_clk: scif {
848 compatible = "fixed-clock";
849 #clock-cells = <0>;
850 /* This value must be overridden by the board. */
851 clock-frequency = <0>;
852 status = "disabled";
853 };
854
855 /* Special CPG clocks */
856 cpg_clocks: cpg_clocks@e6150000 {
857 compatible = "renesas,r8a7793-cpg-clocks",
858 "renesas,rcar-gen2-cpg-clocks";
859 reg = <0 0xe6150000 0 0x1000>;
860 clocks = <&extal_clk>;
861 #clock-cells = <1>;
862 clock-output-names = "main", "pll0", "pll1", "pll3",
863 "lb", "qspi", "sdh", "sd0", "z",
864 "rcan", "adsp";
865 #power-domain-cells = <0>;
866 };
867
868 /* Variable factor clocks */
869 sd2_clk: sd2_clk@e6150078 {
870 compatible = "renesas,r8a7793-div6-clock",
871 "renesas,cpg-div6-clock";
872 reg = <0 0xe6150078 0 4>;
873 clocks = <&pll1_div2_clk>;
874 #clock-cells = <0>;
875 clock-output-names = "sd2";
876 };
877 sd3_clk: sd3_clk@e615026c {
878 compatible = "renesas,r8a7793-div6-clock",
879 "renesas,cpg-div6-clock";
880 reg = <0 0xe615026c 0 4>;
881 clocks = <&pll1_div2_clk>;
882 #clock-cells = <0>;
883 clock-output-names = "sd3";
884 };
885 mmc0_clk: mmc0_clk@e6150240 {
886 compatible = "renesas,r8a7793-div6-clock",
887 "renesas,cpg-div6-clock";
888 reg = <0 0xe6150240 0 4>;
889 clocks = <&pll1_div2_clk>;
890 #clock-cells = <0>;
891 clock-output-names = "mmc0";
892 };
893
894 /* Fixed factor clocks */
895 pll1_div2_clk: pll1_div2_clk {
896 compatible = "fixed-factor-clock";
897 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
898 #clock-cells = <0>;
899 clock-div = <2>;
900 clock-mult = <1>;
901 clock-output-names = "pll1_div2";
902 };
903 zg_clk: zg_clk {
904 compatible = "fixed-factor-clock";
905 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
906 #clock-cells = <0>;
907 clock-div = <5>;
908 clock-mult = <1>;
909 clock-output-names = "zg";
910 };
911 zx_clk: zx_clk {
912 compatible = "fixed-factor-clock";
913 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
914 #clock-cells = <0>;
915 clock-div = <3>;
916 clock-mult = <1>;
917 clock-output-names = "zx";
918 };
919 zs_clk: zs_clk {
920 compatible = "fixed-factor-clock";
921 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
922 #clock-cells = <0>;
923 clock-div = <6>;
924 clock-mult = <1>;
925 clock-output-names = "zs";
926 };
927 hp_clk: hp_clk {
928 compatible = "fixed-factor-clock";
929 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
930 #clock-cells = <0>;
931 clock-div = <12>;
932 clock-mult = <1>;
933 clock-output-names = "hp";
934 };
935 p_clk: p_clk {
936 compatible = "fixed-factor-clock";
937 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
938 #clock-cells = <0>;
939 clock-div = <24>;
940 clock-mult = <1>;
941 clock-output-names = "p";
942 };
943 m2_clk: m2_clk {
944 compatible = "fixed-factor-clock";
945 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
946 #clock-cells = <0>;
947 clock-div = <8>;
948 clock-mult = <1>;
949 clock-output-names = "m2";
950 };
951 rclk_clk: rclk_clk {
952 compatible = "fixed-factor-clock";
953 clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
954 #clock-cells = <0>;
955 clock-div = <(48 * 1024)>;
956 clock-mult = <1>;
957 clock-output-names = "rclk";
958 };
959 mp_clk: mp_clk {
960 compatible = "fixed-factor-clock";
961 clocks = <&pll1_div2_clk>;
962 #clock-cells = <0>;
963 clock-div = <15>;
964 clock-mult = <1>;
965 clock-output-names = "mp";
966 };
967 cp_clk: cp_clk {
968 compatible = "fixed-factor-clock";
969 clocks = <&extal_clk>;
970 #clock-cells = <0>;
971 clock-div = <2>;
972 clock-mult = <1>;
973 clock-output-names = "cp";
974 };
975
976 /* Gate clocks */
977 mstp1_clks: mstp1_clks@e6150134 {
978 compatible = "renesas,r8a7793-mstp-clocks",
979 "renesas,cpg-mstp-clocks";
980 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
981 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
982 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
983 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
984 <&zs_clk>, <&zs_clk>, <&zs_clk>;
985 #clock-cells = <1>;
986 clock-indices = <
987 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
988 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
989 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
990 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
991 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
992 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
993 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
994 R8A7793_CLK_VSP1_S
995 >;
996 clock-output-names =
997 "vcp0", "vpc0", "ssp_dev", "tmu1",
998 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
999 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
1000 "vsp1-du0", "vsps";
1001 };
1002 mstp2_clks: mstp2_clks@e6150138 {
1003 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1004 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1005 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1006 <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>;
1007 #clock-cells = <1>;
1008 clock-indices = <
1009 R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0
1010 R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2
1011 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
1012 >;
1013 clock-output-names =
1014 "scifa2", "scifa1", "scifa0", "scifb0",
1015 "scifb1", "scifb2", "sys-dmac1", "sys-dmac0";
1016 };
1017 mstp3_clks: mstp3_clks@e615013c {
1018 compatible = "renesas,r8a7793-mstp-clocks",
1019 "renesas,cpg-mstp-clocks";
1020 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1021 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
1022 <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
1023 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
1024 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
1025 #clock-cells = <1>;
1026 clock-indices = <
1027 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
1028 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
1029 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
1030 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
1031 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
1032 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
1033 >;
1034 clock-output-names =
1035 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1036 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1037 "usbdmac0", "usbdmac1";
1038 };
1039 mstp4_clks: mstp4_clks@e6150140 {
1040 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1041 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1042 clocks = <&cp_clk>;
1043 #clock-cells = <1>;
1044 clock-indices = <R8A7793_CLK_IRQC>;
1045 clock-output-names = "irqc";
1046 };
1047 mstp5_clks: mstp5_clks@e6150144 {
1048 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1049 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1050 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>;
1051 #clock-cells = <1>;
1052 clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1
1053 R8A7793_CLK_THERMAL>;
1054 clock-output-names = "audmac0", "audmac1", "thermal";
1055 };
1056 mstp7_clks: mstp7_clks@e615014c {
1057 compatible = "renesas,r8a7793-mstp-clocks",
1058 "renesas,cpg-mstp-clocks";
1059 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1060 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>,
1061 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1062 <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
1063 <&zx_clk>, <&zx_clk>;
1064 #clock-cells = <1>;
1065 clock-indices = <
1066 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
1067 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
1068 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
1069 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
1070 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
1071 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
1072 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
1073 >;
1074 clock-output-names =
1075 "ehci", "hsusb", "hscif2", "scif5", "scif4",
1076 "hscif1", "hscif0", "scif3", "scif2",
1077 "scif1", "scif0", "du1", "du0", "lvds0";
1078 };
1079 mstp8_clks: mstp8_clks@e6150990 {
1080 compatible = "renesas,r8a7793-mstp-clocks",
1081 "renesas,cpg-mstp-clocks";
1082 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1083 clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
1084 <&p_clk>, <&zs_clk>, <&zs_clk>;
1085 #clock-cells = <1>;
1086 clock-indices = <
1087 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
1088 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
1089 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
1090 R8A7793_CLK_SATA0
1091 >;
1092 clock-output-names =
1093 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
1094 "sata1", "sata0";
1095 };
1096 mstp9_clks: mstp9_clks@e6150994 {
1097 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1098 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1099 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1100 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1101 <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
1102 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1103 <&hp_clk>, <&hp_clk>;
1104 #clock-cells = <1>;
1105 clock-indices = <
1106 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
1107 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
1108 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
1109 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
1110 R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5
1111 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
1112 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
1113 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
1114 >;
1115 clock-output-names =
1116 "gpio7", "gpio6", "gpio5", "gpio4",
1117 "gpio3", "gpio2", "gpio1", "gpio0",
1118 "qspi_mod", "i2c5", "i2c6", "i2c4",
1119 "i2c3", "i2c2", "i2c1", "i2c0";
1120 };
1121 mstp10_clks: mstp10_clks@e6150998 {
1122 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1123 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1124 clocks = <&p_clk>,
1125 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1126 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1127 <&p_clk>,
1128 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1129 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1130 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1131 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1132 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1133 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>,
1134 <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>;
1135
1136 #clock-cells = <1>;
1137 clock-indices = <
1138 R8A7793_CLK_SSI_ALL
1139 R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5
1140 R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0
1141 R8A7793_CLK_SCU_ALL
1142 R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0
1143 R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0
1144 R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5
1145 R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0
1146 >;
1147 clock-output-names =
1148 "ssi-all",
1149 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1150 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1151 "scu-all",
1152 "scu-dvc1", "scu-dvc0",
1153 "scu-ctu1-mix1", "scu-ctu0-mix0",
1154 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1155 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1156 };
1157 mstp11_clks: mstp11_clks@e615099c {
1158 compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
1159 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1160 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1161 #clock-cells = <1>;
1162 clock-indices = <
1163 R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5
1164 >;
1165 clock-output-names = "scifa3", "scifa4", "scifa5";
1166 };
1167 };
1168
1169 ipmmu_sy0: mmu@e6280000 {
1170 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1171 reg = <0 0xe6280000 0 0x1000>;
1172 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1174 #iommu-cells = <1>;
1175 status = "disabled";
1176 };
1177
1178 ipmmu_sy1: mmu@e6290000 {
1179 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1180 reg = <0 0xe6290000 0 0x1000>;
1181 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1182 #iommu-cells = <1>;
1183 status = "disabled";
1184 };
1185
1186 ipmmu_ds: mmu@e6740000 {
1187 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1188 reg = <0 0xe6740000 0 0x1000>;
1189 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1191 #iommu-cells = <1>;
1192 status = "disabled";
1193 };
1194
1195 ipmmu_mp: mmu@ec680000 {
1196 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1197 reg = <0 0xec680000 0 0x1000>;
1198 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1199 #iommu-cells = <1>;
1200 status = "disabled";
1201 };
1202
1203 ipmmu_mx: mmu@fe951000 {
1204 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1205 reg = <0 0xfe951000 0 0x1000>;
1206 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1208 #iommu-cells = <1>;
1209 status = "disabled";
1210 };
1211
1212 ipmmu_rt: mmu@ffc80000 {
1213 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1214 reg = <0 0xffc80000 0 0x1000>;
1215 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1216 #iommu-cells = <1>;
1217 status = "disabled";
1218 };
1219
1220 ipmmu_gp: mmu@e62a0000 {
1221 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1222 reg = <0 0xe62a0000 0 0x1000>;
1223 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1225 #iommu-cells = <1>;
1226 status = "disabled";
1227 };
1228
1229 rcar_sound: sound@ec500000 {
1230 /*
1231 * #sound-dai-cells is required
1232 *
1233 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1234 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1235 */
1236 compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2";
1237 reg = <0 0xec500000 0 0x1000>, /* SCU */
1238 <0 0xec5a0000 0 0x100>, /* ADG */
1239 <0 0xec540000 0 0x1000>, /* SSIU */
1240 <0 0xec541000 0 0x280>, /* SSI */
1241 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1242 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1243
1244 clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>,
1245 <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>,
1246 <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>,
1247 <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>,
1248 <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>,
1249 <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>,
1250 <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>,
1251 <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>,
1252 <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>,
1253 <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>,
1254 <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>,
1255 <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>,
1256 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1257 clock-names = "ssi-all",
1258 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1259 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1260 "src.9", "src.8", "src.7", "src.6", "src.5",
1261 "src.4", "src.3", "src.2", "src.1", "src.0",
1262 "dvc.0", "dvc.1",
1263 "clk_a", "clk_b", "clk_c", "clk_i";
1264 power-domains = <&cpg_clocks>;
1265
1266 status = "disabled";
1267
1268 rcar_sound,dvc {
1269 dvc0: dvc@0 {
1270 dmas = <&audma0 0xbc>;
1271 dma-names = "tx";
1272 };
1273 dvc1: dvc@1 {
1274 dmas = <&audma0 0xbe>;
1275 dma-names = "tx";
1276 };
1277 };
1278
1279 rcar_sound,src {
1280 src0: src@0 {
1281 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1282 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1283 dma-names = "rx", "tx";
1284 };
1285 src1: src@1 {
1286 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1287 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1288 dma-names = "rx", "tx";
1289 };
1290 src2: src@2 {
1291 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1292 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1293 dma-names = "rx", "tx";
1294 };
1295 src3: src@3 {
1296 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1297 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1298 dma-names = "rx", "tx";
1299 };
1300 src4: src@4 {
1301 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1302 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1303 dma-names = "rx", "tx";
1304 };
1305 src5: src@5 {
1306 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1307 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1308 dma-names = "rx", "tx";
1309 };
1310 src6: src@6 {
1311 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1312 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1313 dma-names = "rx", "tx";
1314 };
1315 src7: src@7 {
1316 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1317 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1318 dma-names = "rx", "tx";
1319 };
1320 src8: src@8 {
1321 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1322 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1323 dma-names = "rx", "tx";
1324 };
1325 src9: src@9 {
1326 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1327 dmas = <&audma0 0x97>, <&audma1 0xba>;
1328 dma-names = "rx", "tx";
1329 };
1330 };
1331
1332 rcar_sound,ssi {
1333 ssi0: ssi@0 {
1334 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1335 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1336 dma-names = "rx", "tx", "rxu", "txu";
1337 };
1338 ssi1: ssi@1 {
1339 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1340 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1341 dma-names = "rx", "tx", "rxu", "txu";
1342 };
1343 ssi2: ssi@2 {
1344 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1345 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1346 dma-names = "rx", "tx", "rxu", "txu";
1347 };
1348 ssi3: ssi@3 {
1349 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1350 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1351 dma-names = "rx", "tx", "rxu", "txu";
1352 };
1353 ssi4: ssi@4 {
1354 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1355 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1356 dma-names = "rx", "tx", "rxu", "txu";
1357 };
1358 ssi5: ssi@5 {
1359 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1360 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1361 dma-names = "rx", "tx", "rxu", "txu";
1362 };
1363 ssi6: ssi@6 {
1364 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1365 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1366 dma-names = "rx", "tx", "rxu", "txu";
1367 };
1368 ssi7: ssi@7 {
1369 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1370 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1371 dma-names = "rx", "tx", "rxu", "txu";
1372 };
1373 ssi8: ssi@8 {
1374 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1375 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1376 dma-names = "rx", "tx", "rxu", "txu";
1377 };
1378 ssi9: ssi@9 {
1379 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1380 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1381 dma-names = "rx", "tx", "rxu", "txu";
1382 };
1383 };
1384 };
1385};