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1/*
2 * Device Tree Source for the r8a7740 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13#include <dt-bindings/clock/r8a7740-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
17/ {
18 compatible = "renesas,r8a7740";
19 interrupt-parent = <&gic>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 cpu@0 {
25 compatible = "arm,cortex-a9";
26 device_type = "cpu";
27 reg = <0x0>;
28 clock-frequency = <800000000>;
29 power-domains = <&pd_a3sm>;
30 next-level-cache = <&L2>;
31 };
32 };
33
34 gic: interrupt-controller@c2800000 {
35 compatible = "arm,pl390";
36 #interrupt-cells = <3>;
37 interrupt-controller;
38 reg = <0xc2800000 0x1000>,
39 <0xc2000000 0x1000>;
40 };
41
42 L2: cache-controller {
43 compatible = "arm,pl310-cache";
44 reg = <0xf0100000 0x1000>;
45 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
46 power-domains = <&pd_a3sm>;
47 arm,data-latency = <3 3 3>;
48 arm,tag-latency = <2 2 2>;
49 arm,shared-override;
50 cache-unified;
51 cache-level = <2>;
52 };
53
54 dbsc3: memory-controller@fe400000 {
55 compatible = "renesas,dbsc3-r8a7740";
56 reg = <0xfe400000 0x400>;
57 power-domains = <&pd_a4s>;
58 };
59
60 pmu {
61 compatible = "arm,cortex-a9-pmu";
62 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
63 };
64
65 ptm {
66 compatible = "arm,coresight-etm3x";
67 power-domains = <&pd_d4>;
68 };
69
70 cmt1: timer@e6138000 {
71 compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
72 reg = <0xe6138000 0x170>;
73 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
75 clock-names = "fck";
76 power-domains = <&pd_c5>;
77
78 renesas,channels-mask = <0x3f>;
79
80 status = "disabled";
81 };
82
83 /* irqpin0: IRQ0 - IRQ7 */
84 irqpin0: interrupt-controller@e6900000 {
85 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 reg = <0xe6900000 4>,
89 <0xe6900010 4>,
90 <0xe6900020 1>,
91 <0xe6900040 1>,
92 <0xe6900060 1>;
93 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
102 power-domains = <&pd_a4s>;
103 };
104
105 /* irqpin1: IRQ8 - IRQ15 */
106 irqpin1: interrupt-controller@e6900004 {
107 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 reg = <0xe6900004 4>,
111 <0xe6900014 4>,
112 <0xe6900024 1>,
113 <0xe6900044 1>,
114 <0xe6900064 1>;
115 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
116 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
117 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
118 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
124 power-domains = <&pd_a4s>;
125 };
126
127 /* irqpin2: IRQ16 - IRQ23 */
128 irqpin2: interrupt-controller@e6900008 {
129 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 reg = <0xe6900008 4>,
133 <0xe6900018 4>,
134 <0xe6900028 1>,
135 <0xe6900048 1>,
136 <0xe6900068 1>;
137 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
138 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
146 power-domains = <&pd_a4s>;
147 };
148
149 /* irqpin3: IRQ24 - IRQ31 */
150 irqpin3: interrupt-controller@e690000c {
151 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 reg = <0xe690000c 4>,
155 <0xe690001c 4>,
156 <0xe690002c 1>,
157 <0xe690004c 1>,
158 <0xe690006c 1>;
159 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
160 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
161 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
162 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
163 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
164 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
165 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
166 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
168 power-domains = <&pd_a4s>;
169 };
170
171 ether: ethernet@e9a00000 {
172 compatible = "renesas,gether-r8a7740";
173 reg = <0xe9a00000 0x800>,
174 <0xe9a01800 0x800>;
175 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
177 power-domains = <&pd_a4s>;
178 phy-mode = "mii";
179 #address-cells = <1>;
180 #size-cells = <0>;
181 status = "disabled";
182 };
183
184 i2c0: i2c@fff20000 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
188 reg = <0xfff20000 0x425>;
189 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
190 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
191 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
192 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
194 power-domains = <&pd_a4r>;
195 status = "disabled";
196 };
197
198 i2c1: i2c@e6c20000 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
202 reg = <0xe6c20000 0x425>;
203 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
204 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
205 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
206 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
208 power-domains = <&pd_a3sp>;
209 status = "disabled";
210 };
211
212 scifa0: serial@e6c40000 {
213 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
214 reg = <0xe6c40000 0x100>;
215 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
217 clock-names = "fck";
218 power-domains = <&pd_a3sp>;
219 status = "disabled";
220 };
221
222 scifa1: serial@e6c50000 {
223 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
224 reg = <0xe6c50000 0x100>;
225 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
227 clock-names = "fck";
228 power-domains = <&pd_a3sp>;
229 status = "disabled";
230 };
231
232 scifa2: serial@e6c60000 {
233 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
234 reg = <0xe6c60000 0x100>;
235 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
237 clock-names = "fck";
238 power-domains = <&pd_a3sp>;
239 status = "disabled";
240 };
241
242 scifa3: serial@e6c70000 {
243 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
244 reg = <0xe6c70000 0x100>;
245 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
247 clock-names = "fck";
248 power-domains = <&pd_a3sp>;
249 status = "disabled";
250 };
251
252 scifa4: serial@e6c80000 {
253 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
254 reg = <0xe6c80000 0x100>;
255 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
257 clock-names = "fck";
258 power-domains = <&pd_a3sp>;
259 status = "disabled";
260 };
261
262 scifa5: serial@e6cb0000 {
263 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
264 reg = <0xe6cb0000 0x100>;
265 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
267 clock-names = "fck";
268 power-domains = <&pd_a3sp>;
269 status = "disabled";
270 };
271
272 scifa6: serial@e6cc0000 {
273 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
274 reg = <0xe6cc0000 0x100>;
275 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
277 clock-names = "fck";
278 power-domains = <&pd_a3sp>;
279 status = "disabled";
280 };
281
282 scifa7: serial@e6cd0000 {
283 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
284 reg = <0xe6cd0000 0x100>;
285 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
287 clock-names = "fck";
288 power-domains = <&pd_a3sp>;
289 status = "disabled";
290 };
291
292 scifb: serial@e6c30000 {
293 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
294 reg = <0xe6c30000 0x100>;
295 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
297 clock-names = "fck";
298 power-domains = <&pd_a3sp>;
299 status = "disabled";
300 };
301
302 pfc: pfc@e6050000 {
303 compatible = "renesas,pfc-r8a7740";
304 reg = <0xe6050000 0x8000>,
305 <0xe605800c 0x20>;
306 gpio-controller;
307 #gpio-cells = <2>;
308 gpio-ranges = <&pfc 0 0 212>;
309 interrupts-extended =
310 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
311 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
312 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
313 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
314 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
315 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
316 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
317 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
318 power-domains = <&pd_c5>;
319 };
320
321 tpu: pwm@e6600000 {
322 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
323 reg = <0xe6600000 0x100>;
324 clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
325 power-domains = <&pd_a3sp>;
326 status = "disabled";
327 #pwm-cells = <3>;
328 };
329
330 mmcif0: mmc@e6bd0000 {
331 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
332 reg = <0xe6bd0000 0x100>;
333 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
334 GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&mstp3_clks R8A7740_CLK_MMC>;
336 power-domains = <&pd_a3sp>;
337 status = "disabled";
338 };
339
340 sdhi0: sd@e6850000 {
341 compatible = "renesas,sdhi-r8a7740";
342 reg = <0xe6850000 0x100>;
343 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
344 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
347 power-domains = <&pd_a3sp>;
348 cap-sd-highspeed;
349 cap-sdio-irq;
350 status = "disabled";
351 };
352
353 sdhi1: sd@e6860000 {
354 compatible = "renesas,sdhi-r8a7740";
355 reg = <0xe6860000 0x100>;
356 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
360 power-domains = <&pd_a3sp>;
361 cap-sd-highspeed;
362 cap-sdio-irq;
363 status = "disabled";
364 };
365
366 sdhi2: sd@e6870000 {
367 compatible = "renesas,sdhi-r8a7740";
368 reg = <0xe6870000 0x100>;
369 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
370 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
371 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
373 power-domains = <&pd_a3sp>;
374 cap-sd-highspeed;
375 cap-sdio-irq;
376 status = "disabled";
377 };
378
379 sh_fsi2: sound@fe1f0000 {
380 #sound-dai-cells = <1>;
381 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
382 reg = <0xfe1f0000 0x400>;
383 interrupts = <GIC_SPI 9 0x4>;
384 clocks = <&mstp3_clks R8A7740_CLK_FSI>;
385 power-domains = <&pd_a4mp>;
386 status = "disabled";
387 };
388
389 tmu0: timer@fff80000 {
390 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
391 reg = <0xfff80000 0x2c>;
392 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
396 clock-names = "fck";
397 power-domains = <&pd_a4r>;
398
399 #renesas,channels = <3>;
400
401 status = "disabled";
402 };
403
404 tmu1: timer@fff90000 {
405 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
406 reg = <0xfff90000 0x2c>;
407 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
411 clock-names = "fck";
412 power-domains = <&pd_a4r>;
413
414 #renesas,channels = <3>;
415
416 status = "disabled";
417 };
418
419 clocks {
420 #address-cells = <1>;
421 #size-cells = <1>;
422 ranges;
423
424 /* External root clock */
425 extalr_clk: extalr_clk {
426 compatible = "fixed-clock";
427 #clock-cells = <0>;
428 clock-frequency = <32768>;
429 clock-output-names = "extalr";
430 };
431 extal1_clk: extal1_clk {
432 compatible = "fixed-clock";
433 #clock-cells = <0>;
434 clock-frequency = <0>;
435 clock-output-names = "extal1";
436 };
437 extal2_clk: extal2_clk {
438 compatible = "fixed-clock";
439 #clock-cells = <0>;
440 clock-frequency = <0>;
441 clock-output-names = "extal2";
442 };
443 dv_clk: dv_clk {
444 compatible = "fixed-clock";
445 #clock-cells = <0>;
446 clock-frequency = <27000000>;
447 clock-output-names = "dv";
448 };
449 fmsick_clk: fmsick_clk {
450 compatible = "fixed-clock";
451 #clock-cells = <0>;
452 clock-frequency = <0>;
453 clock-output-names = "fmsick";
454 };
455 fmsock_clk: fmsock_clk {
456 compatible = "fixed-clock";
457 #clock-cells = <0>;
458 clock-frequency = <0>;
459 clock-output-names = "fmsock";
460 };
461 fsiack_clk: fsiack_clk {
462 compatible = "fixed-clock";
463 #clock-cells = <0>;
464 clock-frequency = <0>;
465 clock-output-names = "fsiack";
466 };
467 fsibck_clk: fsibck_clk {
468 compatible = "fixed-clock";
469 #clock-cells = <0>;
470 clock-frequency = <0>;
471 clock-output-names = "fsibck";
472 };
473
474 /* Special CPG clocks */
475 cpg_clocks: cpg_clocks@e6150000 {
476 compatible = "renesas,r8a7740-cpg-clocks";
477 reg = <0xe6150000 0x10000>;
478 clocks = <&extal1_clk>, <&extalr_clk>;
479 #clock-cells = <1>;
480 clock-output-names = "system", "pllc0", "pllc1",
481 "pllc2", "r",
482 "usb24s",
483 "i", "zg", "b", "m1", "hp",
484 "hpp", "usbp", "s", "zb", "m3",
485 "cp";
486 };
487
488 /* Variable factor clocks (DIV6) */
489 vclk1_clk: vclk1_clk@e6150008 {
490 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
491 reg = <0xe6150008 4>;
492 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
493 <&cpg_clocks R8A7740_CLK_USB24S>,
494 <&extal1_div2_clk>, <&extalr_clk>, <0>,
495 <0>;
496 #clock-cells = <0>;
497 clock-output-names = "vclk1";
498 };
499 vclk2_clk: vclk2_clk@e615000c {
500 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
501 reg = <0xe615000c 4>;
502 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
503 <&cpg_clocks R8A7740_CLK_USB24S>,
504 <&extal1_div2_clk>, <&extalr_clk>, <0>,
505 <0>;
506 #clock-cells = <0>;
507 clock-output-names = "vclk2";
508 };
509 fmsi_clk: fmsi_clk@e6150010 {
510 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
511 reg = <0xe6150010 4>;
512 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
513 #clock-cells = <0>;
514 clock-output-names = "fmsi";
515 };
516 fmso_clk: fmso_clk@e6150014 {
517 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
518 reg = <0xe6150014 4>;
519 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
520 #clock-cells = <0>;
521 clock-output-names = "fmso";
522 };
523 fsia_clk: fsia_clk@e6150018 {
524 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
525 reg = <0xe6150018 4>;
526 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
527 #clock-cells = <0>;
528 clock-output-names = "fsia";
529 };
530 sub_clk: sub_clk@e6150080 {
531 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
532 reg = <0xe6150080 4>;
533 clocks = <&pllc1_div2_clk>,
534 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
535 #clock-cells = <0>;
536 clock-output-names = "sub";
537 };
538 spu_clk: spu_clk@e6150084 {
539 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
540 reg = <0xe6150084 4>;
541 clocks = <&pllc1_div2_clk>,
542 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
543 #clock-cells = <0>;
544 clock-output-names = "spu";
545 };
546 vou_clk: vou_clk@e6150088 {
547 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
548 reg = <0xe6150088 4>;
549 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
550 <0>;
551 #clock-cells = <0>;
552 clock-output-names = "vou";
553 };
554 stpro_clk: stpro_clk@e615009c {
555 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
556 reg = <0xe615009c 4>;
557 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
558 #clock-cells = <0>;
559 clock-output-names = "stpro";
560 };
561
562 /* Fixed factor clocks */
563 pllc1_div2_clk: pllc1_div2_clk {
564 compatible = "fixed-factor-clock";
565 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>;
566 #clock-cells = <0>;
567 clock-div = <2>;
568 clock-mult = <1>;
569 clock-output-names = "pllc1_div2";
570 };
571 extal1_div2_clk: extal1_div2_clk {
572 compatible = "fixed-factor-clock";
573 clocks = <&extal1_clk>;
574 #clock-cells = <0>;
575 clock-div = <2>;
576 clock-mult = <1>;
577 clock-output-names = "extal1_div2";
578 };
579
580 /* Gate clocks */
581 subck_clks: subck_clks@e6150080 {
582 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
583 reg = <0xe6150080 4>;
584 clocks = <&sub_clk>, <&sub_clk>;
585 #clock-cells = <1>;
586 clock-indices = <
587 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
588 >;
589 clock-output-names =
590 "subck", "subck2";
591 };
592 mstp1_clks: mstp1_clks@e6150134 {
593 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
594 reg = <0xe6150134 4>, <0xe6150038 4>;
595 clocks = <&cpg_clocks R8A7740_CLK_S>,
596 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
597 <&cpg_clocks R8A7740_CLK_B>,
598 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
599 <&cpg_clocks R8A7740_CLK_B>;
600 #clock-cells = <1>;
601 clock-indices = <
602 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
603 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
604 R8A7740_CLK_LCDC0
605 >;
606 clock-output-names =
607 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0",
608 "tmu1", "lcdc0";
609 };
610 mstp2_clks: mstp2_clks@e6150138 {
611 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
612 reg = <0xe6150138 4>, <0xe6150040 4>;
613 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
614 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
615 <&cpg_clocks R8A7740_CLK_HP>,
616 <&cpg_clocks R8A7740_CLK_HP>,
617 <&cpg_clocks R8A7740_CLK_HP>,
618 <&sub_clk>, <&sub_clk>, <&sub_clk>,
619 <&sub_clk>, <&sub_clk>, <&sub_clk>,
620 <&sub_clk>;
621 #clock-cells = <1>;
622 clock-indices = <
623 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
624 R8A7740_CLK_SCIFA7
625 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
626 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
627 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
628 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1
629 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3
630 R8A7740_CLK_SCIFA4
631 >;
632 clock-output-names =
633 "scifa6", "intca",
634 "scifa7", "dmac1", "dmac2", "dmac3",
635 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
636 "scifa2", "scifa3", "scifa4";
637 };
638 mstp3_clks: mstp3_clks@e615013c {
639 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
640 reg = <0xe615013c 4>, <0xe6150048 4>;
641 clocks = <&cpg_clocks R8A7740_CLK_R>,
642 <&cpg_clocks R8A7740_CLK_HP>,
643 <&sub_clk>,
644 <&cpg_clocks R8A7740_CLK_HP>,
645 <&cpg_clocks R8A7740_CLK_HP>,
646 <&cpg_clocks R8A7740_CLK_HP>,
647 <&cpg_clocks R8A7740_CLK_HP>,
648 <&cpg_clocks R8A7740_CLK_HP>,
649 <&cpg_clocks R8A7740_CLK_HP>;
650 #clock-cells = <1>;
651 clock-indices = <
652 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
653 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
654 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
655 >;
656 clock-output-names =
657 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1",
658 "mmc", "gether", "tpu0";
659 };
660 mstp4_clks: mstp4_clks@e6150140 {
661 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
662 reg = <0xe6150140 4>, <0xe615004c 4>;
663 clocks = <&cpg_clocks R8A7740_CLK_HP>,
664 <&cpg_clocks R8A7740_CLK_HP>,
665 <&cpg_clocks R8A7740_CLK_HP>,
666 <&cpg_clocks R8A7740_CLK_HP>;
667 #clock-cells = <1>;
668 clock-indices = <
669 R8A7740_CLK_USBH R8A7740_CLK_SDHI2
670 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
671 >;
672 clock-output-names =
673 "usbhost", "sdhi2", "usbfunc", "usphy";
674 };
675 };
676
677 sysc: system-controller@e6180000 {
678 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
679 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
680
681 pm-domains {
682 pd_c5: c5 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 #power-domain-cells = <0>;
686
687 pd_a4lc: a4lc@1 {
688 reg = <1>;
689 #power-domain-cells = <0>;
690 };
691
692 pd_a4mp: a4mp@2 {
693 reg = <2>;
694 #power-domain-cells = <0>;
695 };
696
697 pd_d4: d4@3 {
698 reg = <3>;
699 #power-domain-cells = <0>;
700 };
701
702 pd_a4r: a4r@5 {
703 reg = <5>;
704 #address-cells = <1>;
705 #size-cells = <0>;
706 #power-domain-cells = <0>;
707
708 pd_a3rv: a3rv@6 {
709 reg = <6>;
710 #power-domain-cells = <0>;
711 };
712 };
713
714 pd_a4s: a4s@10 {
715 reg = <10>;
716 #address-cells = <1>;
717 #size-cells = <0>;
718 #power-domain-cells = <0>;
719
720 pd_a3sp: a3sp@11 {
721 reg = <11>;
722 #power-domain-cells = <0>;
723 };
724
725 pd_a3sm: a3sm@12 {
726 reg = <12>;
727 #power-domain-cells = <0>;
728 };
729
730 pd_a3sg: a3sg@13 {
731 reg = <13>;
732 #power-domain-cells = <0>;
733 };
734 };
735
736 pd_a4su: a4su@20 {
737 reg = <20>;
738 #power-domain-cells = <0>;
739 };
740 };
741 };
742 };
743};