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1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14#include "skeleton.dtsi"
15
16/ {
17 aliases {
18 ethernet0 = &fec1;
19 ethernet1 = &fec2;
20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 gpio4 = &gpio5;
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
37 serial6 = &uart7;
38 serial7 = &uart8;
39 spi0 = &ecspi1;
40 spi1 = &ecspi2;
41 spi2 = &ecspi3;
42 spi3 = &ecspi4;
43 usbphy0 = &usbphy1;
44 usbphy1 = &usbphy2;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 compatible = "arm,cortex-a7";
53 device_type = "cpu";
54 reg = <0>;
55 clock-latency = <61036>; /* two CLK32 periods */
56 operating-points = <
57 /* kHz uV */
58 528000 1250000
59 396000 1150000
60 198000 1150000
61 >;
62 fsl,soc-operating-points = <
63 /* KHz uV */
64 528000 1250000
65 396000 1150000
66 198000 1150000
67 >;
68 clocks = <&clks IMX6UL_CLK_ARM>,
69 <&clks IMX6UL_CLK_PLL2_BUS>,
70 <&clks IMX6UL_CLK_PLL2_PFD2>,
71 <&clks IMX6UL_CA7_SECONDARY_SEL>,
72 <&clks IMX6UL_CLK_STEP>,
73 <&clks IMX6UL_CLK_PLL1_SW>,
74 <&clks IMX6UL_CLK_PLL1_SYS>,
75 <&clks IMX6UL_PLL1_BYPASS>,
76 <&clks IMX6UL_CLK_PLL1>,
77 <&clks IMX6UL_PLL1_BYPASS_SRC>,
78 <&clks IMX6UL_CLK_OSC>;
79 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
80 "secondary_sel", "step", "pll1_sw",
81 "pll1_sys", "pll1_bypass", "pll1",
82 "pll1_bypass_src", "osc";
83 arm-supply = <®_arm>;
84 soc-supply = <®_soc>;
85 };
86 };
87
88 intc: interrupt-controller@00a01000 {
89 compatible = "arm,cortex-a7-gic";
90 #interrupt-cells = <3>;
91 interrupt-controller;
92 reg = <0x00a01000 0x1000>,
93 <0x00a02000 0x1000>,
94 <0x00a04000 0x2000>,
95 <0x00a06000 0x2000>;
96 };
97
98 ckil: clock-cli {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock-osc {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <24000000>;
109 clock-output-names = "osc";
110 };
111
112 ipp_di0: clock-di0 {
113 compatible = "fixed-clock";
114 #clock-cells = <0>;
115 clock-frequency = <0>;
116 clock-output-names = "ipp_di0";
117 };
118
119 ipp_di1: clock-di1 {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
124 };
125
126 soc {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "simple-bus";
130 interrupt-parent = <&gpc>;
131 ranges;
132
133 pmu {
134 compatible = "arm,cortex-a7-pmu";
135 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
136 status = "disabled";
137 };
138
139 ocram: sram@00900000 {
140 compatible = "mmio-sram";
141 reg = <0x00900000 0x20000>;
142 };
143
144 dma_apbh: dma-apbh@01804000 {
145 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
146 reg = <0x01804000 0x2000>;
147 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
148 <0 13 IRQ_TYPE_LEVEL_HIGH>,
149 <0 13 IRQ_TYPE_LEVEL_HIGH>,
150 <0 13 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
152 #dma-cells = <1>;
153 dma-channels = <4>;
154 clocks = <&clks IMX6UL_CLK_APBHDMA>;
155 };
156
157 gpmi: gpmi-nand@01806000 {
158 compatible = "fsl,imx6q-gpmi-nand";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
162 reg-names = "gpmi-nand", "bch";
163 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-names = "bch";
165 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
166 <&clks IMX6UL_CLK_GPMI_APB>,
167 <&clks IMX6UL_CLK_GPMI_BCH>,
168 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
169 <&clks IMX6UL_CLK_PER_BCH>;
170 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
171 "gpmi_bch_apb", "per1_bch";
172 dmas = <&dma_apbh 0>;
173 dma-names = "rx-tx";
174 status = "disabled";
175 };
176
177 aips1: aips-bus@02000000 {
178 compatible = "fsl,aips-bus", "simple-bus";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 reg = <0x02000000 0x100000>;
182 ranges;
183
184 spba-bus@02000000 {
185 compatible = "fsl,spba-bus", "simple-bus";
186 #address-cells = <1>;
187 #size-cells = <1>;
188 reg = <0x02000000 0x40000>;
189 ranges;
190
191 ecspi1: ecspi@02008000 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
195 reg = <0x02008000 0x4000>;
196 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clks IMX6UL_CLK_ECSPI1>,
198 <&clks IMX6UL_CLK_ECSPI1>;
199 clock-names = "ipg", "per";
200 status = "disabled";
201 };
202
203 ecspi2: ecspi@0200c000 {
204 #address-cells = <1>;
205 #size-cells = <0>;
206 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
207 reg = <0x0200c000 0x4000>;
208 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&clks IMX6UL_CLK_ECSPI2>,
210 <&clks IMX6UL_CLK_ECSPI2>;
211 clock-names = "ipg", "per";
212 status = "disabled";
213 };
214
215 ecspi3: ecspi@02010000 {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
219 reg = <0x02010000 0x4000>;
220 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&clks IMX6UL_CLK_ECSPI3>,
222 <&clks IMX6UL_CLK_ECSPI3>;
223 clock-names = "ipg", "per";
224 status = "disabled";
225 };
226
227 ecspi4: ecspi@02014000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
231 reg = <0x02014000 0x4000>;
232 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6UL_CLK_ECSPI4>,
234 <&clks IMX6UL_CLK_ECSPI4>;
235 clock-names = "ipg", "per";
236 status = "disabled";
237 };
238
239 uart7: serial@02018000 {
240 compatible = "fsl,imx6ul-uart",
241 "fsl,imx6q-uart";
242 reg = <0x02018000 0x4000>;
243 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
245 <&clks IMX6UL_CLK_UART7_SERIAL>;
246 clock-names = "ipg", "per";
247 status = "disabled";
248 };
249
250 uart1: serial@02020000 {
251 compatible = "fsl,imx6ul-uart",
252 "fsl,imx6q-uart";
253 reg = <0x02020000 0x4000>;
254 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
256 <&clks IMX6UL_CLK_UART1_SERIAL>;
257 clock-names = "ipg", "per";
258 status = "disabled";
259 };
260
261 uart8: serial@02024000 {
262 compatible = "fsl,imx6ul-uart",
263 "fsl,imx6q-uart";
264 reg = <0x02024000 0x4000>;
265 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
267 <&clks IMX6UL_CLK_UART8_SERIAL>;
268 clock-names = "ipg", "per";
269 status = "disabled";
270 };
271
272 sai1: sai@02028000 {
273 #sound-dai-cells = <0>;
274 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
275 reg = <0x02028000 0x4000>;
276 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
278 <&clks IMX6UL_CLK_SAI1>,
279 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
280 clock-names = "bus", "mclk1", "mclk2", "mclk3";
281 dmas = <&sdma 35 24 0>,
282 <&sdma 36 24 0>;
283 dma-names = "rx", "tx";
284 status = "disabled";
285 };
286
287 sai2: sai@0202c000 {
288 #sound-dai-cells = <0>;
289 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
290 reg = <0x0202c000 0x4000>;
291 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
293 <&clks IMX6UL_CLK_SAI2>,
294 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
295 clock-names = "bus", "mclk1", "mclk2", "mclk3";
296 dmas = <&sdma 37 24 0>,
297 <&sdma 38 24 0>;
298 dma-names = "rx", "tx";
299 status = "disabled";
300 };
301
302 sai3: sai@02030000 {
303 #sound-dai-cells = <0>;
304 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
305 reg = <0x02030000 0x4000>;
306 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
308 <&clks IMX6UL_CLK_SAI3>,
309 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
310 clock-names = "bus", "mclk1", "mclk2", "mclk3";
311 dmas = <&sdma 39 24 0>,
312 <&sdma 40 24 0>;
313 dma-names = "rx", "tx";
314 status = "disabled";
315 };
316 };
317
318 tsc: tsc@02040000 {
319 compatible = "fsl,imx6ul-tsc";
320 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
321 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&clks IMX6UL_CLK_IPG>,
324 <&clks IMX6UL_CLK_ADC2>;
325 clock-names = "tsc", "adc";
326 status = "disabled";
327 };
328
329 pwm1: pwm@02080000 {
330 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
331 reg = <0x02080000 0x4000>;
332 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clks IMX6UL_CLK_PWM1>,
334 <&clks IMX6UL_CLK_PWM1>;
335 clock-names = "ipg", "per";
336 #pwm-cells = <2>;
337 status = "disabled";
338 };
339
340 pwm2: pwm@02084000 {
341 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
342 reg = <0x02084000 0x4000>;
343 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clks IMX6UL_CLK_PWM2>,
345 <&clks IMX6UL_CLK_PWM2>;
346 clock-names = "ipg", "per";
347 #pwm-cells = <2>;
348 status = "disabled";
349 };
350
351 pwm3: pwm@02088000 {
352 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
353 reg = <0x02088000 0x4000>;
354 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clks IMX6UL_CLK_PWM3>,
356 <&clks IMX6UL_CLK_PWM3>;
357 clock-names = "ipg", "per";
358 #pwm-cells = <2>;
359 status = "disabled";
360 };
361
362 pwm4: pwm@0208c000 {
363 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
364 reg = <0x0208c000 0x4000>;
365 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clks IMX6UL_CLK_PWM4>,
367 <&clks IMX6UL_CLK_PWM4>;
368 clock-names = "ipg", "per";
369 #pwm-cells = <2>;
370 status = "disabled";
371 };
372
373 can1: flexcan@02090000 {
374 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
375 reg = <0x02090000 0x4000>;
376 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
378 <&clks IMX6UL_CLK_CAN1_SERIAL>;
379 clock-names = "ipg", "per";
380 status = "disabled";
381 };
382
383 can2: flexcan@02094000 {
384 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
385 reg = <0x02094000 0x4000>;
386 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
388 <&clks IMX6UL_CLK_CAN2_SERIAL>;
389 clock-names = "ipg", "per";
390 status = "disabled";
391 };
392
393 gpt1: gpt@02098000 {
394 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
395 reg = <0x02098000 0x4000>;
396 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
398 <&clks IMX6UL_CLK_GPT1_SERIAL>;
399 clock-names = "ipg", "per";
400 };
401
402 gpio1: gpio@0209c000 {
403 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
404 reg = <0x0209c000 0x4000>;
405 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 };
412
413 gpio2: gpio@020a0000 {
414 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
415 reg = <0x020a0000 0x4000>;
416 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 };
423
424 gpio3: gpio@020a4000 {
425 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
426 reg = <0x020a4000 0x4000>;
427 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
429 gpio-controller;
430 #gpio-cells = <2>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
433 };
434
435 gpio4: gpio@020a8000 {
436 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
437 reg = <0x020a8000 0x4000>;
438 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 };
445
446 gpio5: gpio@020ac000 {
447 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
448 reg = <0x020ac000 0x4000>;
449 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
455 };
456
457 fec2: ethernet@020b4000 {
458 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
459 reg = <0x020b4000 0x4000>;
460 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX6UL_CLK_ENET>,
463 <&clks IMX6UL_CLK_ENET_AHB>,
464 <&clks IMX6UL_CLK_ENET_PTP>,
465 <&clks IMX6UL_CLK_ENET2_REF_125M>,
466 <&clks IMX6UL_CLK_ENET2_REF_125M>;
467 clock-names = "ipg", "ahb", "ptp",
468 "enet_clk_ref", "enet_out";
469 fsl,num-tx-queues=<1>;
470 fsl,num-rx-queues=<1>;
471 status = "disabled";
472 };
473
474 kpp: kpp@020b8000 {
475 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
476 reg = <0x020b8000 0x4000>;
477 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&clks IMX6UL_CLK_KPP>;
479 status = "disabled";
480 };
481
482 wdog1: wdog@020bc000 {
483 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
484 reg = <0x020bc000 0x4000>;
485 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clks IMX6UL_CLK_WDOG1>;
487 };
488
489 wdog2: wdog@020c0000 {
490 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
491 reg = <0x020c0000 0x4000>;
492 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clks IMX6UL_CLK_WDOG2>;
494 status = "disabled";
495 };
496
497 clks: ccm@020c4000 {
498 compatible = "fsl,imx6ul-ccm";
499 reg = <0x020c4000 0x4000>;
500 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
502 #clock-cells = <1>;
503 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
504 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
505 };
506
507 anatop: anatop@020c8000 {
508 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
509 "syscon", "simple-bus";
510 reg = <0x020c8000 0x1000>;
511 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
514
515 reg_3p0: regulator-3p0@120 {
516 compatible = "fsl,anatop-regulator";
517 regulator-name = "vdd3p0";
518 regulator-min-microvolt = <2625000>;
519 regulator-max-microvolt = <3400000>;
520 anatop-reg-offset = <0x120>;
521 anatop-vol-bit-shift = <8>;
522 anatop-vol-bit-width = <5>;
523 anatop-min-bit-val = <0>;
524 anatop-min-voltage = <2625000>;
525 anatop-max-voltage = <3400000>;
526 anatop-enable-bit = <0>;
527 };
528
529 reg_arm: regulator-vddcore@140 {
530 compatible = "fsl,anatop-regulator";
531 regulator-name = "cpu";
532 regulator-min-microvolt = <725000>;
533 regulator-max-microvolt = <1450000>;
534 regulator-always-on;
535 anatop-reg-offset = <0x140>;
536 anatop-vol-bit-shift = <0>;
537 anatop-vol-bit-width = <5>;
538 anatop-delay-reg-offset = <0x170>;
539 anatop-delay-bit-shift = <24>;
540 anatop-delay-bit-width = <2>;
541 anatop-min-bit-val = <1>;
542 anatop-min-voltage = <725000>;
543 anatop-max-voltage = <1450000>;
544 };
545
546 reg_soc: regulator-vddsoc@140 {
547 compatible = "fsl,anatop-regulator";
548 regulator-name = "vddsoc";
549 regulator-min-microvolt = <725000>;
550 regulator-max-microvolt = <1450000>;
551 regulator-always-on;
552 anatop-reg-offset = <0x140>;
553 anatop-vol-bit-shift = <18>;
554 anatop-vol-bit-width = <5>;
555 anatop-delay-reg-offset = <0x170>;
556 anatop-delay-bit-shift = <28>;
557 anatop-delay-bit-width = <2>;
558 anatop-min-bit-val = <1>;
559 anatop-min-voltage = <725000>;
560 anatop-max-voltage = <1450000>;
561 };
562 };
563
564 usbphy1: usbphy@020c9000 {
565 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
566 reg = <0x020c9000 0x1000>;
567 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&clks IMX6UL_CLK_USBPHY1>;
569 phy-3p0-supply = <®_3p0>;
570 fsl,anatop = <&anatop>;
571 };
572
573 usbphy2: usbphy@020ca000 {
574 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
575 reg = <0x020ca000 0x1000>;
576 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clks IMX6UL_CLK_USBPHY2>;
578 phy-3p0-supply = <®_3p0>;
579 fsl,anatop = <&anatop>;
580 };
581
582 snvs: snvs@020cc000 {
583 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
584 reg = <0x020cc000 0x4000>;
585
586 snvs_rtc: snvs-rtc-lp {
587 compatible = "fsl,sec-v4.0-mon-rtc-lp";
588 regmap = <&snvs>;
589 offset = <0x34>;
590 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
592 };
593
594 snvs_poweroff: snvs-poweroff {
595 compatible = "syscon-poweroff";
596 regmap = <&snvs>;
597 offset = <0x38>;
598 mask = <0x60>;
599 status = "disabled";
600 };
601
602 snvs_pwrkey: snvs-powerkey {
603 compatible = "fsl,sec-v4.0-pwrkey";
604 regmap = <&snvs>;
605 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
606 linux,keycode = <KEY_POWER>;
607 wakeup-source;
608 };
609 };
610
611 epit1: epit@020d0000 {
612 reg = <0x020d0000 0x4000>;
613 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
614 };
615
616 epit2: epit@020d4000 {
617 reg = <0x020d4000 0x4000>;
618 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
619 };
620
621 src: src@020d8000 {
622 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
623 reg = <0x020d8000 0x4000>;
624 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
626 #reset-cells = <1>;
627 };
628
629 gpc: gpc@020dc000 {
630 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
631 reg = <0x020dc000 0x4000>;
632 interrupt-controller;
633 #interrupt-cells = <3>;
634 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
635 interrupt-parent = <&intc>;
636 };
637
638 iomuxc: iomuxc@020e0000 {
639 compatible = "fsl,imx6ul-iomuxc";
640 reg = <0x020e0000 0x4000>;
641 };
642
643 gpr: iomuxc-gpr@020e4000 {
644 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
645 reg = <0x020e4000 0x4000>;
646 };
647
648 gpt2: gpt@020e8000 {
649 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
650 reg = <0x020e8000 0x4000>;
651 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
653 <&clks IMX6UL_CLK_GPT2_SERIAL>;
654 clock-names = "ipg", "per";
655 };
656
657 sdma: sdma@020ec000 {
658 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
659 "fsl,imx35-sdma";
660 reg = <0x020ec000 0x4000>;
661 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&clks IMX6UL_CLK_SDMA>,
663 <&clks IMX6UL_CLK_SDMA>;
664 clock-names = "ipg", "ahb";
665 #dma-cells = <3>;
666 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
667 };
668
669 pwm5: pwm@020f0000 {
670 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
671 reg = <0x020f0000 0x4000>;
672 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clks IMX6UL_CLK_PWM5>,
674 <&clks IMX6UL_CLK_PWM5>;
675 clock-names = "ipg", "per";
676 #pwm-cells = <2>;
677 status = "disabled";
678 };
679
680 pwm6: pwm@020f4000 {
681 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
682 reg = <0x020f4000 0x4000>;
683 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&clks IMX6UL_CLK_PWM6>,
685 <&clks IMX6UL_CLK_PWM6>;
686 clock-names = "ipg", "per";
687 #pwm-cells = <2>;
688 status = "disabled";
689 };
690
691 pwm7: pwm@020f8000 {
692 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
693 reg = <0x020f8000 0x4000>;
694 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&clks IMX6UL_CLK_PWM7>,
696 <&clks IMX6UL_CLK_PWM7>;
697 clock-names = "ipg", "per";
698 #pwm-cells = <2>;
699 status = "disabled";
700 };
701
702 pwm8: pwm@020fc000 {
703 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
704 reg = <0x020fc000 0x4000>;
705 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&clks IMX6UL_CLK_PWM8>,
707 <&clks IMX6UL_CLK_PWM8>;
708 clock-names = "ipg", "per";
709 #pwm-cells = <2>;
710 status = "disabled";
711 };
712 };
713
714 aips2: aips-bus@02100000 {
715 compatible = "fsl,aips-bus", "simple-bus";
716 #address-cells = <1>;
717 #size-cells = <1>;
718 reg = <0x02100000 0x100000>;
719 ranges;
720
721 usbotg1: usb@02184000 {
722 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
723 reg = <0x02184000 0x200>;
724 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clks IMX6UL_CLK_USBOH3>;
726 fsl,usbphy = <&usbphy1>;
727 fsl,usbmisc = <&usbmisc 0>;
728 fsl,anatop = <&anatop>;
729 ahb-burst-config = <0x0>;
730 tx-burst-size-dword = <0x10>;
731 rx-burst-size-dword = <0x10>;
732 status = "disabled";
733 };
734
735 usbotg2: usb@02184200 {
736 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
737 reg = <0x02184200 0x200>;
738 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&clks IMX6UL_CLK_USBOH3>;
740 fsl,usbphy = <&usbphy2>;
741 fsl,usbmisc = <&usbmisc 1>;
742 ahb-burst-config = <0x0>;
743 tx-burst-size-dword = <0x10>;
744 rx-burst-size-dword = <0x10>;
745 status = "disabled";
746 };
747
748 usbmisc: usbmisc@02184800 {
749 #index-cells = <1>;
750 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
751 reg = <0x02184800 0x200>;
752 };
753
754 fec1: ethernet@02188000 {
755 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
756 reg = <0x02188000 0x4000>;
757 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clks IMX6UL_CLK_ENET>,
760 <&clks IMX6UL_CLK_ENET_AHB>,
761 <&clks IMX6UL_CLK_ENET_PTP>,
762 <&clks IMX6UL_CLK_ENET_REF>,
763 <&clks IMX6UL_CLK_ENET_REF>;
764 clock-names = "ipg", "ahb", "ptp",
765 "enet_clk_ref", "enet_out";
766 fsl,num-tx-queues=<1>;
767 fsl,num-rx-queues=<1>;
768 status = "disabled";
769 };
770
771 usdhc1: usdhc@02190000 {
772 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
773 reg = <0x02190000 0x4000>;
774 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX6UL_CLK_USDHC1>,
776 <&clks IMX6UL_CLK_USDHC1>,
777 <&clks IMX6UL_CLK_USDHC1>;
778 clock-names = "ipg", "ahb", "per";
779 bus-width = <4>;
780 status = "disabled";
781 };
782
783 usdhc2: usdhc@02194000 {
784 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
785 reg = <0x02194000 0x4000>;
786 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clks IMX6UL_CLK_USDHC2>,
788 <&clks IMX6UL_CLK_USDHC2>,
789 <&clks IMX6UL_CLK_USDHC2>;
790 clock-names = "ipg", "ahb", "per";
791 bus-width = <4>;
792 status = "disabled";
793 };
794
795 adc1: adc@02198000 {
796 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
797 reg = <0x02198000 0x4000>;
798 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&clks IMX6UL_CLK_ADC1>;
800 num-channels = <2>;
801 clock-names = "adc";
802 fsl,adck-max-frequency = <30000000>, <40000000>,
803 <20000000>;
804 status = "disabled";
805 };
806
807 i2c1: i2c@021a0000 {
808 #address-cells = <1>;
809 #size-cells = <0>;
810 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
811 reg = <0x021a0000 0x4000>;
812 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&clks IMX6UL_CLK_I2C1>;
814 status = "disabled";
815 };
816
817 i2c2: i2c@021a4000 {
818 #address-cells = <1>;
819 #size-cells = <0>;
820 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
821 reg = <0x021a4000 0x4000>;
822 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&clks IMX6UL_CLK_I2C2>;
824 status = "disabled";
825 };
826
827 i2c3: i2c@021a8000 {
828 #address-cells = <1>;
829 #size-cells = <0>;
830 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
831 reg = <0x021a8000 0x4000>;
832 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&clks IMX6UL_CLK_I2C3>;
834 status = "disabled";
835 };
836
837 mmdc: mmdc@021b0000 {
838 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
839 reg = <0x021b0000 0x4000>;
840 };
841
842 lcdif: lcdif@021c8000 {
843 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
844 reg = <0x021c8000 0x4000>;
845 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
847 <&clks IMX6UL_CLK_LCDIF_APB>,
848 <&clks IMX6UL_CLK_DUMMY>;
849 clock-names = "pix", "axi", "disp_axi";
850 status = "disabled";
851 };
852
853 qspi: qspi@021e0000 {
854 #address-cells = <1>;
855 #size-cells = <0>;
856 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
857 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
858 reg-names = "QuadSPI", "QuadSPI-memory";
859 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&clks IMX6UL_CLK_QSPI>,
861 <&clks IMX6UL_CLK_QSPI>;
862 clock-names = "qspi_en", "qspi";
863 status = "disabled";
864 };
865
866 uart2: serial@021e8000 {
867 compatible = "fsl,imx6ul-uart",
868 "fsl,imx6q-uart";
869 reg = <0x021e8000 0x4000>;
870 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
872 <&clks IMX6UL_CLK_UART2_SERIAL>;
873 clock-names = "ipg", "per";
874 status = "disabled";
875 };
876
877 uart3: serial@021ec000 {
878 compatible = "fsl,imx6ul-uart",
879 "fsl,imx6q-uart";
880 reg = <0x021ec000 0x4000>;
881 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
883 <&clks IMX6UL_CLK_UART3_SERIAL>;
884 clock-names = "ipg", "per";
885 status = "disabled";
886 };
887
888 uart4: serial@021f0000 {
889 compatible = "fsl,imx6ul-uart",
890 "fsl,imx6q-uart";
891 reg = <0x021f0000 0x4000>;
892 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
894 <&clks IMX6UL_CLK_UART4_SERIAL>;
895 clock-names = "ipg", "per";
896 status = "disabled";
897 };
898
899 uart5: serial@021f4000 {
900 compatible = "fsl,imx6ul-uart",
901 "fsl,imx6q-uart";
902 reg = <0x021f4000 0x4000>;
903 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
905 <&clks IMX6UL_CLK_UART5_SERIAL>;
906 clock-names = "ipg", "per";
907 status = "disabled";
908 };
909
910 i2c4: i2c@021f8000 {
911 #address-cells = <1>;
912 #size-cells = <0>;
913 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
914 reg = <0x021f8000 0x4000>;
915 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&clks IMX6UL_CLK_I2C4>;
917 status = "disabled";
918 };
919
920 uart6: serial@021fc000 {
921 compatible = "fsl,imx6ul-uart",
922 "fsl,imx6q-uart";
923 reg = <0x021fc000 0x4000>;
924 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
926 <&clks IMX6UL_CLK_UART6_SERIAL>;
927 clock-names = "ipg", "per";
928 status = "disabled";
929 };
930 };
931 };
932};