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1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <dt-bindings/clock/imx6qdl-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16#include "skeleton.dtsi"
17
18/ {
19 aliases {
20 ethernet0 = &fec;
21 can0 = &can1;
22 can1 = &can2;
23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
33 ipu0 = &ipu1;
34 mmc0 = &usdhc1;
35 mmc1 = &usdhc2;
36 mmc2 = &usdhc3;
37 mmc3 = &usdhc4;
38 serial0 = &uart1;
39 serial1 = &uart2;
40 serial2 = &uart3;
41 serial3 = &uart4;
42 serial4 = &uart5;
43 spi0 = &ecspi1;
44 spi1 = &ecspi2;
45 spi2 = &ecspi3;
46 spi3 = &ecspi4;
47 usbphy0 = &usbphy1;
48 usbphy1 = &usbphy2;
49 };
50
51 clocks {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 ckil {
56 compatible = "fsl,imx-ckil", "fixed-clock";
57 #clock-cells = <0>;
58 clock-frequency = <32768>;
59 };
60
61 ckih1 {
62 compatible = "fsl,imx-ckih1", "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <0>;
65 };
66
67 osc {
68 compatible = "fsl,imx-osc", "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <24000000>;
71 };
72 };
73
74 soc {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "simple-bus";
78 interrupt-parent = <&gpc>;
79 ranges;
80
81 dma_apbh: dma-apbh@00110000 {
82 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
83 reg = <0x00110000 0x2000>;
84 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
85 <0 13 IRQ_TYPE_LEVEL_HIGH>,
86 <0 13 IRQ_TYPE_LEVEL_HIGH>,
87 <0 13 IRQ_TYPE_LEVEL_HIGH>;
88 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
89 #dma-cells = <1>;
90 dma-channels = <4>;
91 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
92 };
93
94 gpmi: gpmi-nand@00112000 {
95 compatible = "fsl,imx6q-gpmi-nand";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
99 reg-names = "gpmi-nand", "bch";
100 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
101 interrupt-names = "bch";
102 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
103 <&clks IMX6QDL_CLK_GPMI_APB>,
104 <&clks IMX6QDL_CLK_GPMI_BCH>,
105 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
106 <&clks IMX6QDL_CLK_PER1_BCH>;
107 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
108 "gpmi_bch_apb", "per1_bch";
109 dmas = <&dma_apbh 0>;
110 dma-names = "rx-tx";
111 status = "disabled";
112 };
113
114 hdmi: hdmi@0120000 {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 reg = <0x00120000 0x9000>;
118 interrupts = <0 115 0x04>;
119 gpr = <&gpr>;
120 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
121 <&clks IMX6QDL_CLK_HDMI_ISFR>;
122 clock-names = "iahb", "isfr";
123 status = "disabled";
124
125 port@0 {
126 reg = <0>;
127
128 hdmi_mux_0: endpoint {
129 remote-endpoint = <&ipu1_di0_hdmi>;
130 };
131 };
132
133 port@1 {
134 reg = <1>;
135
136 hdmi_mux_1: endpoint {
137 remote-endpoint = <&ipu1_di1_hdmi>;
138 };
139 };
140 };
141
142 gpu_3d: gpu@00130000 {
143 compatible = "vivante,gc";
144 reg = <0x00130000 0x4000>;
145 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
147 <&clks IMX6QDL_CLK_GPU3D_CORE>,
148 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
149 clock-names = "bus", "core", "shader";
150 power-domains = <&gpc 1>;
151 };
152
153 gpu_2d: gpu@00134000 {
154 compatible = "vivante,gc";
155 reg = <0x00134000 0x4000>;
156 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
158 <&clks IMX6QDL_CLK_GPU2D_CORE>;
159 clock-names = "bus", "core";
160 power-domains = <&gpc 1>;
161 };
162
163 timer@00a00600 {
164 compatible = "arm,cortex-a9-twd-timer";
165 reg = <0x00a00600 0x20>;
166 interrupts = <1 13 0xf01>;
167 interrupt-parent = <&intc>;
168 clocks = <&clks IMX6QDL_CLK_TWD>;
169 };
170
171 intc: interrupt-controller@00a01000 {
172 compatible = "arm,cortex-a9-gic";
173 #interrupt-cells = <3>;
174 interrupt-controller;
175 reg = <0x00a01000 0x1000>,
176 <0x00a00100 0x100>;
177 interrupt-parent = <&intc>;
178 };
179
180 L2: l2-cache@00a02000 {
181 compatible = "arm,pl310-cache";
182 reg = <0x00a02000 0x1000>;
183 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
184 cache-unified;
185 cache-level = <2>;
186 arm,tag-latency = <4 2 3>;
187 arm,data-latency = <4 2 3>;
188 };
189
190 pcie: pcie@0x01000000 {
191 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
192 reg = <0x01ffc000 0x04000>,
193 <0x01f00000 0x80000>;
194 reg-names = "dbi", "config";
195 #address-cells = <3>;
196 #size-cells = <2>;
197 device_type = "pci";
198 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
199 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
200 num-lanes = <1>;
201 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-names = "msi";
203 #interrupt-cells = <1>;
204 interrupt-map-mask = <0 0 0 0x7>;
205 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
206 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
207 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
208 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
210 <&clks IMX6QDL_CLK_LVDS1_GATE>,
211 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
212 clock-names = "pcie", "pcie_bus", "pcie_phy";
213 status = "disabled";
214 };
215
216 pmu {
217 compatible = "arm,cortex-a9-pmu";
218 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
219 };
220
221 aips-bus@02000000 { /* AIPS1 */
222 compatible = "fsl,aips-bus", "simple-bus";
223 #address-cells = <1>;
224 #size-cells = <1>;
225 reg = <0x02000000 0x100000>;
226 ranges;
227
228 spba-bus@02000000 {
229 compatible = "fsl,spba-bus", "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 reg = <0x02000000 0x40000>;
233 ranges;
234
235 spdif: spdif@02004000 {
236 compatible = "fsl,imx35-spdif";
237 reg = <0x02004000 0x4000>;
238 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
239 dmas = <&sdma 14 18 0>,
240 <&sdma 15 18 0>;
241 dma-names = "rx", "tx";
242 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
243 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
244 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
245 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
246 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
247 clock-names = "core", "rxtx0",
248 "rxtx1", "rxtx2",
249 "rxtx3", "rxtx4",
250 "rxtx5", "rxtx6",
251 "rxtx7", "spba";
252 status = "disabled";
253 };
254
255 ecspi1: ecspi@02008000 {
256 #address-cells = <1>;
257 #size-cells = <0>;
258 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
259 reg = <0x02008000 0x4000>;
260 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
262 <&clks IMX6QDL_CLK_ECSPI1>;
263 clock-names = "ipg", "per";
264 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
265 dma-names = "rx", "tx";
266 status = "disabled";
267 };
268
269 ecspi2: ecspi@0200c000 {
270 #address-cells = <1>;
271 #size-cells = <0>;
272 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
273 reg = <0x0200c000 0x4000>;
274 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
276 <&clks IMX6QDL_CLK_ECSPI2>;
277 clock-names = "ipg", "per";
278 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
279 dma-names = "rx", "tx";
280 status = "disabled";
281 };
282
283 ecspi3: ecspi@02010000 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
287 reg = <0x02010000 0x4000>;
288 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
290 <&clks IMX6QDL_CLK_ECSPI3>;
291 clock-names = "ipg", "per";
292 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
293 dma-names = "rx", "tx";
294 status = "disabled";
295 };
296
297 ecspi4: ecspi@02014000 {
298 #address-cells = <1>;
299 #size-cells = <0>;
300 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
301 reg = <0x02014000 0x4000>;
302 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
304 <&clks IMX6QDL_CLK_ECSPI4>;
305 clock-names = "ipg", "per";
306 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
307 dma-names = "rx", "tx";
308 status = "disabled";
309 };
310
311 uart1: serial@02020000 {
312 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
313 reg = <0x02020000 0x4000>;
314 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
316 <&clks IMX6QDL_CLK_UART_SERIAL>;
317 clock-names = "ipg", "per";
318 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
319 dma-names = "rx", "tx";
320 status = "disabled";
321 };
322
323 esai: esai@02024000 {
324 #sound-dai-cells = <0>;
325 compatible = "fsl,imx35-esai";
326 reg = <0x02024000 0x4000>;
327 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
329 <&clks IMX6QDL_CLK_ESAI_MEM>,
330 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
331 <&clks IMX6QDL_CLK_ESAI_IPG>,
332 <&clks IMX6QDL_CLK_SPBA>;
333 clock-names = "core", "mem", "extal", "fsys", "spba";
334 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
335 dma-names = "rx", "tx";
336 status = "disabled";
337 };
338
339 ssi1: ssi@02028000 {
340 #sound-dai-cells = <0>;
341 compatible = "fsl,imx6q-ssi",
342 "fsl,imx51-ssi";
343 reg = <0x02028000 0x4000>;
344 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
346 <&clks IMX6QDL_CLK_SSI1>;
347 clock-names = "ipg", "baud";
348 dmas = <&sdma 37 1 0>,
349 <&sdma 38 1 0>;
350 dma-names = "rx", "tx";
351 fsl,fifo-depth = <15>;
352 status = "disabled";
353 };
354
355 ssi2: ssi@0202c000 {
356 #sound-dai-cells = <0>;
357 compatible = "fsl,imx6q-ssi",
358 "fsl,imx51-ssi";
359 reg = <0x0202c000 0x4000>;
360 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
362 <&clks IMX6QDL_CLK_SSI2>;
363 clock-names = "ipg", "baud";
364 dmas = <&sdma 41 1 0>,
365 <&sdma 42 1 0>;
366 dma-names = "rx", "tx";
367 fsl,fifo-depth = <15>;
368 status = "disabled";
369 };
370
371 ssi3: ssi@02030000 {
372 #sound-dai-cells = <0>;
373 compatible = "fsl,imx6q-ssi",
374 "fsl,imx51-ssi";
375 reg = <0x02030000 0x4000>;
376 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
378 <&clks IMX6QDL_CLK_SSI3>;
379 clock-names = "ipg", "baud";
380 dmas = <&sdma 45 1 0>,
381 <&sdma 46 1 0>;
382 dma-names = "rx", "tx";
383 fsl,fifo-depth = <15>;
384 status = "disabled";
385 };
386
387 asrc: asrc@02034000 {
388 compatible = "fsl,imx53-asrc";
389 reg = <0x02034000 0x4000>;
390 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
392 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
393 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
394 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
395 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
396 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
397 <&clks IMX6QDL_CLK_SPBA>;
398 clock-names = "mem", "ipg", "asrck_0",
399 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
400 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
401 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
402 "asrck_d", "asrck_e", "asrck_f", "spba";
403 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
404 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
405 dma-names = "rxa", "rxb", "rxc",
406 "txa", "txb", "txc";
407 fsl,asrc-rate = <48000>;
408 fsl,asrc-width = <16>;
409 status = "okay";
410 };
411
412 spba@0203c000 {
413 reg = <0x0203c000 0x4000>;
414 };
415 };
416
417 vpu: vpu@02040000 {
418 compatible = "cnm,coda960";
419 reg = <0x02040000 0x3c000>;
420 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
421 <0 3 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-names = "bit", "jpeg";
423 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
424 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
425 clock-names = "per", "ahb";
426 power-domains = <&gpc 1>;
427 resets = <&src 1>;
428 iram = <&ocram>;
429 };
430
431 aipstz@0207c000 { /* AIPSTZ1 */
432 reg = <0x0207c000 0x4000>;
433 };
434
435 pwm1: pwm@02080000 {
436 #pwm-cells = <2>;
437 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
438 reg = <0x02080000 0x4000>;
439 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clks IMX6QDL_CLK_IPG>,
441 <&clks IMX6QDL_CLK_PWM1>;
442 clock-names = "ipg", "per";
443 status = "disabled";
444 };
445
446 pwm2: pwm@02084000 {
447 #pwm-cells = <2>;
448 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
449 reg = <0x02084000 0x4000>;
450 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clks IMX6QDL_CLK_IPG>,
452 <&clks IMX6QDL_CLK_PWM2>;
453 clock-names = "ipg", "per";
454 status = "disabled";
455 };
456
457 pwm3: pwm@02088000 {
458 #pwm-cells = <2>;
459 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
460 reg = <0x02088000 0x4000>;
461 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX6QDL_CLK_IPG>,
463 <&clks IMX6QDL_CLK_PWM3>;
464 clock-names = "ipg", "per";
465 status = "disabled";
466 };
467
468 pwm4: pwm@0208c000 {
469 #pwm-cells = <2>;
470 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
471 reg = <0x0208c000 0x4000>;
472 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&clks IMX6QDL_CLK_IPG>,
474 <&clks IMX6QDL_CLK_PWM4>;
475 clock-names = "ipg", "per";
476 status = "disabled";
477 };
478
479 can1: flexcan@02090000 {
480 compatible = "fsl,imx6q-flexcan";
481 reg = <0x02090000 0x4000>;
482 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
484 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
485 clock-names = "ipg", "per";
486 status = "disabled";
487 };
488
489 can2: flexcan@02094000 {
490 compatible = "fsl,imx6q-flexcan";
491 reg = <0x02094000 0x4000>;
492 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
494 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
495 clock-names = "ipg", "per";
496 status = "disabled";
497 };
498
499 gpt: gpt@02098000 {
500 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
501 reg = <0x02098000 0x4000>;
502 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
504 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
505 <&clks IMX6QDL_CLK_GPT_3M>;
506 clock-names = "ipg", "per", "osc_per";
507 };
508
509 gpio1: gpio@0209c000 {
510 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
511 reg = <0x0209c000 0x4000>;
512 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
513 <0 67 IRQ_TYPE_LEVEL_HIGH>;
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-controller;
517 #interrupt-cells = <2>;
518 };
519
520 gpio2: gpio@020a0000 {
521 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
522 reg = <0x020a0000 0x4000>;
523 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
524 <0 69 IRQ_TYPE_LEVEL_HIGH>;
525 gpio-controller;
526 #gpio-cells = <2>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
529 };
530
531 gpio3: gpio@020a4000 {
532 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
533 reg = <0x020a4000 0x4000>;
534 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
535 <0 71 IRQ_TYPE_LEVEL_HIGH>;
536 gpio-controller;
537 #gpio-cells = <2>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
540 };
541
542 gpio4: gpio@020a8000 {
543 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
544 reg = <0x020a8000 0x4000>;
545 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
546 <0 73 IRQ_TYPE_LEVEL_HIGH>;
547 gpio-controller;
548 #gpio-cells = <2>;
549 interrupt-controller;
550 #interrupt-cells = <2>;
551 };
552
553 gpio5: gpio@020ac000 {
554 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
555 reg = <0x020ac000 0x4000>;
556 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
557 <0 75 IRQ_TYPE_LEVEL_HIGH>;
558 gpio-controller;
559 #gpio-cells = <2>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
562 };
563
564 gpio6: gpio@020b0000 {
565 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
566 reg = <0x020b0000 0x4000>;
567 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
568 <0 77 IRQ_TYPE_LEVEL_HIGH>;
569 gpio-controller;
570 #gpio-cells = <2>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 };
574
575 gpio7: gpio@020b4000 {
576 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
577 reg = <0x020b4000 0x4000>;
578 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
579 <0 79 IRQ_TYPE_LEVEL_HIGH>;
580 gpio-controller;
581 #gpio-cells = <2>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
584 };
585
586 kpp: kpp@020b8000 {
587 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
588 reg = <0x020b8000 0x4000>;
589 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&clks IMX6QDL_CLK_IPG>;
591 status = "disabled";
592 };
593
594 wdog1: wdog@020bc000 {
595 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
596 reg = <0x020bc000 0x4000>;
597 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&clks IMX6QDL_CLK_DUMMY>;
599 };
600
601 wdog2: wdog@020c0000 {
602 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
603 reg = <0x020c0000 0x4000>;
604 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&clks IMX6QDL_CLK_DUMMY>;
606 status = "disabled";
607 };
608
609 clks: ccm@020c4000 {
610 compatible = "fsl,imx6q-ccm";
611 reg = <0x020c4000 0x4000>;
612 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
613 <0 88 IRQ_TYPE_LEVEL_HIGH>;
614 #clock-cells = <1>;
615 };
616
617 anatop: anatop@020c8000 {
618 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
619 reg = <0x020c8000 0x1000>;
620 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
621 <0 54 IRQ_TYPE_LEVEL_HIGH>,
622 <0 127 IRQ_TYPE_LEVEL_HIGH>;
623
624 regulator-1p1@110 {
625 compatible = "fsl,anatop-regulator";
626 regulator-name = "vdd1p1";
627 regulator-min-microvolt = <800000>;
628 regulator-max-microvolt = <1375000>;
629 regulator-always-on;
630 anatop-reg-offset = <0x110>;
631 anatop-vol-bit-shift = <8>;
632 anatop-vol-bit-width = <5>;
633 anatop-min-bit-val = <4>;
634 anatop-min-voltage = <800000>;
635 anatop-max-voltage = <1375000>;
636 };
637
638 regulator-3p0@120 {
639 compatible = "fsl,anatop-regulator";
640 regulator-name = "vdd3p0";
641 regulator-min-microvolt = <2800000>;
642 regulator-max-microvolt = <3150000>;
643 regulator-always-on;
644 anatop-reg-offset = <0x120>;
645 anatop-vol-bit-shift = <8>;
646 anatop-vol-bit-width = <5>;
647 anatop-min-bit-val = <0>;
648 anatop-min-voltage = <2625000>;
649 anatop-max-voltage = <3400000>;
650 };
651
652 regulator-2p5@130 {
653 compatible = "fsl,anatop-regulator";
654 regulator-name = "vdd2p5";
655 regulator-min-microvolt = <2000000>;
656 regulator-max-microvolt = <2750000>;
657 regulator-always-on;
658 anatop-reg-offset = <0x130>;
659 anatop-vol-bit-shift = <8>;
660 anatop-vol-bit-width = <5>;
661 anatop-min-bit-val = <0>;
662 anatop-min-voltage = <2000000>;
663 anatop-max-voltage = <2750000>;
664 };
665
666 reg_arm: regulator-vddcore@140 {
667 compatible = "fsl,anatop-regulator";
668 regulator-name = "vddarm";
669 regulator-min-microvolt = <725000>;
670 regulator-max-microvolt = <1450000>;
671 regulator-always-on;
672 anatop-reg-offset = <0x140>;
673 anatop-vol-bit-shift = <0>;
674 anatop-vol-bit-width = <5>;
675 anatop-delay-reg-offset = <0x170>;
676 anatop-delay-bit-shift = <24>;
677 anatop-delay-bit-width = <2>;
678 anatop-min-bit-val = <1>;
679 anatop-min-voltage = <725000>;
680 anatop-max-voltage = <1450000>;
681 };
682
683 reg_pu: regulator-vddpu@140 {
684 compatible = "fsl,anatop-regulator";
685 regulator-name = "vddpu";
686 regulator-min-microvolt = <725000>;
687 regulator-max-microvolt = <1450000>;
688 regulator-enable-ramp-delay = <150>;
689 anatop-reg-offset = <0x140>;
690 anatop-vol-bit-shift = <9>;
691 anatop-vol-bit-width = <5>;
692 anatop-delay-reg-offset = <0x170>;
693 anatop-delay-bit-shift = <26>;
694 anatop-delay-bit-width = <2>;
695 anatop-min-bit-val = <1>;
696 anatop-min-voltage = <725000>;
697 anatop-max-voltage = <1450000>;
698 };
699
700 reg_soc: regulator-vddsoc@140 {
701 compatible = "fsl,anatop-regulator";
702 regulator-name = "vddsoc";
703 regulator-min-microvolt = <725000>;
704 regulator-max-microvolt = <1450000>;
705 regulator-always-on;
706 anatop-reg-offset = <0x140>;
707 anatop-vol-bit-shift = <18>;
708 anatop-vol-bit-width = <5>;
709 anatop-delay-reg-offset = <0x170>;
710 anatop-delay-bit-shift = <28>;
711 anatop-delay-bit-width = <2>;
712 anatop-min-bit-val = <1>;
713 anatop-min-voltage = <725000>;
714 anatop-max-voltage = <1450000>;
715 };
716 };
717
718 tempmon: tempmon {
719 compatible = "fsl,imx6q-tempmon";
720 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
721 fsl,tempmon = <&anatop>;
722 fsl,tempmon-data = <&ocotp>;
723 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
724 };
725
726 usbphy1: usbphy@020c9000 {
727 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
728 reg = <0x020c9000 0x1000>;
729 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
731 fsl,anatop = <&anatop>;
732 };
733
734 usbphy2: usbphy@020ca000 {
735 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
736 reg = <0x020ca000 0x1000>;
737 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
739 fsl,anatop = <&anatop>;
740 };
741
742 snvs: snvs@020cc000 {
743 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
744 reg = <0x020cc000 0x4000>;
745
746 snvs_rtc: snvs-rtc-lp {
747 compatible = "fsl,sec-v4.0-mon-rtc-lp";
748 regmap = <&snvs>;
749 offset = <0x34>;
750 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
751 <0 20 IRQ_TYPE_LEVEL_HIGH>;
752 };
753
754 snvs_poweroff: snvs-poweroff {
755 compatible = "syscon-poweroff";
756 regmap = <&snvs>;
757 offset = <0x38>;
758 mask = <0x60>;
759 status = "disabled";
760 };
761 };
762
763 epit1: epit@020d0000 { /* EPIT1 */
764 reg = <0x020d0000 0x4000>;
765 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
766 };
767
768 epit2: epit@020d4000 { /* EPIT2 */
769 reg = <0x020d4000 0x4000>;
770 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
771 };
772
773 src: src@020d8000 {
774 compatible = "fsl,imx6q-src", "fsl,imx51-src";
775 reg = <0x020d8000 0x4000>;
776 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
777 <0 96 IRQ_TYPE_LEVEL_HIGH>;
778 #reset-cells = <1>;
779 };
780
781 gpc: gpc@020dc000 {
782 compatible = "fsl,imx6q-gpc";
783 reg = <0x020dc000 0x4000>;
784 interrupt-controller;
785 #interrupt-cells = <3>;
786 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
787 <0 90 IRQ_TYPE_LEVEL_HIGH>;
788 interrupt-parent = <&intc>;
789 pu-supply = <®_pu>;
790 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
791 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
792 <&clks IMX6QDL_CLK_GPU2D_CORE>,
793 <&clks IMX6QDL_CLK_GPU2D_AXI>,
794 <&clks IMX6QDL_CLK_OPENVG_AXI>,
795 <&clks IMX6QDL_CLK_VPU_AXI>;
796 #power-domain-cells = <1>;
797 };
798
799 gpr: iomuxc-gpr@020e0000 {
800 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
801 reg = <0x020e0000 0x38>;
802 };
803
804 iomuxc: iomuxc@020e0000 {
805 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
806 reg = <0x020e0000 0x4000>;
807 };
808
809 ldb: ldb@020e0008 {
810 #address-cells = <1>;
811 #size-cells = <0>;
812 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
813 gpr = <&gpr>;
814 status = "disabled";
815
816 lvds-channel@0 {
817 #address-cells = <1>;
818 #size-cells = <0>;
819 reg = <0>;
820 status = "disabled";
821
822 port@0 {
823 reg = <0>;
824
825 lvds0_mux_0: endpoint {
826 remote-endpoint = <&ipu1_di0_lvds0>;
827 };
828 };
829
830 port@1 {
831 reg = <1>;
832
833 lvds0_mux_1: endpoint {
834 remote-endpoint = <&ipu1_di1_lvds0>;
835 };
836 };
837 };
838
839 lvds-channel@1 {
840 #address-cells = <1>;
841 #size-cells = <0>;
842 reg = <1>;
843 status = "disabled";
844
845 port@0 {
846 reg = <0>;
847
848 lvds1_mux_0: endpoint {
849 remote-endpoint = <&ipu1_di0_lvds1>;
850 };
851 };
852
853 port@1 {
854 reg = <1>;
855
856 lvds1_mux_1: endpoint {
857 remote-endpoint = <&ipu1_di1_lvds1>;
858 };
859 };
860 };
861 };
862
863 dcic1: dcic@020e4000 {
864 reg = <0x020e4000 0x4000>;
865 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
866 };
867
868 dcic2: dcic@020e8000 {
869 reg = <0x020e8000 0x4000>;
870 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
871 };
872
873 sdma: sdma@020ec000 {
874 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
875 reg = <0x020ec000 0x4000>;
876 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&clks IMX6QDL_CLK_SDMA>,
878 <&clks IMX6QDL_CLK_SDMA>;
879 clock-names = "ipg", "ahb";
880 #dma-cells = <3>;
881 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
882 };
883 };
884
885 aips-bus@02100000 { /* AIPS2 */
886 compatible = "fsl,aips-bus", "simple-bus";
887 #address-cells = <1>;
888 #size-cells = <1>;
889 reg = <0x02100000 0x100000>;
890 ranges;
891
892 crypto: caam@2100000 {
893 compatible = "fsl,sec-v4.0";
894 fsl,sec-era = <4>;
895 #address-cells = <1>;
896 #size-cells = <1>;
897 reg = <0x2100000 0x10000>;
898 ranges = <0 0x2100000 0x10000>;
899 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
900 <&clks IMX6QDL_CLK_CAAM_ACLK>,
901 <&clks IMX6QDL_CLK_CAAM_IPG>,
902 <&clks IMX6QDL_CLK_EIM_SLOW>;
903 clock-names = "mem", "aclk", "ipg", "emi_slow";
904
905 sec_jr0: jr0@1000 {
906 compatible = "fsl,sec-v4.0-job-ring";
907 reg = <0x1000 0x1000>;
908 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
909 };
910
911 sec_jr1: jr1@2000 {
912 compatible = "fsl,sec-v4.0-job-ring";
913 reg = <0x2000 0x1000>;
914 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
915 };
916 };
917
918 aipstz@0217c000 { /* AIPSTZ2 */
919 reg = <0x0217c000 0x4000>;
920 };
921
922 usbotg: usb@02184000 {
923 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
924 reg = <0x02184000 0x200>;
925 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&clks IMX6QDL_CLK_USBOH3>;
927 fsl,usbphy = <&usbphy1>;
928 fsl,usbmisc = <&usbmisc 0>;
929 ahb-burst-config = <0x0>;
930 tx-burst-size-dword = <0x10>;
931 rx-burst-size-dword = <0x10>;
932 status = "disabled";
933 };
934
935 usbh1: usb@02184200 {
936 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
937 reg = <0x02184200 0x200>;
938 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&clks IMX6QDL_CLK_USBOH3>;
940 fsl,usbphy = <&usbphy2>;
941 fsl,usbmisc = <&usbmisc 1>;
942 dr_mode = "host";
943 ahb-burst-config = <0x0>;
944 tx-burst-size-dword = <0x10>;
945 rx-burst-size-dword = <0x10>;
946 status = "disabled";
947 };
948
949 usbh2: usb@02184400 {
950 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
951 reg = <0x02184400 0x200>;
952 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&clks IMX6QDL_CLK_USBOH3>;
954 fsl,usbmisc = <&usbmisc 2>;
955 dr_mode = "host";
956 ahb-burst-config = <0x0>;
957 tx-burst-size-dword = <0x10>;
958 rx-burst-size-dword = <0x10>;
959 status = "disabled";
960 };
961
962 usbh3: usb@02184600 {
963 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
964 reg = <0x02184600 0x200>;
965 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&clks IMX6QDL_CLK_USBOH3>;
967 fsl,usbmisc = <&usbmisc 3>;
968 dr_mode = "host";
969 ahb-burst-config = <0x0>;
970 tx-burst-size-dword = <0x10>;
971 rx-burst-size-dword = <0x10>;
972 status = "disabled";
973 };
974
975 usbmisc: usbmisc@02184800 {
976 #index-cells = <1>;
977 compatible = "fsl,imx6q-usbmisc";
978 reg = <0x02184800 0x200>;
979 clocks = <&clks IMX6QDL_CLK_USBOH3>;
980 };
981
982 fec: ethernet@02188000 {
983 compatible = "fsl,imx6q-fec";
984 reg = <0x02188000 0x4000>;
985 interrupts-extended =
986 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
987 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&clks IMX6QDL_CLK_ENET>,
989 <&clks IMX6QDL_CLK_ENET>,
990 <&clks IMX6QDL_CLK_ENET_REF>;
991 clock-names = "ipg", "ahb", "ptp";
992 status = "disabled";
993 };
994
995 mlb@0218c000 {
996 reg = <0x0218c000 0x4000>;
997 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
998 <0 117 IRQ_TYPE_LEVEL_HIGH>,
999 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1000 };
1001
1002 usdhc1: usdhc@02190000 {
1003 compatible = "fsl,imx6q-usdhc";
1004 reg = <0x02190000 0x4000>;
1005 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1007 <&clks IMX6QDL_CLK_USDHC1>,
1008 <&clks IMX6QDL_CLK_USDHC1>;
1009 clock-names = "ipg", "ahb", "per";
1010 bus-width = <4>;
1011 status = "disabled";
1012 };
1013
1014 usdhc2: usdhc@02194000 {
1015 compatible = "fsl,imx6q-usdhc";
1016 reg = <0x02194000 0x4000>;
1017 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1019 <&clks IMX6QDL_CLK_USDHC2>,
1020 <&clks IMX6QDL_CLK_USDHC2>;
1021 clock-names = "ipg", "ahb", "per";
1022 bus-width = <4>;
1023 status = "disabled";
1024 };
1025
1026 usdhc3: usdhc@02198000 {
1027 compatible = "fsl,imx6q-usdhc";
1028 reg = <0x02198000 0x4000>;
1029 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1031 <&clks IMX6QDL_CLK_USDHC3>,
1032 <&clks IMX6QDL_CLK_USDHC3>;
1033 clock-names = "ipg", "ahb", "per";
1034 bus-width = <4>;
1035 status = "disabled";
1036 };
1037
1038 usdhc4: usdhc@0219c000 {
1039 compatible = "fsl,imx6q-usdhc";
1040 reg = <0x0219c000 0x4000>;
1041 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1043 <&clks IMX6QDL_CLK_USDHC4>,
1044 <&clks IMX6QDL_CLK_USDHC4>;
1045 clock-names = "ipg", "ahb", "per";
1046 bus-width = <4>;
1047 status = "disabled";
1048 };
1049
1050 i2c1: i2c@021a0000 {
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1053 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1054 reg = <0x021a0000 0x4000>;
1055 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&clks IMX6QDL_CLK_I2C1>;
1057 status = "disabled";
1058 };
1059
1060 i2c2: i2c@021a4000 {
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1064 reg = <0x021a4000 0x4000>;
1065 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&clks IMX6QDL_CLK_I2C2>;
1067 status = "disabled";
1068 };
1069
1070 i2c3: i2c@021a8000 {
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1073 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1074 reg = <0x021a8000 0x4000>;
1075 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clks IMX6QDL_CLK_I2C3>;
1077 status = "disabled";
1078 };
1079
1080 romcp@021ac000 {
1081 reg = <0x021ac000 0x4000>;
1082 };
1083
1084 mmdc0: mmdc@021b0000 { /* MMDC0 */
1085 compatible = "fsl,imx6q-mmdc";
1086 reg = <0x021b0000 0x4000>;
1087 };
1088
1089 mmdc1: mmdc@021b4000 { /* MMDC1 */
1090 reg = <0x021b4000 0x4000>;
1091 };
1092
1093 weim: weim@021b8000 {
1094 compatible = "fsl,imx6q-weim";
1095 reg = <0x021b8000 0x4000>;
1096 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1098 };
1099
1100 ocotp: ocotp@021bc000 {
1101 compatible = "fsl,imx6q-ocotp", "syscon";
1102 reg = <0x021bc000 0x4000>;
1103 };
1104
1105 tzasc@021d0000 { /* TZASC1 */
1106 reg = <0x021d0000 0x4000>;
1107 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1108 };
1109
1110 tzasc@021d4000 { /* TZASC2 */
1111 reg = <0x021d4000 0x4000>;
1112 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1113 };
1114
1115 audmux: audmux@021d8000 {
1116 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1117 reg = <0x021d8000 0x4000>;
1118 status = "disabled";
1119 };
1120
1121 mipi_csi: mipi@021dc000 {
1122 reg = <0x021dc000 0x4000>;
1123 };
1124
1125 mipi_dsi: mipi@021e0000 {
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 reg = <0x021e0000 0x4000>;
1129 status = "disabled";
1130
1131 ports {
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1134
1135 port@0 {
1136 reg = <0>;
1137
1138 mipi_mux_0: endpoint {
1139 remote-endpoint = <&ipu1_di0_mipi>;
1140 };
1141 };
1142
1143 port@1 {
1144 reg = <1>;
1145
1146 mipi_mux_1: endpoint {
1147 remote-endpoint = <&ipu1_di1_mipi>;
1148 };
1149 };
1150 };
1151 };
1152
1153 vdoa@021e4000 {
1154 reg = <0x021e4000 0x4000>;
1155 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1156 };
1157
1158 uart2: serial@021e8000 {
1159 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1160 reg = <0x021e8000 0x4000>;
1161 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1163 <&clks IMX6QDL_CLK_UART_SERIAL>;
1164 clock-names = "ipg", "per";
1165 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1166 dma-names = "rx", "tx";
1167 status = "disabled";
1168 };
1169
1170 uart3: serial@021ec000 {
1171 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1172 reg = <0x021ec000 0x4000>;
1173 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1174 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1175 <&clks IMX6QDL_CLK_UART_SERIAL>;
1176 clock-names = "ipg", "per";
1177 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1178 dma-names = "rx", "tx";
1179 status = "disabled";
1180 };
1181
1182 uart4: serial@021f0000 {
1183 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1184 reg = <0x021f0000 0x4000>;
1185 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1186 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1187 <&clks IMX6QDL_CLK_UART_SERIAL>;
1188 clock-names = "ipg", "per";
1189 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1190 dma-names = "rx", "tx";
1191 status = "disabled";
1192 };
1193
1194 uart5: serial@021f4000 {
1195 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1196 reg = <0x021f4000 0x4000>;
1197 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1199 <&clks IMX6QDL_CLK_UART_SERIAL>;
1200 clock-names = "ipg", "per";
1201 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1202 dma-names = "rx", "tx";
1203 status = "disabled";
1204 };
1205 };
1206
1207 ipu1: ipu@02400000 {
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1210 compatible = "fsl,imx6q-ipu";
1211 reg = <0x02400000 0x400000>;
1212 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1213 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&clks IMX6QDL_CLK_IPU1>,
1215 <&clks IMX6QDL_CLK_IPU1_DI0>,
1216 <&clks IMX6QDL_CLK_IPU1_DI1>;
1217 clock-names = "bus", "di0", "di1";
1218 resets = <&src 2>;
1219
1220 ipu1_csi0: port@0 {
1221 reg = <0>;
1222 };
1223
1224 ipu1_csi1: port@1 {
1225 reg = <1>;
1226 };
1227
1228 ipu1_di0: port@2 {
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1231 reg = <2>;
1232
1233 ipu1_di0_disp0: endpoint@0 {
1234 };
1235
1236 ipu1_di0_hdmi: endpoint@1 {
1237 remote-endpoint = <&hdmi_mux_0>;
1238 };
1239
1240 ipu1_di0_mipi: endpoint@2 {
1241 remote-endpoint = <&mipi_mux_0>;
1242 };
1243
1244 ipu1_di0_lvds0: endpoint@3 {
1245 remote-endpoint = <&lvds0_mux_0>;
1246 };
1247
1248 ipu1_di0_lvds1: endpoint@4 {
1249 remote-endpoint = <&lvds1_mux_0>;
1250 };
1251 };
1252
1253 ipu1_di1: port@3 {
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1256 reg = <3>;
1257
1258 ipu1_di0_disp1: endpoint@0 {
1259 };
1260
1261 ipu1_di1_hdmi: endpoint@1 {
1262 remote-endpoint = <&hdmi_mux_1>;
1263 };
1264
1265 ipu1_di1_mipi: endpoint@2 {
1266 remote-endpoint = <&mipi_mux_1>;
1267 };
1268
1269 ipu1_di1_lvds0: endpoint@3 {
1270 remote-endpoint = <&lvds0_mux_1>;
1271 };
1272
1273 ipu1_di1_lvds1: endpoint@4 {
1274 remote-endpoint = <&lvds1_mux_1>;
1275 };
1276 };
1277 };
1278 };
1279};