1/*
  2 * Device Tree file for Marvell Armada 375 evaluation board
  3 * (DB-88F6720)
  4 *
  5 *  Copyright (C) 2014 Marvell
  6 *
  7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9 *
 10 * This file is dual-licensed: you can use it either under the terms
 11 * of the GPL or the X11 license, at your option. Note that this dual
 12 * licensing only applies to this file, and not this project as a
 13 * whole.
 14 *
 15 *  a) This file is free software; you can redistribute it and/or
 16 *     modify it under the terms of the GNU General Public License as
 17 *     published by the Free Software Foundation; either version 2 of the
 18 *     License, or (at your option) any later version.
 19 *
 20 *     This file is distributed in the hope that it will be useful
 21 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 22 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 23 *     GNU General Public License for more details.
 24 *
 25 * Or, alternatively
 26 *
 27 *  b) Permission is hereby granted, free of charge, to any person
 28 *     obtaining a copy of this software and associated documentation
 29 *     files (the "Software"), to deal in the Software without
 30 *     restriction, including without limitation the rights to use
 31 *     copy, modify, merge, publish, distribute, sublicense, and/or
 32 *     sell copies of the Software, and to permit persons to whom the
 33 *     Software is furnished to do so, subject to the following
 34 *     conditions:
 35 *
 36 *     The above copyright notice and this permission notice shall be
 37 *     included in all copies or substantial portions of the Software.
 38 *
 39 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 46 *     OTHER DEALINGS IN THE SOFTWARE.
 47 */
 48
 49/dts-v1/;
 50#include <dt-bindings/gpio/gpio.h>
 51#include "armada-375.dtsi"
 52
 53/ {
 54	model = "Marvell Armada 375 Development Board";
 55	compatible = "marvell,a375-db", "marvell,armada375";
 56
 57	chosen {
 58		stdout-path = "serial0:115200n8";
 59	};
 60
 61	memory {
 62		device_type = "memory";
 63		reg = <0x00000000 0x40000000>; /* 1 GB */
 64	};
 65
 66	soc {
 67		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 68			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
 69			  MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
 70			  MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
 71
 72		internal-regs {
 73			spi@10600 {
 74				pinctrl-0 = <&spi0_pins>;
 75				pinctrl-names = "default";
 76				/*
 77				 * SPI conflicts with NAND, so we disable it
 78				 * here, and select NAND as the enabled device
 79				 * by default.
 80				 */
 81				status = "disabled";
 82
 83				spi-flash@0 {
 84					#address-cells = <1>;
 85					#size-cells = <1>;
 86					compatible = "n25q128a13", "jedec,spi-nor";
 87					reg = <0>; /* Chip select 0 */
 88					spi-max-frequency = <108000000>;
 89				};
 90			};
 91
 92			i2c@11000 {
 93				status = "okay";
 94				clock-frequency = <100000>;
 95				pinctrl-0 = <&i2c0_pins>;
 96				pinctrl-names = "default";
 97			};
 98
 99			i2c@11100 {
100				status = "okay";
101				clock-frequency = <100000>;
102				pinctrl-0 = <&i2c1_pins>;
103				pinctrl-names = "default";
104			};
105
106			serial@12000 {
107				status = "okay";
108			};
109
110			pinctrl {
111				sdio_st_pins: sdio-st-pins {
112					marvell,pins = "mpp44", "mpp45";
113					marvell,function = "gpio";
114				};
115			};
116
117			sata@a0000 {
118				status = "okay";
119				nr-ports = <2>;
120			};
121
122			nand: nand@d0000 {
123				pinctrl-0 = <&nand_pins>;
124				pinctrl-names = "default";
125				status = "okay";
126				num-cs = <1>;
127				marvell,nand-keep-config;
128				marvell,nand-enable-arbiter;
129				nand-on-flash-bbt;
130				nand-ecc-strength = <4>;
131				nand-ecc-step-size = <512>;
132
133				partition@0 {
134					label = "U-Boot";
135					reg = <0 0x800000>;
136				};
137				partition@800000 {
138					label = "Linux";
139					reg = <0x800000 0x800000>;
140				};
141				partition@1000000 {
142					label = "Filesystem";
143					reg = <0x1000000 0x3f000000>;
144				};
145			};
146
147			usb@54000 {
148				status = "okay";
149			};
150
151			usb3@58000 {
152				status = "okay";
153			};
154
155			mvsdio@d4000 {
156				pinctrl-0 = <&sdio_pins &sdio_st_pins>;
157				pinctrl-names = "default";
158				status = "okay";
159				cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
160				wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
161			};
162
163			mdio {
164				phy0: ethernet-phy@0 {
165					reg = <0>;
166				};
167
168				phy3: ethernet-phy@3 {
169					reg = <3>;
170				};
171			};
172
173			ethernet@f0000 {
174				status = "okay";
175
176				eth0@c4000 {
177					status = "okay";
178					phy = <&phy0>;
179					phy-mode = "rgmii-id";
180				};
181
182				eth1@c5000 {
183					status = "okay";
184					phy = <&phy3>;
185					phy-mode = "gmii";
186				};
187			};
188		};
189
190		pcie-controller {
191			status = "okay";
192			/*
193			 * The two PCIe units are accessible through
194			 * standard PCIe slots on the board.
195			 */
196			pcie@1,0 {
197				/* Port 0, Lane 0 */
198				status = "okay";
199			};
200			pcie@2,0 {
201				/* Port 1, Lane 0 */
202				status = "okay";
203			};
204		};
205	};
206};